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003910eb NM |
1 | /* |
2 | * Support for configuration of IO Delay module found on Texas Instruments SoCs | |
3 | * such as DRA7 | |
4 | * | |
5 | * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ | |
6 | * | |
7 | * This file is licensed under the terms of the GNU General Public | |
8 | * License version 2. This program is licensed "as is" without any | |
9 | * warranty of any kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #include <linux/err.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/of.h> | |
17 | #include <linux/of_device.h> | |
18 | #include <linux/pinctrl/pinconf.h> | |
19 | #include <linux/pinctrl/pinconf-generic.h> | |
20 | #include <linux/pinctrl/pinctrl.h> | |
21 | #include <linux/regmap.h> | |
22 | #include <linux/slab.h> | |
23 | ||
24 | #include "../core.h" | |
25 | #include "../devicetree.h" | |
26 | ||
27 | #define DRIVER_NAME "ti-iodelay" | |
28 | ||
29 | /** | |
30 | * struct ti_iodelay_reg_data - Describes the registers for the iodelay instance | |
31 | * @signature_mask: CONFIG_REG mask for the signature bits (see TRM) | |
32 | * @signature_value: CONFIG_REG signature value to be written (see TRM) | |
33 | * @lock_mask: CONFIG_REG mask for the lock bits (see TRM) | |
34 | * @lock_val: CONFIG_REG lock value for the lock bits (see TRM) | |
35 | * @unlock_val:CONFIG_REG unlock value for the lock bits (see TRM) | |
36 | * @binary_data_coarse_mask: CONFIG_REG coarse mask (see TRM) | |
37 | * @binary_data_fine_mask: CONFIG_REG fine mask (see TRM) | |
38 | * @reg_refclk_offset: Refclk register offset | |
39 | * @refclk_period_mask: Refclk mask | |
40 | * @reg_coarse_offset: Coarse register configuration offset | |
41 | * @coarse_delay_count_mask: Coarse delay count mask | |
42 | * @coarse_ref_count_mask: Coarse ref count mask | |
43 | * @reg_fine_offset: Fine register configuration offset | |
44 | * @fine_delay_count_mask: Fine delay count mask | |
45 | * @fine_ref_count_mask: Fine ref count mask | |
46 | * @reg_global_lock_offset: Global iodelay module lock register offset | |
47 | * @global_lock_mask: Lock mask | |
48 | * @global_unlock_val: Unlock value | |
49 | * @global_lock_val: Lock value | |
50 | * @reg_start_offset: Offset to iodelay registers after the CONFIG_REG_0 to 8 | |
51 | * @reg_nr_per_pin: Number of iodelay registers for each pin | |
52 | * @regmap_config: Regmap configuration for the IODelay region | |
53 | */ | |
54 | struct ti_iodelay_reg_data { | |
55 | u32 signature_mask; | |
56 | u32 signature_value; | |
57 | u32 lock_mask; | |
58 | u32 lock_val; | |
59 | u32 unlock_val; | |
60 | u32 binary_data_coarse_mask; | |
61 | u32 binary_data_fine_mask; | |
62 | ||
63 | u32 reg_refclk_offset; | |
64 | u32 refclk_period_mask; | |
65 | ||
66 | u32 reg_coarse_offset; | |
67 | u32 coarse_delay_count_mask; | |
68 | u32 coarse_ref_count_mask; | |
69 | ||
70 | u32 reg_fine_offset; | |
71 | u32 fine_delay_count_mask; | |
72 | u32 fine_ref_count_mask; | |
73 | ||
74 | u32 reg_global_lock_offset; | |
75 | u32 global_lock_mask; | |
76 | u32 global_unlock_val; | |
77 | u32 global_lock_val; | |
78 | ||
79 | u32 reg_start_offset; | |
80 | u32 reg_nr_per_pin; | |
81 | ||
82 | struct regmap_config *regmap_config; | |
83 | }; | |
84 | ||
85 | /** | |
86 | * struct ti_iodelay_reg_values - Computed io_reg configuration values (see TRM) | |
87 | * @coarse_ref_count: Coarse reference count | |
88 | * @coarse_delay_count: Coarse delay count | |
89 | * @fine_ref_count: Fine reference count | |
90 | * @fine_delay_count: Fine Delay count | |
91 | * @ref_clk_period: Reference Clock period | |
92 | * @cdpe: Coarse delay parameter | |
93 | * @fdpe: Fine delay parameter | |
94 | */ | |
95 | struct ti_iodelay_reg_values { | |
96 | u16 coarse_ref_count; | |
97 | u16 coarse_delay_count; | |
98 | ||
99 | u16 fine_ref_count; | |
100 | u16 fine_delay_count; | |
101 | ||
102 | u16 ref_clk_period; | |
103 | ||
104 | u32 cdpe; | |
105 | u32 fdpe; | |
106 | }; | |
107 | ||
108 | /** | |
109 | * struct ti_iodelay_cfg - Description of each configuration parameters | |
110 | * @offset: Configuration register offset | |
111 | * @a_delay: Agnostic Delay (in ps) | |
112 | * @g_delay: Gnostic Delay (in ps) | |
113 | */ | |
114 | struct ti_iodelay_cfg { | |
115 | u16 offset; | |
116 | u16 a_delay; | |
117 | u16 g_delay; | |
118 | }; | |
119 | ||
120 | /** | |
121 | * struct ti_iodelay_pingroup - Structure that describes one group | |
122 | * @cfg: configuration array for the pin (from dt) | |
123 | * @ncfg: number of configuration values allocated | |
124 | * @config: pinconf "Config" - currently a dummy value | |
125 | */ | |
126 | struct ti_iodelay_pingroup { | |
127 | struct ti_iodelay_cfg *cfg; | |
128 | int ncfg; | |
129 | unsigned long config; | |
130 | }; | |
131 | ||
132 | /** | |
133 | * struct ti_iodelay_device - Represents information for a iodelay instance | |
134 | * @dev: Device pointer | |
135 | * @phys_base: Physical address base of the iodelay device | |
136 | * @reg_base: Virtual address base of the iodelay device | |
137 | * @regmap: Regmap for this iodelay instance | |
138 | * @pctl: Pinctrl device | |
139 | * @desc: pinctrl descriptor for pctl | |
140 | * @pa: pinctrl pin wise description | |
141 | * @reg_data: Register definition data for the IODelay instance | |
142 | * @reg_init_conf_values: Initial configuration values. | |
143 | */ | |
144 | struct ti_iodelay_device { | |
145 | struct device *dev; | |
146 | unsigned long phys_base; | |
147 | void __iomem *reg_base; | |
148 | struct regmap *regmap; | |
149 | ||
150 | struct pinctrl_dev *pctl; | |
151 | struct pinctrl_desc desc; | |
152 | struct pinctrl_pin_desc *pa; | |
153 | ||
154 | const struct ti_iodelay_reg_data *reg_data; | |
155 | struct ti_iodelay_reg_values reg_init_conf_values; | |
156 | }; | |
157 | ||
158 | /** | |
159 | * ti_iodelay_extract() - extract bits for a field | |
160 | * @val: Register value | |
161 | * @mask: Mask | |
162 | * | |
163 | * Return: extracted value which is appropriately shifted | |
164 | */ | |
165 | static inline u32 ti_iodelay_extract(u32 val, u32 mask) | |
166 | { | |
167 | return (val & mask) >> __ffs(mask); | |
168 | } | |
169 | ||
170 | /** | |
171 | * ti_iodelay_compute_dpe() - Compute equation for delay parameter | |
172 | * @period: Period to use | |
173 | * @ref: Reference Count | |
174 | * @delay: Delay count | |
175 | * @delay_m: Delay multiplier | |
176 | * | |
177 | * Return: Computed delay parameter | |
178 | */ | |
179 | static inline u32 ti_iodelay_compute_dpe(u16 period, u16 ref, u16 delay, | |
180 | u16 delay_m) | |
181 | { | |
182 | u64 m, d; | |
183 | ||
184 | /* Handle overflow conditions */ | |
185 | m = 10 * (u64)period * (u64)ref; | |
186 | d = 2 * (u64)delay * (u64)delay_m; | |
187 | ||
188 | /* Truncate result back to 32 bits */ | |
189 | return div64_u64(m, d); | |
190 | } | |
191 | ||
192 | /** | |
193 | * ti_iodelay_pinconf_set() - Configure the pin configuration | |
194 | * @iod: iodelay device | |
195 | * @cfg: Configuration | |
196 | * | |
197 | * Update the configuration register as per TRM and lockup once done. | |
198 | * *IMPORTANT NOTE* SoC TRM does recommend doing iodelay programmation only | |
199 | * while in Isolation. But, then, isolation also implies that every pin | |
200 | * on the SoC (including DDR) will be isolated out. The only benefit being | |
201 | * a glitchless configuration, However, the intent of this driver is purely | |
202 | * to support a "glitchy" configuration where applicable. | |
203 | * | |
204 | * Return: 0 in case of success, else appropriate error value | |
205 | */ | |
206 | static int ti_iodelay_pinconf_set(struct ti_iodelay_device *iod, | |
207 | struct ti_iodelay_cfg *cfg) | |
208 | { | |
209 | const struct ti_iodelay_reg_data *reg = iod->reg_data; | |
210 | struct ti_iodelay_reg_values *ival = &iod->reg_init_conf_values; | |
211 | struct device *dev = iod->dev; | |
212 | u32 g_delay_coarse, g_delay_fine; | |
213 | u32 a_delay_coarse, a_delay_fine; | |
214 | u32 c_elements, f_elements; | |
215 | u32 total_delay; | |
216 | u32 reg_mask, reg_val, tmp_val; | |
217 | int r; | |
218 | ||
219 | /* NOTE: Truncation is expected in all division below */ | |
220 | g_delay_coarse = cfg->g_delay / 920; | |
221 | g_delay_fine = ((cfg->g_delay % 920) * 10) / 60; | |
222 | ||
223 | a_delay_coarse = cfg->a_delay / ival->cdpe; | |
224 | a_delay_fine = ((cfg->a_delay % ival->cdpe) * 10) / ival->fdpe; | |
225 | ||
226 | c_elements = g_delay_coarse + a_delay_coarse; | |
227 | f_elements = (g_delay_fine + a_delay_fine) / 10; | |
228 | ||
229 | if (f_elements > 22) { | |
230 | total_delay = c_elements * ival->cdpe + f_elements * ival->fdpe; | |
231 | c_elements = total_delay / ival->cdpe; | |
232 | f_elements = (total_delay % ival->cdpe) / ival->fdpe; | |
233 | } | |
234 | ||
235 | reg_mask = reg->signature_mask; | |
236 | reg_val = reg->signature_value << __ffs(reg->signature_mask); | |
237 | ||
238 | reg_mask |= reg->binary_data_coarse_mask; | |
239 | tmp_val = c_elements << __ffs(reg->binary_data_coarse_mask); | |
240 | if (tmp_val & ~reg->binary_data_coarse_mask) { | |
241 | dev_err(dev, "Masking overflow of coarse elements %08x\n", | |
242 | tmp_val); | |
243 | tmp_val &= reg->binary_data_coarse_mask; | |
244 | } | |
245 | reg_val |= tmp_val; | |
246 | ||
247 | reg_mask |= reg->binary_data_fine_mask; | |
248 | tmp_val = f_elements << __ffs(reg->binary_data_fine_mask); | |
249 | if (tmp_val & ~reg->binary_data_fine_mask) { | |
250 | dev_err(dev, "Masking overflow of fine elements %08x\n", | |
251 | tmp_val); | |
252 | tmp_val &= reg->binary_data_fine_mask; | |
253 | } | |
254 | reg_val |= tmp_val; | |
255 | ||
256 | /* | |
257 | * NOTE: we leave the iodelay values unlocked - this is to work around | |
258 | * situations such as those found with mmc mode change. | |
259 | * However, this leaves open any unwarranted changes to padconf register | |
260 | * impacting iodelay configuration. Use with care! | |
261 | */ | |
262 | reg_mask |= reg->lock_mask; | |
263 | reg_val |= reg->unlock_val << __ffs(reg->lock_mask); | |
264 | r = regmap_update_bits(iod->regmap, cfg->offset, reg_mask, reg_val); | |
265 | ||
266 | dev_info(dev, "Set reg 0x%x Delay(a: %d g: %d), Elements(C=%d F=%d)0x%x\n", | |
267 | cfg->offset, cfg->a_delay, cfg->g_delay, c_elements, | |
268 | f_elements, reg_val); | |
269 | ||
270 | return r; | |
271 | } | |
272 | ||
273 | /** | |
274 | * ti_iodelay_pinconf_init_dev() - Initialize IODelay device | |
275 | * @iod: iodelay device | |
276 | * | |
277 | * Unlocks the iodelay region, computes the common parameters | |
278 | * | |
279 | * Return: 0 in case of success, else appropriate error value | |
280 | */ | |
281 | static int ti_iodelay_pinconf_init_dev(struct ti_iodelay_device *iod) | |
282 | { | |
283 | const struct ti_iodelay_reg_data *reg = iod->reg_data; | |
284 | struct device *dev = iod->dev; | |
285 | struct ti_iodelay_reg_values *ival = &iod->reg_init_conf_values; | |
286 | u32 val; | |
287 | int r; | |
288 | ||
289 | /* unlock the iodelay region */ | |
290 | r = regmap_update_bits(iod->regmap, reg->reg_global_lock_offset, | |
291 | reg->global_lock_mask, reg->global_unlock_val); | |
292 | if (r) | |
293 | return r; | |
294 | ||
295 | /* Read up Recalibration sequence done by bootloader */ | |
296 | r = regmap_read(iod->regmap, reg->reg_refclk_offset, &val); | |
297 | if (r) | |
298 | return r; | |
299 | ival->ref_clk_period = ti_iodelay_extract(val, reg->refclk_period_mask); | |
300 | dev_dbg(dev, "refclk_period=0x%04x\n", ival->ref_clk_period); | |
301 | ||
302 | r = regmap_read(iod->regmap, reg->reg_coarse_offset, &val); | |
303 | if (r) | |
304 | return r; | |
305 | ival->coarse_ref_count = | |
306 | ti_iodelay_extract(val, reg->coarse_ref_count_mask); | |
307 | ival->coarse_delay_count = | |
308 | ti_iodelay_extract(val, reg->coarse_delay_count_mask); | |
309 | if (!ival->coarse_delay_count) { | |
310 | dev_err(dev, "Invalid Coarse delay count (0) (reg=0x%08x)\n", | |
311 | val); | |
312 | return -EINVAL; | |
313 | } | |
314 | ival->cdpe = ti_iodelay_compute_dpe(ival->ref_clk_period, | |
315 | ival->coarse_ref_count, | |
316 | ival->coarse_delay_count, 88); | |
317 | if (!ival->cdpe) { | |
318 | dev_err(dev, "Invalid cdpe computed params = %d %d %d\n", | |
319 | ival->ref_clk_period, ival->coarse_ref_count, | |
320 | ival->coarse_delay_count); | |
321 | return -EINVAL; | |
322 | } | |
323 | dev_dbg(iod->dev, "coarse: ref=0x%04x delay=0x%04x cdpe=0x%08x\n", | |
324 | ival->coarse_ref_count, ival->coarse_delay_count, ival->cdpe); | |
325 | ||
326 | r = regmap_read(iod->regmap, reg->reg_fine_offset, &val); | |
327 | if (r) | |
328 | return r; | |
329 | ival->fine_ref_count = | |
330 | ti_iodelay_extract(val, reg->fine_ref_count_mask); | |
331 | ival->fine_delay_count = | |
332 | ti_iodelay_extract(val, reg->fine_delay_count_mask); | |
333 | if (!ival->fine_delay_count) { | |
334 | dev_err(dev, "Invalid Fine delay count (0) (reg=0x%08x)\n", | |
335 | val); | |
336 | return -EINVAL; | |
337 | } | |
338 | ival->fdpe = ti_iodelay_compute_dpe(ival->ref_clk_period, | |
339 | ival->fine_ref_count, | |
340 | ival->fine_delay_count, 264); | |
341 | if (!ival->fdpe) { | |
342 | dev_err(dev, "Invalid fdpe(0) computed params = %d %d %d\n", | |
343 | ival->ref_clk_period, ival->fine_ref_count, | |
344 | ival->fine_delay_count); | |
345 | return -EINVAL; | |
346 | } | |
347 | dev_dbg(iod->dev, "fine: ref=0x%04x delay=0x%04x fdpe=0x%08x\n", | |
348 | ival->fine_ref_count, ival->fine_delay_count, ival->fdpe); | |
349 | ||
350 | return 0; | |
351 | } | |
352 | ||
353 | /** | |
354 | * ti_iodelay_pinconf_deinit_dev() - deinit the iodelay device | |
355 | * @iod: IODelay device | |
356 | * | |
357 | * Deinitialize the IODelay device (basically just lock the region back up. | |
358 | */ | |
359 | static void ti_iodelay_pinconf_deinit_dev(struct ti_iodelay_device *iod) | |
360 | { | |
361 | const struct ti_iodelay_reg_data *reg = iod->reg_data; | |
362 | ||
363 | /* lock the iodelay region back again */ | |
364 | regmap_update_bits(iod->regmap, reg->reg_global_lock_offset, | |
365 | reg->global_lock_mask, reg->global_lock_val); | |
366 | } | |
367 | ||
368 | /** | |
369 | * ti_iodelay_get_pingroup() - Find the group mapped by a group selector | |
370 | * @iod: iodelay device | |
371 | * @selector: Group Selector | |
372 | * | |
373 | * Return: Corresponding group representing group selector | |
374 | */ | |
375 | static struct ti_iodelay_pingroup * | |
376 | ti_iodelay_get_pingroup(struct ti_iodelay_device *iod, unsigned int selector) | |
377 | { | |
378 | struct group_desc *g; | |
379 | ||
380 | g = pinctrl_generic_get_group(iod->pctl, selector); | |
381 | if (!g) { | |
382 | dev_err(iod->dev, "%s could not find pingroup %i\n", __func__, | |
383 | selector); | |
384 | ||
385 | return NULL; | |
386 | } | |
387 | ||
388 | return g->data; | |
389 | } | |
390 | ||
391 | /** | |
392 | * ti_iodelay_offset_to_pin() - get a pin index based on the register offset | |
393 | * @iod: iodelay driver instance | |
394 | * @offset: register offset from the base | |
395 | */ | |
396 | static int ti_iodelay_offset_to_pin(struct ti_iodelay_device *iod, | |
397 | unsigned int offset) | |
398 | { | |
399 | const struct ti_iodelay_reg_data *r = iod->reg_data; | |
400 | unsigned int index; | |
401 | ||
402 | if (offset > r->regmap_config->max_register) { | |
403 | dev_err(iod->dev, "mux offset out of range: 0x%x (0x%x)\n", | |
404 | offset, r->regmap_config->max_register); | |
405 | return -EINVAL; | |
406 | } | |
407 | ||
408 | index = (offset - r->reg_start_offset) / r->regmap_config->reg_stride; | |
409 | index /= r->reg_nr_per_pin; | |
410 | ||
411 | return index; | |
412 | } | |
413 | ||
414 | /** | |
415 | * ti_iodelay_node_iterator() - Iterate iodelay node | |
416 | * @pctldev: Pin controller driver | |
417 | * @np: Device node | |
418 | * @pinctrl_spec: Parsed arguments from device tree | |
419 | * @pins: Array of pins in the pin group | |
420 | * @pin_index: Pin index in the pin array | |
421 | * @data: Pin controller driver specific data | |
422 | * | |
423 | */ | |
424 | static int ti_iodelay_node_iterator(struct pinctrl_dev *pctldev, | |
425 | struct device_node *np, | |
426 | const struct of_phandle_args *pinctrl_spec, | |
427 | int *pins, int pin_index, void *data) | |
428 | { | |
429 | struct ti_iodelay_device *iod; | |
430 | struct ti_iodelay_cfg *cfg = data; | |
431 | const struct ti_iodelay_reg_data *r; | |
432 | struct pinctrl_pin_desc *pd; | |
433 | int pin; | |
434 | ||
435 | iod = pinctrl_dev_get_drvdata(pctldev); | |
436 | if (!iod) | |
437 | return -EINVAL; | |
438 | ||
439 | r = iod->reg_data; | |
440 | ||
441 | if (pinctrl_spec->args_count < r->reg_nr_per_pin) { | |
442 | dev_err(iod->dev, "invalid args_count for spec: %i\n", | |
443 | pinctrl_spec->args_count); | |
444 | ||
445 | return -EINVAL; | |
446 | } | |
447 | ||
448 | /* Index plus two value cells */ | |
449 | cfg[pin_index].offset = pinctrl_spec->args[0]; | |
450 | cfg[pin_index].a_delay = pinctrl_spec->args[1] & 0xffff; | |
451 | cfg[pin_index].g_delay = pinctrl_spec->args[2] & 0xffff; | |
452 | ||
453 | pin = ti_iodelay_offset_to_pin(iod, cfg[pin_index].offset); | |
454 | if (pin < 0) { | |
455 | dev_err(iod->dev, "could not add functions for %s %ux\n", | |
456 | np->name, cfg[pin_index].offset); | |
457 | return -ENODEV; | |
458 | } | |
459 | pins[pin_index] = pin; | |
460 | ||
461 | pd = &iod->pa[pin]; | |
462 | pd->drv_data = &cfg[pin_index]; | |
463 | ||
464 | dev_dbg(iod->dev, "%s offset=%x a_delay = %d g_delay = %d\n", | |
465 | np->name, cfg[pin_index].offset, cfg[pin_index].a_delay, | |
466 | cfg[pin_index].g_delay); | |
467 | ||
468 | return 0; | |
469 | } | |
470 | ||
471 | /** | |
472 | * ti_iodelay_dt_node_to_map() - Map a device tree node to appropriate group | |
473 | * @pctldev: pinctrl device representing IODelay device | |
474 | * @np: Node Pointer (device tree) | |
475 | * @map: Pinctrl Map returned back to pinctrl framework | |
476 | * @num_maps: Number of maps (1) | |
477 | * | |
478 | * Maps the device tree description into a group of configuration parameters | |
479 | * for iodelay block entry. | |
480 | * | |
481 | * Return: 0 in case of success, else appropriate error value | |
482 | */ | |
483 | static int ti_iodelay_dt_node_to_map(struct pinctrl_dev *pctldev, | |
484 | struct device_node *np, | |
485 | struct pinctrl_map **map, | |
486 | unsigned int *num_maps) | |
487 | { | |
488 | struct ti_iodelay_device *iod; | |
489 | struct ti_iodelay_cfg *cfg; | |
490 | struct ti_iodelay_pingroup *g; | |
491 | const char *name = "pinctrl-pin-array"; | |
492 | int rows, *pins, error = -EINVAL, i; | |
493 | ||
494 | iod = pinctrl_dev_get_drvdata(pctldev); | |
495 | if (!iod) | |
496 | return -EINVAL; | |
497 | ||
498 | rows = pinctrl_count_index_with_args(np, name); | |
499 | if (rows == -EINVAL) | |
500 | return rows; | |
501 | ||
502 | *map = devm_kzalloc(iod->dev, sizeof(**map), GFP_KERNEL); | |
503 | if (!*map) | |
504 | return -ENOMEM; | |
505 | *num_maps = 0; | |
506 | ||
507 | g = devm_kzalloc(iod->dev, sizeof(*g), GFP_KERNEL); | |
508 | if (!g) { | |
509 | error = -ENOMEM; | |
510 | goto free_map; | |
511 | } | |
512 | ||
513 | pins = devm_kzalloc(iod->dev, sizeof(*pins) * rows, GFP_KERNEL); | |
514 | if (!pins) | |
515 | goto free_group; | |
516 | ||
517 | cfg = devm_kzalloc(iod->dev, sizeof(*cfg) * rows, GFP_KERNEL); | |
518 | if (!cfg) { | |
519 | error = -ENOMEM; | |
520 | goto free_pins; | |
521 | } | |
522 | ||
523 | for (i = 0; i < rows; i++) { | |
524 | struct of_phandle_args pinctrl_spec; | |
525 | ||
526 | error = pinctrl_parse_index_with_args(np, name, i, | |
527 | &pinctrl_spec); | |
528 | if (error) | |
529 | goto free_data; | |
530 | ||
531 | error = ti_iodelay_node_iterator(pctldev, np, &pinctrl_spec, | |
532 | pins, i, cfg); | |
533 | if (error) | |
534 | goto free_data; | |
535 | } | |
536 | ||
537 | g->cfg = cfg; | |
538 | g->ncfg = i; | |
539 | g->config = PIN_CONFIG_END; | |
540 | ||
541 | error = pinctrl_generic_add_group(iod->pctl, np->name, pins, i, g); | |
542 | if (error < 0) | |
543 | goto free_data; | |
544 | ||
545 | (*map)->type = PIN_MAP_TYPE_CONFIGS_GROUP; | |
546 | (*map)->data.configs.group_or_pin = np->name; | |
547 | (*map)->data.configs.configs = &g->config; | |
548 | (*map)->data.configs.num_configs = 1; | |
549 | *num_maps = 1; | |
550 | ||
551 | return 0; | |
552 | ||
553 | free_data: | |
554 | devm_kfree(iod->dev, cfg); | |
555 | free_pins: | |
556 | devm_kfree(iod->dev, pins); | |
557 | free_group: | |
558 | devm_kfree(iod->dev, g); | |
559 | free_map: | |
560 | devm_kfree(iod->dev, *map); | |
561 | ||
562 | return error; | |
563 | } | |
564 | ||
565 | /** | |
566 | * ti_iodelay_pinconf_group_get() - Get the group configuration | |
567 | * @pctldev: pinctrl device representing IODelay device | |
568 | * @selector: Group selector | |
569 | * @config: Configuration returned | |
570 | * | |
571 | * Return: The configuration if the group is valid, else returns -EINVAL | |
572 | */ | |
573 | static int ti_iodelay_pinconf_group_get(struct pinctrl_dev *pctldev, | |
574 | unsigned int selector, | |
575 | unsigned long *config) | |
576 | { | |
577 | struct ti_iodelay_device *iod; | |
578 | struct device *dev; | |
579 | struct ti_iodelay_pingroup *group; | |
580 | ||
581 | iod = pinctrl_dev_get_drvdata(pctldev); | |
582 | dev = iod->dev; | |
583 | group = ti_iodelay_get_pingroup(iod, selector); | |
584 | ||
585 | if (!group) | |
586 | return -EINVAL; | |
587 | ||
588 | *config = group->config; | |
589 | return 0; | |
590 | } | |
591 | ||
592 | /** | |
593 | * ti_iodelay_pinconf_group_set() - Configure the groups of pins | |
594 | * @pctldev: pinctrl device representing IODelay device | |
595 | * @selector: Group selector | |
596 | * @configs: Configurations | |
597 | * @num_configs: Number of configurations | |
598 | * | |
599 | * Return: 0 if all went fine, else appropriate error value. | |
600 | */ | |
601 | static int ti_iodelay_pinconf_group_set(struct pinctrl_dev *pctldev, | |
602 | unsigned int selector, | |
603 | unsigned long *configs, | |
604 | unsigned int num_configs) | |
605 | { | |
606 | struct ti_iodelay_device *iod; | |
607 | struct device *dev; | |
608 | struct ti_iodelay_pingroup *group; | |
609 | int i; | |
610 | ||
611 | iod = pinctrl_dev_get_drvdata(pctldev); | |
612 | dev = iod->dev; | |
613 | group = ti_iodelay_get_pingroup(iod, selector); | |
614 | ||
615 | if (num_configs != 1) { | |
616 | dev_err(dev, "Unsupported number of configurations %d\n", | |
617 | num_configs); | |
618 | return -EINVAL; | |
619 | } | |
620 | ||
621 | if (*configs != PIN_CONFIG_END) { | |
622 | dev_err(dev, "Unsupported configuration\n"); | |
623 | return -EINVAL; | |
624 | } | |
625 | ||
626 | for (i = 0; i < group->ncfg; i++) { | |
627 | if (ti_iodelay_pinconf_set(iod, &group->cfg[i])) | |
628 | return -ENOTSUPP; | |
629 | } | |
630 | ||
631 | return 0; | |
632 | } | |
633 | ||
634 | #ifdef CONFIG_DEBUG_FS | |
635 | /** | |
636 | * ti_iodelay_pin_to_offset() - get pin register offset based on the pin index | |
637 | * @iod: iodelay driver instance | |
638 | * @selector: Pin index | |
639 | */ | |
640 | static unsigned int ti_iodelay_pin_to_offset(struct ti_iodelay_device *iod, | |
641 | unsigned int selector) | |
642 | { | |
643 | const struct ti_iodelay_reg_data *r = iod->reg_data; | |
644 | unsigned int offset; | |
645 | ||
646 | offset = selector * r->regmap_config->reg_stride; | |
647 | offset *= r->reg_nr_per_pin; | |
648 | offset += r->reg_start_offset; | |
649 | ||
650 | return offset; | |
651 | } | |
652 | ||
653 | static void ti_iodelay_pin_dbg_show(struct pinctrl_dev *pctldev, | |
654 | struct seq_file *s, | |
655 | unsigned int pin) | |
656 | { | |
657 | struct ti_iodelay_device *iod; | |
658 | struct pinctrl_pin_desc *pd; | |
659 | struct ti_iodelay_cfg *cfg; | |
660 | const struct ti_iodelay_reg_data *r; | |
661 | unsigned long offset; | |
662 | u32 in, oen, out; | |
663 | ||
664 | iod = pinctrl_dev_get_drvdata(pctldev); | |
665 | r = iod->reg_data; | |
666 | ||
667 | offset = ti_iodelay_pin_to_offset(iod, pin); | |
003910eb NM |
668 | pd = &iod->pa[pin]; |
669 | cfg = pd->drv_data; | |
670 | ||
671 | regmap_read(iod->regmap, offset, &in); | |
672 | regmap_read(iod->regmap, offset + r->regmap_config->reg_stride, &oen); | |
673 | regmap_read(iod->regmap, offset + r->regmap_config->reg_stride * 2, | |
674 | &out); | |
675 | ||
676 | seq_printf(s, "%lx a: %i g: %i (%08x %08x %08x) %s ", | |
677 | iod->phys_base + offset, | |
678 | cfg ? cfg->a_delay : -1, | |
679 | cfg ? cfg->g_delay : -1, | |
680 | in, oen, out, DRIVER_NAME); | |
681 | } | |
682 | ||
683 | /** | |
684 | * ti_iodelay_pinconf_group_dbg_show() - show the group information | |
685 | * @pctldev: Show the group information | |
686 | * @s: Sequence file | |
687 | * @selector: Group selector | |
688 | * | |
689 | * Provide the configuration information of the selected group | |
690 | */ | |
691 | static void ti_iodelay_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, | |
692 | struct seq_file *s, | |
693 | unsigned int selector) | |
694 | { | |
695 | struct ti_iodelay_device *iod; | |
696 | struct device *dev; | |
697 | struct ti_iodelay_pingroup *group; | |
698 | int i; | |
699 | ||
700 | iod = pinctrl_dev_get_drvdata(pctldev); | |
701 | dev = iod->dev; | |
702 | group = ti_iodelay_get_pingroup(iod, selector); | |
703 | if (!group) | |
704 | return; | |
705 | ||
706 | for (i = 0; i < group->ncfg; i++) { | |
707 | struct ti_iodelay_cfg *cfg; | |
708 | u32 reg = 0; | |
709 | ||
710 | cfg = &group->cfg[i]; | |
711 | regmap_read(iod->regmap, cfg->offset, ®), | |
712 | seq_printf(s, "\n\t0x%08x = 0x%08x (%3d, %3d)", | |
713 | cfg->offset, reg, cfg->a_delay, | |
714 | cfg->g_delay); | |
715 | } | |
716 | } | |
717 | #endif | |
718 | ||
719 | static struct pinctrl_ops ti_iodelay_pinctrl_ops = { | |
720 | .get_groups_count = pinctrl_generic_get_group_count, | |
721 | .get_group_name = pinctrl_generic_get_group_name, | |
722 | .get_group_pins = pinctrl_generic_get_group_pins, | |
723 | #ifdef CONFIG_DEBUG_FS | |
724 | .pin_dbg_show = ti_iodelay_pin_dbg_show, | |
725 | #endif | |
726 | .dt_node_to_map = ti_iodelay_dt_node_to_map, | |
727 | }; | |
728 | ||
729 | static struct pinconf_ops ti_iodelay_pinctrl_pinconf_ops = { | |
730 | .pin_config_group_get = ti_iodelay_pinconf_group_get, | |
731 | .pin_config_group_set = ti_iodelay_pinconf_group_set, | |
732 | #ifdef CONFIG_DEBUG_FS | |
733 | .pin_config_group_dbg_show = ti_iodelay_pinconf_group_dbg_show, | |
734 | #endif | |
735 | }; | |
736 | ||
737 | /** | |
738 | * ti_iodelay_alloc_pins() - Allocate structures needed for pins for iodelay | |
739 | * @dev: Device pointer | |
740 | * @iod: iodelay device | |
741 | * @base_phy: Base Physical Address | |
742 | * | |
743 | * Return: 0 if all went fine, else appropriate error value. | |
744 | */ | |
745 | static int ti_iodelay_alloc_pins(struct device *dev, | |
746 | struct ti_iodelay_device *iod, u32 base_phy) | |
747 | { | |
748 | const struct ti_iodelay_reg_data *r = iod->reg_data; | |
749 | struct pinctrl_pin_desc *pin; | |
750 | u32 phy_reg; | |
751 | int nr_pins, i; | |
752 | ||
753 | nr_pins = ti_iodelay_offset_to_pin(iod, r->regmap_config->max_register); | |
754 | dev_dbg(dev, "Allocating %i pins\n", nr_pins); | |
755 | ||
756 | iod->pa = devm_kzalloc(dev, sizeof(*iod->pa) * nr_pins, GFP_KERNEL); | |
757 | if (!iod->pa) | |
758 | return -ENOMEM; | |
759 | ||
760 | iod->desc.pins = iod->pa; | |
761 | iod->desc.npins = nr_pins; | |
762 | ||
763 | phy_reg = r->reg_start_offset + base_phy; | |
764 | ||
765 | for (i = 0; i < nr_pins; i++, phy_reg += 4) { | |
766 | pin = &iod->pa[i]; | |
767 | pin->number = i; | |
768 | } | |
769 | ||
770 | return 0; | |
771 | } | |
772 | ||
773 | static struct regmap_config dra7_iodelay_regmap_config = { | |
774 | .reg_bits = 32, | |
775 | .reg_stride = 4, | |
776 | .val_bits = 32, | |
777 | .max_register = 0xd1c, | |
778 | }; | |
779 | ||
780 | static struct ti_iodelay_reg_data dra7_iodelay_data = { | |
781 | .signature_mask = 0x0003f000, | |
782 | .signature_value = 0x29, | |
783 | .lock_mask = 0x00000400, | |
784 | .lock_val = 1, | |
785 | .unlock_val = 0, | |
786 | .binary_data_coarse_mask = 0x000003e0, | |
787 | .binary_data_fine_mask = 0x0000001f, | |
788 | ||
789 | .reg_refclk_offset = 0x14, | |
790 | .refclk_period_mask = 0xffff, | |
791 | ||
792 | .reg_coarse_offset = 0x18, | |
793 | .coarse_delay_count_mask = 0xffff0000, | |
794 | .coarse_ref_count_mask = 0x0000ffff, | |
795 | ||
796 | .reg_fine_offset = 0x1C, | |
797 | .fine_delay_count_mask = 0xffff0000, | |
798 | .fine_ref_count_mask = 0x0000ffff, | |
799 | ||
800 | .reg_global_lock_offset = 0x2c, | |
801 | .global_lock_mask = 0x0000ffff, | |
802 | .global_unlock_val = 0x0000aaaa, | |
803 | .global_lock_val = 0x0000aaab, | |
804 | ||
805 | .reg_start_offset = 0x30, | |
806 | .reg_nr_per_pin = 3, | |
807 | .regmap_config = &dra7_iodelay_regmap_config, | |
808 | }; | |
809 | ||
810 | static const struct of_device_id ti_iodelay_of_match[] = { | |
811 | {.compatible = "ti,dra7-iodelay", .data = &dra7_iodelay_data}, | |
812 | { /* Hopefully no more.. */ }, | |
813 | }; | |
814 | MODULE_DEVICE_TABLE(of, ti_iodelay_of_match); | |
815 | ||
816 | /** | |
817 | * ti_iodelay_probe() - Standard probe | |
818 | * @pdev: platform device | |
819 | * | |
820 | * Return: 0 if all went fine, else appropriate error value. | |
821 | */ | |
822 | static int ti_iodelay_probe(struct platform_device *pdev) | |
823 | { | |
824 | struct device *dev = &pdev->dev; | |
825 | struct device_node *np = of_node_get(dev->of_node); | |
826 | const struct of_device_id *match; | |
827 | struct resource *res; | |
828 | struct ti_iodelay_device *iod; | |
829 | int ret = 0; | |
830 | ||
831 | if (!np) { | |
832 | ret = -EINVAL; | |
833 | dev_err(dev, "No OF node\n"); | |
834 | goto exit_out; | |
835 | } | |
836 | ||
837 | match = of_match_device(ti_iodelay_of_match, dev); | |
838 | if (!match) { | |
839 | ret = -EINVAL; | |
840 | dev_err(dev, "No DATA match\n"); | |
841 | goto exit_out; | |
842 | } | |
843 | ||
844 | iod = devm_kzalloc(dev, sizeof(*iod), GFP_KERNEL); | |
845 | if (!iod) { | |
846 | ret = -ENOMEM; | |
847 | goto exit_out; | |
848 | } | |
849 | iod->dev = dev; | |
850 | iod->reg_data = match->data; | |
851 | ||
852 | /* So far We can assume there is only 1 bank of registers */ | |
853 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
854 | if (!res) { | |
855 | dev_err(dev, "Missing MEM resource\n"); | |
856 | ret = -ENODEV; | |
857 | goto exit_out; | |
858 | } | |
859 | ||
860 | iod->phys_base = res->start; | |
861 | iod->reg_base = devm_ioremap_resource(dev, res); | |
862 | if (IS_ERR(iod->reg_base)) { | |
863 | ret = PTR_ERR(iod->reg_base); | |
864 | goto exit_out; | |
865 | } | |
866 | ||
867 | iod->regmap = devm_regmap_init_mmio(dev, iod->reg_base, | |
868 | iod->reg_data->regmap_config); | |
869 | if (IS_ERR(iod->regmap)) { | |
870 | dev_err(dev, "Regmap MMIO init failed.\n"); | |
871 | ret = PTR_ERR(iod->regmap); | |
872 | goto exit_out; | |
873 | } | |
874 | ||
875 | if (ti_iodelay_pinconf_init_dev(iod)) | |
876 | goto exit_out; | |
877 | ||
878 | ret = ti_iodelay_alloc_pins(dev, iod, res->start); | |
879 | if (ret) | |
880 | goto exit_out; | |
881 | ||
882 | iod->desc.pctlops = &ti_iodelay_pinctrl_ops; | |
883 | /* no pinmux ops - we are pinconf */ | |
884 | iod->desc.confops = &ti_iodelay_pinctrl_pinconf_ops; | |
885 | iod->desc.name = dev_name(dev); | |
886 | iod->desc.owner = THIS_MODULE; | |
887 | ||
950b0d91 TL |
888 | ret = pinctrl_register_and_init(&iod->desc, dev, iod, &iod->pctl); |
889 | if (ret) { | |
003910eb | 890 | dev_err(dev, "Failed to register pinctrl\n"); |
003910eb NM |
891 | goto exit_out; |
892 | } | |
893 | ||
894 | platform_set_drvdata(pdev, iod); | |
895 | ||
896 | exit_out: | |
897 | of_node_put(np); | |
898 | return ret; | |
899 | } | |
900 | ||
901 | /** | |
902 | * ti_iodelay_remove() - standard remove | |
903 | * @pdev: platform device | |
904 | * | |
905 | * Return: 0 if all went fine, else appropriate error value. | |
906 | */ | |
907 | static int ti_iodelay_remove(struct platform_device *pdev) | |
908 | { | |
909 | struct ti_iodelay_device *iod = platform_get_drvdata(pdev); | |
910 | ||
911 | if (!iod) | |
912 | return 0; | |
913 | ||
914 | if (iod->pctl) | |
915 | pinctrl_unregister(iod->pctl); | |
916 | ||
917 | ti_iodelay_pinconf_deinit_dev(iod); | |
918 | ||
919 | /* Expect other allocations to be freed by devm */ | |
920 | ||
921 | return 0; | |
922 | } | |
923 | ||
924 | static struct platform_driver ti_iodelay_driver = { | |
925 | .probe = ti_iodelay_probe, | |
926 | .remove = ti_iodelay_remove, | |
927 | .driver = { | |
928 | .owner = THIS_MODULE, | |
929 | .name = DRIVER_NAME, | |
930 | .of_match_table = ti_iodelay_of_match, | |
931 | }, | |
932 | }; | |
933 | module_platform_driver(ti_iodelay_driver); | |
934 | ||
935 | MODULE_AUTHOR("Texas Instruments, Inc."); | |
936 | MODULE_DESCRIPTION("Pinconf driver for TI's IO Delay module"); | |
937 | MODULE_LICENSE("GPL v2"); |