[mirror_ubuntu-focal-kernel.git] / drivers / pinctrl / uniphier / pinctrl-uniphier.h

/*
 * Copyright (C) 2015-2017 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef __PINCTRL_UNIPHIER_H__
#define __PINCTRL_UNIPHIER_H__

#include <linux/bitops.h>
#include <linux/bug.h>
#include <linux/kernel.h>
#include <linux/types.h>

struct platform_device;

/* input enable control register bit */
#define UNIPHIER_PIN_IECTRL_SHIFT	0
#define UNIPHIER_PIN_IECTRL_BITS	3
#define UNIPHIER_PIN_IECTRL_MASK	((1UL << (UNIPHIER_PIN_IECTRL_BITS)) \
					 - 1)

/* drive strength control register number */
#define UNIPHIER_PIN_DRVCTRL_SHIFT	((UNIPHIER_PIN_IECTRL_SHIFT) + \
					(UNIPHIER_PIN_IECTRL_BITS))
#define UNIPHIER_PIN_DRVCTRL_BITS	9
#define UNIPHIER_PIN_DRVCTRL_MASK	((1UL << (UNIPHIER_PIN_DRVCTRL_BITS)) \
					 - 1)

/* drive control type */
#define UNIPHIER_PIN_DRV_TYPE_SHIFT	((UNIPHIER_PIN_DRVCTRL_SHIFT) + \
					 (UNIPHIER_PIN_DRVCTRL_BITS))
#define UNIPHIER_PIN_DRV_TYPE_BITS	3
#define UNIPHIER_PIN_DRV_TYPE_MASK	((1UL << (UNIPHIER_PIN_DRV_TYPE_BITS)) \
					 - 1)

/* pull-up / pull-down register number */
#define UNIPHIER_PIN_PUPDCTRL_SHIFT	((UNIPHIER_PIN_DRV_TYPE_SHIFT) + \
					 (UNIPHIER_PIN_DRV_TYPE_BITS))
#define UNIPHIER_PIN_PUPDCTRL_BITS	9
#define UNIPHIER_PIN_PUPDCTRL_MASK	((1UL << (UNIPHIER_PIN_PUPDCTRL_BITS))\
					 - 1)

/* direction of pull register */
#define UNIPHIER_PIN_PULL_DIR_SHIFT	((UNIPHIER_PIN_PUPDCTRL_SHIFT) + \
					 (UNIPHIER_PIN_PUPDCTRL_BITS))
#define UNIPHIER_PIN_PULL_DIR_BITS	3
#define UNIPHIER_PIN_PULL_DIR_MASK	((1UL << (UNIPHIER_PIN_PULL_DIR_BITS))\
					 - 1)

#if UNIPHIER_PIN_PULL_DIR_SHIFT + UNIPHIER_PIN_PULL_DIR_BITS > BITS_PER_LONG
#error "unable to pack pin attributes."
#endif

#define UNIPHIER_PIN_IECTRL_NONE	(UNIPHIER_PIN_IECTRL_MASK)
#define UNIPHIER_PIN_IECTRL_EXIST	0

/* drive control type */
enum uniphier_pin_drv_type {
	UNIPHIER_PIN_DRV_1BIT,		/* 2 level control: 4/8 mA */
	UNIPHIER_PIN_DRV_2BIT,		/* 4 level control: 8/12/16/20 mA */
	UNIPHIER_PIN_DRV_3BIT,		/* 8 level control: 4/5/7/9/11/12/14/16 mA */
	UNIPHIER_PIN_DRV_FIXED4,	/* fixed to 4mA */
	UNIPHIER_PIN_DRV_FIXED5,	/* fixed to 5mA */
	UNIPHIER_PIN_DRV_FIXED8,	/* fixed to 8mA */
	UNIPHIER_PIN_DRV_NONE,		/* no support (input only pin) */
};

/* direction of pull register (no pin supports bi-directional pull biasing) */
enum uniphier_pin_pull_dir {
	UNIPHIER_PIN_PULL_UP,		/* pull-up or disabled */
	UNIPHIER_PIN_PULL_DOWN,		/* pull-down or disabled */
	UNIPHIER_PIN_PULL_UP_FIXED,	/* always pull-up */
	UNIPHIER_PIN_PULL_DOWN_FIXED,	/* always pull-down */
	UNIPHIER_PIN_PULL_NONE,		/* no pull register */
};

#define UNIPHIER_PIN_IECTRL(x) \
	(((x) & (UNIPHIER_PIN_IECTRL_MASK)) << (UNIPHIER_PIN_IECTRL_SHIFT))
#define UNIPHIER_PIN_DRVCTRL(x) \
	(((x) & (UNIPHIER_PIN_DRVCTRL_MASK)) << (UNIPHIER_PIN_DRVCTRL_SHIFT))
#define UNIPHIER_PIN_DRV_TYPE(x) \
	(((x) & (UNIPHIER_PIN_DRV_TYPE_MASK)) << (UNIPHIER_PIN_DRV_TYPE_SHIFT))
#define UNIPHIER_PIN_PUPDCTRL(x) \
	(((x) & (UNIPHIER_PIN_PUPDCTRL_MASK)) << (UNIPHIER_PIN_PUPDCTRL_SHIFT))
#define UNIPHIER_PIN_PULL_DIR(x) \
	(((x) & (UNIPHIER_PIN_PULL_DIR_MASK)) << (UNIPHIER_PIN_PULL_DIR_SHIFT))

#define UNIPHIER_PIN_ATTR_PACKED(iectrl, drvctrl, drv_type, pupdctrl, pull_dir)\
				(UNIPHIER_PIN_IECTRL(iectrl) |		\
				 UNIPHIER_PIN_DRVCTRL(drvctrl) |	\
				 UNIPHIER_PIN_DRV_TYPE(drv_type) |	\
				 UNIPHIER_PIN_PUPDCTRL(pupdctrl) |	\
				 UNIPHIER_PIN_PULL_DIR(pull_dir))

static inline unsigned int uniphier_pin_get_iectrl(void *drv_data)
{
	return ((unsigned long)drv_data >> UNIPHIER_PIN_IECTRL_SHIFT) &
						UNIPHIER_PIN_IECTRL_MASK;
}

static inline unsigned int uniphier_pin_get_drvctrl(void *drv_data)
{
	return ((unsigned long)drv_data >> UNIPHIER_PIN_DRVCTRL_SHIFT) &
						UNIPHIER_PIN_DRVCTRL_MASK;
}

static inline unsigned int uniphier_pin_get_drv_type(void *drv_data)
{
	return ((unsigned long)drv_data >> UNIPHIER_PIN_DRV_TYPE_SHIFT) &
						UNIPHIER_PIN_DRV_TYPE_MASK;
}

static inline unsigned int uniphier_pin_get_pupdctrl(void *drv_data)
{
	return ((unsigned long)drv_data >> UNIPHIER_PIN_PUPDCTRL_SHIFT) &
						UNIPHIER_PIN_PUPDCTRL_MASK;
}

static inline unsigned int uniphier_pin_get_pull_dir(void *drv_data)
{
	return ((unsigned long)drv_data >> UNIPHIER_PIN_PULL_DIR_SHIFT) &
						UNIPHIER_PIN_PULL_DIR_MASK;
}

struct uniphier_pinctrl_group {
	const char *name;
	const unsigned *pins;
	unsigned num_pins;
	const int *muxvals;
};

struct uniphier_pinmux_function {
	const char *name;
	const char * const *groups;
	unsigned num_groups;
};

struct uniphier_pinctrl_socdata {
	const struct pinctrl_pin_desc *pins;
	unsigned int npins;
	const struct uniphier_pinctrl_group *groups;
	int groups_count;
	const struct uniphier_pinmux_function *functions;
	int functions_count;
	int (*get_gpio_muxval)(unsigned int pin, unsigned int gpio_offset);
	unsigned int caps;
#define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL	BIT(1)
#define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE	BIT(0)
};

#define UNIPHIER_PINCTRL_PIN(a, b, c, d, e, f, g)			\
{									\
	.number = a,							\
	.name = b,							\
	.drv_data = (void *)UNIPHIER_PIN_ATTR_PACKED(c, d, e, f, g),	\
}

#define __UNIPHIER_PINCTRL_GROUP(grp, mux)				\
	{								\
		.name = #grp,						\
		.pins = grp##_pins,					\
		.num_pins = ARRAY_SIZE(grp##_pins),			\
		.muxvals = mux,						\
	}

#define UNIPHIER_PINCTRL_GROUP(grp)					\
	__UNIPHIER_PINCTRL_GROUP(grp,					\
			grp##_muxvals +					\
			BUILD_BUG_ON_ZERO(ARRAY_SIZE(grp##_pins) !=	\
					  ARRAY_SIZE(grp##_muxvals)))

#define UNIPHIER_PINCTRL_GROUP_GPIO(grp)				\
	__UNIPHIER_PINCTRL_GROUP(grp, NULL)

#define UNIPHIER_PINMUX_FUNCTION(func)					\
	{								\
		.name = #func,						\
		.groups = func##_groups,				\
		.num_groups = ARRAY_SIZE(func##_groups),		\
	}

int uniphier_pinctrl_probe(struct platform_device *pdev,
			   struct uniphier_pinctrl_socdata *socdata);

extern const struct dev_pm_ops uniphier_pinctrl_pm_ops;

#endif /* __PINCTRL_UNIPHIER_H__ */
Commit	Line	Data
6e908892	1	/*
8ef364b3 MY	2	* Copyright (C) 2015-2017 Socionext Inc.
8ef364b3 MY	3	* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6e908892 MY	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#ifndef __PINCTRL_UNIPHIER_H__
	17	#define __PINCTRL_UNIPHIER_H__
	18
c2ebf475	19	#include <linux/bitops.h>
6e908892 MY	20	#include <linux/bug.h>
	21	#include <linux/kernel.h>
	22	#include <linux/types.h>
	23
fc78a566 MY	24	struct platform_device;
fc78a566 MY	25
6e908892 MY	26	/* input enable control register bit */
6e908892 MY	27	#define UNIPHIER_PIN_IECTRL_SHIFT 0
4e767983	28	#define UNIPHIER_PIN_IECTRL_BITS 3
6e908892 MY	29	#define UNIPHIER_PIN_IECTRL_MASK ((1UL << (UNIPHIER_PIN_IECTRL_BITS)) \
	30	- 1)
	31
	32	/* drive strength control register number */
	33	#define UNIPHIER_PIN_DRVCTRL_SHIFT ((UNIPHIER_PIN_IECTRL_SHIFT) + \
	34	(UNIPHIER_PIN_IECTRL_BITS))
	35	#define UNIPHIER_PIN_DRVCTRL_BITS 9
	36	#define UNIPHIER_PIN_DRVCTRL_MASK ((1UL << (UNIPHIER_PIN_DRVCTRL_BITS)) \
	37	- 1)
	38
9eaa98a6 MY	39	/* drive control type */
9eaa98a6 MY	40	#define UNIPHIER_PIN_DRV_TYPE_SHIFT ((UNIPHIER_PIN_DRVCTRL_SHIFT) + \
6e908892	41	(UNIPHIER_PIN_DRVCTRL_BITS))
9eaa98a6 MY	42	#define UNIPHIER_PIN_DRV_TYPE_BITS 3
9eaa98a6 MY	43	#define UNIPHIER_PIN_DRV_TYPE_MASK ((1UL << (UNIPHIER_PIN_DRV_TYPE_BITS)) \
6e908892 MY	44	- 1)
	45
	46	/* pull-up / pull-down register number */
9eaa98a6 MY	47	#define UNIPHIER_PIN_PUPDCTRL_SHIFT ((UNIPHIER_PIN_DRV_TYPE_SHIFT) + \
9eaa98a6 MY	48	(UNIPHIER_PIN_DRV_TYPE_BITS))
6e908892 MY	49	#define UNIPHIER_PIN_PUPDCTRL_BITS 9
	50	#define UNIPHIER_PIN_PUPDCTRL_MASK ((1UL << (UNIPHIER_PIN_PUPDCTRL_BITS))\
	51	- 1)
	52
	53	/* direction of pull register */
	54	#define UNIPHIER_PIN_PULL_DIR_SHIFT ((UNIPHIER_PIN_PUPDCTRL_SHIFT) + \
	55	(UNIPHIER_PIN_PUPDCTRL_BITS))
	56	#define UNIPHIER_PIN_PULL_DIR_BITS 3
	57	#define UNIPHIER_PIN_PULL_DIR_MASK ((1UL << (UNIPHIER_PIN_PULL_DIR_BITS))\
	58	- 1)
	59
	60	#if UNIPHIER_PIN_PULL_DIR_SHIFT + UNIPHIER_PIN_PULL_DIR_BITS > BITS_PER_LONG
	61	#error "unable to pack pin attributes."
	62	#endif
	63
	64	#define UNIPHIER_PIN_IECTRL_NONE (UNIPHIER_PIN_IECTRL_MASK)
4e767983	65	#define UNIPHIER_PIN_IECTRL_EXIST 0
6e908892	66
9eaa98a6 MY	67	/* drive control type */
	68	enum uniphier_pin_drv_type {
	69	UNIPHIER_PIN_DRV_1BIT, /* 2 level control: 4/8 mA */
	70	UNIPHIER_PIN_DRV_2BIT, /* 4 level control: 8/12/16/20 mA */
72e5706a	71	UNIPHIER_PIN_DRV_3BIT, /* 8 level control: 4/5/7/9/11/12/14/16 mA */
9eaa98a6 MY	72	UNIPHIER_PIN_DRV_FIXED4, /* fixed to 4mA */
	73	UNIPHIER_PIN_DRV_FIXED5, /* fixed to 5mA */
	74	UNIPHIER_PIN_DRV_FIXED8, /* fixed to 8mA */
6e908892 MY	75	UNIPHIER_PIN_DRV_NONE, /* no support (input only pin) */
	76	};
	77
	78	/* direction of pull register (no pin supports bi-directional pull biasing) */
	79	enum uniphier_pin_pull_dir {
	80	UNIPHIER_PIN_PULL_UP, /* pull-up or disabled */
	81	UNIPHIER_PIN_PULL_DOWN, /* pull-down or disabled */
	82	UNIPHIER_PIN_PULL_UP_FIXED, /* always pull-up */
	83	UNIPHIER_PIN_PULL_DOWN_FIXED, /* always pull-down */
	84	UNIPHIER_PIN_PULL_NONE, /* no pull register */
	85	};
	86
	87	#define UNIPHIER_PIN_IECTRL(x) \
	88	(((x) & (UNIPHIER_PIN_IECTRL_MASK)) << (UNIPHIER_PIN_IECTRL_SHIFT))
	89	#define UNIPHIER_PIN_DRVCTRL(x) \
	90	(((x) & (UNIPHIER_PIN_DRVCTRL_MASK)) << (UNIPHIER_PIN_DRVCTRL_SHIFT))
9eaa98a6 MY	91	#define UNIPHIER_PIN_DRV_TYPE(x) \
9eaa98a6 MY	92	(((x) & (UNIPHIER_PIN_DRV_TYPE_MASK)) << (UNIPHIER_PIN_DRV_TYPE_SHIFT))
6e908892 MY	93	#define UNIPHIER_PIN_PUPDCTRL(x) \
	94	(((x) & (UNIPHIER_PIN_PUPDCTRL_MASK)) << (UNIPHIER_PIN_PUPDCTRL_SHIFT))
	95	#define UNIPHIER_PIN_PULL_DIR(x) \
	96	(((x) & (UNIPHIER_PIN_PULL_DIR_MASK)) << (UNIPHIER_PIN_PULL_DIR_SHIFT))
	97
9eaa98a6	98	#define UNIPHIER_PIN_ATTR_PACKED(iectrl, drvctrl, drv_type, pupdctrl, pull_dir)\
6e908892 MY	99	(UNIPHIER_PIN_IECTRL(iectrl) \| \
6e908892 MY	100	UNIPHIER_PIN_DRVCTRL(drvctrl) \| \
9eaa98a6	101	UNIPHIER_PIN_DRV_TYPE(drv_type) \| \
6e908892 MY	102	UNIPHIER_PIN_PUPDCTRL(pupdctrl) \| \
	103	UNIPHIER_PIN_PULL_DIR(pull_dir))
	104
	105	static inline unsigned int uniphier_pin_get_iectrl(void *drv_data)
	106	{
	107	return ((unsigned long)drv_data >> UNIPHIER_PIN_IECTRL_SHIFT) &
	108	UNIPHIER_PIN_IECTRL_MASK;
	109	}
	110
	111	static inline unsigned int uniphier_pin_get_drvctrl(void *drv_data)
	112	{
	113	return ((unsigned long)drv_data >> UNIPHIER_PIN_DRVCTRL_SHIFT) &
	114	UNIPHIER_PIN_DRVCTRL_MASK;
	115	}
	116
9eaa98a6	117	static inline unsigned int uniphier_pin_get_drv_type(void *drv_data)
6e908892	118	{
9eaa98a6 MY	119	return ((unsigned long)drv_data >> UNIPHIER_PIN_DRV_TYPE_SHIFT) &
9eaa98a6 MY	120	UNIPHIER_PIN_DRV_TYPE_MASK;
6e908892 MY	121	}
	122
	123	static inline unsigned int uniphier_pin_get_pupdctrl(void *drv_data)
	124	{
	125	return ((unsigned long)drv_data >> UNIPHIER_PIN_PUPDCTRL_SHIFT) &
	126	UNIPHIER_PIN_PUPDCTRL_MASK;
	127	}
	128
	129	static inline unsigned int uniphier_pin_get_pull_dir(void *drv_data)
	130	{
	131	return ((unsigned long)drv_data >> UNIPHIER_PIN_PULL_DIR_SHIFT) &
	132	UNIPHIER_PIN_PULL_DIR_MASK;
	133	}
	134
6e908892 MY	135	struct uniphier_pinctrl_group {
	136	const char *name;
	137	const unsigned *pins;
	138	unsigned num_pins;
39ec9ace	139	const int *muxvals;
6e908892 MY	140	};
	141
	142	struct uniphier_pinmux_function {
	143	const char *name;
	144	const char * const *groups;
	145	unsigned num_groups;
	146	};
	147
	148	struct uniphier_pinctrl_socdata {
fc78a566 MY	149	const struct pinctrl_pin_desc *pins;
fc78a566 MY	150	unsigned int npins;
6e908892 MY	151	const struct uniphier_pinctrl_group *groups;
	152	int groups_count;
	153	const struct uniphier_pinmux_function *functions;
	154	int functions_count;
7f6ee0a5	155	int (*get_gpio_muxval)(unsigned int pin, unsigned int gpio_offset);
c2ebf475	156	unsigned int caps;
aa543888	157	#define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL BIT(1)
c2ebf475	158	#define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(0)
6e908892 MY	159	};
	160
	161	#define UNIPHIER_PINCTRL_PIN(a, b, c, d, e, f, g) \
	162	{ \
	163	.number = a, \
	164	.name = b, \
	165	.drv_data = (void *)UNIPHIER_PIN_ATTR_PACKED(c, d, e, f, g), \
	166	}
	167
7f6ee0a5	168	#define __UNIPHIER_PINCTRL_GROUP(grp, mux) \
6e908892 MY	169	{ \
	170	.name = #grp, \
	171	.pins = grp##_pins, \
	172	.num_pins = ARRAY_SIZE(grp##_pins), \
7f6ee0a5	173	.muxvals = mux, \
6e908892 MY	174	}
	175
	176	#define UNIPHIER_PINCTRL_GROUP(grp) \
7f6ee0a5 MY	177	__UNIPHIER_PINCTRL_GROUP(grp, \
	178	grp##_muxvals + \
	179	BUILD_BUG_ON_ZERO(ARRAY_SIZE(grp##_pins) != \
	180	ARRAY_SIZE(grp##_muxvals)))
6e908892	181
7f6ee0a5 MY	182	#define UNIPHIER_PINCTRL_GROUP_GPIO(grp) \
7f6ee0a5 MY	183	__UNIPHIER_PINCTRL_GROUP(grp, NULL)
6e908892 MY	184
	185	#define UNIPHIER_PINMUX_FUNCTION(func) \
	186	{ \
	187	.name = #func, \
	188	.groups = func##_groups, \
	189	.num_groups = ARRAY_SIZE(func##_groups), \
	190	}
	191
6e908892	192	int uniphier_pinctrl_probe(struct platform_device *pdev,
6e908892 MY	193	struct uniphier_pinctrl_socdata *socdata);
6e908892 MY	194
9697509e MY	195	extern const struct dev_pm_ops uniphier_pinctrl_pm_ops;
9697509e MY	196
6e908892	197	#endif /* __PINCTRL_UNIPHIER_H__ */