]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - drivers/pinctrl/zte/pinctrl-zx296718.c
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 499
[mirror_ubuntu-hirsute-kernel.git] / drivers / pinctrl / zte / pinctrl-zx296718.c
CommitLineData
cbff0c4d
SG		 1/*
2 * Copyright (C) 2017 Sanechips Technology Co., Ltd.
3 * Copyright 2017 Linaro Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/of_address.h>
13#include <linux/of_device.h>
14#include <linux/pinctrl/pinctrl.h>
15#include <linux/platform_device.h>
16
17#include "pinctrl-zx.h"
18
19#define TOP_REG0 0x00
20#define TOP_REG1 0x04
21#define TOP_REG2 0x08
22#define TOP_REG3 0x0c
23#define TOP_REG4 0x10
24#define TOP_REG5 0x14
25#define TOP_REG6 0x18
26#define TOP_REG7 0x1c
27#define TOP_REG8 0x20
28
29/*
30 * The pin numbering starts from AON pins with reserved ones included,
31 * so that register data like offset and bit position for AON pins can
32 * be calculated from pin number.
33 */
34enum zx296718_pin {
35 /* aon_pmm_reg_0 */
36 I2C3_SCL = 0,
37 I2C3_SDA = 1,
38 AON_RESERVED0 = 2,
39 AON_RESERVED1 = 3,
40 SEC_EN = 4,
41 UART0_RXD = 5,
42 UART0_TXD = 6,
43 IR_IN = 7,
44 SPI0_CLK = 8,
45 SPI0_CS = 9,
46 SPI0_TXD = 10,
47 SPI0_RXD = 11,
48 KEY_COL0 = 12,
49 KEY_COL1 = 13,
50 KEY_COL2 = 14,
51 KEY_ROW0 = 15,
52
53 /* aon_pmm_reg_1 */
54 KEY_ROW1 = 16,
55 KEY_ROW2 = 17,
56 HDMI_SCL = 18,
57 HDMI_SDA = 19,
58 JTAG_TCK = 20,
59 JTAG_TRSTN = 21,
60 JTAG_TMS = 22,
61 JTAG_TDI = 23,
62 JTAG_TDO = 24,
63 I2C0_SCL = 25,
64 I2C0_SDA = 26,
65 I2C1_SCL = 27,
66 I2C1_SDA = 28,
67 AON_RESERVED2 = 29,
68 AON_RESERVED3 = 30,
69 AON_RESERVED4 = 31,
70
71 /* aon_pmm_reg_2 */
72 SPI1_CLK = 32,
73 SPI1_CS = 33,
74 SPI1_TXD = 34,
75 SPI1_RXD = 35,
76 AON_RESERVED5 = 36,
77 AON_RESERVED6 = 37,
78 AUDIO_DET = 38,
79 SPDIF_OUT = 39,
80 HDMI_CEC = 40,
81 HDMI_HPD = 41,
82 GMAC_25M_OUT = 42,
83 BOOT_SEL0 = 43,
84 BOOT_SEL1 = 44,
85 BOOT_SEL2 = 45,
86 DEEP_SLEEP_OUT_N = 46,
87 AON_RESERVED7 = 47,
88
89 /* top_pmm_reg_0 */
90 GMII_GTX_CLK = 48,
91 GMII_TX_CLK = 49,
92 GMII_TXD0 = 50,
93 GMII_TXD1 = 51,
94 GMII_TXD2 = 52,
95 GMII_TXD3 = 53,
96 GMII_TXD4 = 54,
97 GMII_TXD5 = 55,
98 GMII_TXD6 = 56,
99 GMII_TXD7 = 57,
100 GMII_TX_ER = 58,
101 GMII_TX_EN = 59,
102 GMII_RX_CLK = 60,
103 GMII_RXD0 = 61,
104 GMII_RXD1 = 62,
105 GMII_RXD2 = 63,
106
107 /* top_pmm_reg_1 */
108 GMII_RXD3 = 64,
109 GMII_RXD4 = 65,
110 GMII_RXD5 = 66,
111 GMII_RXD6 = 67,
112 GMII_RXD7 = 68,
113 GMII_RX_ER = 69,
114 GMII_RX_DV = 70,
115 GMII_COL = 71,
116 GMII_CRS = 72,
117 GMII_MDC = 73,
118 GMII_MDIO = 74,
119 SDIO1_CLK = 75,
120 SDIO1_CMD = 76,
121 SDIO1_DATA0 = 77,
122 SDIO1_DATA1 = 78,
123 SDIO1_DATA2 = 79,
124
125 /* top_pmm_reg_2 */
126 SDIO1_DATA3 = 80,
127 SDIO1_CD = 81,
128 SDIO1_WP = 82,
129 USIM1_CD = 83,
130 USIM1_CLK = 84,
131 USIM1_RST = 85,
132
133 /* top_pmm_reg_3 */
134 USIM1_DATA = 86,
135 SDIO0_CLK = 87,
136 SDIO0_CMD = 88,
137 SDIO0_DATA0 = 89,
138 SDIO0_DATA1 = 90,
139 SDIO0_DATA2 = 91,
140 SDIO0_DATA3 = 92,
141 SDIO0_CD = 93,
142 SDIO0_WP = 94,
143
144 /* top_pmm_reg_4 */
145 TSI0_DATA0 = 95,
146 SPINOR_CLK = 96,
147 TSI2_DATA = 97,
148 TSI2_CLK = 98,
149 TSI2_SYNC = 99,
150 TSI2_VALID = 100,
151 SPINOR_CS = 101,
152 SPINOR_DQ0 = 102,
153 SPINOR_DQ1 = 103,
154 SPINOR_DQ2 = 104,
155 SPINOR_DQ3 = 105,
156 VGA_HS = 106,
157 VGA_VS = 107,
158 TSI3_DATA = 108,
159
160 /* top_pmm_reg_5 */
161 TSI3_CLK = 109,
162 TSI3_SYNC = 110,
163 TSI3_VALID = 111,
164 I2S1_WS = 112,
165 I2S1_BCLK = 113,
166 I2S1_MCLK = 114,
167 I2S1_DIN0 = 115,
168 I2S1_DOUT0 = 116,
169 SPI3_CLK = 117,
170 SPI3_CS = 118,
171 SPI3_TXD = 119,
172 NAND_LDO_MS18_SEL = 120,
173
174 /* top_pmm_reg_6 */
175 SPI3_RXD = 121,
176 I2S0_MCLK = 122,
177 I2S0_BCLK = 123,
178 I2S0_WS = 124,
179 I2S0_DIN0 = 125,
180 I2S0_DOUT0 = 126,
181 I2C5_SCL = 127,
182 I2C5_SDA = 128,
183 SPI2_CLK = 129,
184 SPI2_CS = 130,
185 SPI2_TXD = 131,
186
187 /* top_pmm_reg_7 */
188 SPI2_RXD = 132,
189 NAND_WP_N = 133,
190 NAND_PAGE_SIZE0 = 134,
191 NAND_PAGE_SIZE1 = 135,
192 NAND_ADDR_CYCLE = 136,
193 NAND_RB0 = 137,
194 NAND_RB1 = 138,
195 NAND_RB2 = 139,
196 NAND_RB3 = 140,
197
198 /* top_pmm_reg_8 */
199 GMAC_125M_IN = 141,
200 GMAC_50M_OUT = 142,
201 SPINOR_SSCLK_LOOPBACK = 143,
202 SPINOR_SDIO1CLK_LOOPBACK = 144,
203};
204
205static const struct pinctrl_pin_desc zx296718_pins[] = {
206 /* aon_pmm_reg_0 */
207 AON_PIN(I2C3_SCL, TOP_REG2, 18, 2, 0x48, 0,
208 AON_MUX(0x0, "ANMI"), /* anmi */
209 AON_MUX(0x1, "AGPIO"), /* agpio29 */
210 AON_MUX(0x2, "nonAON"), /* pin0 */
211 AON_MUX(0x3, "EXT_INT"), /* int4 */
212 TOP_MUX(0x0, "I2C3"), /* scl */
213 TOP_MUX(0x1, "SPI2"), /* txd */
214 TOP_MUX(0x2, "I2S1")), /* din0 */
215 AON_PIN(I2C3_SDA, TOP_REG2, 20, 2, 0x48, 9,
216 AON_MUX(0x0, "WD"), /* rst_b */
217 AON_MUX(0x1, "AGPIO"), /* agpio30 */
218 AON_MUX(0x2, "nonAON"), /* pin1 */
219 AON_MUX(0x3, "EXT_INT"), /* int5 */
220 TOP_MUX(0x0, "I2C3"), /* sda */
221 TOP_MUX(0x1, "SPI2"), /* rxd */
222 TOP_MUX(0x2, "I2S0")), /* mclk */
223 ZX_RESERVED(AON_RESERVED0),
224 ZX_RESERVED(AON_RESERVED1),
225 AON_PIN(SEC_EN, TOP_REG3, 5, 1, 0x50, 0,
226 AON_MUX(0x0, "SEC"), /* en */
227 AON_MUX(0x1, "AGPIO"), /* agpio28 */
228 AON_MUX(0x2, "nonAON"), /* pin3 */
229 AON_MUX(0x3, "EXT_INT"), /* int7 */
230 TOP_MUX(0x0, "I2C2"), /* sda */
231 TOP_MUX(0x1, "SPI2")), /* cs */
232 AON_PIN(UART0_RXD, 0, 0, 0, 0x50, 9,
233 AON_MUX(0x0, "UART0"), /* rxd */
234 AON_MUX(0x1, "AGPIO"), /* agpio20 */
235 AON_MUX(0x2, "nonAON")), /* pin34 */
236 AON_PIN(UART0_TXD, 0, 0, 0, 0x50, 18,
237 AON_MUX(0x0, "UART0"), /* txd */
238 AON_MUX(0x1, "AGPIO"), /* agpio21 */
239 AON_MUX(0x2, "nonAON")), /* pin32 */
240 AON_PIN(IR_IN, 0, 0, 0, 0x64, 0,
241 AON_MUX(0x0, "IR"), /* in */
242 AON_MUX(0x1, "AGPIO"), /* agpio0 */
243 AON_MUX(0x2, "nonAON")), /* pin27 */
244 AON_PIN(SPI0_CLK, TOP_REG3, 16, 1, 0x64, 9,
245 AON_MUX(0x0, "EXT_INT"), /* int0 */
246 AON_MUX(0x1, "AGPIO"), /* agpio23 */
247 AON_MUX(0x2, "nonAON"), /* pin5 */
248 AON_MUX(0x3, "PCU"), /* test6 */
249 TOP_MUX(0x0, "SPI0"), /* clk */
250 TOP_MUX(0x1, "ISP")), /* flash_trig */
251 AON_PIN(SPI0_CS, TOP_REG3, 17, 1, 0x64, 18,
252 AON_MUX(0x0, "EXT_INT"), /* int1 */
253 AON_MUX(0x1, "AGPIO"), /* agpio24 */
254 AON_MUX(0x2, "nonAON"), /* pin6 */
255 AON_MUX(0x3, "PCU"), /* test0 */
256 TOP_MUX(0x0, "SPI0"), /* cs */
257 TOP_MUX(0x1, "ISP")), /* prelight_trig */
258 AON_PIN(SPI0_TXD, TOP_REG3, 18, 1, 0x68, 0,
259 AON_MUX(0x0, "EXT_INT"), /* int2 */
260 AON_MUX(0x1, "AGPIO"), /* agpio25 */
261 AON_MUX(0x2, "nonAON"), /* pin7 */
262 AON_MUX(0x3, "PCU"), /* test1 */
263 TOP_MUX(0x0, "SPI0"), /* txd */
264 TOP_MUX(0x1, "ISP")), /* shutter_trig */
265 AON_PIN(SPI0_RXD, TOP_REG3, 19, 1, 0x68, 9,
266 AON_MUX(0x0, "EXT_INT"), /* int3 */
267 AON_MUX(0x1, "AGPIO"), /* agpio26 */
268 AON_MUX(0x2, "nonAON"), /* pin8 */
269 AON_MUX(0x3, "PCU"), /* test2 */
270 TOP_MUX(0x0, "SPI0"), /* rxd */
271 TOP_MUX(0x1, "ISP")), /* shutter_open */
272 AON_PIN(KEY_COL0, TOP_REG3, 20, 1, 0x68, 18,
273 AON_MUX(0x0, "KEY"), /* col0 */
274 AON_MUX(0x1, "AGPIO"), /* agpio5 */
275 AON_MUX(0x2, "nonAON"), /* pin9 */
276 AON_MUX(0x3, "PCU"), /* test3 */
277 TOP_MUX(0x0, "UART3"), /* rxd */
278 TOP_MUX(0x1, "I2S0")), /* din1 */
279 AON_PIN(KEY_COL1, TOP_REG3, 21, 2, 0x6c, 0,
280 AON_MUX(0x0, "KEY"), /* col1 */
281 AON_MUX(0x1, "AGPIO"), /* agpio6 */
282 AON_MUX(0x2, "nonAON"), /* pin10 */
283 TOP_MUX(0x0, "UART3"), /* txd */
284 TOP_MUX(0x1, "I2S0"), /* din2 */
285 TOP_MUX(0x2, "VGA")), /* scl */
286 AON_PIN(KEY_COL2, TOP_REG3, 23, 2, 0x6c, 9,
287 AON_MUX(0x0, "KEY"), /* col2 */
288 AON_MUX(0x1, "AGPIO"), /* agpio7 */
289 AON_MUX(0x2, "nonAON"), /* pin11 */
290 TOP_MUX(0x0, "PWM"), /* out1 */
291 TOP_MUX(0x1, "I2S0"), /* din3 */
292 TOP_MUX(0x2, "VGA")), /* sda */
293 AON_PIN(KEY_ROW0, 0, 0, 0, 0x6c, 18,
294 AON_MUX(0x0, "KEY"), /* row0 */
295 AON_MUX(0x1, "AGPIO"), /* agpio8 */
296 AON_MUX(0x2, "nonAON"), /* pin33 */
297 AON_MUX(0x3, "WD")), /* rst_b */
298
299 /* aon_pmm_reg_1 */
300 AON_PIN(KEY_ROW1, TOP_REG3, 25, 2, 0x70, 0,
301 AON_MUX(0x0, "KEY"), /* row1 */
302 AON_MUX(0x1, "AGPIO"), /* agpio9 */
303 AON_MUX(0x2, "nonAON"), /* pin12 */
304 TOP_MUX(0x0, "LCD"), /* port0 lcd_te */
305 TOP_MUX(0x1, "I2S0"), /* dout2 */
306 TOP_MUX(0x2, "PWM"), /* out2 */
307 TOP_MUX(0x3, "VGA")), /* hs1 */
308 AON_PIN(KEY_ROW2, TOP_REG3, 27, 2, 0x70, 9,
309 AON_MUX(0x0, "KEY"), /* row2 */
310 AON_MUX(0x1, "AGPIO"), /* agpio10 */
311 AON_MUX(0x2, "nonAON"), /* pin13 */
312 TOP_MUX(0x0, "LCD"), /* port1 lcd_te */
313 TOP_MUX(0x1, "I2S0"), /* dout3 */
314 TOP_MUX(0x2, "PWM"), /* out3 */
315 TOP_MUX(0x3, "VGA")), /* vs1 */
316 AON_PIN(HDMI_SCL, TOP_REG3, 29, 1, 0x70, 18,
317 AON_MUX(0x0, "PCU"), /* test7 */
318 AON_MUX(0x1, "AGPIO"), /* agpio3 */
319 AON_MUX(0x2, "nonAON"), /* pin14 */
320 TOP_MUX(0x0, "HDMI"), /* scl */
321 TOP_MUX(0x1, "UART3")), /* rxd */
322 AON_PIN(HDMI_SDA, TOP_REG3, 30, 1, 0x74, 0,
323 AON_MUX(0x0, "PCU"), /* test8 */
324 AON_MUX(0x1, "AGPIO"), /* agpio4 */
325 AON_MUX(0x2, "nonAON"), /* pin15 */
326 TOP_MUX(0x0, "HDMI"), /* sda */
327 TOP_MUX(0x1, "UART3")), /* txd */
328 AON_PIN(JTAG_TCK, TOP_REG7, 3, 1, 0x78, 18,
329 AON_MUX(0x0, "JTAG"), /* tck */
330 AON_MUX(0x1, "AGPIO"), /* agpio11 */
331 AON_MUX(0x2, "nonAON"), /* pin22 */
332 AON_MUX(0x3, "EXT_INT"), /* int4 */
333 TOP_MUX(0x0, "SPI4"), /* clk */
334 TOP_MUX(0x1, "UART1")), /* rxd */
335 AON_PIN(JTAG_TRSTN, TOP_REG7, 4, 1, 0xac, 0,
336 AON_MUX(0x0, "JTAG"), /* trstn */
337 AON_MUX(0x1, "AGPIO"), /* agpio12 */
338 AON_MUX(0x2, "nonAON"), /* pin23 */
339 AON_MUX(0x3, "EXT_INT"), /* int5 */
340 TOP_MUX(0x0, "SPI4"), /* cs */
341 TOP_MUX(0x1, "UART1")), /* txd */
342 AON_PIN(JTAG_TMS, TOP_REG7, 5, 1, 0xac, 9,
343 AON_MUX(0x0, "JTAG"), /* tms */
344 AON_MUX(0x1, "AGPIO"), /* agpio13 */
345 AON_MUX(0x2, "nonAON"), /* pin24 */
346 AON_MUX(0x3, "EXT_INT"), /* int6 */
347 TOP_MUX(0x0, "SPI4"), /* txd */
348 TOP_MUX(0x1, "UART2")), /* rxd */
349 AON_PIN(JTAG_TDI, TOP_REG7, 6, 1, 0xac, 18,
350 AON_MUX(0x0, "JTAG"), /* tdi */
351 AON_MUX(0x1, "AGPIO"), /* agpio14 */
352 AON_MUX(0x2, "nonAON"), /* pin25 */
353 AON_MUX(0x3, "EXT_INT"), /* int7 */
354 TOP_MUX(0x0, "SPI4"), /* rxd */
355 TOP_MUX(0x1, "UART2")), /* txd */
356 AON_PIN(JTAG_TDO, 0, 0, 0, 0xb0, 0,
357 AON_MUX(0x0, "JTAG"), /* tdo */
358 AON_MUX(0x1, "AGPIO"), /* agpio15 */
359 AON_MUX(0x2, "nonAON")), /* pin26 */
360 AON_PIN(I2C0_SCL, 0, 0, 0, 0xb0, 9,
361 AON_MUX(0x0, "I2C0"), /* scl */
362 AON_MUX(0x1, "AGPIO"), /* agpio16 */
363 AON_MUX(0x2, "nonAON")), /* pin28 */
364 AON_PIN(I2C0_SDA, 0, 0, 0, 0xb0, 18,
365 AON_MUX(0x0, "I2C0"), /* sda */
366 AON_MUX(0x1, "AGPIO"), /* agpio17 */
367 AON_MUX(0x2, "nonAON")), /* pin29 */
368 AON_PIN(I2C1_SCL, TOP_REG8, 4, 1, 0xb4, 0,
369 AON_MUX(0x0, "I2C1"), /* scl */
370 AON_MUX(0x1, "AGPIO"), /* agpio18 */
371 AON_MUX(0x2, "nonAON"), /* pin30 */
372 TOP_MUX(0x0, "LCD")), /* port0 lcd_te */
373 AON_PIN(I2C1_SDA, TOP_REG8, 5, 1, 0xb4, 9,
374 AON_MUX(0x0, "I2C1"), /* sda */
375 AON_MUX(0x1, "AGPIO"), /* agpio19 */
376 AON_MUX(0x2, "nonAON"), /* pin31 */
377 TOP_MUX(0x0, "LCD")), /* port1 lcd_te */
378 ZX_RESERVED(AON_RESERVED2),
379 ZX_RESERVED(AON_RESERVED3),
380 ZX_RESERVED(AON_RESERVED4),
381
382 /* aon_pmm_reg_2 */
383 AON_PIN(SPI1_CLK, TOP_REG2, 6, 3, 0x40, 9,
384 AON_MUX(0x0, "EXT_INT"), /* int0 */
385 AON_MUX(0x1, "PCU"), /* test12 */
386 AON_MUX(0x2, "nonAON"), /* pin39 */
387 TOP_MUX(0x0, "SPI1"), /* clk */
388 TOP_MUX(0x1, "PCM"), /* clk */
389 TOP_MUX(0x2, "BGPIO"), /* gpio35 */
390 TOP_MUX(0x3, "I2C4"), /* scl */
391 TOP_MUX(0x4, "I2S1"), /* mclk */
392 TOP_MUX(0x5, "ISP")), /* flash_trig */
393 AON_PIN(SPI1_CS, TOP_REG2, 9, 3, 0x40, 18,
394 AON_MUX(0x0, "EXT_INT"), /* int1 */
395 AON_MUX(0x1, "PCU"), /* test13 */
396 AON_MUX(0x2, "nonAON"), /* pin40 */
397 TOP_MUX(0x0, "SPI1"), /* cs */
398 TOP_MUX(0x1, "PCM"), /* fs */
399 TOP_MUX(0x2, "BGPIO"), /* gpio36 */
400 TOP_MUX(0x3, "I2C4"), /* sda */
401 TOP_MUX(0x4, "I2S1"), /* bclk */
402 TOP_MUX(0x5, "ISP")), /* prelight_trig */
403 AON_PIN(SPI1_TXD, TOP_REG2, 12, 3, 0x44, 0,
404 AON_MUX(0x0, "EXT_INT"), /* int2 */
405 AON_MUX(0x1, "PCU"), /* test14 */
406 AON_MUX(0x2, "nonAON"), /* pin41 */
407 TOP_MUX(0x0, "SPI1"), /* txd */
408 TOP_MUX(0x1, "PCM"), /* txd */
409 TOP_MUX(0x2, "BGPIO"), /* gpio37 */
410 TOP_MUX(0x3, "UART5"), /* rxd */
411 TOP_MUX(0x4, "I2S1"), /* ws */
412 TOP_MUX(0x5, "ISP")), /* shutter_trig */
413 AON_PIN(SPI1_RXD, TOP_REG2, 15, 3, 0x44, 9,
414 AON_MUX(0x0, "EXT_INT"), /* int3 */
415 AON_MUX(0x1, "PCU"), /* test15 */
416 AON_MUX(0x2, "nonAON"), /* pin42 */
417 TOP_MUX(0x0, "SPI1"), /* rxd */
418 TOP_MUX(0x1, "PCM"), /* rxd */
419 TOP_MUX(0x2, "BGPIO"), /* gpio38 */
420 TOP_MUX(0x3, "UART5"), /* txd */
421 TOP_MUX(0x4, "I2S1"), /* dout0 */
422 TOP_MUX(0x5, "ISP")), /* shutter_open */
423 ZX_RESERVED(AON_RESERVED5),
424 ZX_RESERVED(AON_RESERVED6),
425 AON_PIN(AUDIO_DET, TOP_REG3, 3, 2, 0x48, 18,
426 AON_MUX(0x0, "PCU"), /* test4 */
427 AON_MUX(0x1, "AGPIO"), /* agpio27 */
428 AON_MUX(0x2, "nonAON"), /* pin2 */
429 AON_MUX(0x3, "EXT_INT"), /* int16 */
430 TOP_MUX(0x0, "AUDIO"), /* detect */
431 TOP_MUX(0x1, "I2C2"), /* scl */
432 TOP_MUX(0x2, "SPI2")), /* clk */
433 AON_PIN(SPDIF_OUT, TOP_REG3, 14, 2, 0x78, 9,
434 AON_MUX(0x0, "PCU"), /* test5 */
435 AON_MUX(0x1, "AGPIO"), /* agpio22 */
436 AON_MUX(0x2, "nonAON"), /* pin4 */
437 TOP_MUX(0x0, "SPDIF"), /* out */
438 TOP_MUX(0x1, "PWM"), /* out0 */
439 TOP_MUX(0x2, "ISP")), /* fl_trig */
440 AON_PIN(HDMI_CEC, 0, 0, 0, 0x74, 9,
441 AON_MUX(0x0, "PCU"), /* test9 */
442 AON_MUX(0x1, "AGPIO"), /* agpio1 */
443 AON_MUX(0x2, "nonAON")), /* pin16 */
444 AON_PIN(HDMI_HPD, 0, 0, 0, 0x74, 18,
445 AON_MUX(0x0, "PCU"), /* test10 */
446 AON_MUX(0x1, "AGPIO"), /* agpio2 */
447 AON_MUX(0x2, "nonAON")), /* pin17 */
448 AON_PIN(GMAC_25M_OUT, 0, 0, 0, 0x78, 0,
449 AON_MUX(0x0, "PCU"), /* test11 */
450 AON_MUX(0x1, "AGPIO"), /* agpio31 */
451 AON_MUX(0x2, "nonAON")), /* pin43 */
452 AON_PIN(BOOT_SEL0, 0, 0, 0, 0xc0, 9,
453 AON_MUX(0x0, "BOOT"), /* sel0 */
454 AON_MUX(0x1, "AGPIO"), /* agpio18 */
455 AON_MUX(0x2, "nonAON")), /* pin18 */
456 AON_PIN(BOOT_SEL1, 0, 0, 0, 0xc0, 18,
457 AON_MUX(0x0, "BOOT"), /* sel1 */
458 AON_MUX(0x1, "AGPIO"), /* agpio19 */
459 AON_MUX(0x2, "nonAON")), /* pin19 */
460 AON_PIN(BOOT_SEL2, 0, 0, 0, 0xc4, 0,
461 AON_MUX(0x0, "BOOT"), /* sel2 */
462 AON_MUX(0x1, "AGPIO"), /* agpio20 */
463 AON_MUX(0x2, "nonAON")), /* pin20 */
464 AON_PIN(DEEP_SLEEP_OUT_N, 0, 0, 0, 0xc4, 9,
465 AON_MUX(0x0, "DEEPSLP"), /* deep sleep out_n */
466 AON_MUX(0x1, "AGPIO"), /* agpio21 */
467 AON_MUX(0x2, "nonAON")), /* pin21 */
468 ZX_RESERVED(AON_RESERVED7),
469
470 /* top_pmm_reg_0 */
471 TOP_PIN(GMII_GTX_CLK, TOP_REG0, 0, 2, 0x10, 0,
472 TOP_MUX(0x0, "GMII"), /* gtx_clk */
473 TOP_MUX(0x1, "DVI0"), /* clk */
474 TOP_MUX(0x2, "BGPIO")), /* gpio0 */
475 TOP_PIN(GMII_TX_CLK, TOP_REG0, 2, 2, 0x10, 9,
476 TOP_MUX(0x0, "GMII"), /* tx_clk */
477 TOP_MUX(0x1, "DVI0"), /* vs */
478 TOP_MUX(0x2, "BGPIO")), /* gpio1 */
479 TOP_PIN(GMII_TXD0, TOP_REG0, 4, 2, 0x10, 18,
480 TOP_MUX(0x0, "GMII"), /* txd0 */
481 TOP_MUX(0x1, "DVI0"), /* hs */
482 TOP_MUX(0x2, "BGPIO")), /* gpio2 */
483 TOP_PIN(GMII_TXD1, TOP_REG0, 6, 2, 0x14, 0,
484 TOP_MUX(0x0, "GMII"), /* txd1 */
485 TOP_MUX(0x1, "DVI0"), /* d0 */
486 TOP_MUX(0x2, "BGPIO")), /* gpio3 */
487 TOP_PIN(GMII_TXD2, TOP_REG0, 8, 2, 0x14, 9,
488 TOP_MUX(0x0, "GMII"), /* txd2 */
489 TOP_MUX(0x1, "DVI0"), /* d1 */
490 TOP_MUX(0x2, "BGPIO")), /* gpio4 */
491 TOP_PIN(GMII_TXD3, TOP_REG0, 10, 2, 0x14, 18,
492 TOP_MUX(0x0, "GMII"), /* txd3 */
493 TOP_MUX(0x1, "DVI0"), /* d2 */
494 TOP_MUX(0x2, "BGPIO")), /* gpio5 */
495 TOP_PIN(GMII_TXD4, TOP_REG0, 12, 2, 0x18, 0,
496 TOP_MUX(0x0, "GMII"), /* txd4 */
497 TOP_MUX(0x1, "DVI0"), /* d3 */
498 TOP_MUX(0x2, "BGPIO")), /* gpio6 */
499 TOP_PIN(GMII_TXD5, TOP_REG0, 14, 2, 0x18, 9,
500 TOP_MUX(0x0, "GMII"), /* txd5 */
501 TOP_MUX(0x1, "DVI0"), /* d4 */
502 TOP_MUX(0x2, "BGPIO")), /* gpio7 */
503 TOP_PIN(GMII_TXD6, TOP_REG0, 16, 2, 0x18, 18,
504 TOP_MUX(0x0, "GMII"), /* txd6 */
505 TOP_MUX(0x1, "DVI0"), /* d5 */
506 TOP_MUX(0x2, "BGPIO")), /* gpio8 */
507 TOP_PIN(GMII_TXD7, TOP_REG0, 18, 2, 0x1c, 0,
508 TOP_MUX(0x0, "GMII"), /* txd7 */
509 TOP_MUX(0x1, "DVI0"), /* d6 */
510 TOP_MUX(0x2, "BGPIO")), /* gpio9 */
511 TOP_PIN(GMII_TX_ER, TOP_REG0, 20, 2, 0x1c, 9,
512 TOP_MUX(0x0, "GMII"), /* tx_er */
513 TOP_MUX(0x1, "DVI0"), /* d7 */
514 TOP_MUX(0x2, "BGPIO")), /* gpio10 */
515 TOP_PIN(GMII_TX_EN, TOP_REG0, 22, 2, 0x1c, 18,
516 TOP_MUX(0x0, "GMII"), /* tx_en */
517 TOP_MUX(0x1, "DVI0"), /* d8 */
518 TOP_MUX(0x3, "BGPIO")), /* gpio11 */
519 TOP_PIN(GMII_RX_CLK, TOP_REG0, 24, 2, 0x20, 0,
520 TOP_MUX(0x0, "GMII"), /* rx_clk */
521 TOP_MUX(0x1, "DVI0"), /* d9 */
522 TOP_MUX(0x3, "BGPIO")), /* gpio12 */
523 TOP_PIN(GMII_RXD0, TOP_REG0, 26, 2, 0x20, 9,
524 TOP_MUX(0x0, "GMII"), /* rxd0 */
525 TOP_MUX(0x1, "DVI0"), /* d10 */
526 TOP_MUX(0x3, "BGPIO")), /* gpio13 */
527 TOP_PIN(GMII_RXD1, TOP_REG0, 28, 2, 0x20, 18,
528 TOP_MUX(0x0, "GMII"), /* rxd1 */
529 TOP_MUX(0x1, "DVI0"), /* d11 */
530 TOP_MUX(0x2, "BGPIO")), /* gpio14 */
531 TOP_PIN(GMII_RXD2, TOP_REG0, 30, 2, 0x24, 0,
532 TOP_MUX(0x0, "GMII"), /* rxd2 */
533 TOP_MUX(0x1, "DVI1"), /* clk */
534 TOP_MUX(0x2, "BGPIO")), /* gpio15 */
535
536 /* top_pmm_reg_1 */
537 TOP_PIN(GMII_RXD3, TOP_REG1, 0, 2, 0x24, 9,
538 TOP_MUX(0x0, "GMII"), /* rxd3 */
539 TOP_MUX(0x1, "DVI1"), /* hs */
540 TOP_MUX(0x2, "BGPIO")), /* gpio16 */
541 TOP_PIN(GMII_RXD4, TOP_REG1, 2, 2, 0x24, 18,
542 TOP_MUX(0x0, "GMII"), /* rxd4 */
543 TOP_MUX(0x1, "DVI1"), /* vs */
544 TOP_MUX(0x2, "BGPIO")), /* gpio17 */
545 TOP_PIN(GMII_RXD5, TOP_REG1, 4, 2, 0x28, 0,
546 TOP_MUX(0x0, "GMII"), /* rxd5 */
547 TOP_MUX(0x1, "DVI1"), /* d0 */
548 TOP_MUX(0x2, "BGPIO"), /* gpio18 */
549 TOP_MUX(0x3, "TSI0")), /* dat0 */
550 TOP_PIN(GMII_RXD6, TOP_REG1, 6, 2, 0x28, 9,
551 TOP_MUX(0x0, "GMII"), /* rxd6 */
552 TOP_MUX(0x1, "DVI1"), /* d1 */
553 TOP_MUX(0x2, "BGPIO"), /* gpio19 */
554 TOP_MUX(0x3, "TSI0")), /* clk */
555 TOP_PIN(GMII_RXD7, TOP_REG1, 8, 2, 0x28, 18,
556 TOP_MUX(0x0, "GMII"), /* rxd7 */
557 TOP_MUX(0x1, "DVI1"), /* d2 */
558 TOP_MUX(0x2, "BGPIO"), /* gpio20 */
559 TOP_MUX(0x3, "TSI0")), /* sync */
560 TOP_PIN(GMII_RX_ER, TOP_REG1, 10, 2, 0x2c, 0,
561 TOP_MUX(0x0, "GMII"), /* rx_er */
562 TOP_MUX(0x1, "DVI1"), /* d3 */
563 TOP_MUX(0x2, "BGPIO"), /* gpio21 */
564 TOP_MUX(0x3, "TSI0")), /* valid */
565 TOP_PIN(GMII_RX_DV, TOP_REG1, 12, 2, 0x2c, 9,
566 TOP_MUX(0x0, "GMII"), /* rx_dv */
567 TOP_MUX(0x1, "DVI1"), /* d4 */
568 TOP_MUX(0x2, "BGPIO"), /* gpio22 */
569 TOP_MUX(0x3, "TSI1")), /* dat0 */
570 TOP_PIN(GMII_COL, TOP_REG1, 14, 2, 0x2c, 18,
571 TOP_MUX(0x0, "GMII"), /* col */
572 TOP_MUX(0x1, "DVI1"), /* d5 */
573 TOP_MUX(0x2, "BGPIO"), /* gpio23 */
574 TOP_MUX(0x3, "TSI1")), /* clk */
575 TOP_PIN(GMII_CRS, TOP_REG1, 16, 2, 0x30, 0,
576 TOP_MUX(0x0, "GMII"), /* crs */
577 TOP_MUX(0x1, "DVI1"), /* d6 */
578 TOP_MUX(0x2, "BGPIO"), /* gpio24 */
579 TOP_MUX(0x3, "TSI1")), /* sync */
580 TOP_PIN(GMII_MDC, TOP_REG1, 18, 2, 0x30, 9,
581 TOP_MUX(0x0, "GMII"), /* mdc */
582 TOP_MUX(0x1, "DVI1"), /* d7 */
583 TOP_MUX(0x2, "BGPIO"), /* gpio25 */
584 TOP_MUX(0x3, "TSI1")), /* valid */
585 TOP_PIN(GMII_MDIO, TOP_REG1, 20, 1, 0x30, 18,
586 TOP_MUX(0x0, "GMII"), /* mdio */
587 TOP_MUX(0x2, "BGPIO")), /* gpio26 */
588 TOP_PIN(SDIO1_CLK, TOP_REG1, 21, 2, 0x34, 18,
589 TOP_MUX(0x0, "SDIO1"), /* clk */
590 TOP_MUX(0x1, "USIM0"), /* clk */
591 TOP_MUX(0x2, "BGPIO"), /* gpio27 */
592 TOP_MUX(0x3, "SPINOR")), /* clk */
593 TOP_PIN(SDIO1_CMD, TOP_REG1, 23, 2, 0x38, 0,
594 TOP_MUX(0x0, "SDIO1"), /* cmd */
595 TOP_MUX(0x1, "USIM0"), /* cd */
596 TOP_MUX(0x2, "BGPIO"), /* gpio28 */
597 TOP_MUX(0x3, "SPINOR")), /* cs */
598 TOP_PIN(SDIO1_DATA0, TOP_REG1, 25, 2, 0x38, 9,
599 TOP_MUX(0x0, "SDIO1"), /* dat0 */
600 TOP_MUX(0x1, "USIM0"), /* rst */
601 TOP_MUX(0x2, "BGPIO"), /* gpio29 */
602 TOP_MUX(0x3, "SPINOR")), /* dq0 */
603 TOP_PIN(SDIO1_DATA1, TOP_REG1, 27, 2, 0x38, 18,
604 TOP_MUX(0x0, "SDIO1"), /* dat1 */
605 TOP_MUX(0x1, "USIM0"), /* data */
606 TOP_MUX(0x2, "BGPIO"), /* gpio30 */
607 TOP_MUX(0x3, "SPINOR")), /* dq1 */
608 TOP_PIN(SDIO1_DATA2, TOP_REG1, 29, 2, 0x3c, 0,
609 TOP_MUX(0x0, "SDIO1"), /* dat2 */
610 TOP_MUX(0x1, "BGPIO"), /* gpio31 */
611 TOP_MUX(0x2, "SPINOR")), /* dq2 */
612
613 /* top_pmm_reg_2 */
614 TOP_PIN(SDIO1_DATA3, TOP_REG2, 0, 2, 0x3c, 9,
615 TOP_MUX(0x0, "SDIO1"), /* dat3 */
616 TOP_MUX(0x1, "BGPIO"), /* gpio32 */
617 TOP_MUX(0x2, "SPINOR")), /* dq3 */
618 TOP_PIN(SDIO1_CD, TOP_REG2, 2, 2, 0x3c, 18,
619 TOP_MUX(0x0, "SDIO1"), /* cd */
620 TOP_MUX(0x1, "BGPIO"), /* gpio33 */
621 TOP_MUX(0x2, "ISP")), /* fl_trig */
622 TOP_PIN(SDIO1_WP, TOP_REG2, 4, 2, 0x40, 0,
623 TOP_MUX(0x0, "SDIO1"), /* wp */
624 TOP_MUX(0x1, "BGPIO"), /* gpio34 */
625 TOP_MUX(0x2, "ISP")), /* ref_clk */
626 TOP_PIN(USIM1_CD, TOP_REG2, 22, 3, 0x44, 18,
627 TOP_MUX(0x0, "USIM1"), /* cd */
628 TOP_MUX(0x1, "UART4"), /* rxd */
629 TOP_MUX(0x2, "BGPIO"), /* gpio39 */
630 TOP_MUX(0x3, "SPI3"), /* clk */
631 TOP_MUX(0x4, "I2S0"), /* bclk */
632 TOP_MUX(0x5, "B_DVI0")), /* d8 */
633 TOP_PIN(USIM1_CLK, TOP_REG2, 25, 3, 0x4c, 18,
634 TOP_MUX(0x0, "USIM1"), /* clk */
635 TOP_MUX(0x1, "UART4"), /* txd */
636 TOP_MUX(0x2, "BGPIO"), /* gpio40 */
637 TOP_MUX(0x3, "SPI3"), /* cs */
638 TOP_MUX(0x4, "I2S0"), /* ws */
639 TOP_MUX(0x5, "B_DVI0")), /* d9 */
640 TOP_PIN(USIM1_RST, TOP_REG2, 28, 3, 0x4c, 0,
641 TOP_MUX(0x0, "USIM1"), /* rst */
642 TOP_MUX(0x1, "UART4"), /* cts */
643 TOP_MUX(0x2, "BGPIO"), /* gpio41 */
644 TOP_MUX(0x3, "SPI3"), /* txd */
645 TOP_MUX(0x4, "I2S0"), /* dout0 */
646 TOP_MUX(0x5, "B_DVI0")), /* d10 */
647
648 /* top_pmm_reg_3 */
649 TOP_PIN(USIM1_DATA, TOP_REG3, 0, 3, 0x4c, 9,
650 TOP_MUX(0x0, "USIM1"), /* dat */
651 TOP_MUX(0x1, "UART4"), /* rst */
652 TOP_MUX(0x2, "BGPIO"), /* gpio42 */
653 TOP_MUX(0x3, "SPI3"), /* rxd */
654 TOP_MUX(0x4, "I2S0"), /* din0 */
655 TOP_MUX(0x5, "B_DVI0")), /* d11 */
656 TOP_PIN(SDIO0_CLK, TOP_REG3, 6, 1, 0x58, 0,
657 TOP_MUX(0x0, "SDIO0"), /* clk */
658 TOP_MUX(0x1, "GPIO")), /* gpio43 */
659 TOP_PIN(SDIO0_CMD, TOP_REG3, 7, 1, 0x58, 9,
660 TOP_MUX(0x0, "SDIO0"), /* cmd */
661 TOP_MUX(0x1, "GPIO")), /* gpio44 */
662 TOP_PIN(SDIO0_DATA0, TOP_REG3, 8, 1, 0x58, 18,
663 TOP_MUX(0x0, "SDIO0"), /* dat0 */
664 TOP_MUX(0x1, "GPIO")), /* gpio45 */
665 TOP_PIN(SDIO0_DATA1, TOP_REG3, 9, 1, 0x5c, 0,
666 TOP_MUX(0x0, "SDIO0"), /* dat1 */
667 TOP_MUX(0x1, "GPIO")), /* gpio46 */
668 TOP_PIN(SDIO0_DATA2, TOP_REG3, 10, 1, 0x5c, 9,
669 TOP_MUX(0x0, "SDIO0"), /* dat2 */
670 TOP_MUX(0x1, "GPIO")), /* gpio47 */
671 TOP_PIN(SDIO0_DATA3, TOP_REG3, 11, 1, 0x5c, 18,
672 TOP_MUX(0x0, "SDIO0"), /* dat3 */
673 TOP_MUX(0x1, "GPIO")), /* gpio48 */
674 TOP_PIN(SDIO0_CD, TOP_REG3, 12, 1, 0x60, 0,
675 TOP_MUX(0x0, "SDIO0"), /* cd */
676 TOP_MUX(0x1, "GPIO")), /* gpio49 */
677 TOP_PIN(SDIO0_WP, TOP_REG3, 13, 1, 0x60, 9,
678 TOP_MUX(0x0, "SDIO0"), /* wp */
679 TOP_MUX(0x1, "GPIO")), /* gpio50 */
680
681 /* top_pmm_reg_4 */
682 TOP_PIN(TSI0_DATA0, TOP_REG4, 0, 2, 0x60, 18,
683 TOP_MUX(0x0, "TSI0"), /* dat0 */
684 TOP_MUX(0x1, "LCD"), /* clk */
685 TOP_MUX(0x2, "BGPIO")), /* gpio51 */
686 TOP_PIN(SPINOR_CLK, TOP_REG4, 2, 2, 0xa8, 18,
687 TOP_MUX(0x0, "SPINOR"), /* clk */
688 TOP_MUX(0x1, "TSI0"), /* dat1 */
689 TOP_MUX(0x2, "LCD"), /* dat0 */
690 TOP_MUX(0x3, "BGPIO")), /* gpio52 */
691 TOP_PIN(TSI2_DATA, TOP_REG4, 4, 2, 0x7c, 0,
692 TOP_MUX(0x0, "TSI2"), /* dat */
693 TOP_MUX(0x1, "TSI0"), /* dat2 */
694 TOP_MUX(0x2, "LCD"), /* dat1 */
695 TOP_MUX(0x3, "BGPIO")), /* gpio53 */
696 TOP_PIN(TSI2_CLK, TOP_REG4, 6, 2, 0x7c, 9,
697 TOP_MUX(0x0, "TSI2"), /* clk */
698 TOP_MUX(0x1, "TSI0"), /* dat3 */
699 TOP_MUX(0x2, "LCD"), /* dat2 */
700 TOP_MUX(0x3, "BGPIO")), /* gpio54 */
701 TOP_PIN(TSI2_SYNC, TOP_REG4, 8, 2, 0x7c, 18,
702 TOP_MUX(0x0, "TSI2"), /* sync */
703 TOP_MUX(0x1, "TSI0"), /* dat4 */
704 TOP_MUX(0x2, "LCD"), /* dat3 */
705 TOP_MUX(0x3, "BGPIO")), /* gpio55 */
706 TOP_PIN(TSI2_VALID, TOP_REG4, 10, 2, 0x80, 0,
707 TOP_MUX(0x0, "TSI2"), /* valid */
708 TOP_MUX(0x1, "TSI0"), /* dat5 */
709 TOP_MUX(0x2, "LCD"), /* dat4 */
710 TOP_MUX(0x3, "BGPIO")), /* gpio56 */
711 TOP_PIN(SPINOR_CS, TOP_REG4, 12, 2, 0x80, 9,
712 TOP_MUX(0x0, "SPINOR"), /* cs */
713 TOP_MUX(0x1, "TSI0"), /* dat6 */
714 TOP_MUX(0x2, "LCD"), /* dat5 */
715 TOP_MUX(0x3, "BGPIO")), /* gpio57 */
716 TOP_PIN(SPINOR_DQ0, TOP_REG4, 14, 2, 0x80, 18,
717 TOP_MUX(0x0, "SPINOR"), /* dq0 */
718 TOP_MUX(0x1, "TSI0"), /* dat7 */
719 TOP_MUX(0x2, "LCD"), /* dat6 */
720 TOP_MUX(0x3, "BGPIO")), /* gpio58 */
721 TOP_PIN(SPINOR_DQ1, TOP_REG4, 16, 2, 0x84, 0,
722 TOP_MUX(0x0, "SPINOR"), /* dq1 */
723 TOP_MUX(0x1, "TSI0"), /* clk */
724 TOP_MUX(0x2, "LCD"), /* dat7 */
725 TOP_MUX(0x3, "BGPIO")), /* gpio59 */
726 TOP_PIN(SPINOR_DQ2, TOP_REG4, 18, 2, 0x84, 9,
727 TOP_MUX(0x0, "SPINOR"), /* dq2 */
728 TOP_MUX(0x1, "TSI0"), /* sync */
729 TOP_MUX(0x2, "LCD"), /* dat8 */
730 TOP_MUX(0x3, "BGPIO")), /* gpio60 */
731 TOP_PIN(SPINOR_DQ3, TOP_REG4, 20, 2, 0x84, 18,
732 TOP_MUX(0x0, "SPINOR"), /* dq3 */
733 TOP_MUX(0x1, "TSI0"), /* valid */
734 TOP_MUX(0x2, "LCD"), /* dat9 */
735 TOP_MUX(0x3, "BGPIO")), /* gpio61 */
736 TOP_PIN(VGA_HS, TOP_REG4, 22, 3, 0x88, 0,
737 TOP_MUX(0x0, "VGA"), /* hs */
738 TOP_MUX(0x1, "TSI1"), /* dat0 */
739 TOP_MUX(0x2, "LCD"), /* dat10 */
740 TOP_MUX(0x3, "BGPIO"), /* gpio62 */
741 TOP_MUX(0x4, "I2S1"), /* din1 */
742 TOP_MUX(0x5, "B_DVI0")), /* clk */
743 TOP_PIN(VGA_VS, TOP_REG4, 25, 3, 0x88, 9,
744 TOP_MUX(0x0, "VGA"), /* vs0 */
745 TOP_MUX(0x1, "TSI1"), /* dat1 */
746 TOP_MUX(0x2, "LCD"), /* dat11 */
747 TOP_MUX(0x3, "BGPIO"), /* gpio63 */
748 TOP_MUX(0x4, "I2S1"), /* din2 */
749 TOP_MUX(0x5, "B_DVI0")), /* vs */
750 TOP_PIN(TSI3_DATA, TOP_REG4, 28, 3, 0x88, 18,
751 TOP_MUX(0x0, "TSI3"), /* dat */
752 TOP_MUX(0x1, "TSI1"), /* dat2 */
753 TOP_MUX(0x2, "LCD"), /* dat12 */
754 TOP_MUX(0x3, "BGPIO"), /* gpio64 */
755 TOP_MUX(0x4, "I2S1"), /* din3 */
756 TOP_MUX(0x5, "B_DVI0")), /* hs */
757
758 /* top_pmm_reg_5 */
759 TOP_PIN(TSI3_CLK, TOP_REG5, 0, 3, 0x8c, 0,
760 TOP_MUX(0x0, "TSI3"), /* clk */
761 TOP_MUX(0x1, "TSI1"), /* dat3 */
762 TOP_MUX(0x2, "LCD"), /* dat13 */
763 TOP_MUX(0x3, "BGPIO"), /* gpio65 */
764 TOP_MUX(0x4, "I2S1"), /* dout1 */
765 TOP_MUX(0x5, "B_DVI0")), /* d0 */
766 TOP_PIN(TSI3_SYNC, TOP_REG5, 3, 3, 0x8c, 9,
767 TOP_MUX(0x0, "TSI3"), /* sync */
768 TOP_MUX(0x1, "TSI1"), /* dat4 */
769 TOP_MUX(0x2, "LCD"), /* dat14 */
770 TOP_MUX(0x3, "BGPIO"), /* gpio66 */
771 TOP_MUX(0x4, "I2S1"), /* dout2 */
772 TOP_MUX(0x5, "B_DVI0")), /* d1 */
773 TOP_PIN(TSI3_VALID, TOP_REG5, 6, 3, 0x8c, 18,
774 TOP_MUX(0x0, "TSI3"), /* valid */
775 TOP_MUX(0x1, "TSI1"), /* dat5 */
776 TOP_MUX(0x2, "LCD"), /* dat15 */
777 TOP_MUX(0x3, "BGPIO"), /* gpio67 */
778 TOP_MUX(0x4, "I2S1"), /* dout3 */
779 TOP_MUX(0x5, "B_DVI0")), /* d2 */
780 TOP_PIN(I2S1_WS, TOP_REG5, 9, 3, 0x90, 0,
781 TOP_MUX(0x0, "I2S1"), /* ws */
782 TOP_MUX(0x1, "TSI1"), /* dat6 */
783 TOP_MUX(0x2, "LCD"), /* dat16 */
784 TOP_MUX(0x3, "BGPIO"), /* gpio68 */
785 TOP_MUX(0x4, "VGA"), /* scl */
786 TOP_MUX(0x5, "B_DVI0")), /* d3 */
787 TOP_PIN(I2S1_BCLK, TOP_REG5, 12, 3, 0x90, 9,
788 TOP_MUX(0x0, "I2S1"), /* bclk */
789 TOP_MUX(0x1, "TSI1"), /* dat7 */
790 TOP_MUX(0x2, "LCD"), /* dat17 */
791 TOP_MUX(0x3, "BGPIO"), /* gpio69 */
792 TOP_MUX(0x4, "VGA"), /* sda */
793 TOP_MUX(0x5, "B_DVI0")), /* d4 */
794 TOP_PIN(I2S1_MCLK, TOP_REG5, 15, 2, 0x90, 18,
795 TOP_MUX(0x0, "I2S1"), /* mclk */
796 TOP_MUX(0x1, "TSI1"), /* clk */
797 TOP_MUX(0x2, "LCD"), /* dat18 */
798 TOP_MUX(0x3, "BGPIO")), /* gpio70 */
799 TOP_PIN(I2S1_DIN0, TOP_REG5, 17, 2, 0x94, 0,
800 TOP_MUX(0x0, "I2S1"), /* din0 */
801 TOP_MUX(0x1, "TSI1"), /* sync */
802 TOP_MUX(0x2, "LCD"), /* dat19 */
803 TOP_MUX(0x3, "BGPIO")), /* gpio71 */
804 TOP_PIN(I2S1_DOUT0, TOP_REG5, 19, 2, 0x94, 9,
805 TOP_MUX(0x0, "I2S1"), /* dout0 */
806 TOP_MUX(0x1, "TSI1"), /* valid */
807 TOP_MUX(0x2, "LCD"), /* dat20 */
808 TOP_MUX(0x3, "BGPIO")), /* gpio72 */
809 TOP_PIN(SPI3_CLK, TOP_REG5, 21, 3, 0x94, 18,
810 TOP_MUX(0x0, "SPI3"), /* clk */
811 TOP_MUX(0x1, "TSO1"), /* clk */
812 TOP_MUX(0x2, "LCD"), /* dat21 */
813 TOP_MUX(0x3, "BGPIO"), /* gpio73 */
814 TOP_MUX(0x4, "UART5"), /* rxd */
815 TOP_MUX(0x5, "PCM"), /* fs */
816 TOP_MUX(0x6, "I2S0"), /* din1 */
817 TOP_MUX(0x7, "B_DVI0")), /* d5 */
818 TOP_PIN(SPI3_CS, TOP_REG5, 24, 3, 0x98, 0,
819 TOP_MUX(0x0, "SPI3"), /* cs */
820 TOP_MUX(0x1, "TSO1"), /* dat0 */
821 TOP_MUX(0x2, "LCD"), /* dat22 */
822 TOP_MUX(0x3, "BGPIO"), /* gpio74 */
823 TOP_MUX(0x4, "UART5"), /* txd */
824 TOP_MUX(0x5, "PCM"), /* clk */
825 TOP_MUX(0x6, "I2S0"), /* din2 */
826 TOP_MUX(0x7, "B_DVI0")), /* d6 */
827 TOP_PIN(SPI3_TXD, TOP_REG5, 27, 3, 0x98, 9,
828 TOP_MUX(0x0, "SPI3"), /* txd */
829 TOP_MUX(0x1, "TSO1"), /* dat1 */
830 TOP_MUX(0x2, "LCD"), /* dat23 */
831 TOP_MUX(0x3, "BGPIO"), /* gpio75 */
832 TOP_MUX(0x4, "UART5"), /* cts */
833 TOP_MUX(0x5, "PCM"), /* txd */
834 TOP_MUX(0x6, "I2S0"), /* din3 */
835 TOP_MUX(0x7, "B_DVI0")), /* d7 */
836 TOP_PIN(NAND_LDO_MS18_SEL, TOP_REG5, 30, 1, 0xe4, 0,
837 TOP_MUX(0x0, "NAND"), /* ldo_ms18_sel */
838 TOP_MUX(0x1, "BGPIO")), /* gpio99 */
839
840 /* top_pmm_reg_6 */
841 TOP_PIN(SPI3_RXD, TOP_REG6, 0, 3, 0x98, 18,
842 TOP_MUX(0x0, "SPI3"), /* rxd */
843 TOP_MUX(0x1, "TSO1"), /* dat2 */
844 TOP_MUX(0x2, "LCD"), /* stvu_vsync */
845 TOP_MUX(0x3, "BGPIO"), /* gpio76 */
846 TOP_MUX(0x4, "UART5"), /* rts */
847 TOP_MUX(0x5, "PCM"), /* rxd */
848 TOP_MUX(0x6, "I2S0"), /* dout1 */
849 TOP_MUX(0x7, "B_DVI1")), /* clk */
850 TOP_PIN(I2S0_MCLK, TOP_REG6, 3, 3, 0x9c, 0,
851 TOP_MUX(0x0, "I2S0"), /* mclk */
852 TOP_MUX(0x1, "TSO1"), /* dat3 */
853 TOP_MUX(0x2, "LCD"), /* stvd */
854 TOP_MUX(0x3, "BGPIO"), /* gpio77 */
855 TOP_MUX(0x4, "USIM0"), /* cd */
856 TOP_MUX(0x5, "B_DVI1")), /* vs */
857 TOP_PIN(I2S0_BCLK, TOP_REG6, 6, 3, 0x9c, 9,
858 TOP_MUX(0x0, "I2S0"), /* bclk */
859 TOP_MUX(0x1, "TSO1"), /* dat4 */
860 TOP_MUX(0x2, "LCD"), /* sthl_hsync */
861 TOP_MUX(0x3, "BGPIO"), /* gpio78 */
862 TOP_MUX(0x4, "USIM0"), /* clk */
863 TOP_MUX(0x5, "B_DVI1")), /* hs */
864 TOP_PIN(I2S0_WS, TOP_REG6, 9, 3, 0x9c, 18,
865 TOP_MUX(0x0, "I2S0"), /* ws */
866 TOP_MUX(0x1, "TSO1"), /* dat5 */
867 TOP_MUX(0x2, "LCD"), /* sthr */
868 TOP_MUX(0x3, "BGPIO"), /* gpio79 */
869 TOP_MUX(0x4, "USIM0"), /* rst */
870 TOP_MUX(0x5, "B_DVI1")), /* d0 */
871 TOP_PIN(I2S0_DIN0, TOP_REG6, 12, 3, 0xa0, 0,
872 TOP_MUX(0x0, "I2S0"), /* din0 */
873 TOP_MUX(0x1, "TSO1"), /* dat6 */
874 TOP_MUX(0x2, "LCD"), /* oev_dataen */
875 TOP_MUX(0x3, "BGPIO"), /* gpio80 */
876 TOP_MUX(0x4, "USIM0"), /* dat */
877 TOP_MUX(0x5, "B_DVI1")), /* d1 */
878 TOP_PIN(I2S0_DOUT0, TOP_REG6, 15, 2, 0xa0, 9,
879 TOP_MUX(0x0, "I2S0"), /* dout0 */
880 TOP_MUX(0x1, "TSO1"), /* dat7 */
881 TOP_MUX(0x2, "LCD"), /* ckv */
882 TOP_MUX(0x3, "BGPIO")), /* gpio81 */
883 TOP_PIN(I2C5_SCL, TOP_REG6, 17, 3, 0xa0, 18,
884 TOP_MUX(0x0, "I2C5"), /* scl */
885 TOP_MUX(0x1, "TSO1"), /* sync */
886 TOP_MUX(0x2, "LCD"), /* ld */
887 TOP_MUX(0x3, "BGPIO"), /* gpio82 */
888 TOP_MUX(0x4, "PWM"), /* out2 */
889 TOP_MUX(0x5, "I2S0"), /* dout2 */
890 TOP_MUX(0x6, "B_DVI1")), /* d2 */
891 TOP_PIN(I2C5_SDA, TOP_REG6, 20, 3, 0xa4, 0,
892 TOP_MUX(0x0, "I2C5"), /* sda */
893 TOP_MUX(0x1, "TSO1"), /* vld */
894 TOP_MUX(0x2, "LCD"), /* pol */
895 TOP_MUX(0x3, "BGPIO"), /* gpio83 */
896 TOP_MUX(0x4, "PWM"), /* out3 */
897 TOP_MUX(0x5, "I2S0"), /* dout3 */
898 TOP_MUX(0x6, "B_DVI1")), /* d3 */
899 TOP_PIN(SPI2_CLK, TOP_REG6, 23, 3, 0xa4, 9,
900 TOP_MUX(0x0, "SPI2"), /* clk */
901 TOP_MUX(0x1, "TSO0"), /* clk */
902 TOP_MUX(0x2, "LCD"), /* degsl */
903 TOP_MUX(0x3, "BGPIO"), /* gpio84 */
904 TOP_MUX(0x4, "I2C4"), /* scl */
905 TOP_MUX(0x5, "B_DVI1")), /* d4 */
906 TOP_PIN(SPI2_CS, TOP_REG6, 26, 3, 0xa4, 18,
907 TOP_MUX(0x0, "SPI2"), /* cs */
908 TOP_MUX(0x1, "TSO0"), /* data */
909 TOP_MUX(0x2, "LCD"), /* rev */
910 TOP_MUX(0x3, "BGPIO"), /* gpio85 */
911 TOP_MUX(0x4, "I2C4"), /* sda */
912 TOP_MUX(0x5, "B_DVI1")), /* d5 */
913 TOP_PIN(SPI2_TXD, TOP_REG6, 29, 3, 0xa8, 0,
914 TOP_MUX(0x0, "SPI2"), /* txd */
915 TOP_MUX(0x1, "TSO0"), /* sync */
916 TOP_MUX(0x2, "LCD"), /* u_d */
917 TOP_MUX(0x3, "BGPIO"), /* gpio86 */
918 TOP_MUX(0x4, "I2C4"), /* scl */
919 TOP_MUX(0x5, "B_DVI1")), /* d6 */
920
921 /* top_pmm_reg_7 */
922 TOP_PIN(SPI2_RXD, TOP_REG7, 0, 3, 0xa8, 9,
923 TOP_MUX(0x0, "SPI2"), /* rxd */
924 TOP_MUX(0x1, "TSO0"), /* vld */
925 TOP_MUX(0x2, "LCD"), /* r_l */
926 TOP_MUX(0x3, "BGPIO"), /* gpio87 */
927 TOP_MUX(0x4, "I2C3"), /* sda */
928 TOP_MUX(0x5, "B_DVI1")), /* d7 */
929 TOP_PIN(NAND_WP_N, TOP_REG7, 7, 3, 0x54, 9,
930 TOP_MUX(0x0, "NAND"), /* wp */
931 TOP_MUX(0x1, "PWM"), /* out2 */
932 TOP_MUX(0x2, "SPI2"), /* clk */
933 TOP_MUX(0x3, "BGPIO"), /* gpio88 */
934 TOP_MUX(0x4, "TSI0"), /* dat0 */
935 TOP_MUX(0x5, "I2S1")), /* din1 */
936 TOP_PIN(NAND_PAGE_SIZE0, TOP_REG7, 10, 3, 0xb8, 0,
937 TOP_MUX(0x0, "NAND"), /* boot_pagesize0 */
938 TOP_MUX(0x1, "PWM"), /* out3 */
939 TOP_MUX(0x2, "SPI2"), /* cs */
940 TOP_MUX(0x3, "BGPIO"), /* gpio89 */
941 TOP_MUX(0x4, "TSI0"), /* clk */
942 TOP_MUX(0x5, "I2S1")), /* din2 */
943 TOP_PIN(NAND_PAGE_SIZE1, TOP_REG7, 13, 3, 0xb8, 9,
944 TOP_MUX(0x0, "NAND"), /* boot_pagesize1 */
945 TOP_MUX(0x1, "I2C4"), /* scl */
946 TOP_MUX(0x2, "SPI2"), /* txd */
947 TOP_MUX(0x3, "BGPIO"), /* gpio90 */
948 TOP_MUX(0x4, "TSI0"), /* sync */
949 TOP_MUX(0x5, "I2S1")), /* din3 */
950 TOP_PIN(NAND_ADDR_CYCLE, TOP_REG7, 16, 3, 0xb8, 18,
951 TOP_MUX(0x0, "NAND"), /* boot_addr_cycles */
952 TOP_MUX(0x1, "I2C4"), /* sda */
953 TOP_MUX(0x2, "SPI2"), /* rxd */
954 TOP_MUX(0x3, "BGPIO"), /* gpio91 */
955 TOP_MUX(0x4, "TSI0"), /* valid */
956 TOP_MUX(0x5, "I2S1")), /* dout1 */
957 TOP_PIN(NAND_RB0, TOP_REG7, 19, 3, 0xbc, 0,
958 TOP_MUX(0x0, "NAND"), /* rdy_busy0 */
959 TOP_MUX(0x1, "I2C2"), /* scl */
960 TOP_MUX(0x2, "USIM0"), /* cd */
961 TOP_MUX(0x3, "BGPIO"), /* gpio92 */
962 TOP_MUX(0x4, "TSI1")), /* data0 */
963 TOP_PIN(NAND_RB1, TOP_REG7, 22, 3, 0xbc, 9,
964 TOP_MUX(0x0, "NAND"), /* rdy_busy1 */
965 TOP_MUX(0x1, "I2C2"), /* sda */
966 TOP_MUX(0x2, "USIM0"), /* clk */
967 TOP_MUX(0x3, "BGPIO"), /* gpio93 */
968 TOP_MUX(0x4, "TSI1")), /* clk */
969 TOP_PIN(NAND_RB2, TOP_REG7, 25, 3, 0xbc, 18,
970 TOP_MUX(0x0, "NAND"), /* rdy_busy2 */
971 TOP_MUX(0x1, "UART5"), /* rxd */
972 TOP_MUX(0x2, "USIM0"), /* rst */
973 TOP_MUX(0x3, "BGPIO"), /* gpio94 */
974 TOP_MUX(0x4, "TSI1"), /* sync */
975 TOP_MUX(0x4, "I2S1")), /* dout2 */
976 TOP_PIN(NAND_RB3, TOP_REG7, 28, 3, 0x54, 18,
977 TOP_MUX(0x0, "NAND"), /* rdy_busy3 */
978 TOP_MUX(0x1, "UART5"), /* txd */
979 TOP_MUX(0x2, "USIM0"), /* dat */
980 TOP_MUX(0x3, "BGPIO"), /* gpio95 */
981 TOP_MUX(0x4, "TSI1"), /* valid */
982 TOP_MUX(0x4, "I2S1")), /* dout3 */
983
984 /* top_pmm_reg_8 */
985 TOP_PIN(GMAC_125M_IN, TOP_REG8, 0, 2, 0x34, 0,
986 TOP_MUX(0x0, "GMII"), /* 125m_in */
987 TOP_MUX(0x1, "USB2"), /* 0_drvvbus */
988 TOP_MUX(0x2, "ISP"), /* ref_clk */
989 TOP_MUX(0x3, "BGPIO")), /* gpio96 */
990 TOP_PIN(GMAC_50M_OUT, TOP_REG8, 2, 2, 0x34, 9,
991 TOP_MUX(0x0, "GMII"), /* 50m_out */
992 TOP_MUX(0x1, "USB2"), /* 1_drvvbus */
993 TOP_MUX(0x2, "BGPIO"), /* gpio97 */
994 TOP_MUX(0x3, "USB2")), /* 0_drvvbus */
995 TOP_PIN(SPINOR_SSCLK_LOOPBACK, TOP_REG8, 6, 1, 0xc8, 9,
996 TOP_MUX(0x0, "SPINOR")), /* sdio1_clk_i */
997 TOP_PIN(SPINOR_SDIO1CLK_LOOPBACK, TOP_REG8, 7, 1, 0xc8, 18,
998 TOP_MUX(0x0, "SPINOR")), /* ssclk_i */
999};
1000
1001static struct zx_pinctrl_soc_info zx296718_pinctrl_info = {
1002 .pins = zx296718_pins,
1003 .npins = ARRAY_SIZE(zx296718_pins),
1004};
1005
1006static int zx296718_pinctrl_probe(struct platform_device *pdev)
1007{
1008 return zx_pinctrl_init(pdev, &zx296718_pinctrl_info);
1009}
1010
1011static const struct of_device_id zx296718_pinctrl_match[] = {
1012 { .compatible = "zte,zx296718-pmm", },
1013 {}
1014};
1015MODULE_DEVICE_TABLE(of, zx296718_pinctrl_match);
1016
1017static struct platform_driver zx296718_pinctrl_driver = {
1018 .probe = zx296718_pinctrl_probe,
1019 .driver = {
1020 .name = "zx296718-pinctrl",
1021 .of_match_table = zx296718_pinctrl_match,
1022 },
1023};
1024builtin_platform_driver(zx296718_pinctrl_driver);
1025
1026MODULE_DESCRIPTION("ZTE ZX296718 pinctrl driver");
1027MODULE_LICENSE("GPL");
Ubuntu Hirsute Linux kernel mirror