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aa7ffc01 JB |
1 | /* |
2 | * Copyright (c) 2009-2010 Intel Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program; if not, write to the Free Software Foundation, Inc., | |
15 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
16 | * | |
17 | * The full GNU General Public License is included in this distribution in | |
18 | * the file called "COPYING". | |
19 | * | |
20 | * Authors: | |
21 | * Jesse Barnes <jbarnes@virtuousgeek.org> | |
22 | */ | |
23 | ||
24 | /* | |
25 | * Some Intel Ibex Peak based platforms support so-called "intelligent | |
26 | * power sharing", which allows the CPU and GPU to cooperate to maximize | |
27 | * performance within a given TDP (thermal design point). This driver | |
28 | * performs the coordination between the CPU and GPU, monitors thermal and | |
29 | * power statistics in the platform, and initializes power monitoring | |
30 | * hardware. It also provides a few tunables to control behavior. Its | |
31 | * primary purpose is to safely allow CPU and GPU turbo modes to be enabled | |
32 | * by tracking power and thermal budget; secondarily it can boost turbo | |
33 | * performance by allocating more power or thermal budget to the CPU or GPU | |
34 | * based on available headroom and activity. | |
35 | * | |
36 | * The basic algorithm is driven by a 5s moving average of tempurature. If | |
37 | * thermal headroom is available, the CPU and/or GPU power clamps may be | |
38 | * adjusted upwards. If we hit the thermal ceiling or a thermal trigger, | |
39 | * we scale back the clamp. Aside from trigger events (when we're critically | |
40 | * close or over our TDP) we don't adjust the clamps more than once every | |
41 | * five seconds. | |
42 | * | |
43 | * The thermal device (device 31, function 6) has a set of registers that | |
44 | * are updated by the ME firmware. The ME should also take the clamp values | |
45 | * written to those registers and write them to the CPU, but we currently | |
46 | * bypass that functionality and write the CPU MSR directly. | |
47 | * | |
48 | * UNSUPPORTED: | |
49 | * - dual MCP configs | |
50 | * | |
51 | * TODO: | |
52 | * - handle CPU hotplug | |
53 | * - provide turbo enable/disable api | |
aa7ffc01 JB |
54 | * |
55 | * Related documents: | |
56 | * - CDI 403777, 403778 - Auburndale EDS vol 1 & 2 | |
57 | * - CDI 401376 - Ibex Peak EDS | |
58 | * - ref 26037, 26641 - IPS BIOS spec | |
59 | * - ref 26489 - Nehalem BIOS writer's guide | |
60 | * - ref 26921 - Ibex Peak BIOS Specification | |
61 | */ | |
62 | ||
63 | #include <linux/debugfs.h> | |
64 | #include <linux/delay.h> | |
65 | #include <linux/interrupt.h> | |
66 | #include <linux/kernel.h> | |
67 | #include <linux/kthread.h> | |
68 | #include <linux/module.h> | |
69 | #include <linux/pci.h> | |
70 | #include <linux/sched.h> | |
71 | #include <linux/seq_file.h> | |
72 | #include <linux/string.h> | |
73 | #include <linux/tick.h> | |
74 | #include <linux/timer.h> | |
75 | #include <drm/i915_drm.h> | |
76 | #include <asm/msr.h> | |
77 | #include <asm/processor.h> | |
78 | ||
79 | #define PCI_DEVICE_ID_INTEL_THERMAL_SENSOR 0x3b32 | |
80 | ||
81 | /* | |
82 | * Package level MSRs for monitor/control | |
83 | */ | |
84 | #define PLATFORM_INFO 0xce | |
85 | #define PLATFORM_TDP (1<<29) | |
86 | #define PLATFORM_RATIO (1<<28) | |
87 | ||
88 | #define IA32_MISC_ENABLE 0x1a0 | |
89 | #define IA32_MISC_TURBO_EN (1ULL<<38) | |
90 | ||
91 | #define TURBO_POWER_CURRENT_LIMIT 0x1ac | |
92 | #define TURBO_TDC_OVR_EN (1UL<<31) | |
93 | #define TURBO_TDC_MASK (0x000000007fff0000UL) | |
94 | #define TURBO_TDC_SHIFT (16) | |
95 | #define TURBO_TDP_OVR_EN (1UL<<15) | |
96 | #define TURBO_TDP_MASK (0x0000000000003fffUL) | |
97 | ||
98 | /* | |
99 | * Core/thread MSRs for monitoring | |
100 | */ | |
101 | #define IA32_PERF_CTL 0x199 | |
102 | #define IA32_PERF_TURBO_DIS (1ULL<<32) | |
103 | ||
104 | /* | |
105 | * Thermal PCI device regs | |
106 | */ | |
107 | #define THM_CFG_TBAR 0x10 | |
108 | #define THM_CFG_TBAR_HI 0x14 | |
109 | ||
110 | #define THM_TSIU 0x00 | |
111 | #define THM_TSE 0x01 | |
112 | #define TSE_EN 0xb8 | |
113 | #define THM_TSS 0x02 | |
114 | #define THM_TSTR 0x03 | |
115 | #define THM_TSTTP 0x04 | |
116 | #define THM_TSCO 0x08 | |
117 | #define THM_TSES 0x0c | |
118 | #define THM_TSGPEN 0x0d | |
119 | #define TSGPEN_HOT_LOHI (1<<1) | |
120 | #define TSGPEN_CRIT_LOHI (1<<2) | |
121 | #define THM_TSPC 0x0e | |
122 | #define THM_PPEC 0x10 | |
123 | #define THM_CTA 0x12 | |
124 | #define THM_PTA 0x14 | |
125 | #define PTA_SLOPE_MASK (0xff00) | |
126 | #define PTA_SLOPE_SHIFT 8 | |
127 | #define PTA_OFFSET_MASK (0x00ff) | |
128 | #define THM_MGTA 0x16 | |
129 | #define MGTA_SLOPE_MASK (0xff00) | |
130 | #define MGTA_SLOPE_SHIFT 8 | |
131 | #define MGTA_OFFSET_MASK (0x00ff) | |
132 | #define THM_TRC 0x1a | |
133 | #define TRC_CORE2_EN (1<<15) | |
134 | #define TRC_THM_EN (1<<12) | |
135 | #define TRC_C6_WAR (1<<8) | |
136 | #define TRC_CORE1_EN (1<<7) | |
137 | #define TRC_CORE_PWR (1<<6) | |
138 | #define TRC_PCH_EN (1<<5) | |
139 | #define TRC_MCH_EN (1<<4) | |
140 | #define TRC_DIMM4 (1<<3) | |
141 | #define TRC_DIMM3 (1<<2) | |
142 | #define TRC_DIMM2 (1<<1) | |
143 | #define TRC_DIMM1 (1<<0) | |
144 | #define THM_TES 0x20 | |
145 | #define THM_TEN 0x21 | |
146 | #define TEN_UPDATE_EN 1 | |
147 | #define THM_PSC 0x24 | |
148 | #define PSC_NTG (1<<0) /* No GFX turbo support */ | |
149 | #define PSC_NTPC (1<<1) /* No CPU turbo support */ | |
150 | #define PSC_PP_DEF (0<<2) /* Perf policy up to driver */ | |
151 | #define PSP_PP_PC (1<<2) /* BIOS prefers CPU perf */ | |
152 | #define PSP_PP_BAL (2<<2) /* BIOS wants balanced perf */ | |
153 | #define PSP_PP_GFX (3<<2) /* BIOS prefers GFX perf */ | |
154 | #define PSP_PBRT (1<<4) /* BIOS run time support */ | |
155 | #define THM_CTV1 0x30 | |
156 | #define CTV_TEMP_ERROR (1<<15) | |
157 | #define CTV_TEMP_MASK 0x3f | |
158 | #define CTV_ | |
159 | #define THM_CTV2 0x32 | |
160 | #define THM_CEC 0x34 /* undocumented power accumulator in joules */ | |
161 | #define THM_AE 0x3f | |
162 | #define THM_HTS 0x50 /* 32 bits */ | |
163 | #define HTS_PCPL_MASK (0x7fe00000) | |
164 | #define HTS_PCPL_SHIFT 21 | |
165 | #define HTS_GPL_MASK (0x001ff000) | |
166 | #define HTS_GPL_SHIFT 12 | |
167 | #define HTS_PP_MASK (0x00000c00) | |
168 | #define HTS_PP_SHIFT 10 | |
169 | #define HTS_PP_DEF 0 | |
170 | #define HTS_PP_PROC 1 | |
171 | #define HTS_PP_BAL 2 | |
172 | #define HTS_PP_GFX 3 | |
173 | #define HTS_PCTD_DIS (1<<9) | |
174 | #define HTS_GTD_DIS (1<<8) | |
175 | #define HTS_PTL_MASK (0x000000fe) | |
176 | #define HTS_PTL_SHIFT 1 | |
177 | #define HTS_NVV (1<<0) | |
178 | #define THM_HTSHI 0x54 /* 16 bits */ | |
179 | #define HTS2_PPL_MASK (0x03ff) | |
180 | #define HTS2_PRST_MASK (0x3c00) | |
181 | #define HTS2_PRST_SHIFT 10 | |
182 | #define HTS2_PRST_UNLOADED 0 | |
183 | #define HTS2_PRST_RUNNING 1 | |
184 | #define HTS2_PRST_TDISOP 2 /* turbo disabled due to power */ | |
185 | #define HTS2_PRST_TDISHT 3 /* turbo disabled due to high temp */ | |
186 | #define HTS2_PRST_TDISUSR 4 /* user disabled turbo */ | |
187 | #define HTS2_PRST_TDISPLAT 5 /* platform disabled turbo */ | |
188 | #define HTS2_PRST_TDISPM 6 /* power management disabled turbo */ | |
189 | #define HTS2_PRST_TDISERR 7 /* some kind of error disabled turbo */ | |
190 | #define THM_PTL 0x56 | |
191 | #define THM_MGTV 0x58 | |
192 | #define TV_MASK 0x000000000000ff00 | |
193 | #define TV_SHIFT 8 | |
194 | #define THM_PTV 0x60 | |
195 | #define PTV_MASK 0x00ff | |
196 | #define THM_MMGPC 0x64 | |
197 | #define THM_MPPC 0x66 | |
198 | #define THM_MPCPC 0x68 | |
199 | #define THM_TSPIEN 0x82 | |
200 | #define TSPIEN_AUX_LOHI (1<<0) | |
201 | #define TSPIEN_HOT_LOHI (1<<1) | |
202 | #define TSPIEN_CRIT_LOHI (1<<2) | |
203 | #define TSPIEN_AUX2_LOHI (1<<3) | |
204 | #define THM_TSLOCK 0x83 | |
205 | #define THM_ATR 0x84 | |
206 | #define THM_TOF 0x87 | |
207 | #define THM_STS 0x98 | |
208 | #define STS_PCPL_MASK (0x7fe00000) | |
209 | #define STS_PCPL_SHIFT 21 | |
210 | #define STS_GPL_MASK (0x001ff000) | |
211 | #define STS_GPL_SHIFT 12 | |
212 | #define STS_PP_MASK (0x00000c00) | |
213 | #define STS_PP_SHIFT 10 | |
214 | #define STS_PP_DEF 0 | |
215 | #define STS_PP_PROC 1 | |
216 | #define STS_PP_BAL 2 | |
217 | #define STS_PP_GFX 3 | |
218 | #define STS_PCTD_DIS (1<<9) | |
219 | #define STS_GTD_DIS (1<<8) | |
220 | #define STS_PTL_MASK (0x000000fe) | |
221 | #define STS_PTL_SHIFT 1 | |
222 | #define STS_NVV (1<<0) | |
223 | #define THM_SEC 0x9c | |
224 | #define SEC_ACK (1<<0) | |
225 | #define THM_TC3 0xa4 | |
226 | #define THM_TC1 0xa8 | |
227 | #define STS_PPL_MASK (0x0003ff00) | |
228 | #define STS_PPL_SHIFT 16 | |
229 | #define THM_TC2 0xac | |
230 | #define THM_DTV 0xb0 | |
231 | #define THM_ITV 0xd8 | |
6230d18c | 232 | #define ITV_ME_SEQNO_MASK 0x00ff0000 /* ME should update every ~200ms */ |
aa7ffc01 JB |
233 | #define ITV_ME_SEQNO_SHIFT (16) |
234 | #define ITV_MCH_TEMP_MASK 0x0000ff00 | |
235 | #define ITV_MCH_TEMP_SHIFT (8) | |
236 | #define ITV_PCH_TEMP_MASK 0x000000ff | |
237 | ||
238 | #define thm_readb(off) readb(ips->regmap + (off)) | |
239 | #define thm_readw(off) readw(ips->regmap + (off)) | |
240 | #define thm_readl(off) readl(ips->regmap + (off)) | |
241 | #define thm_readq(off) readq(ips->regmap + (off)) | |
242 | ||
243 | #define thm_writeb(off, val) writeb((val), ips->regmap + (off)) | |
244 | #define thm_writew(off, val) writew((val), ips->regmap + (off)) | |
245 | #define thm_writel(off, val) writel((val), ips->regmap + (off)) | |
246 | ||
247 | static const int IPS_ADJUST_PERIOD = 5000; /* ms */ | |
248 | ||
249 | /* For initial average collection */ | |
250 | static const int IPS_SAMPLE_PERIOD = 200; /* ms */ | |
251 | static const int IPS_SAMPLE_WINDOW = 5000; /* 5s moving window of samples */ | |
252 | #define IPS_SAMPLE_COUNT (IPS_SAMPLE_WINDOW / IPS_SAMPLE_PERIOD) | |
253 | ||
254 | /* Per-SKU limits */ | |
255 | struct ips_mcp_limits { | |
256 | int cpu_family; | |
257 | int cpu_model; /* includes extended model... */ | |
258 | int mcp_power_limit; /* mW units */ | |
259 | int core_power_limit; | |
260 | int mch_power_limit; | |
261 | int core_temp_limit; /* degrees C */ | |
262 | int mch_temp_limit; | |
263 | }; | |
264 | ||
265 | /* Max temps are -10 degrees C to avoid PROCHOT# */ | |
266 | ||
267 | struct ips_mcp_limits ips_sv_limits = { | |
268 | .mcp_power_limit = 35000, | |
269 | .core_power_limit = 29000, | |
270 | .mch_power_limit = 20000, | |
271 | .core_temp_limit = 95, | |
272 | .mch_temp_limit = 90 | |
273 | }; | |
274 | ||
275 | struct ips_mcp_limits ips_lv_limits = { | |
276 | .mcp_power_limit = 25000, | |
277 | .core_power_limit = 21000, | |
278 | .mch_power_limit = 13000, | |
279 | .core_temp_limit = 95, | |
280 | .mch_temp_limit = 90 | |
281 | }; | |
282 | ||
283 | struct ips_mcp_limits ips_ulv_limits = { | |
284 | .mcp_power_limit = 18000, | |
285 | .core_power_limit = 14000, | |
286 | .mch_power_limit = 11000, | |
287 | .core_temp_limit = 95, | |
288 | .mch_temp_limit = 90 | |
289 | }; | |
290 | ||
291 | struct ips_driver { | |
292 | struct pci_dev *dev; | |
293 | void *regmap; | |
294 | struct task_struct *monitor; | |
295 | struct task_struct *adjust; | |
296 | struct dentry *debug_root; | |
297 | ||
298 | /* Average CPU core temps (all averages in .01 degrees C for precision) */ | |
299 | u16 ctv1_avg_temp; | |
300 | u16 ctv2_avg_temp; | |
301 | /* GMCH average */ | |
302 | u16 mch_avg_temp; | |
303 | /* Average for the CPU (both cores?) */ | |
304 | u16 mcp_avg_temp; | |
305 | /* Average power consumption (in mW) */ | |
306 | u32 cpu_avg_power; | |
307 | u32 mch_avg_power; | |
308 | ||
309 | /* Offset values */ | |
310 | u16 cta_val; | |
311 | u16 pta_val; | |
312 | u16 mgta_val; | |
313 | ||
314 | /* Maximums & prefs, protected by turbo status lock */ | |
315 | spinlock_t turbo_status_lock; | |
316 | u16 mcp_temp_limit; | |
317 | u16 mcp_power_limit; | |
318 | u16 core_power_limit; | |
319 | u16 mch_power_limit; | |
320 | bool cpu_turbo_enabled; | |
321 | bool __cpu_turbo_on; | |
322 | bool gpu_turbo_enabled; | |
323 | bool __gpu_turbo_on; | |
324 | bool gpu_preferred; | |
325 | bool poll_turbo_status; | |
326 | bool second_cpu; | |
354aeeb1 | 327 | bool turbo_toggle_allowed; |
aa7ffc01 JB |
328 | struct ips_mcp_limits *limits; |
329 | ||
330 | /* Optional MCH interfaces for if i915 is in use */ | |
331 | unsigned long (*read_mch_val)(void); | |
332 | bool (*gpu_raise)(void); | |
333 | bool (*gpu_lower)(void); | |
334 | bool (*gpu_busy)(void); | |
335 | bool (*gpu_turbo_disable)(void); | |
336 | ||
337 | /* For restoration at unload */ | |
338 | u64 orig_turbo_limit; | |
339 | u64 orig_turbo_ratios; | |
340 | }; | |
341 | ||
342 | /** | |
343 | * ips_cpu_busy - is CPU busy? | |
344 | * @ips: IPS driver struct | |
345 | * | |
346 | * Check CPU for load to see whether we should increase its thermal budget. | |
347 | * | |
348 | * RETURNS: | |
349 | * True if the CPU could use more power, false otherwise. | |
350 | */ | |
351 | static bool ips_cpu_busy(struct ips_driver *ips) | |
352 | { | |
353 | if ((avenrun[0] >> FSHIFT) > 1) | |
354 | return true; | |
355 | ||
356 | return false; | |
357 | } | |
358 | ||
359 | /** | |
360 | * ips_cpu_raise - raise CPU power clamp | |
361 | * @ips: IPS driver struct | |
362 | * | |
363 | * Raise the CPU power clamp by %IPS_CPU_STEP, in accordance with TDP for | |
364 | * this platform. | |
365 | * | |
366 | * We do this by adjusting the TURBO_POWER_CURRENT_LIMIT MSR upwards (as | |
367 | * long as we haven't hit the TDP limit for the SKU). | |
368 | */ | |
369 | static void ips_cpu_raise(struct ips_driver *ips) | |
370 | { | |
371 | u64 turbo_override; | |
372 | u16 cur_tdp_limit, new_tdp_limit; | |
373 | ||
374 | if (!ips->cpu_turbo_enabled) | |
375 | return; | |
376 | ||
377 | rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); | |
378 | ||
379 | cur_tdp_limit = turbo_override & TURBO_TDP_MASK; | |
380 | new_tdp_limit = cur_tdp_limit + 8; /* 1W increase */ | |
381 | ||
382 | /* Clamp to SKU TDP limit */ | |
383 | if (((new_tdp_limit * 10) / 8) > ips->core_power_limit) | |
384 | new_tdp_limit = cur_tdp_limit; | |
385 | ||
386 | thm_writew(THM_MPCPC, (new_tdp_limit * 10) / 8); | |
387 | ||
388 | turbo_override |= TURBO_TDC_OVR_EN | TURBO_TDC_OVR_EN; | |
389 | wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); | |
390 | ||
391 | turbo_override &= ~TURBO_TDP_MASK; | |
392 | turbo_override |= new_tdp_limit; | |
393 | ||
394 | wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); | |
395 | } | |
396 | ||
397 | /** | |
398 | * ips_cpu_lower - lower CPU power clamp | |
399 | * @ips: IPS driver struct | |
400 | * | |
401 | * Lower CPU power clamp b %IPS_CPU_STEP if possible. | |
402 | * | |
403 | * We do this by adjusting the TURBO_POWER_CURRENT_LIMIT MSR down, going | |
404 | * as low as the platform limits will allow (though we could go lower there | |
405 | * wouldn't be much point). | |
406 | */ | |
407 | static void ips_cpu_lower(struct ips_driver *ips) | |
408 | { | |
409 | u64 turbo_override; | |
410 | u16 cur_limit, new_limit; | |
411 | ||
412 | rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); | |
413 | ||
414 | cur_limit = turbo_override & TURBO_TDP_MASK; | |
415 | new_limit = cur_limit - 8; /* 1W decrease */ | |
416 | ||
417 | /* Clamp to SKU TDP limit */ | |
418 | if (((new_limit * 10) / 8) < (ips->orig_turbo_limit & TURBO_TDP_MASK)) | |
419 | new_limit = ips->orig_turbo_limit & TURBO_TDP_MASK; | |
420 | ||
421 | thm_writew(THM_MPCPC, (new_limit * 10) / 8); | |
422 | ||
423 | turbo_override |= TURBO_TDC_OVR_EN | TURBO_TDC_OVR_EN; | |
424 | wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); | |
425 | ||
426 | turbo_override &= ~TURBO_TDP_MASK; | |
427 | turbo_override |= new_limit; | |
428 | ||
429 | wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); | |
430 | } | |
431 | ||
432 | /** | |
433 | * do_enable_cpu_turbo - internal turbo enable function | |
434 | * @data: unused | |
435 | * | |
436 | * Internal function for actually updating MSRs. When we enable/disable | |
437 | * turbo, we need to do it on each CPU; this function is the one called | |
438 | * by on_each_cpu() when needed. | |
439 | */ | |
440 | static void do_enable_cpu_turbo(void *data) | |
441 | { | |
442 | u64 perf_ctl; | |
443 | ||
444 | rdmsrl(IA32_PERF_CTL, perf_ctl); | |
445 | if (perf_ctl & IA32_PERF_TURBO_DIS) { | |
446 | perf_ctl &= ~IA32_PERF_TURBO_DIS; | |
447 | wrmsrl(IA32_PERF_CTL, perf_ctl); | |
448 | } | |
449 | } | |
450 | ||
451 | /** | |
452 | * ips_enable_cpu_turbo - enable turbo mode on all CPUs | |
453 | * @ips: IPS driver struct | |
454 | * | |
455 | * Enable turbo mode by clearing the disable bit in IA32_PERF_CTL on | |
456 | * all logical threads. | |
457 | */ | |
458 | static void ips_enable_cpu_turbo(struct ips_driver *ips) | |
459 | { | |
460 | /* Already on, no need to mess with MSRs */ | |
461 | if (ips->__cpu_turbo_on) | |
462 | return; | |
463 | ||
354aeeb1 JB |
464 | if (ips->turbo_toggle_allowed) |
465 | on_each_cpu(do_enable_cpu_turbo, ips, 1); | |
aa7ffc01 JB |
466 | |
467 | ips->__cpu_turbo_on = true; | |
468 | } | |
469 | ||
470 | /** | |
471 | * do_disable_cpu_turbo - internal turbo disable function | |
472 | * @data: unused | |
473 | * | |
474 | * Internal function for actually updating MSRs. When we enable/disable | |
475 | * turbo, we need to do it on each CPU; this function is the one called | |
476 | * by on_each_cpu() when needed. | |
477 | */ | |
478 | static void do_disable_cpu_turbo(void *data) | |
479 | { | |
480 | u64 perf_ctl; | |
481 | ||
482 | rdmsrl(IA32_PERF_CTL, perf_ctl); | |
483 | if (!(perf_ctl & IA32_PERF_TURBO_DIS)) { | |
484 | perf_ctl |= IA32_PERF_TURBO_DIS; | |
485 | wrmsrl(IA32_PERF_CTL, perf_ctl); | |
486 | } | |
487 | } | |
488 | ||
489 | /** | |
490 | * ips_disable_cpu_turbo - disable turbo mode on all CPUs | |
491 | * @ips: IPS driver struct | |
492 | * | |
493 | * Disable turbo mode by setting the disable bit in IA32_PERF_CTL on | |
494 | * all logical threads. | |
495 | */ | |
496 | static void ips_disable_cpu_turbo(struct ips_driver *ips) | |
497 | { | |
498 | /* Already off, leave it */ | |
499 | if (!ips->__cpu_turbo_on) | |
500 | return; | |
501 | ||
354aeeb1 JB |
502 | if (ips->turbo_toggle_allowed) |
503 | on_each_cpu(do_disable_cpu_turbo, ips, 1); | |
aa7ffc01 JB |
504 | |
505 | ips->__cpu_turbo_on = false; | |
506 | } | |
507 | ||
508 | /** | |
509 | * ips_gpu_busy - is GPU busy? | |
510 | * @ips: IPS driver struct | |
511 | * | |
512 | * Check GPU for load to see whether we should increase its thermal budget. | |
513 | * We need to call into the i915 driver in this case. | |
514 | * | |
515 | * RETURNS: | |
516 | * True if the GPU could use more power, false otherwise. | |
517 | */ | |
518 | static bool ips_gpu_busy(struct ips_driver *ips) | |
519 | { | |
0385e521 JB |
520 | if (!ips->gpu_turbo_enabled) |
521 | return false; | |
522 | ||
523 | return ips->gpu_busy(); | |
aa7ffc01 JB |
524 | } |
525 | ||
526 | /** | |
527 | * ips_gpu_raise - raise GPU power clamp | |
528 | * @ips: IPS driver struct | |
529 | * | |
530 | * Raise the GPU frequency/power if possible. We need to call into the | |
531 | * i915 driver in this case. | |
532 | */ | |
533 | static void ips_gpu_raise(struct ips_driver *ips) | |
534 | { | |
535 | if (!ips->gpu_turbo_enabled) | |
536 | return; | |
537 | ||
538 | if (!ips->gpu_raise()) | |
539 | ips->gpu_turbo_enabled = false; | |
540 | ||
541 | return; | |
542 | } | |
543 | ||
544 | /** | |
545 | * ips_gpu_lower - lower GPU power clamp | |
546 | * @ips: IPS driver struct | |
547 | * | |
548 | * Lower GPU frequency/power if possible. Need to call i915. | |
549 | */ | |
550 | static void ips_gpu_lower(struct ips_driver *ips) | |
551 | { | |
552 | if (!ips->gpu_turbo_enabled) | |
553 | return; | |
554 | ||
555 | if (!ips->gpu_lower()) | |
556 | ips->gpu_turbo_enabled = false; | |
557 | ||
558 | return; | |
559 | } | |
560 | ||
561 | /** | |
562 | * ips_enable_gpu_turbo - notify the gfx driver turbo is available | |
563 | * @ips: IPS driver struct | |
564 | * | |
565 | * Call into the graphics driver indicating that it can safely use | |
566 | * turbo mode. | |
567 | */ | |
568 | static void ips_enable_gpu_turbo(struct ips_driver *ips) | |
569 | { | |
570 | if (ips->__gpu_turbo_on) | |
571 | return; | |
572 | ips->__gpu_turbo_on = true; | |
573 | } | |
574 | ||
575 | /** | |
576 | * ips_disable_gpu_turbo - notify the gfx driver to disable turbo mode | |
577 | * @ips: IPS driver struct | |
578 | * | |
579 | * Request that the graphics driver disable turbo mode. | |
580 | */ | |
581 | static void ips_disable_gpu_turbo(struct ips_driver *ips) | |
582 | { | |
583 | /* Avoid calling i915 if turbo is already disabled */ | |
584 | if (!ips->__gpu_turbo_on) | |
585 | return; | |
586 | ||
587 | if (!ips->gpu_turbo_disable()) | |
588 | dev_err(&ips->dev->dev, "failed to disable graphis turbo\n"); | |
589 | else | |
590 | ips->__gpu_turbo_on = false; | |
591 | } | |
592 | ||
593 | /** | |
594 | * mcp_exceeded - check whether we're outside our thermal & power limits | |
595 | * @ips: IPS driver struct | |
596 | * | |
597 | * Check whether the MCP is over its thermal or power budget. | |
598 | */ | |
599 | static bool mcp_exceeded(struct ips_driver *ips) | |
600 | { | |
601 | unsigned long flags; | |
602 | bool ret = false; | |
a8c096ad TG |
603 | u32 temp_limit; |
604 | u32 avg_power; | |
605 | const char *msg = "MCP limit exceeded: "; | |
aa7ffc01 JB |
606 | |
607 | spin_lock_irqsave(&ips->turbo_status_lock, flags); | |
a8c096ad TG |
608 | |
609 | temp_limit = ips->mcp_temp_limit * 100; | |
610 | if (ips->mcp_avg_temp > temp_limit) { | |
611 | dev_info(&ips->dev->dev, | |
612 | "%sAvg temp %u, limit %u\n", msg, ips->mcp_avg_temp, | |
613 | temp_limit); | |
aa7ffc01 | 614 | ret = true; |
a8c096ad | 615 | } |
aa7ffc01 | 616 | |
a8c096ad TG |
617 | avg_power = ips->cpu_avg_power + ips->mch_avg_power; |
618 | if (avg_power > ips->mcp_power_limit) { | |
1a14703d | 619 | dev_info(&ips->dev->dev, |
a8c096ad TG |
620 | "%sAvg power %u, limit %u\n", msg, avg_power, |
621 | ips->mcp_power_limit); | |
622 | ret = true; | |
623 | } | |
624 | ||
625 | spin_unlock_irqrestore(&ips->turbo_status_lock, flags); | |
aa7ffc01 JB |
626 | |
627 | return ret; | |
628 | } | |
629 | ||
630 | /** | |
631 | * cpu_exceeded - check whether a CPU core is outside its limits | |
632 | * @ips: IPS driver struct | |
633 | * @cpu: CPU number to check | |
634 | * | |
635 | * Check a given CPU's average temp or power is over its limit. | |
636 | */ | |
637 | static bool cpu_exceeded(struct ips_driver *ips, int cpu) | |
638 | { | |
639 | unsigned long flags; | |
640 | int avg; | |
641 | bool ret = false; | |
642 | ||
643 | spin_lock_irqsave(&ips->turbo_status_lock, flags); | |
644 | avg = cpu ? ips->ctv2_avg_temp : ips->ctv1_avg_temp; | |
645 | if (avg > (ips->limits->core_temp_limit * 100)) | |
646 | ret = true; | |
0385e521 | 647 | if (ips->cpu_avg_power > ips->core_power_limit * 100) |
aa7ffc01 JB |
648 | ret = true; |
649 | spin_unlock_irqrestore(&ips->turbo_status_lock, flags); | |
650 | ||
651 | if (ret) | |
1a14703d | 652 | dev_info(&ips->dev->dev, |
aa7ffc01 JB |
653 | "CPU power or thermal limit exceeded\n"); |
654 | ||
655 | return ret; | |
656 | } | |
657 | ||
658 | /** | |
659 | * mch_exceeded - check whether the GPU is over budget | |
660 | * @ips: IPS driver struct | |
661 | * | |
662 | * Check the MCH temp & power against their maximums. | |
663 | */ | |
664 | static bool mch_exceeded(struct ips_driver *ips) | |
665 | { | |
666 | unsigned long flags; | |
667 | bool ret = false; | |
668 | ||
669 | spin_lock_irqsave(&ips->turbo_status_lock, flags); | |
670 | if (ips->mch_avg_temp > (ips->limits->mch_temp_limit * 100)) | |
671 | ret = true; | |
0385e521 JB |
672 | if (ips->mch_avg_power > ips->mch_power_limit) |
673 | ret = true; | |
aa7ffc01 JB |
674 | spin_unlock_irqrestore(&ips->turbo_status_lock, flags); |
675 | ||
676 | return ret; | |
677 | } | |
678 | ||
eceab272 JB |
679 | /** |
680 | * verify_limits - verify BIOS provided limits | |
681 | * @ips: IPS structure | |
682 | * | |
683 | * BIOS can optionally provide non-default limits for power and temp. Check | |
684 | * them here and use the defaults if the BIOS values are not provided or | |
685 | * are otherwise unusable. | |
686 | */ | |
687 | static void verify_limits(struct ips_driver *ips) | |
688 | { | |
689 | if (ips->mcp_power_limit < ips->limits->mcp_power_limit || | |
690 | ips->mcp_power_limit > 35000) | |
691 | ips->mcp_power_limit = ips->limits->mcp_power_limit; | |
692 | ||
693 | if (ips->mcp_temp_limit < ips->limits->core_temp_limit || | |
694 | ips->mcp_temp_limit < ips->limits->mch_temp_limit || | |
695 | ips->mcp_temp_limit > 150) | |
696 | ips->mcp_temp_limit = min(ips->limits->core_temp_limit, | |
697 | ips->limits->mch_temp_limit); | |
698 | } | |
699 | ||
aa7ffc01 JB |
700 | /** |
701 | * update_turbo_limits - get various limits & settings from regs | |
702 | * @ips: IPS driver struct | |
703 | * | |
704 | * Update the IPS power & temp limits, along with turbo enable flags, | |
705 | * based on latest register contents. | |
706 | * | |
707 | * Used at init time and for runtime BIOS support, which requires polling | |
708 | * the regs for updates (as a result of AC->DC transition for example). | |
709 | * | |
710 | * LOCKING: | |
711 | * Caller must hold turbo_status_lock (outside of init) | |
712 | */ | |
713 | static void update_turbo_limits(struct ips_driver *ips) | |
714 | { | |
715 | u32 hts = thm_readl(THM_HTS); | |
716 | ||
717 | ips->cpu_turbo_enabled = !(hts & HTS_PCTD_DIS); | |
070c0ee1 AW |
718 | if (ips->gpu_busy) |
719 | ips->gpu_turbo_enabled = !(hts & HTS_GTD_DIS); | |
aa7ffc01 JB |
720 | ips->core_power_limit = thm_readw(THM_MPCPC); |
721 | ips->mch_power_limit = thm_readw(THM_MMGPC); | |
722 | ips->mcp_temp_limit = thm_readw(THM_PTL); | |
723 | ips->mcp_power_limit = thm_readw(THM_MPPC); | |
724 | ||
eceab272 | 725 | verify_limits(ips); |
aa7ffc01 JB |
726 | /* Ignore BIOS CPU vs GPU pref */ |
727 | } | |
728 | ||
729 | /** | |
730 | * ips_adjust - adjust power clamp based on thermal state | |
731 | * @data: ips driver structure | |
732 | * | |
733 | * Wake up every 5s or so and check whether we should adjust the power clamp. | |
734 | * Check CPU and GPU load to determine which needs adjustment. There are | |
735 | * several things to consider here: | |
736 | * - do we need to adjust up or down? | |
737 | * - is CPU busy? | |
738 | * - is GPU busy? | |
739 | * - is CPU in turbo? | |
740 | * - is GPU in turbo? | |
741 | * - is CPU or GPU preferred? (CPU is default) | |
742 | * | |
743 | * So, given the above, we do the following: | |
744 | * - up (TDP available) | |
745 | * - CPU not busy, GPU not busy - nothing | |
746 | * - CPU busy, GPU not busy - adjust CPU up | |
747 | * - CPU not busy, GPU busy - adjust GPU up | |
748 | * - CPU busy, GPU busy - adjust preferred unit up, taking headroom from | |
749 | * non-preferred unit if necessary | |
750 | * - down (at TDP limit) | |
751 | * - adjust both CPU and GPU down if possible | |
752 | * | |
753 | cpu+ gpu+ cpu+gpu- cpu-gpu+ cpu-gpu- | |
754 | cpu < gpu < cpu+gpu+ cpu+ gpu+ nothing | |
755 | cpu < gpu >= cpu+gpu-(mcp<) cpu+gpu-(mcp<) gpu- gpu- | |
756 | cpu >= gpu < cpu-gpu+(mcp<) cpu- cpu-gpu+(mcp<) cpu- | |
757 | cpu >= gpu >= cpu-gpu- cpu-gpu- cpu-gpu- cpu-gpu- | |
758 | * | |
759 | */ | |
760 | static int ips_adjust(void *data) | |
761 | { | |
762 | struct ips_driver *ips = data; | |
763 | unsigned long flags; | |
764 | ||
765 | dev_dbg(&ips->dev->dev, "starting ips-adjust thread\n"); | |
766 | ||
767 | /* | |
768 | * Adjust CPU and GPU clamps every 5s if needed. Doing it more | |
769 | * often isn't recommended due to ME interaction. | |
770 | */ | |
771 | do { | |
772 | bool cpu_busy = ips_cpu_busy(ips); | |
773 | bool gpu_busy = ips_gpu_busy(ips); | |
774 | ||
775 | spin_lock_irqsave(&ips->turbo_status_lock, flags); | |
776 | if (ips->poll_turbo_status) | |
777 | update_turbo_limits(ips); | |
778 | spin_unlock_irqrestore(&ips->turbo_status_lock, flags); | |
779 | ||
780 | /* Update turbo status if necessary */ | |
781 | if (ips->cpu_turbo_enabled) | |
782 | ips_enable_cpu_turbo(ips); | |
783 | else | |
784 | ips_disable_cpu_turbo(ips); | |
785 | ||
786 | if (ips->gpu_turbo_enabled) | |
787 | ips_enable_gpu_turbo(ips); | |
788 | else | |
789 | ips_disable_gpu_turbo(ips); | |
790 | ||
791 | /* We're outside our comfort zone, crank them down */ | |
0385e521 | 792 | if (mcp_exceeded(ips)) { |
aa7ffc01 JB |
793 | ips_cpu_lower(ips); |
794 | ips_gpu_lower(ips); | |
795 | goto sleep; | |
796 | } | |
797 | ||
798 | if (!cpu_exceeded(ips, 0) && cpu_busy) | |
799 | ips_cpu_raise(ips); | |
800 | else | |
801 | ips_cpu_lower(ips); | |
802 | ||
803 | if (!mch_exceeded(ips) && gpu_busy) | |
804 | ips_gpu_raise(ips); | |
805 | else | |
806 | ips_gpu_lower(ips); | |
807 | ||
808 | sleep: | |
809 | schedule_timeout_interruptible(msecs_to_jiffies(IPS_ADJUST_PERIOD)); | |
810 | } while (!kthread_should_stop()); | |
811 | ||
812 | dev_dbg(&ips->dev->dev, "ips-adjust thread stopped\n"); | |
813 | ||
814 | return 0; | |
815 | } | |
816 | ||
817 | /* | |
818 | * Helpers for reading out temp/power values and calculating their | |
819 | * averages for the decision making and monitoring functions. | |
820 | */ | |
821 | ||
822 | static u16 calc_avg_temp(struct ips_driver *ips, u16 *array) | |
823 | { | |
824 | u64 total = 0; | |
825 | int i; | |
826 | u16 avg; | |
827 | ||
828 | for (i = 0; i < IPS_SAMPLE_COUNT; i++) | |
829 | total += (u64)(array[i] * 100); | |
830 | ||
831 | do_div(total, IPS_SAMPLE_COUNT); | |
832 | ||
833 | avg = (u16)total; | |
834 | ||
835 | return avg; | |
836 | } | |
837 | ||
838 | static u16 read_mgtv(struct ips_driver *ips) | |
839 | { | |
840 | u16 ret; | |
841 | u64 slope, offset; | |
842 | u64 val; | |
843 | ||
844 | val = thm_readq(THM_MGTV); | |
845 | val = (val & TV_MASK) >> TV_SHIFT; | |
846 | ||
847 | slope = offset = thm_readw(THM_MGTA); | |
848 | slope = (slope & MGTA_SLOPE_MASK) >> MGTA_SLOPE_SHIFT; | |
849 | offset = offset & MGTA_OFFSET_MASK; | |
850 | ||
851 | ret = ((val * slope + 0x40) >> 7) + offset; | |
852 | ||
0385e521 | 853 | return 0; /* MCH temp reporting buggy */ |
aa7ffc01 JB |
854 | } |
855 | ||
856 | static u16 read_ptv(struct ips_driver *ips) | |
857 | { | |
858 | u16 val, slope, offset; | |
859 | ||
860 | slope = (ips->pta_val & PTA_SLOPE_MASK) >> PTA_SLOPE_SHIFT; | |
861 | offset = ips->pta_val & PTA_OFFSET_MASK; | |
862 | ||
863 | val = thm_readw(THM_PTV) & PTV_MASK; | |
864 | ||
865 | return val; | |
866 | } | |
867 | ||
868 | static u16 read_ctv(struct ips_driver *ips, int cpu) | |
869 | { | |
870 | int reg = cpu ? THM_CTV2 : THM_CTV1; | |
871 | u16 val; | |
872 | ||
873 | val = thm_readw(reg); | |
874 | if (!(val & CTV_TEMP_ERROR)) | |
875 | val = (val) >> 6; /* discard fractional component */ | |
876 | else | |
877 | val = 0; | |
878 | ||
879 | return val; | |
880 | } | |
881 | ||
882 | static u32 get_cpu_power(struct ips_driver *ips, u32 *last, int period) | |
883 | { | |
884 | u32 val; | |
885 | u32 ret; | |
886 | ||
887 | /* | |
888 | * CEC is in joules/65535. Take difference over time to | |
889 | * get watts. | |
890 | */ | |
891 | val = thm_readl(THM_CEC); | |
892 | ||
893 | /* period is in ms and we want mW */ | |
894 | ret = (((val - *last) * 1000) / period); | |
895 | ret = (ret * 1000) / 65535; | |
896 | *last = val; | |
897 | ||
898 | return ret; | |
899 | } | |
900 | ||
901 | static const u16 temp_decay_factor = 2; | |
902 | static u16 update_average_temp(u16 avg, u16 val) | |
903 | { | |
904 | u16 ret; | |
905 | ||
906 | /* Multiply by 100 for extra precision */ | |
907 | ret = (val * 100 / temp_decay_factor) + | |
908 | (((temp_decay_factor - 1) * avg) / temp_decay_factor); | |
909 | return ret; | |
910 | } | |
911 | ||
912 | static const u16 power_decay_factor = 2; | |
913 | static u16 update_average_power(u32 avg, u32 val) | |
914 | { | |
915 | u32 ret; | |
916 | ||
917 | ret = (val / power_decay_factor) + | |
918 | (((power_decay_factor - 1) * avg) / power_decay_factor); | |
919 | ||
920 | return ret; | |
921 | } | |
922 | ||
923 | static u32 calc_avg_power(struct ips_driver *ips, u32 *array) | |
924 | { | |
925 | u64 total = 0; | |
926 | u32 avg; | |
927 | int i; | |
928 | ||
929 | for (i = 0; i < IPS_SAMPLE_COUNT; i++) | |
930 | total += array[i]; | |
931 | ||
932 | do_div(total, IPS_SAMPLE_COUNT); | |
933 | avg = (u32)total; | |
934 | ||
935 | return avg; | |
936 | } | |
937 | ||
938 | static void monitor_timeout(unsigned long arg) | |
939 | { | |
940 | wake_up_process((struct task_struct *)arg); | |
941 | } | |
942 | ||
943 | /** | |
944 | * ips_monitor - temp/power monitoring thread | |
945 | * @data: ips driver structure | |
946 | * | |
947 | * This is the main function for the IPS driver. It monitors power and | |
948 | * tempurature in the MCP and adjusts CPU and GPU power clams accordingly. | |
949 | * | |
950 | * We keep a 5s moving average of power consumption and tempurature. Using | |
951 | * that data, along with CPU vs GPU preference, we adjust the power clamps | |
952 | * up or down. | |
953 | */ | |
954 | static int ips_monitor(void *data) | |
955 | { | |
956 | struct ips_driver *ips = data; | |
957 | struct timer_list timer; | |
958 | unsigned long seqno_timestamp, expire, last_msecs, last_sample_period; | |
959 | int i; | |
e9ec7f35 JS |
960 | u32 *cpu_samples, *mchp_samples, old_cpu_power; |
961 | u16 *mcp_samples, *ctv1_samples, *ctv2_samples, *mch_samples; | |
aa7ffc01 JB |
962 | u8 cur_seqno, last_seqno; |
963 | ||
964 | mcp_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL); | |
965 | ctv1_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL); | |
966 | ctv2_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL); | |
967 | mch_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL); | |
968 | cpu_samples = kzalloc(sizeof(u32) * IPS_SAMPLE_COUNT, GFP_KERNEL); | |
969 | mchp_samples = kzalloc(sizeof(u32) * IPS_SAMPLE_COUNT, GFP_KERNEL); | |
e9ec7f35 JS |
970 | if (!mcp_samples || !ctv1_samples || !ctv2_samples || !mch_samples || |
971 | !cpu_samples || !mchp_samples) { | |
aa7ffc01 JB |
972 | dev_err(&ips->dev->dev, |
973 | "failed to allocate sample array, ips disabled\n"); | |
974 | kfree(mcp_samples); | |
975 | kfree(ctv1_samples); | |
976 | kfree(ctv2_samples); | |
977 | kfree(mch_samples); | |
978 | kfree(cpu_samples); | |
e9ec7f35 | 979 | kfree(mchp_samples); |
aa7ffc01 JB |
980 | return -ENOMEM; |
981 | } | |
982 | ||
983 | last_seqno = (thm_readl(THM_ITV) & ITV_ME_SEQNO_MASK) >> | |
984 | ITV_ME_SEQNO_SHIFT; | |
985 | seqno_timestamp = get_jiffies_64(); | |
986 | ||
c21eae4f | 987 | old_cpu_power = thm_readl(THM_CEC); |
aa7ffc01 JB |
988 | schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD)); |
989 | ||
990 | /* Collect an initial average */ | |
991 | for (i = 0; i < IPS_SAMPLE_COUNT; i++) { | |
992 | u32 mchp, cpu_power; | |
993 | u16 val; | |
994 | ||
995 | mcp_samples[i] = read_ptv(ips); | |
996 | ||
997 | val = read_ctv(ips, 0); | |
998 | ctv1_samples[i] = val; | |
999 | ||
1000 | val = read_ctv(ips, 1); | |
1001 | ctv2_samples[i] = val; | |
1002 | ||
1003 | val = read_mgtv(ips); | |
1004 | mch_samples[i] = val; | |
1005 | ||
1006 | cpu_power = get_cpu_power(ips, &old_cpu_power, | |
1007 | IPS_SAMPLE_PERIOD); | |
1008 | cpu_samples[i] = cpu_power; | |
1009 | ||
1010 | if (ips->read_mch_val) { | |
1011 | mchp = ips->read_mch_val(); | |
1012 | mchp_samples[i] = mchp; | |
1013 | } | |
1014 | ||
1015 | schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD)); | |
1016 | if (kthread_should_stop()) | |
1017 | break; | |
1018 | } | |
1019 | ||
1020 | ips->mcp_avg_temp = calc_avg_temp(ips, mcp_samples); | |
1021 | ips->ctv1_avg_temp = calc_avg_temp(ips, ctv1_samples); | |
1022 | ips->ctv2_avg_temp = calc_avg_temp(ips, ctv2_samples); | |
1023 | ips->mch_avg_temp = calc_avg_temp(ips, mch_samples); | |
1024 | ips->cpu_avg_power = calc_avg_power(ips, cpu_samples); | |
1025 | ips->mch_avg_power = calc_avg_power(ips, mchp_samples); | |
1026 | kfree(mcp_samples); | |
1027 | kfree(ctv1_samples); | |
1028 | kfree(ctv2_samples); | |
1029 | kfree(mch_samples); | |
1030 | kfree(cpu_samples); | |
1031 | kfree(mchp_samples); | |
1032 | ||
1033 | /* Start the adjustment thread now that we have data */ | |
1034 | wake_up_process(ips->adjust); | |
1035 | ||
1036 | /* | |
1037 | * Ok, now we have an initial avg. From here on out, we track the | |
1038 | * running avg using a decaying average calculation. This allows | |
1039 | * us to reduce the sample frequency if the CPU and GPU are idle. | |
1040 | */ | |
1041 | old_cpu_power = thm_readl(THM_CEC); | |
1042 | schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD)); | |
1043 | last_sample_period = IPS_SAMPLE_PERIOD; | |
1044 | ||
1045 | setup_deferrable_timer_on_stack(&timer, monitor_timeout, | |
1046 | (unsigned long)current); | |
1047 | do { | |
1048 | u32 cpu_val, mch_val; | |
1049 | u16 val; | |
1050 | ||
1051 | /* MCP itself */ | |
1052 | val = read_ptv(ips); | |
1053 | ips->mcp_avg_temp = update_average_temp(ips->mcp_avg_temp, val); | |
1054 | ||
1055 | /* Processor 0 */ | |
1056 | val = read_ctv(ips, 0); | |
1057 | ips->ctv1_avg_temp = | |
1058 | update_average_temp(ips->ctv1_avg_temp, val); | |
1059 | /* Power */ | |
1060 | cpu_val = get_cpu_power(ips, &old_cpu_power, | |
1061 | last_sample_period); | |
1062 | ips->cpu_avg_power = | |
1063 | update_average_power(ips->cpu_avg_power, cpu_val); | |
1064 | ||
1065 | if (ips->second_cpu) { | |
1066 | /* Processor 1 */ | |
1067 | val = read_ctv(ips, 1); | |
1068 | ips->ctv2_avg_temp = | |
1069 | update_average_temp(ips->ctv2_avg_temp, val); | |
1070 | } | |
1071 | ||
1072 | /* MCH */ | |
1073 | val = read_mgtv(ips); | |
1074 | ips->mch_avg_temp = update_average_temp(ips->mch_avg_temp, val); | |
1075 | /* Power */ | |
1076 | if (ips->read_mch_val) { | |
1077 | mch_val = ips->read_mch_val(); | |
1078 | ips->mch_avg_power = | |
1079 | update_average_power(ips->mch_avg_power, | |
1080 | mch_val); | |
1081 | } | |
1082 | ||
1083 | /* | |
1084 | * Make sure ME is updating thermal regs. | |
1085 | * Note: | |
1086 | * If it's been more than a second since the last update, | |
1087 | * the ME is probably hung. | |
1088 | */ | |
1089 | cur_seqno = (thm_readl(THM_ITV) & ITV_ME_SEQNO_MASK) >> | |
1090 | ITV_ME_SEQNO_SHIFT; | |
1091 | if (cur_seqno == last_seqno && | |
1092 | time_after(jiffies, seqno_timestamp + HZ)) { | |
1093 | dev_warn(&ips->dev->dev, "ME failed to update for more than 1s, likely hung\n"); | |
1094 | } else { | |
1095 | seqno_timestamp = get_jiffies_64(); | |
1096 | last_seqno = cur_seqno; | |
1097 | } | |
1098 | ||
1099 | last_msecs = jiffies_to_msecs(jiffies); | |
1100 | expire = jiffies + msecs_to_jiffies(IPS_SAMPLE_PERIOD); | |
1101 | ||
1102 | __set_current_state(TASK_UNINTERRUPTIBLE); | |
1103 | mod_timer(&timer, expire); | |
1104 | schedule(); | |
1105 | ||
1106 | /* Calculate actual sample period for power averaging */ | |
1107 | last_sample_period = jiffies_to_msecs(jiffies) - last_msecs; | |
1108 | if (!last_sample_period) | |
1109 | last_sample_period = 1; | |
1110 | } while (!kthread_should_stop()); | |
1111 | ||
1112 | del_timer_sync(&timer); | |
1113 | destroy_timer_on_stack(&timer); | |
1114 | ||
1115 | dev_dbg(&ips->dev->dev, "ips-monitor thread stopped\n"); | |
1116 | ||
1117 | return 0; | |
1118 | } | |
1119 | ||
1120 | #if 0 | |
1121 | #define THM_DUMPW(reg) \ | |
1122 | { \ | |
1123 | u16 val = thm_readw(reg); \ | |
1124 | dev_dbg(&ips->dev->dev, #reg ": 0x%04x\n", val); \ | |
1125 | } | |
1126 | #define THM_DUMPL(reg) \ | |
1127 | { \ | |
1128 | u32 val = thm_readl(reg); \ | |
1129 | dev_dbg(&ips->dev->dev, #reg ": 0x%08x\n", val); \ | |
1130 | } | |
1131 | #define THM_DUMPQ(reg) \ | |
1132 | { \ | |
1133 | u64 val = thm_readq(reg); \ | |
1134 | dev_dbg(&ips->dev->dev, #reg ": 0x%016x\n", val); \ | |
1135 | } | |
1136 | ||
1137 | static void dump_thermal_info(struct ips_driver *ips) | |
1138 | { | |
1139 | u16 ptl; | |
1140 | ||
1141 | ptl = thm_readw(THM_PTL); | |
1142 | dev_dbg(&ips->dev->dev, "Processor temp limit: %d\n", ptl); | |
1143 | ||
1144 | THM_DUMPW(THM_CTA); | |
1145 | THM_DUMPW(THM_TRC); | |
1146 | THM_DUMPW(THM_CTV1); | |
1147 | THM_DUMPL(THM_STS); | |
1148 | THM_DUMPW(THM_PTV); | |
1149 | THM_DUMPQ(THM_MGTV); | |
1150 | } | |
1151 | #endif | |
1152 | ||
1153 | /** | |
1154 | * ips_irq_handler - handle temperature triggers and other IPS events | |
1155 | * @irq: irq number | |
1156 | * @arg: unused | |
1157 | * | |
1158 | * Handle temperature limit trigger events, generally by lowering the clamps. | |
1159 | * If we're at a critical limit, we clamp back to the lowest possible value | |
1160 | * to prevent emergency shutdown. | |
1161 | */ | |
1162 | static irqreturn_t ips_irq_handler(int irq, void *arg) | |
1163 | { | |
1164 | struct ips_driver *ips = arg; | |
1165 | u8 tses = thm_readb(THM_TSES); | |
1166 | u8 tes = thm_readb(THM_TES); | |
1167 | ||
1168 | if (!tses && !tes) | |
1169 | return IRQ_NONE; | |
1170 | ||
1171 | dev_info(&ips->dev->dev, "TSES: 0x%02x\n", tses); | |
1172 | dev_info(&ips->dev->dev, "TES: 0x%02x\n", tes); | |
1173 | ||
1174 | /* STS update from EC? */ | |
1175 | if (tes & 1) { | |
1176 | u32 sts, tc1; | |
1177 | ||
1178 | sts = thm_readl(THM_STS); | |
1179 | tc1 = thm_readl(THM_TC1); | |
1180 | ||
1181 | if (sts & STS_NVV) { | |
1182 | spin_lock(&ips->turbo_status_lock); | |
1183 | ips->core_power_limit = (sts & STS_PCPL_MASK) >> | |
1184 | STS_PCPL_SHIFT; | |
1185 | ips->mch_power_limit = (sts & STS_GPL_MASK) >> | |
1186 | STS_GPL_SHIFT; | |
1187 | /* ignore EC CPU vs GPU pref */ | |
1188 | ips->cpu_turbo_enabled = !(sts & STS_PCTD_DIS); | |
070c0ee1 AW |
1189 | if (ips->gpu_busy) |
1190 | ips->gpu_turbo_enabled = !(sts & STS_GTD_DIS); | |
aa7ffc01 JB |
1191 | ips->mcp_temp_limit = (sts & STS_PTL_MASK) >> |
1192 | STS_PTL_SHIFT; | |
1193 | ips->mcp_power_limit = (tc1 & STS_PPL_MASK) >> | |
1194 | STS_PPL_SHIFT; | |
eceab272 | 1195 | verify_limits(ips); |
aa7ffc01 JB |
1196 | spin_unlock(&ips->turbo_status_lock); |
1197 | ||
1198 | thm_writeb(THM_SEC, SEC_ACK); | |
1199 | } | |
1200 | thm_writeb(THM_TES, tes); | |
1201 | } | |
1202 | ||
1203 | /* Thermal trip */ | |
1204 | if (tses) { | |
1205 | dev_warn(&ips->dev->dev, | |
1206 | "thermal trip occurred, tses: 0x%04x\n", tses); | |
1207 | thm_writeb(THM_TSES, tses); | |
1208 | } | |
1209 | ||
1210 | return IRQ_HANDLED; | |
1211 | } | |
1212 | ||
1213 | #ifndef CONFIG_DEBUG_FS | |
1214 | static void ips_debugfs_init(struct ips_driver *ips) { return; } | |
1215 | static void ips_debugfs_cleanup(struct ips_driver *ips) { return; } | |
1216 | #else | |
1217 | ||
1218 | /* Expose current state and limits in debugfs if possible */ | |
1219 | ||
1220 | struct ips_debugfs_node { | |
1221 | struct ips_driver *ips; | |
1222 | char *name; | |
1223 | int (*show)(struct seq_file *m, void *data); | |
1224 | }; | |
1225 | ||
1226 | static int show_cpu_temp(struct seq_file *m, void *data) | |
1227 | { | |
1228 | struct ips_driver *ips = m->private; | |
1229 | ||
1230 | seq_printf(m, "%d.%02d\n", ips->ctv1_avg_temp / 100, | |
1231 | ips->ctv1_avg_temp % 100); | |
1232 | ||
1233 | return 0; | |
1234 | } | |
1235 | ||
1236 | static int show_cpu_power(struct seq_file *m, void *data) | |
1237 | { | |
1238 | struct ips_driver *ips = m->private; | |
1239 | ||
1240 | seq_printf(m, "%dmW\n", ips->cpu_avg_power); | |
1241 | ||
1242 | return 0; | |
1243 | } | |
1244 | ||
1245 | static int show_cpu_clamp(struct seq_file *m, void *data) | |
1246 | { | |
1247 | u64 turbo_override; | |
1248 | int tdp, tdc; | |
1249 | ||
1250 | rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); | |
1251 | ||
1252 | tdp = (int)(turbo_override & TURBO_TDP_MASK); | |
1253 | tdc = (int)((turbo_override & TURBO_TDC_MASK) >> TURBO_TDC_SHIFT); | |
1254 | ||
1255 | /* Convert to .1W/A units */ | |
1256 | tdp = tdp * 10 / 8; | |
1257 | tdc = tdc * 10 / 8; | |
1258 | ||
1259 | /* Watts Amperes */ | |
1260 | seq_printf(m, "%d.%dW %d.%dA\n", tdp / 10, tdp % 10, | |
1261 | tdc / 10, tdc % 10); | |
1262 | ||
1263 | return 0; | |
1264 | } | |
1265 | ||
1266 | static int show_mch_temp(struct seq_file *m, void *data) | |
1267 | { | |
1268 | struct ips_driver *ips = m->private; | |
1269 | ||
1270 | seq_printf(m, "%d.%02d\n", ips->mch_avg_temp / 100, | |
1271 | ips->mch_avg_temp % 100); | |
1272 | ||
1273 | return 0; | |
1274 | } | |
1275 | ||
1276 | static int show_mch_power(struct seq_file *m, void *data) | |
1277 | { | |
1278 | struct ips_driver *ips = m->private; | |
1279 | ||
1280 | seq_printf(m, "%dmW\n", ips->mch_avg_power); | |
1281 | ||
1282 | return 0; | |
1283 | } | |
1284 | ||
1285 | static struct ips_debugfs_node ips_debug_files[] = { | |
1286 | { NULL, "cpu_temp", show_cpu_temp }, | |
1287 | { NULL, "cpu_power", show_cpu_power }, | |
1288 | { NULL, "cpu_clamp", show_cpu_clamp }, | |
1289 | { NULL, "mch_temp", show_mch_temp }, | |
1290 | { NULL, "mch_power", show_mch_power }, | |
1291 | }; | |
1292 | ||
1293 | static int ips_debugfs_open(struct inode *inode, struct file *file) | |
1294 | { | |
1295 | struct ips_debugfs_node *node = inode->i_private; | |
1296 | ||
1297 | return single_open(file, node->show, node->ips); | |
1298 | } | |
1299 | ||
1300 | static const struct file_operations ips_debugfs_ops = { | |
1301 | .owner = THIS_MODULE, | |
1302 | .open = ips_debugfs_open, | |
1303 | .read = seq_read, | |
1304 | .llseek = seq_lseek, | |
1305 | .release = single_release, | |
1306 | }; | |
1307 | ||
1308 | static void ips_debugfs_cleanup(struct ips_driver *ips) | |
1309 | { | |
1310 | if (ips->debug_root) | |
1311 | debugfs_remove_recursive(ips->debug_root); | |
1312 | return; | |
1313 | } | |
1314 | ||
1315 | static void ips_debugfs_init(struct ips_driver *ips) | |
1316 | { | |
1317 | int i; | |
1318 | ||
1319 | ips->debug_root = debugfs_create_dir("ips", NULL); | |
1320 | if (!ips->debug_root) { | |
1321 | dev_err(&ips->dev->dev, | |
1322 | "failed to create debugfs entries: %ld\n", | |
1323 | PTR_ERR(ips->debug_root)); | |
1324 | return; | |
1325 | } | |
1326 | ||
1327 | for (i = 0; i < ARRAY_SIZE(ips_debug_files); i++) { | |
1328 | struct dentry *ent; | |
1329 | struct ips_debugfs_node *node = &ips_debug_files[i]; | |
1330 | ||
1331 | node->ips = ips; | |
1332 | ent = debugfs_create_file(node->name, S_IFREG | S_IRUGO, | |
1333 | ips->debug_root, node, | |
1334 | &ips_debugfs_ops); | |
1335 | if (!ent) { | |
1336 | dev_err(&ips->dev->dev, | |
1337 | "failed to create debug file: %ld\n", | |
1338 | PTR_ERR(ent)); | |
1339 | goto err_cleanup; | |
1340 | } | |
1341 | } | |
1342 | ||
1343 | return; | |
1344 | ||
1345 | err_cleanup: | |
1346 | ips_debugfs_cleanup(ips); | |
1347 | return; | |
1348 | } | |
1349 | #endif /* CONFIG_DEBUG_FS */ | |
1350 | ||
1351 | /** | |
1352 | * ips_detect_cpu - detect whether CPU supports IPS | |
1353 | * | |
1354 | * Walk our list and see if we're on a supported CPU. If we find one, | |
1355 | * return the limits for it. | |
1356 | */ | |
1357 | static struct ips_mcp_limits *ips_detect_cpu(struct ips_driver *ips) | |
1358 | { | |
1359 | u64 turbo_power, misc_en; | |
1360 | struct ips_mcp_limits *limits = NULL; | |
1361 | u16 tdp; | |
1362 | ||
1363 | if (!(boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 37)) { | |
1364 | dev_info(&ips->dev->dev, "Non-IPS CPU detected.\n"); | |
1365 | goto out; | |
1366 | } | |
1367 | ||
1368 | rdmsrl(IA32_MISC_ENABLE, misc_en); | |
1369 | /* | |
1370 | * If the turbo enable bit isn't set, we shouldn't try to enable/disable | |
1371 | * turbo manually or we'll get an illegal MSR access, even though | |
1372 | * turbo will still be available. | |
1373 | */ | |
354aeeb1 JB |
1374 | if (misc_en & IA32_MISC_TURBO_EN) |
1375 | ips->turbo_toggle_allowed = true; | |
1376 | else | |
1377 | ips->turbo_toggle_allowed = false; | |
aa7ffc01 JB |
1378 | |
1379 | if (strstr(boot_cpu_data.x86_model_id, "CPU M")) | |
1380 | limits = &ips_sv_limits; | |
1381 | else if (strstr(boot_cpu_data.x86_model_id, "CPU L")) | |
1382 | limits = &ips_lv_limits; | |
1383 | else if (strstr(boot_cpu_data.x86_model_id, "CPU U")) | |
1384 | limits = &ips_ulv_limits; | |
52d7ee55 | 1385 | else { |
aa7ffc01 | 1386 | dev_info(&ips->dev->dev, "No CPUID match found.\n"); |
52d7ee55 DC |
1387 | goto out; |
1388 | } | |
aa7ffc01 JB |
1389 | |
1390 | rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_power); | |
1391 | tdp = turbo_power & TURBO_TDP_MASK; | |
1392 | ||
1393 | /* Sanity check TDP against CPU */ | |
4fd07ac0 JB |
1394 | if (limits->core_power_limit != (tdp / 8) * 1000) { |
1395 | dev_info(&ips->dev->dev, "CPU TDP doesn't match expected value (found %d, expected %d)\n", | |
1396 | tdp / 8, limits->core_power_limit / 1000); | |
1397 | limits->core_power_limit = (tdp / 8) * 1000; | |
aa7ffc01 JB |
1398 | } |
1399 | ||
1400 | out: | |
1401 | return limits; | |
1402 | } | |
1403 | ||
1404 | /** | |
1405 | * ips_get_i915_syms - try to get GPU control methods from i915 driver | |
1406 | * @ips: IPS driver | |
1407 | * | |
1408 | * The i915 driver exports several interfaces to allow the IPS driver to | |
1409 | * monitor and control graphics turbo mode. If we can find them, we can | |
1410 | * enable graphics turbo, otherwise we must disable it to avoid exceeding | |
1411 | * thermal and power limits in the MCP. | |
1412 | */ | |
1413 | static bool ips_get_i915_syms(struct ips_driver *ips) | |
1414 | { | |
1415 | ips->read_mch_val = symbol_get(i915_read_mch_val); | |
1416 | if (!ips->read_mch_val) | |
1417 | goto out_err; | |
1418 | ips->gpu_raise = symbol_get(i915_gpu_raise); | |
1419 | if (!ips->gpu_raise) | |
1420 | goto out_put_mch; | |
1421 | ips->gpu_lower = symbol_get(i915_gpu_lower); | |
1422 | if (!ips->gpu_lower) | |
1423 | goto out_put_raise; | |
1424 | ips->gpu_busy = symbol_get(i915_gpu_busy); | |
1425 | if (!ips->gpu_busy) | |
1426 | goto out_put_lower; | |
1427 | ips->gpu_turbo_disable = symbol_get(i915_gpu_turbo_disable); | |
1428 | if (!ips->gpu_turbo_disable) | |
1429 | goto out_put_busy; | |
1430 | ||
1431 | return true; | |
1432 | ||
1433 | out_put_busy: | |
fed522f7 | 1434 | symbol_put(i915_gpu_busy); |
aa7ffc01 JB |
1435 | out_put_lower: |
1436 | symbol_put(i915_gpu_lower); | |
1437 | out_put_raise: | |
1438 | symbol_put(i915_gpu_raise); | |
1439 | out_put_mch: | |
1440 | symbol_put(i915_read_mch_val); | |
1441 | out_err: | |
1442 | return false; | |
1443 | } | |
1444 | ||
1445 | static DEFINE_PCI_DEVICE_TABLE(ips_id_table) = { | |
1446 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, | |
1447 | PCI_DEVICE_ID_INTEL_THERMAL_SENSOR), }, | |
1448 | { 0, } | |
1449 | }; | |
1450 | ||
1451 | MODULE_DEVICE_TABLE(pci, ips_id_table); | |
1452 | ||
1453 | static int ips_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
1454 | { | |
1455 | u64 platform_info; | |
1456 | struct ips_driver *ips; | |
1457 | u32 hts; | |
1458 | int ret = 0; | |
1459 | u16 htshi, trc, trc_required_mask; | |
1460 | u8 tse; | |
1461 | ||
1462 | ips = kzalloc(sizeof(struct ips_driver), GFP_KERNEL); | |
1463 | if (!ips) | |
1464 | return -ENOMEM; | |
1465 | ||
1466 | pci_set_drvdata(dev, ips); | |
1467 | ips->dev = dev; | |
1468 | ||
1469 | ips->limits = ips_detect_cpu(ips); | |
1470 | if (!ips->limits) { | |
1471 | dev_info(&dev->dev, "IPS not supported on this CPU\n"); | |
1472 | ret = -ENXIO; | |
1473 | goto error_free; | |
1474 | } | |
1475 | ||
1476 | spin_lock_init(&ips->turbo_status_lock); | |
1477 | ||
5629236b KV |
1478 | ret = pci_enable_device(dev); |
1479 | if (ret) { | |
1480 | dev_err(&dev->dev, "can't enable PCI device, aborting\n"); | |
1481 | goto error_free; | |
1482 | } | |
1483 | ||
aa7ffc01 JB |
1484 | if (!pci_resource_start(dev, 0)) { |
1485 | dev_err(&dev->dev, "TBAR not assigned, aborting\n"); | |
1486 | ret = -ENXIO; | |
1487 | goto error_free; | |
1488 | } | |
1489 | ||
1490 | ret = pci_request_regions(dev, "ips thermal sensor"); | |
1491 | if (ret) { | |
1492 | dev_err(&dev->dev, "thermal resource busy, aborting\n"); | |
1493 | goto error_free; | |
1494 | } | |
1495 | ||
aa7ffc01 JB |
1496 | |
1497 | ips->regmap = ioremap(pci_resource_start(dev, 0), | |
1498 | pci_resource_len(dev, 0)); | |
1499 | if (!ips->regmap) { | |
1500 | dev_err(&dev->dev, "failed to map thermal regs, aborting\n"); | |
1501 | ret = -EBUSY; | |
1502 | goto error_release; | |
1503 | } | |
1504 | ||
1505 | tse = thm_readb(THM_TSE); | |
1506 | if (tse != TSE_EN) { | |
1507 | dev_err(&dev->dev, "thermal device not enabled (0x%02x), aborting\n", tse); | |
1508 | ret = -ENXIO; | |
1509 | goto error_unmap; | |
1510 | } | |
1511 | ||
1512 | trc = thm_readw(THM_TRC); | |
1513 | trc_required_mask = TRC_CORE1_EN | TRC_CORE_PWR | TRC_MCH_EN; | |
1514 | if ((trc & trc_required_mask) != trc_required_mask) { | |
1515 | dev_err(&dev->dev, "thermal reporting for required devices not enabled, aborting\n"); | |
1516 | ret = -ENXIO; | |
1517 | goto error_unmap; | |
1518 | } | |
1519 | ||
1520 | if (trc & TRC_CORE2_EN) | |
1521 | ips->second_cpu = true; | |
1522 | ||
aa7ffc01 JB |
1523 | update_turbo_limits(ips); |
1524 | dev_dbg(&dev->dev, "max cpu power clamp: %dW\n", | |
1525 | ips->mcp_power_limit / 10); | |
1526 | dev_dbg(&dev->dev, "max core power clamp: %dW\n", | |
1527 | ips->core_power_limit / 10); | |
1528 | /* BIOS may update limits at runtime */ | |
1529 | if (thm_readl(THM_PSC) & PSP_PBRT) | |
1530 | ips->poll_turbo_status = true; | |
1531 | ||
0385e521 JB |
1532 | if (!ips_get_i915_syms(ips)) { |
1533 | dev_err(&dev->dev, "failed to get i915 symbols, graphics turbo disabled\n"); | |
1534 | ips->gpu_turbo_enabled = false; | |
1535 | } else { | |
1536 | dev_dbg(&dev->dev, "graphics turbo enabled\n"); | |
1537 | ips->gpu_turbo_enabled = true; | |
1538 | } | |
1539 | ||
aa7ffc01 JB |
1540 | /* |
1541 | * Check PLATFORM_INFO MSR to make sure this chip is | |
1542 | * turbo capable. | |
1543 | */ | |
1544 | rdmsrl(PLATFORM_INFO, platform_info); | |
1545 | if (!(platform_info & PLATFORM_TDP)) { | |
1546 | dev_err(&dev->dev, "platform indicates TDP override unavailable, aborting\n"); | |
1547 | ret = -ENODEV; | |
1548 | goto error_unmap; | |
1549 | } | |
1550 | ||
1551 | /* | |
1552 | * IRQ handler for ME interaction | |
1553 | * Note: don't use MSI here as the PCH has bugs. | |
1554 | */ | |
1555 | pci_disable_msi(dev); | |
1556 | ret = request_irq(dev->irq, ips_irq_handler, IRQF_SHARED, "ips", | |
1557 | ips); | |
1558 | if (ret) { | |
1559 | dev_err(&dev->dev, "request irq failed, aborting\n"); | |
1560 | goto error_unmap; | |
1561 | } | |
1562 | ||
1563 | /* Enable aux, hot & critical interrupts */ | |
1564 | thm_writeb(THM_TSPIEN, TSPIEN_AUX2_LOHI | TSPIEN_CRIT_LOHI | | |
1565 | TSPIEN_HOT_LOHI | TSPIEN_AUX_LOHI); | |
1566 | thm_writeb(THM_TEN, TEN_UPDATE_EN); | |
1567 | ||
1568 | /* Collect adjustment values */ | |
1569 | ips->cta_val = thm_readw(THM_CTA); | |
1570 | ips->pta_val = thm_readw(THM_PTA); | |
1571 | ips->mgta_val = thm_readw(THM_MGTA); | |
1572 | ||
1573 | /* Save turbo limits & ratios */ | |
1574 | rdmsrl(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit); | |
1575 | ||
1576 | ips_enable_cpu_turbo(ips); | |
1577 | ips->cpu_turbo_enabled = true; | |
1578 | ||
a7abda8d | 1579 | /* Create thermal adjust thread */ |
1580 | ips->adjust = kthread_create(ips_adjust, ips, "ips-adjust"); | |
1581 | if (IS_ERR(ips->adjust)) { | |
aa7ffc01 | 1582 | dev_err(&dev->dev, |
a7abda8d | 1583 | "failed to create thermal adjust thread, aborting\n"); |
aa7ffc01 JB |
1584 | ret = -ENOMEM; |
1585 | goto error_free_irq; | |
a7abda8d | 1586 | |
aa7ffc01 JB |
1587 | } |
1588 | ||
a7abda8d | 1589 | /* |
1590 | * Set up the work queue and monitor thread. The monitor thread | |
1591 | * will wake up ips_adjust thread. | |
1592 | */ | |
1593 | ips->monitor = kthread_run(ips_monitor, ips, "ips-monitor"); | |
1594 | if (IS_ERR(ips->monitor)) { | |
aa7ffc01 | 1595 | dev_err(&dev->dev, |
a7abda8d | 1596 | "failed to create thermal monitor thread, aborting\n"); |
aa7ffc01 JB |
1597 | ret = -ENOMEM; |
1598 | goto error_thread_cleanup; | |
1599 | } | |
1600 | ||
1601 | hts = (ips->core_power_limit << HTS_PCPL_SHIFT) | | |
1602 | (ips->mcp_temp_limit << HTS_PTL_SHIFT) | HTS_NVV; | |
1603 | htshi = HTS2_PRST_RUNNING << HTS2_PRST_SHIFT; | |
1604 | ||
1605 | thm_writew(THM_HTSHI, htshi); | |
1606 | thm_writel(THM_HTS, hts); | |
1607 | ||
1608 | ips_debugfs_init(ips); | |
1609 | ||
1610 | dev_info(&dev->dev, "IPS driver initialized, MCP temp limit %d\n", | |
1611 | ips->mcp_temp_limit); | |
1612 | return ret; | |
1613 | ||
1614 | error_thread_cleanup: | |
a7abda8d | 1615 | kthread_stop(ips->adjust); |
aa7ffc01 JB |
1616 | error_free_irq: |
1617 | free_irq(ips->dev->irq, ips); | |
1618 | error_unmap: | |
1619 | iounmap(ips->regmap); | |
1620 | error_release: | |
1621 | pci_release_regions(dev); | |
1622 | error_free: | |
1623 | kfree(ips); | |
1624 | return ret; | |
1625 | } | |
1626 | ||
1627 | static void ips_remove(struct pci_dev *dev) | |
1628 | { | |
1629 | struct ips_driver *ips = pci_get_drvdata(dev); | |
1630 | u64 turbo_override; | |
1631 | ||
1632 | if (!ips) | |
1633 | return; | |
1634 | ||
1635 | ips_debugfs_cleanup(ips); | |
1636 | ||
1637 | /* Release i915 driver */ | |
1638 | if (ips->read_mch_val) | |
1639 | symbol_put(i915_read_mch_val); | |
1640 | if (ips->gpu_raise) | |
1641 | symbol_put(i915_gpu_raise); | |
1642 | if (ips->gpu_lower) | |
1643 | symbol_put(i915_gpu_lower); | |
1644 | if (ips->gpu_busy) | |
1645 | symbol_put(i915_gpu_busy); | |
1646 | if (ips->gpu_turbo_disable) | |
1647 | symbol_put(i915_gpu_turbo_disable); | |
1648 | ||
1649 | rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); | |
1650 | turbo_override &= ~(TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN); | |
1651 | wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); | |
1652 | wrmsrl(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit); | |
1653 | ||
1654 | free_irq(ips->dev->irq, ips); | |
1655 | if (ips->adjust) | |
1656 | kthread_stop(ips->adjust); | |
1657 | if (ips->monitor) | |
1658 | kthread_stop(ips->monitor); | |
1659 | iounmap(ips->regmap); | |
1660 | pci_release_regions(dev); | |
1661 | kfree(ips); | |
1662 | dev_dbg(&dev->dev, "IPS driver removed\n"); | |
1663 | } | |
1664 | ||
1665 | #ifdef CONFIG_PM | |
1666 | static int ips_suspend(struct pci_dev *dev, pm_message_t state) | |
1667 | { | |
1668 | return 0; | |
1669 | } | |
1670 | ||
1671 | static int ips_resume(struct pci_dev *dev) | |
1672 | { | |
1673 | return 0; | |
1674 | } | |
1675 | #else | |
1676 | #define ips_suspend NULL | |
1677 | #define ips_resume NULL | |
1678 | #endif /* CONFIG_PM */ | |
1679 | ||
1680 | static void ips_shutdown(struct pci_dev *dev) | |
1681 | { | |
1682 | } | |
1683 | ||
1684 | static struct pci_driver ips_pci_driver = { | |
1685 | .name = "intel ips", | |
1686 | .id_table = ips_id_table, | |
1687 | .probe = ips_probe, | |
1688 | .remove = ips_remove, | |
1689 | .suspend = ips_suspend, | |
1690 | .resume = ips_resume, | |
1691 | .shutdown = ips_shutdown, | |
1692 | }; | |
1693 | ||
1694 | static int __init ips_init(void) | |
1695 | { | |
1696 | return pci_register_driver(&ips_pci_driver); | |
1697 | } | |
1698 | module_init(ips_init); | |
1699 | ||
1700 | static void ips_exit(void) | |
1701 | { | |
1702 | pci_unregister_driver(&ips_pci_driver); | |
1703 | return; | |
1704 | } | |
1705 | module_exit(ips_exit); | |
1706 | ||
1707 | MODULE_LICENSE("GPL"); | |
1708 | MODULE_AUTHOR("Jesse Barnes <jbarnes@virtuousgeek.org>"); | |
1709 | MODULE_DESCRIPTION("Intelligent Power Sharing Driver"); |