]>
Commit | Line | Data |
---|---|---|
0a8b8353 | 1 | /* |
2 | * intel_pmc_ipc.c: Driver for the Intel PMC IPC mechanism | |
3 | * | |
4 | * (C) Copyright 2014-2015 Intel Corporation | |
5 | * | |
6 | * This driver is based on Intel SCU IPC driver(intel_scu_opc.c) by | |
7 | * Sreedhara DS <sreedhara.ds@intel.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; version 2 | |
12 | * of the License. | |
13 | * | |
14 | * PMC running in ARC processor communicates with other entity running in IA | |
15 | * core through IPC mechanism which in turn messaging between IA core ad PMC. | |
16 | */ | |
17 | ||
18 | #include <linux/module.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/device.h> | |
43aaf4f0 | 23 | #include <linux/mfd/core.h> |
0a8b8353 | 24 | #include <linux/pm.h> |
25 | #include <linux/pci.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/pm_qos.h> | |
29 | #include <linux/kernel.h> | |
30 | #include <linux/bitops.h> | |
31 | #include <linux/sched.h> | |
32 | #include <linux/atomic.h> | |
33 | #include <linux/notifier.h> | |
34 | #include <linux/suspend.h> | |
35 | #include <linux/acpi.h> | |
76062b4a | 36 | #include <linux/io-64-nonatomic-lo-hi.h> |
e3075fd6 | 37 | #include <linux/spinlock.h> |
76062b4a | 38 | |
0a8b8353 | 39 | #include <asm/intel_pmc_ipc.h> |
76062b4a | 40 | |
420b54de | 41 | #include <linux/platform_data/itco_wdt.h> |
0a8b8353 | 42 | |
43 | /* | |
44 | * IPC registers | |
45 | * The IA write to IPC_CMD command register triggers an interrupt to the ARC, | |
46 | * The ARC handles the interrupt and services it, writing optional data to | |
47 | * the IPC1 registers, updates the IPC_STS response register with the status. | |
48 | */ | |
49 | #define IPC_CMD 0x0 | |
50 | #define IPC_CMD_MSI 0x100 | |
51 | #define IPC_CMD_SIZE 16 | |
52 | #define IPC_CMD_SUBCMD 12 | |
53 | #define IPC_STATUS 0x04 | |
54 | #define IPC_STATUS_IRQ 0x4 | |
55 | #define IPC_STATUS_ERR 0x2 | |
56 | #define IPC_STATUS_BUSY 0x1 | |
57 | #define IPC_SPTR 0x08 | |
58 | #define IPC_DPTR 0x0C | |
59 | #define IPC_WRITE_BUFFER 0x80 | |
60 | #define IPC_READ_BUFFER 0x90 | |
61 | ||
76062b4a SM |
62 | /* Residency with clock rate at 19.2MHz to usecs */ |
63 | #define S0IX_RESIDENCY_IN_USECS(d, s) \ | |
64 | ({ \ | |
65 | u64 result = 10ull * ((d) + (s)); \ | |
66 | do_div(result, 192); \ | |
67 | result; \ | |
68 | }) | |
69 | ||
0a8b8353 | 70 | /* |
71 | * 16-byte buffer for sending data associated with IPC command. | |
72 | */ | |
73 | #define IPC_DATA_BUFFER_SIZE 16 | |
74 | ||
75 | #define IPC_LOOP_CNT 3000000 | |
76 | #define IPC_MAX_SEC 3 | |
77 | ||
78 | #define IPC_TRIGGER_MODE_IRQ true | |
79 | ||
80 | /* exported resources from IFWI */ | |
81 | #define PLAT_RESOURCE_IPC_INDEX 0 | |
82 | #define PLAT_RESOURCE_IPC_SIZE 0x1000 | |
e6749c89 | 83 | #define PLAT_RESOURCE_GCR_OFFSET 0x1000 |
76062b4a | 84 | #define PLAT_RESOURCE_GCR_SIZE 0x1000 |
8cc7fb4a QZ |
85 | #define PLAT_RESOURCE_BIOS_DATA_INDEX 1 |
86 | #define PLAT_RESOURCE_BIOS_IFACE_INDEX 2 | |
48c19170 | 87 | #define PLAT_RESOURCE_TELEM_SSRAM_INDEX 3 |
8cc7fb4a QZ |
88 | #define PLAT_RESOURCE_ISP_DATA_INDEX 4 |
89 | #define PLAT_RESOURCE_ISP_IFACE_INDEX 5 | |
90 | #define PLAT_RESOURCE_GTD_DATA_INDEX 6 | |
91 | #define PLAT_RESOURCE_GTD_IFACE_INDEX 7 | |
43aaf4f0 | 92 | #define PLAT_RESOURCE_MEM_MAX_INDEX 8 |
0a8b8353 | 93 | #define PLAT_RESOURCE_ACPI_IO_INDEX 0 |
94 | ||
95 | /* | |
96 | * BIOS does not create an ACPI device for each PMC function, | |
97 | * but exports multiple resources from one ACPI device(IPC) for | |
98 | * multiple functions. This driver is responsible to create a | |
99 | * platform device and to export resources for those functions. | |
100 | */ | |
101 | #define TCO_DEVICE_NAME "iTCO_wdt" | |
334da2d6 | 102 | #define SMI_EN_OFFSET 0x40 |
0a8b8353 | 103 | #define SMI_EN_SIZE 4 |
104 | #define TCO_BASE_OFFSET 0x60 | |
105 | #define TCO_REGS_SIZE 16 | |
106 | #define PUNIT_DEVICE_NAME "intel_punit_ipc" | |
48c19170 SKC |
107 | #define TELEMETRY_DEVICE_NAME "intel_telemetry" |
108 | #define TELEM_SSRAM_SIZE 240 | |
109 | #define TELEM_PMC_SSRAM_OFFSET 0x1B00 | |
110 | #define TELEM_PUNIT_SSRAM_OFFSET 0x1A00 | |
0a8b8353 | 111 | |
9d855d46 KS |
112 | /* PMC register bit definitions */ |
113 | ||
114 | /* PMC_CFG_REG bit masks */ | |
115 | #define PMC_CFG_NO_REBOOT_MASK (1 << 4) | |
116 | #define PMC_CFG_NO_REBOOT_EN (1 << 4) | |
117 | #define PMC_CFG_NO_REBOOT_DIS (0 << 4) | |
118 | ||
0a8b8353 | 119 | static struct intel_pmc_ipc_dev { |
120 | struct device *dev; | |
121 | void __iomem *ipc_base; | |
122 | bool irq_mode; | |
123 | int irq; | |
124 | int cmd; | |
125 | struct completion cmd_complete; | |
126 | ||
0a8b8353 | 127 | /* gcr */ |
49670206 | 128 | void __iomem *gcr_mem_base; |
76062b4a | 129 | bool has_gcr_regs; |
e3075fd6 | 130 | spinlock_t gcr_lock; |
0a8b8353 | 131 | } ipcdev; |
132 | ||
133 | static char *ipc_err_sources[] = { | |
134 | [IPC_ERR_NONE] = | |
135 | "no error", | |
136 | [IPC_ERR_CMD_NOT_SUPPORTED] = | |
137 | "command not supported", | |
138 | [IPC_ERR_CMD_NOT_SERVICED] = | |
139 | "command not serviced", | |
140 | [IPC_ERR_UNABLE_TO_SERVICE] = | |
141 | "unable to service", | |
142 | [IPC_ERR_CMD_INVALID] = | |
143 | "command invalid", | |
144 | [IPC_ERR_CMD_FAILED] = | |
145 | "command failed", | |
146 | [IPC_ERR_EMSECURITY] = | |
147 | "Invalid Battery", | |
148 | [IPC_ERR_UNSIGNEDKERNEL] = | |
149 | "Unsigned kernel", | |
150 | }; | |
151 | ||
152 | /* Prevent concurrent calls to the PMC */ | |
153 | static DEFINE_MUTEX(ipclock); | |
154 | ||
155 | static inline void ipc_send_command(u32 cmd) | |
156 | { | |
157 | ipcdev.cmd = cmd; | |
158 | if (ipcdev.irq_mode) { | |
159 | reinit_completion(&ipcdev.cmd_complete); | |
160 | cmd |= IPC_CMD_MSI; | |
161 | } | |
162 | writel(cmd, ipcdev.ipc_base + IPC_CMD); | |
163 | } | |
164 | ||
165 | static inline u32 ipc_read_status(void) | |
166 | { | |
167 | return readl(ipcdev.ipc_base + IPC_STATUS); | |
168 | } | |
169 | ||
170 | static inline void ipc_data_writel(u32 data, u32 offset) | |
171 | { | |
172 | writel(data, ipcdev.ipc_base + IPC_WRITE_BUFFER + offset); | |
173 | } | |
174 | ||
6bee1af9 | 175 | static inline u8 __maybe_unused ipc_data_readb(u32 offset) |
0a8b8353 | 176 | { |
177 | return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset); | |
178 | } | |
179 | ||
180 | static inline u32 ipc_data_readl(u32 offset) | |
181 | { | |
182 | return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset); | |
183 | } | |
184 | ||
76062b4a SM |
185 | static inline u64 gcr_data_readq(u32 offset) |
186 | { | |
62a7b9c8 | 187 | return readq(ipcdev.gcr_mem_base + offset); |
76062b4a SM |
188 | } |
189 | ||
49670206 KS |
190 | static inline int is_gcr_valid(u32 offset) |
191 | { | |
192 | if (!ipcdev.has_gcr_regs) | |
193 | return -EACCES; | |
194 | ||
195 | if (offset > PLAT_RESOURCE_GCR_SIZE) | |
196 | return -EINVAL; | |
197 | ||
198 | return 0; | |
199 | } | |
200 | ||
201 | /** | |
202 | * intel_pmc_gcr_read() - Read PMC GCR register | |
203 | * @offset: offset of GCR register from GCR address base | |
204 | * @data: data pointer for storing the register output | |
205 | * | |
206 | * Reads the PMC GCR register of given offset. | |
207 | * | |
208 | * Return: negative value on error or 0 on success. | |
209 | */ | |
210 | int intel_pmc_gcr_read(u32 offset, u32 *data) | |
211 | { | |
212 | int ret; | |
213 | ||
e3075fd6 | 214 | spin_lock(&ipcdev.gcr_lock); |
49670206 KS |
215 | |
216 | ret = is_gcr_valid(offset); | |
217 | if (ret < 0) { | |
e3075fd6 | 218 | spin_unlock(&ipcdev.gcr_lock); |
49670206 KS |
219 | return ret; |
220 | } | |
221 | ||
222 | *data = readl(ipcdev.gcr_mem_base + offset); | |
223 | ||
e3075fd6 | 224 | spin_unlock(&ipcdev.gcr_lock); |
49670206 KS |
225 | |
226 | return 0; | |
227 | } | |
228 | EXPORT_SYMBOL_GPL(intel_pmc_gcr_read); | |
229 | ||
230 | /** | |
231 | * intel_pmc_gcr_write() - Write PMC GCR register | |
232 | * @offset: offset of GCR register from GCR address base | |
233 | * @data: register update value | |
234 | * | |
235 | * Writes the PMC GCR register of given offset with given | |
236 | * value. | |
237 | * | |
238 | * Return: negative value on error or 0 on success. | |
239 | */ | |
240 | int intel_pmc_gcr_write(u32 offset, u32 data) | |
241 | { | |
242 | int ret; | |
243 | ||
e3075fd6 | 244 | spin_lock(&ipcdev.gcr_lock); |
49670206 KS |
245 | |
246 | ret = is_gcr_valid(offset); | |
247 | if (ret < 0) { | |
e3075fd6 | 248 | spin_unlock(&ipcdev.gcr_lock); |
49670206 KS |
249 | return ret; |
250 | } | |
251 | ||
252 | writel(data, ipcdev.gcr_mem_base + offset); | |
253 | ||
e3075fd6 | 254 | spin_unlock(&ipcdev.gcr_lock); |
49670206 KS |
255 | |
256 | return 0; | |
257 | } | |
258 | EXPORT_SYMBOL_GPL(intel_pmc_gcr_write); | |
259 | ||
260 | /** | |
261 | * intel_pmc_gcr_update() - Update PMC GCR register bits | |
262 | * @offset: offset of GCR register from GCR address base | |
263 | * @mask: bit mask for update operation | |
264 | * @val: update value | |
265 | * | |
266 | * Updates the bits of given GCR register as specified by | |
267 | * @mask and @val. | |
268 | * | |
269 | * Return: negative value on error or 0 on success. | |
270 | */ | |
271 | int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val) | |
272 | { | |
273 | u32 new_val; | |
274 | int ret = 0; | |
275 | ||
e3075fd6 | 276 | spin_lock(&ipcdev.gcr_lock); |
49670206 KS |
277 | |
278 | ret = is_gcr_valid(offset); | |
279 | if (ret < 0) | |
280 | goto gcr_ipc_unlock; | |
281 | ||
282 | new_val = readl(ipcdev.gcr_mem_base + offset); | |
283 | ||
284 | new_val &= ~mask; | |
285 | new_val |= val & mask; | |
286 | ||
287 | writel(new_val, ipcdev.gcr_mem_base + offset); | |
288 | ||
289 | new_val = readl(ipcdev.gcr_mem_base + offset); | |
290 | ||
291 | /* check whether the bit update is successful */ | |
292 | if ((new_val & mask) != (val & mask)) { | |
293 | ret = -EIO; | |
294 | goto gcr_ipc_unlock; | |
295 | } | |
296 | ||
297 | gcr_ipc_unlock: | |
e3075fd6 | 298 | spin_unlock(&ipcdev.gcr_lock); |
49670206 KS |
299 | return ret; |
300 | } | |
301 | EXPORT_SYMBOL_GPL(intel_pmc_gcr_update); | |
302 | ||
9d855d46 KS |
303 | static int update_no_reboot_bit(void *priv, bool set) |
304 | { | |
305 | u32 value = set ? PMC_CFG_NO_REBOOT_EN : PMC_CFG_NO_REBOOT_DIS; | |
306 | ||
307 | return intel_pmc_gcr_update(PMC_GCR_PMC_CFG_REG, | |
308 | PMC_CFG_NO_REBOOT_MASK, value); | |
309 | } | |
310 | ||
0a8b8353 | 311 | static int intel_pmc_ipc_check_status(void) |
312 | { | |
313 | int status; | |
314 | int ret = 0; | |
315 | ||
316 | if (ipcdev.irq_mode) { | |
317 | if (0 == wait_for_completion_timeout( | |
318 | &ipcdev.cmd_complete, IPC_MAX_SEC * HZ)) | |
319 | ret = -ETIMEDOUT; | |
320 | } else { | |
321 | int loop_count = IPC_LOOP_CNT; | |
322 | ||
323 | while ((ipc_read_status() & IPC_STATUS_BUSY) && --loop_count) | |
324 | udelay(1); | |
325 | if (loop_count == 0) | |
326 | ret = -ETIMEDOUT; | |
327 | } | |
328 | ||
329 | status = ipc_read_status(); | |
330 | if (ret == -ETIMEDOUT) { | |
331 | dev_err(ipcdev.dev, | |
332 | "IPC timed out, TS=0x%x, CMD=0x%x\n", | |
333 | status, ipcdev.cmd); | |
334 | return ret; | |
335 | } | |
336 | ||
337 | if (status & IPC_STATUS_ERR) { | |
338 | int i; | |
339 | ||
340 | ret = -EIO; | |
341 | i = (status >> IPC_CMD_SIZE) & 0xFF; | |
342 | if (i < ARRAY_SIZE(ipc_err_sources)) | |
343 | dev_err(ipcdev.dev, | |
344 | "IPC failed: %s, STS=0x%x, CMD=0x%x\n", | |
345 | ipc_err_sources[i], status, ipcdev.cmd); | |
346 | else | |
347 | dev_err(ipcdev.dev, | |
348 | "IPC failed: unknown, STS=0x%x, CMD=0x%x\n", | |
349 | status, ipcdev.cmd); | |
350 | if ((i == IPC_ERR_UNSIGNEDKERNEL) || (i == IPC_ERR_EMSECURITY)) | |
351 | ret = -EACCES; | |
352 | } | |
353 | ||
354 | return ret; | |
355 | } | |
356 | ||
02941007 | 357 | /** |
358 | * intel_pmc_ipc_simple_command() - Simple IPC command | |
359 | * @cmd: IPC command code. | |
360 | * @sub: IPC command sub type. | |
361 | * | |
362 | * Send a simple IPC command to PMC when don't need to specify | |
363 | * input/output data and source/dest pointers. | |
364 | * | |
365 | * Return: an IPC error code or 0 on success. | |
0a8b8353 | 366 | */ |
367 | int intel_pmc_ipc_simple_command(int cmd, int sub) | |
368 | { | |
369 | int ret; | |
370 | ||
371 | mutex_lock(&ipclock); | |
372 | if (ipcdev.dev == NULL) { | |
373 | mutex_unlock(&ipclock); | |
374 | return -ENODEV; | |
375 | } | |
376 | ipc_send_command(sub << IPC_CMD_SUBCMD | cmd); | |
377 | ret = intel_pmc_ipc_check_status(); | |
378 | mutex_unlock(&ipclock); | |
379 | ||
380 | return ret; | |
381 | } | |
382 | EXPORT_SYMBOL_GPL(intel_pmc_ipc_simple_command); | |
383 | ||
02941007 | 384 | /** |
385 | * intel_pmc_ipc_raw_cmd() - IPC command with data and pointers | |
386 | * @cmd: IPC command code. | |
387 | * @sub: IPC command sub type. | |
388 | * @in: input data of this IPC command. | |
389 | * @inlen: input data length in bytes. | |
390 | * @out: output data of this IPC command. | |
391 | * @outlen: output data length in dwords. | |
392 | * @sptr: data writing to SPTR register. | |
393 | * @dptr: data writing to DPTR register. | |
394 | * | |
395 | * Send an IPC command to PMC with input/output data and source/dest pointers. | |
396 | * | |
397 | * Return: an IPC error code or 0 on success. | |
0a8b8353 | 398 | */ |
399 | int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen, u32 *out, | |
400 | u32 outlen, u32 dptr, u32 sptr) | |
401 | { | |
402 | u32 wbuf[4] = { 0 }; | |
403 | int ret; | |
404 | int i; | |
405 | ||
406 | if (inlen > IPC_DATA_BUFFER_SIZE || outlen > IPC_DATA_BUFFER_SIZE / 4) | |
407 | return -EINVAL; | |
408 | ||
409 | mutex_lock(&ipclock); | |
410 | if (ipcdev.dev == NULL) { | |
411 | mutex_unlock(&ipclock); | |
412 | return -ENODEV; | |
413 | } | |
414 | memcpy(wbuf, in, inlen); | |
415 | writel(dptr, ipcdev.ipc_base + IPC_DPTR); | |
416 | writel(sptr, ipcdev.ipc_base + IPC_SPTR); | |
417 | /* The input data register is 32bit register and inlen is in Byte */ | |
418 | for (i = 0; i < ((inlen + 3) / 4); i++) | |
419 | ipc_data_writel(wbuf[i], 4 * i); | |
420 | ipc_send_command((inlen << IPC_CMD_SIZE) | | |
421 | (sub << IPC_CMD_SUBCMD) | cmd); | |
422 | ret = intel_pmc_ipc_check_status(); | |
423 | if (!ret) { | |
424 | /* out is read from 32bit register and outlen is in 32bit */ | |
425 | for (i = 0; i < outlen; i++) | |
426 | *out++ = ipc_data_readl(4 * i); | |
427 | } | |
428 | mutex_unlock(&ipclock); | |
429 | ||
430 | return ret; | |
431 | } | |
432 | EXPORT_SYMBOL_GPL(intel_pmc_ipc_raw_cmd); | |
433 | ||
02941007 | 434 | /** |
435 | * intel_pmc_ipc_command() - IPC command with input/output data | |
436 | * @cmd: IPC command code. | |
437 | * @sub: IPC command sub type. | |
438 | * @in: input data of this IPC command. | |
439 | * @inlen: input data length in bytes. | |
440 | * @out: output data of this IPC command. | |
441 | * @outlen: output data length in dwords. | |
442 | * | |
443 | * Send an IPC command to PMC with input/output data. | |
444 | * | |
445 | * Return: an IPC error code or 0 on success. | |
0a8b8353 | 446 | */ |
447 | int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen, | |
448 | u32 *out, u32 outlen) | |
449 | { | |
450 | return intel_pmc_ipc_raw_cmd(cmd, sub, in, inlen, out, outlen, 0, 0); | |
451 | } | |
452 | EXPORT_SYMBOL_GPL(intel_pmc_ipc_command); | |
453 | ||
454 | static irqreturn_t ioc(int irq, void *dev_id) | |
455 | { | |
456 | int status; | |
457 | ||
458 | if (ipcdev.irq_mode) { | |
459 | status = ipc_read_status(); | |
460 | writel(status | IPC_STATUS_IRQ, ipcdev.ipc_base + IPC_STATUS); | |
461 | } | |
462 | complete(&ipcdev.cmd_complete); | |
463 | ||
464 | return IRQ_HANDLED; | |
465 | } | |
466 | ||
467 | static int ipc_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |
468 | { | |
d7ca5ebf | 469 | struct intel_pmc_ipc_dev *pmc = &ipcdev; |
0a8b8353 | 470 | int ret; |
0a8b8353 | 471 | |
d7ca5ebf KS |
472 | /* Only one PMC is supported */ |
473 | if (pmc->dev) | |
474 | return -EBUSY; | |
0a8b8353 | 475 | |
d7ca5ebf KS |
476 | pmc->irq_mode = IPC_TRIGGER_MODE_IRQ; |
477 | ||
e3075fd6 KS |
478 | spin_lock_init(&ipcdev.gcr_lock); |
479 | ||
d7ca5ebf | 480 | ret = pcim_enable_device(pdev); |
0a8b8353 | 481 | if (ret) |
482 | return ret; | |
483 | ||
d7ca5ebf | 484 | ret = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev)); |
0a8b8353 | 485 | if (ret) |
486 | return ret; | |
487 | ||
d7ca5ebf | 488 | init_completion(&pmc->cmd_complete); |
0a8b8353 | 489 | |
d7ca5ebf | 490 | pmc->ipc_base = pcim_iomap_table(pdev)[0]; |
0a8b8353 | 491 | |
d7ca5ebf KS |
492 | ret = devm_request_irq(&pdev->dev, pdev->irq, ioc, 0, "intel_pmc_ipc", |
493 | pmc); | |
494 | if (ret) { | |
43aaf4f0 | 495 | dev_err(&pdev->dev, "Failed to request IRQ\n"); |
d7ca5ebf | 496 | return ret; |
0a8b8353 | 497 | } |
498 | ||
d7ca5ebf | 499 | pmc->dev = &pdev->dev; |
0a8b8353 | 500 | |
d7ca5ebf | 501 | pci_set_drvdata(pdev, pmc); |
0a8b8353 | 502 | |
d7ca5ebf | 503 | return 0; |
0a8b8353 | 504 | } |
505 | ||
506 | static const struct pci_device_id ipc_pci_ids[] = { | |
507 | {PCI_VDEVICE(INTEL, 0x0a94), 0}, | |
508 | {PCI_VDEVICE(INTEL, 0x1a94), 0}, | |
23e775db | 509 | {PCI_VDEVICE(INTEL, 0x5a94), 0}, |
0a8b8353 | 510 | { 0,} |
511 | }; | |
512 | MODULE_DEVICE_TABLE(pci, ipc_pci_ids); | |
513 | ||
514 | static struct pci_driver ipc_pci_driver = { | |
515 | .name = "intel_pmc_ipc", | |
516 | .id_table = ipc_pci_ids, | |
517 | .probe = ipc_pci_probe, | |
0a8b8353 | 518 | }; |
519 | ||
520 | static ssize_t intel_pmc_ipc_simple_cmd_store(struct device *dev, | |
521 | struct device_attribute *attr, | |
522 | const char *buf, size_t count) | |
523 | { | |
524 | int subcmd; | |
525 | int cmd; | |
526 | int ret; | |
527 | ||
528 | ret = sscanf(buf, "%d %d", &cmd, &subcmd); | |
529 | if (ret != 2) { | |
530 | dev_err(dev, "Error args\n"); | |
531 | return -EINVAL; | |
532 | } | |
533 | ||
534 | ret = intel_pmc_ipc_simple_command(cmd, subcmd); | |
535 | if (ret) { | |
536 | dev_err(dev, "command %d error with %d\n", cmd, ret); | |
537 | return ret; | |
538 | } | |
539 | return (ssize_t)count; | |
540 | } | |
541 | ||
542 | static ssize_t intel_pmc_ipc_northpeak_store(struct device *dev, | |
543 | struct device_attribute *attr, | |
544 | const char *buf, size_t count) | |
545 | { | |
546 | unsigned long val; | |
547 | int subcmd; | |
548 | int ret; | |
549 | ||
550 | if (kstrtoul(buf, 0, &val)) | |
551 | return -EINVAL; | |
552 | ||
553 | if (val) | |
554 | subcmd = 1; | |
555 | else | |
556 | subcmd = 0; | |
557 | ret = intel_pmc_ipc_simple_command(PMC_IPC_NORTHPEAK_CTRL, subcmd); | |
558 | if (ret) { | |
559 | dev_err(dev, "command north %d error with %d\n", subcmd, ret); | |
560 | return ret; | |
561 | } | |
562 | return (ssize_t)count; | |
563 | } | |
564 | ||
565 | static DEVICE_ATTR(simplecmd, S_IWUSR, | |
566 | NULL, intel_pmc_ipc_simple_cmd_store); | |
567 | static DEVICE_ATTR(northpeak, S_IWUSR, | |
568 | NULL, intel_pmc_ipc_northpeak_store); | |
569 | ||
570 | static struct attribute *intel_ipc_attrs[] = { | |
571 | &dev_attr_northpeak.attr, | |
572 | &dev_attr_simplecmd.attr, | |
573 | NULL | |
574 | }; | |
575 | ||
576 | static const struct attribute_group intel_ipc_group = { | |
577 | .attrs = intel_ipc_attrs, | |
578 | }; | |
579 | ||
420b54de | 580 | static struct itco_wdt_platform_data tco_info = { |
0a8b8353 | 581 | .name = "Apollo Lake SoC", |
334da2d6 | 582 | .version = 5, |
9d855d46 KS |
583 | .no_reboot_priv = &ipcdev, |
584 | .update_no_reboot_bit = update_no_reboot_bit, | |
0a8b8353 | 585 | }; |
586 | ||
43aaf4f0 | 587 | static int ipc_create_punit_device(struct platform_device *pdev) |
0a8b8353 | 588 | { |
43aaf4f0 KS |
589 | struct resource punit_res[PLAT_RESOURCE_MEM_MAX_INDEX]; |
590 | struct mfd_cell punit_cell; | |
591 | struct resource *res; | |
592 | int mindex, pindex = 0; | |
593 | ||
594 | for (mindex = 0; mindex <= PLAT_RESOURCE_MEM_MAX_INDEX; mindex++) { | |
595 | ||
596 | res = platform_get_resource(pdev, IORESOURCE_MEM, mindex); | |
597 | ||
598 | switch (mindex) { | |
599 | /* Get PUNIT resources */ | |
600 | case PLAT_RESOURCE_BIOS_DATA_INDEX: | |
601 | case PLAT_RESOURCE_BIOS_IFACE_INDEX: | |
602 | /* BIOS resources are required, so return error if not | |
603 | * available | |
604 | */ | |
605 | if (!res) { | |
606 | dev_err(&pdev->dev, | |
607 | "Failed to get PUNIT MEM resource %d\n", | |
608 | pindex); | |
609 | return -ENXIO; | |
610 | } | |
611 | case PLAT_RESOURCE_ISP_DATA_INDEX: | |
612 | case PLAT_RESOURCE_ISP_IFACE_INDEX: | |
613 | case PLAT_RESOURCE_GTD_DATA_INDEX: | |
614 | case PLAT_RESOURCE_GTD_IFACE_INDEX: | |
615 | /* if valid resource found, copy the resource to PUNIT | |
616 | * resource | |
617 | */ | |
618 | if (res) | |
619 | memcpy(&punit_res[pindex], res, sizeof(*res)); | |
620 | punit_res[pindex].flags = IORESOURCE_MEM; | |
621 | dev_dbg(&pdev->dev, "PUNIT memory res: %pR\n", | |
622 | &punit_res[pindex]); | |
623 | pindex++; | |
624 | break; | |
ea1a76ba | 625 | }; |
43aaf4f0 | 626 | } |
ea1a76ba | 627 | |
43aaf4f0 KS |
628 | /* Create PUNIT IPC MFD cell */ |
629 | punit_cell.name = PUNIT_DEVICE_NAME; | |
630 | punit_cell.num_resources = ARRAY_SIZE(punit_res); | |
631 | punit_cell.resources = punit_res; | |
632 | punit_cell.ignore_resource_conflicts = 1; | |
0a8b8353 | 633 | |
43aaf4f0 KS |
634 | return devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, |
635 | &punit_cell, 1, NULL, 0, NULL); | |
0a8b8353 | 636 | } |
637 | ||
43aaf4f0 | 638 | static int ipc_create_wdt_device(struct platform_device *pdev) |
0a8b8353 | 639 | { |
43aaf4f0 | 640 | static struct resource wdt_ipc_res[2]; |
0a8b8353 | 641 | struct resource *res; |
43aaf4f0 | 642 | static struct mfd_cell wdt_cell; |
0a8b8353 | 643 | |
43aaf4f0 KS |
644 | /* If we have ACPI based watchdog use that instead, othewise create |
645 | * a MFD cell for iTCO watchdog | |
646 | */ | |
647 | if (acpi_has_watchdog()) | |
648 | return 0; | |
0a8b8353 | 649 | |
43aaf4f0 KS |
650 | /* Get iTCO watchdog resources */ |
651 | res = platform_get_resource(pdev, IORESOURCE_IO, | |
652 | PLAT_RESOURCE_ACPI_IO_INDEX); | |
653 | if (!res) { | |
654 | dev_err(&pdev->dev, "Failed to get WDT resource\n"); | |
655 | return -ENXIO; | |
656 | } | |
0a8b8353 | 657 | |
43aaf4f0 KS |
658 | wdt_ipc_res[0].start = res->start + TCO_BASE_OFFSET; |
659 | wdt_ipc_res[0].end = res->start + | |
660 | TCO_BASE_OFFSET + TCO_REGS_SIZE - 1; | |
661 | wdt_ipc_res[0].flags = IORESOURCE_IO; | |
662 | wdt_ipc_res[1].start = res->start + SMI_EN_OFFSET; | |
663 | wdt_ipc_res[1].end = res->start + | |
664 | SMI_EN_OFFSET + SMI_EN_SIZE - 1; | |
665 | wdt_ipc_res[1].flags = IORESOURCE_IO; | |
0a8b8353 | 666 | |
43aaf4f0 KS |
667 | dev_dbg(&pdev->dev, "watchdog res 0: %pR\n", &wdt_ipc_res[0]); |
668 | dev_dbg(&pdev->dev, "watchdog res 1: %pR\n", &wdt_ipc_res[1]); | |
0a8b8353 | 669 | |
43aaf4f0 KS |
670 | wdt_cell.name = TCO_DEVICE_NAME; |
671 | wdt_cell.platform_data = &tco_info; | |
672 | wdt_cell.pdata_size = sizeof(tco_info); | |
673 | wdt_cell.num_resources = ARRAY_SIZE(wdt_ipc_res); | |
674 | wdt_cell.resources = wdt_ipc_res; | |
675 | wdt_cell.ignore_resource_conflicts = 1; | |
676 | ||
677 | return devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, | |
678 | &wdt_cell, 1, NULL, 0, NULL); | |
0a8b8353 | 679 | } |
680 | ||
43aaf4f0 | 681 | static int ipc_create_telemetry_device(struct platform_device *pdev) |
48c19170 | 682 | { |
43aaf4f0 KS |
683 | struct resource telemetry_ipc_res[2]; |
684 | struct mfd_cell telemetry_cell; | |
48c19170 | 685 | struct resource *res; |
48c19170 | 686 | |
43aaf4f0 KS |
687 | /* Get telemetry resources */ |
688 | res = platform_get_resource(pdev, IORESOURCE_MEM, | |
689 | PLAT_RESOURCE_TELEM_SSRAM_INDEX); | |
690 | if (!res) { | |
691 | dev_err(&pdev->dev, "Failed to get telemetry resource\n"); | |
692 | return -ENXIO; | |
693 | } | |
48c19170 | 694 | |
43aaf4f0 KS |
695 | telemetry_ipc_res[0].start = res->start + TELEM_PUNIT_SSRAM_OFFSET; |
696 | telemetry_ipc_res[0].end = res->start + | |
697 | TELEM_PUNIT_SSRAM_OFFSET + TELEM_SSRAM_SIZE - 1; | |
698 | telemetry_ipc_res[0].flags = IORESOURCE_MEM; | |
699 | telemetry_ipc_res[1].start = res->start + TELEM_PMC_SSRAM_OFFSET; | |
700 | telemetry_ipc_res[1].end = res->start + | |
701 | TELEM_PMC_SSRAM_OFFSET + TELEM_SSRAM_SIZE - 1; | |
702 | telemetry_ipc_res[1].flags = IORESOURCE_MEM; | |
48c19170 | 703 | |
43aaf4f0 KS |
704 | dev_dbg(&pdev->dev, "Telemetry res 0: %pR\n", &telemetry_ipc_res[0]); |
705 | dev_dbg(&pdev->dev, "Telemetry res 1: %pR\n", &telemetry_ipc_res[1]); | |
48c19170 | 706 | |
43aaf4f0 KS |
707 | telemetry_cell.name = TELEMETRY_DEVICE_NAME; |
708 | telemetry_cell.num_resources = ARRAY_SIZE(telemetry_ipc_res); | |
709 | telemetry_cell.resources = telemetry_ipc_res; | |
710 | telemetry_cell.ignore_resource_conflicts = 1; | |
48c19170 | 711 | |
43aaf4f0 KS |
712 | return devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, |
713 | &telemetry_cell, 1, NULL, 0, NULL); | |
48c19170 SKC |
714 | } |
715 | ||
43aaf4f0 | 716 | static int ipc_create_pmc_devices(struct platform_device *pdev) |
0a8b8353 | 717 | { |
718 | int ret; | |
719 | ||
43aaf4f0 KS |
720 | ret = ipc_create_punit_device(pdev); |
721 | if (ret < 0) | |
722 | return ret; | |
bba6529e | 723 | |
43aaf4f0 KS |
724 | ret = ipc_create_wdt_device(pdev); |
725 | if (ret < 0) | |
726 | return ret; | |
48c19170 | 727 | |
43aaf4f0 KS |
728 | ret = ipc_create_telemetry_device(pdev); |
729 | if (ret < 0) | |
730 | return ret; | |
48c19170 | 731 | |
43aaf4f0 | 732 | return 0; |
0a8b8353 | 733 | } |
734 | ||
735 | static int ipc_plat_get_res(struct platform_device *pdev) | |
736 | { | |
43aaf4f0 | 737 | struct resource *res; |
0a8b8353 | 738 | void __iomem *addr; |
0a8b8353 | 739 | |
43aaf4f0 | 740 | /* Get IPC resources */ |
0a8b8353 | 741 | res = platform_get_resource(pdev, IORESOURCE_MEM, |
742 | PLAT_RESOURCE_IPC_INDEX); | |
743 | if (!res) { | |
43aaf4f0 | 744 | dev_err(&pdev->dev, "Failed to get IPC resources\n"); |
0a8b8353 | 745 | return -ENXIO; |
746 | } | |
43aaf4f0 KS |
747 | |
748 | res->end = res->start + | |
749 | PLAT_RESOURCE_IPC_SIZE + PLAT_RESOURCE_GCR_SIZE - 1; | |
d7ca5ebf KS |
750 | |
751 | addr = devm_ioremap_resource(&pdev->dev, res); | |
752 | if (IS_ERR(addr)) | |
753 | return PTR_ERR(addr); | |
76062b4a | 754 | |
0a8b8353 | 755 | ipcdev.ipc_base = addr; |
49670206 | 756 | ipcdev.gcr_mem_base = addr + PLAT_RESOURCE_GCR_OFFSET; |
43aaf4f0 | 757 | dev_dbg(&pdev->dev, "PMC IPC resource %pR\n", res); |
48c19170 | 758 | |
0a8b8353 | 759 | return 0; |
760 | } | |
761 | ||
76062b4a SM |
762 | /** |
763 | * intel_pmc_s0ix_counter_read() - Read S0ix residency. | |
764 | * @data: Out param that contains current S0ix residency count. | |
765 | * | |
766 | * Return: an error code or 0 on success. | |
767 | */ | |
768 | int intel_pmc_s0ix_counter_read(u64 *data) | |
769 | { | |
770 | u64 deep, shlw; | |
771 | ||
772 | if (!ipcdev.has_gcr_regs) | |
773 | return -EACCES; | |
774 | ||
62a7b9c8 KS |
775 | deep = gcr_data_readq(PMC_GCR_TELEM_DEEP_S0IX_REG); |
776 | shlw = gcr_data_readq(PMC_GCR_TELEM_SHLW_S0IX_REG); | |
76062b4a SM |
777 | |
778 | *data = S0IX_RESIDENCY_IN_USECS(deep, shlw); | |
779 | ||
780 | return 0; | |
781 | } | |
782 | EXPORT_SYMBOL_GPL(intel_pmc_s0ix_counter_read); | |
783 | ||
0a8b8353 | 784 | #ifdef CONFIG_ACPI |
785 | static const struct acpi_device_id ipc_acpi_ids[] = { | |
786 | { "INT34D2", 0}, | |
787 | { } | |
788 | }; | |
789 | MODULE_DEVICE_TABLE(acpi, ipc_acpi_ids); | |
790 | #endif | |
791 | ||
792 | static int ipc_plat_probe(struct platform_device *pdev) | |
793 | { | |
0a8b8353 | 794 | int ret; |
795 | ||
796 | ipcdev.dev = &pdev->dev; | |
797 | ipcdev.irq_mode = IPC_TRIGGER_MODE_IRQ; | |
798 | init_completion(&ipcdev.cmd_complete); | |
e3075fd6 | 799 | spin_lock_init(&ipcdev.gcr_lock); |
0a8b8353 | 800 | |
801 | ipcdev.irq = platform_get_irq(pdev, 0); | |
802 | if (ipcdev.irq < 0) { | |
43aaf4f0 | 803 | dev_err(&pdev->dev, "Failed to get IRQ\n"); |
0a8b8353 | 804 | return -EINVAL; |
805 | } | |
806 | ||
807 | ret = ipc_plat_get_res(pdev); | |
808 | if (ret) { | |
809 | dev_err(&pdev->dev, "Failed to request resource\n"); | |
810 | return ret; | |
811 | } | |
812 | ||
43aaf4f0 | 813 | ret = ipc_create_pmc_devices(pdev); |
0a8b8353 | 814 | if (ret) { |
43aaf4f0 | 815 | dev_err(&pdev->dev, "Failed to create PMC devices\n"); |
d7ca5ebf | 816 | return ret; |
0a8b8353 | 817 | } |
818 | ||
43aaf4f0 KS |
819 | ret = devm_request_irq(&pdev->dev, ipcdev.irq, ioc, IRQF_NO_SUSPEND, |
820 | "intel_pmc_ipc", &ipcdev); | |
821 | if (ret) { | |
822 | dev_err(&pdev->dev, "Failed to request IRQ\n"); | |
823 | return ret; | |
0a8b8353 | 824 | } |
825 | ||
826 | ret = sysfs_create_group(&pdev->dev.kobj, &intel_ipc_group); | |
827 | if (ret) { | |
828 | dev_err(&pdev->dev, "Failed to create sysfs group %d\n", | |
829 | ret); | |
43aaf4f0 KS |
830 | devm_free_irq(&pdev->dev, ipcdev.irq, &ipcdev); |
831 | return ret; | |
0a8b8353 | 832 | } |
833 | ||
76062b4a SM |
834 | ipcdev.has_gcr_regs = true; |
835 | ||
0a8b8353 | 836 | return 0; |
0a8b8353 | 837 | } |
838 | ||
839 | static int ipc_plat_remove(struct platform_device *pdev) | |
840 | { | |
0a8b8353 | 841 | sysfs_remove_group(&pdev->dev.kobj, &intel_ipc_group); |
d7ca5ebf | 842 | devm_free_irq(&pdev->dev, ipcdev.irq, &ipcdev); |
0a8b8353 | 843 | ipcdev.dev = NULL; |
43aaf4f0 | 844 | |
0a8b8353 | 845 | return 0; |
846 | } | |
847 | ||
848 | static struct platform_driver ipc_plat_driver = { | |
849 | .remove = ipc_plat_remove, | |
850 | .probe = ipc_plat_probe, | |
851 | .driver = { | |
852 | .name = "pmc-ipc-plat", | |
853 | .acpi_match_table = ACPI_PTR(ipc_acpi_ids), | |
854 | }, | |
855 | }; | |
856 | ||
857 | static int __init intel_pmc_ipc_init(void) | |
858 | { | |
859 | int ret; | |
860 | ||
861 | ret = platform_driver_register(&ipc_plat_driver); | |
862 | if (ret) { | |
43aaf4f0 | 863 | pr_err("Failed to register PMC IPC platform driver\n"); |
0a8b8353 | 864 | return ret; |
865 | } | |
866 | ret = pci_register_driver(&ipc_pci_driver); | |
867 | if (ret) { | |
43aaf4f0 | 868 | pr_err("Failed to register PMC IPC PCI driver\n"); |
0a8b8353 | 869 | platform_driver_unregister(&ipc_plat_driver); |
870 | return ret; | |
871 | } | |
872 | return ret; | |
873 | } | |
874 | ||
875 | static void __exit intel_pmc_ipc_exit(void) | |
876 | { | |
877 | pci_unregister_driver(&ipc_pci_driver); | |
878 | platform_driver_unregister(&ipc_plat_driver); | |
879 | } | |
880 | ||
881 | MODULE_AUTHOR("Zha Qipeng <qipeng.zha@intel.com>"); | |
882 | MODULE_DESCRIPTION("Intel PMC IPC driver"); | |
883 | MODULE_LICENSE("GPL"); | |
884 | ||
885 | /* Some modules are dependent on this, so init earlier */ | |
886 | fs_initcall(intel_pmc_ipc_init); | |
887 | module_exit(intel_pmc_ipc_exit); |