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ad51f287 | 1 | // SPDX-License-Identifier: GPL-2.0 |
0a8b8353 | 2 | /* |
ad51f287 | 3 | * Driver for the Intel PMC IPC mechanism |
0a8b8353 | 4 | * |
5 | * (C) Copyright 2014-2015 Intel Corporation | |
6 | * | |
ad51f287 | 7 | * This driver is based on Intel SCU IPC driver(intel_scu_ipc.c) by |
0a8b8353 | 8 | * Sreedhara DS <sreedhara.ds@intel.com> |
9 | * | |
0a8b8353 | 10 | * PMC running in ARC processor communicates with other entity running in IA |
11 | * core through IPC mechanism which in turn messaging between IA core ad PMC. | |
12 | */ | |
13 | ||
90881772 AS |
14 | #include <linux/acpi.h> |
15 | #include <linux/atomic.h> | |
16 | #include <linux/bitops.h> | |
0a8b8353 | 17 | #include <linux/delay.h> |
0a8b8353 | 18 | #include <linux/device.h> |
90881772 AS |
19 | #include <linux/errno.h> |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/io-64-nonatomic-lo-hi.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/notifier.h> | |
0a8b8353 | 25 | #include <linux/pci.h> |
26 | #include <linux/platform_device.h> | |
90881772 | 27 | #include <linux/pm.h> |
0a8b8353 | 28 | #include <linux/pm_qos.h> |
0a8b8353 | 29 | #include <linux/sched.h> |
6687aeb9 | 30 | #include <linux/spinlock.h> |
90881772 | 31 | #include <linux/suspend.h> |
76062b4a | 32 | |
0a8b8353 | 33 | #include <asm/intel_pmc_ipc.h> |
76062b4a | 34 | |
420b54de | 35 | #include <linux/platform_data/itco_wdt.h> |
0a8b8353 | 36 | |
37 | /* | |
38 | * IPC registers | |
39 | * The IA write to IPC_CMD command register triggers an interrupt to the ARC, | |
40 | * The ARC handles the interrupt and services it, writing optional data to | |
41 | * the IPC1 registers, updates the IPC_STS response register with the status. | |
42 | */ | |
9eac0d75 | 43 | #define IPC_CMD 0x00 |
0084cf6a | 44 | #define IPC_CMD_MSI BIT(8) |
0a8b8353 | 45 | #define IPC_CMD_SIZE 16 |
46 | #define IPC_CMD_SUBCMD 12 | |
47 | #define IPC_STATUS 0x04 | |
0084cf6a AS |
48 | #define IPC_STATUS_IRQ BIT(2) |
49 | #define IPC_STATUS_ERR BIT(1) | |
50 | #define IPC_STATUS_BUSY BIT(0) | |
0a8b8353 | 51 | #define IPC_SPTR 0x08 |
52 | #define IPC_DPTR 0x0C | |
53 | #define IPC_WRITE_BUFFER 0x80 | |
54 | #define IPC_READ_BUFFER 0x90 | |
55 | ||
76062b4a SM |
56 | /* Residency with clock rate at 19.2MHz to usecs */ |
57 | #define S0IX_RESIDENCY_IN_USECS(d, s) \ | |
58 | ({ \ | |
59 | u64 result = 10ull * ((d) + (s)); \ | |
60 | do_div(result, 192); \ | |
61 | result; \ | |
62 | }) | |
63 | ||
0a8b8353 | 64 | /* |
65 | * 16-byte buffer for sending data associated with IPC command. | |
66 | */ | |
67 | #define IPC_DATA_BUFFER_SIZE 16 | |
68 | ||
69 | #define IPC_LOOP_CNT 3000000 | |
70 | #define IPC_MAX_SEC 3 | |
71 | ||
72 | #define IPC_TRIGGER_MODE_IRQ true | |
73 | ||
74 | /* exported resources from IFWI */ | |
75 | #define PLAT_RESOURCE_IPC_INDEX 0 | |
76 | #define PLAT_RESOURCE_IPC_SIZE 0x1000 | |
e6749c89 | 77 | #define PLAT_RESOURCE_GCR_OFFSET 0x1000 |
76062b4a | 78 | #define PLAT_RESOURCE_GCR_SIZE 0x1000 |
8cc7fb4a QZ |
79 | #define PLAT_RESOURCE_BIOS_DATA_INDEX 1 |
80 | #define PLAT_RESOURCE_BIOS_IFACE_INDEX 2 | |
48c19170 | 81 | #define PLAT_RESOURCE_TELEM_SSRAM_INDEX 3 |
8cc7fb4a QZ |
82 | #define PLAT_RESOURCE_ISP_DATA_INDEX 4 |
83 | #define PLAT_RESOURCE_ISP_IFACE_INDEX 5 | |
84 | #define PLAT_RESOURCE_GTD_DATA_INDEX 6 | |
85 | #define PLAT_RESOURCE_GTD_IFACE_INDEX 7 | |
0a8b8353 | 86 | #define PLAT_RESOURCE_ACPI_IO_INDEX 0 |
87 | ||
88 | /* | |
89 | * BIOS does not create an ACPI device for each PMC function, | |
90 | * but exports multiple resources from one ACPI device(IPC) for | |
91 | * multiple functions. This driver is responsible to create a | |
92 | * platform device and to export resources for those functions. | |
93 | */ | |
94 | #define TCO_DEVICE_NAME "iTCO_wdt" | |
334da2d6 | 95 | #define SMI_EN_OFFSET 0x40 |
0a8b8353 | 96 | #define SMI_EN_SIZE 4 |
97 | #define TCO_BASE_OFFSET 0x60 | |
98 | #define TCO_REGS_SIZE 16 | |
99 | #define PUNIT_DEVICE_NAME "intel_punit_ipc" | |
48c19170 SKC |
100 | #define TELEMETRY_DEVICE_NAME "intel_telemetry" |
101 | #define TELEM_SSRAM_SIZE 240 | |
102 | #define TELEM_PMC_SSRAM_OFFSET 0x1B00 | |
103 | #define TELEM_PUNIT_SSRAM_OFFSET 0x1A00 | |
9eac0d75 AS |
104 | #define TCO_PMC_OFFSET 0x08 |
105 | #define TCO_PMC_SIZE 0x04 | |
0a8b8353 | 106 | |
9d855d46 KS |
107 | /* PMC register bit definitions */ |
108 | ||
109 | /* PMC_CFG_REG bit masks */ | |
0084cf6a | 110 | #define PMC_CFG_NO_REBOOT_MASK BIT_MASK(4) |
9d855d46 KS |
111 | #define PMC_CFG_NO_REBOOT_EN (1 << 4) |
112 | #define PMC_CFG_NO_REBOOT_DIS (0 << 4) | |
113 | ||
0a8b8353 | 114 | static struct intel_pmc_ipc_dev { |
115 | struct device *dev; | |
116 | void __iomem *ipc_base; | |
117 | bool irq_mode; | |
118 | int irq; | |
119 | int cmd; | |
120 | struct completion cmd_complete; | |
121 | ||
122 | /* The following PMC BARs share the same ACPI device with the IPC */ | |
b78fb51b | 123 | resource_size_t acpi_io_base; |
0a8b8353 | 124 | int acpi_io_size; |
125 | struct platform_device *tco_dev; | |
126 | ||
127 | /* gcr */ | |
49670206 | 128 | void __iomem *gcr_mem_base; |
76062b4a | 129 | bool has_gcr_regs; |
6687aeb9 | 130 | spinlock_t gcr_lock; |
0a8b8353 | 131 | |
132 | /* punit */ | |
0a8b8353 | 133 | struct platform_device *punit_dev; |
af6c7e1f | 134 | unsigned int punit_res_count; |
48c19170 SKC |
135 | |
136 | /* Telemetry */ | |
137 | resource_size_t telem_pmc_ssram_base; | |
138 | resource_size_t telem_punit_ssram_base; | |
139 | int telem_pmc_ssram_size; | |
140 | int telem_punit_ssram_size; | |
141 | u8 telem_res_inval; | |
142 | struct platform_device *telemetry_dev; | |
0a8b8353 | 143 | } ipcdev; |
144 | ||
145 | static char *ipc_err_sources[] = { | |
146 | [IPC_ERR_NONE] = | |
147 | "no error", | |
148 | [IPC_ERR_CMD_NOT_SUPPORTED] = | |
149 | "command not supported", | |
150 | [IPC_ERR_CMD_NOT_SERVICED] = | |
151 | "command not serviced", | |
152 | [IPC_ERR_UNABLE_TO_SERVICE] = | |
153 | "unable to service", | |
154 | [IPC_ERR_CMD_INVALID] = | |
155 | "command invalid", | |
156 | [IPC_ERR_CMD_FAILED] = | |
157 | "command failed", | |
158 | [IPC_ERR_EMSECURITY] = | |
159 | "Invalid Battery", | |
160 | [IPC_ERR_UNSIGNEDKERNEL] = | |
161 | "Unsigned kernel", | |
162 | }; | |
163 | ||
164 | /* Prevent concurrent calls to the PMC */ | |
165 | static DEFINE_MUTEX(ipclock); | |
166 | ||
167 | static inline void ipc_send_command(u32 cmd) | |
168 | { | |
169 | ipcdev.cmd = cmd; | |
170 | if (ipcdev.irq_mode) { | |
171 | reinit_completion(&ipcdev.cmd_complete); | |
172 | cmd |= IPC_CMD_MSI; | |
173 | } | |
174 | writel(cmd, ipcdev.ipc_base + IPC_CMD); | |
175 | } | |
176 | ||
177 | static inline u32 ipc_read_status(void) | |
178 | { | |
179 | return readl(ipcdev.ipc_base + IPC_STATUS); | |
180 | } | |
181 | ||
182 | static inline void ipc_data_writel(u32 data, u32 offset) | |
183 | { | |
184 | writel(data, ipcdev.ipc_base + IPC_WRITE_BUFFER + offset); | |
185 | } | |
186 | ||
6bee1af9 | 187 | static inline u8 __maybe_unused ipc_data_readb(u32 offset) |
0a8b8353 | 188 | { |
189 | return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset); | |
190 | } | |
191 | ||
192 | static inline u32 ipc_data_readl(u32 offset) | |
193 | { | |
194 | return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset); | |
195 | } | |
196 | ||
76062b4a SM |
197 | static inline u64 gcr_data_readq(u32 offset) |
198 | { | |
62a7b9c8 | 199 | return readq(ipcdev.gcr_mem_base + offset); |
76062b4a SM |
200 | } |
201 | ||
49670206 KS |
202 | static inline int is_gcr_valid(u32 offset) |
203 | { | |
204 | if (!ipcdev.has_gcr_regs) | |
205 | return -EACCES; | |
206 | ||
207 | if (offset > PLAT_RESOURCE_GCR_SIZE) | |
208 | return -EINVAL; | |
209 | ||
210 | return 0; | |
211 | } | |
212 | ||
213 | /** | |
9c916549 | 214 | * intel_pmc_gcr_read() - Read a 32-bit PMC GCR register |
49670206 KS |
215 | * @offset: offset of GCR register from GCR address base |
216 | * @data: data pointer for storing the register output | |
217 | * | |
9c916549 | 218 | * Reads the 32-bit PMC GCR register at given offset. |
49670206 KS |
219 | * |
220 | * Return: negative value on error or 0 on success. | |
221 | */ | |
222 | int intel_pmc_gcr_read(u32 offset, u32 *data) | |
223 | { | |
224 | int ret; | |
225 | ||
6687aeb9 | 226 | spin_lock(&ipcdev.gcr_lock); |
49670206 KS |
227 | |
228 | ret = is_gcr_valid(offset); | |
229 | if (ret < 0) { | |
6687aeb9 | 230 | spin_unlock(&ipcdev.gcr_lock); |
49670206 KS |
231 | return ret; |
232 | } | |
233 | ||
234 | *data = readl(ipcdev.gcr_mem_base + offset); | |
235 | ||
6687aeb9 | 236 | spin_unlock(&ipcdev.gcr_lock); |
49670206 KS |
237 | |
238 | return 0; | |
239 | } | |
240 | EXPORT_SYMBOL_GPL(intel_pmc_gcr_read); | |
241 | ||
9c916549 CS |
242 | /** |
243 | * intel_pmc_gcr_read64() - Read a 64-bit PMC GCR register | |
244 | * @offset: offset of GCR register from GCR address base | |
245 | * @data: data pointer for storing the register output | |
246 | * | |
247 | * Reads the 64-bit PMC GCR register at given offset. | |
248 | * | |
249 | * Return: negative value on error or 0 on success. | |
250 | */ | |
251 | int intel_pmc_gcr_read64(u32 offset, u64 *data) | |
252 | { | |
253 | int ret; | |
254 | ||
255 | spin_lock(&ipcdev.gcr_lock); | |
256 | ||
257 | ret = is_gcr_valid(offset); | |
258 | if (ret < 0) { | |
259 | spin_unlock(&ipcdev.gcr_lock); | |
260 | return ret; | |
261 | } | |
262 | ||
263 | *data = readq(ipcdev.gcr_mem_base + offset); | |
264 | ||
265 | spin_unlock(&ipcdev.gcr_lock); | |
266 | ||
267 | return 0; | |
268 | } | |
269 | EXPORT_SYMBOL_GPL(intel_pmc_gcr_read64); | |
270 | ||
49670206 KS |
271 | /** |
272 | * intel_pmc_gcr_write() - Write PMC GCR register | |
273 | * @offset: offset of GCR register from GCR address base | |
274 | * @data: register update value | |
275 | * | |
276 | * Writes the PMC GCR register of given offset with given | |
277 | * value. | |
278 | * | |
279 | * Return: negative value on error or 0 on success. | |
280 | */ | |
281 | int intel_pmc_gcr_write(u32 offset, u32 data) | |
282 | { | |
283 | int ret; | |
284 | ||
6687aeb9 | 285 | spin_lock(&ipcdev.gcr_lock); |
49670206 KS |
286 | |
287 | ret = is_gcr_valid(offset); | |
288 | if (ret < 0) { | |
6687aeb9 | 289 | spin_unlock(&ipcdev.gcr_lock); |
49670206 KS |
290 | return ret; |
291 | } | |
292 | ||
293 | writel(data, ipcdev.gcr_mem_base + offset); | |
294 | ||
6687aeb9 | 295 | spin_unlock(&ipcdev.gcr_lock); |
49670206 KS |
296 | |
297 | return 0; | |
298 | } | |
299 | EXPORT_SYMBOL_GPL(intel_pmc_gcr_write); | |
300 | ||
301 | /** | |
302 | * intel_pmc_gcr_update() - Update PMC GCR register bits | |
303 | * @offset: offset of GCR register from GCR address base | |
304 | * @mask: bit mask for update operation | |
305 | * @val: update value | |
306 | * | |
307 | * Updates the bits of given GCR register as specified by | |
308 | * @mask and @val. | |
309 | * | |
310 | * Return: negative value on error or 0 on success. | |
311 | */ | |
312 | int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val) | |
313 | { | |
314 | u32 new_val; | |
315 | int ret = 0; | |
316 | ||
6687aeb9 | 317 | spin_lock(&ipcdev.gcr_lock); |
49670206 KS |
318 | |
319 | ret = is_gcr_valid(offset); | |
320 | if (ret < 0) | |
321 | goto gcr_ipc_unlock; | |
322 | ||
323 | new_val = readl(ipcdev.gcr_mem_base + offset); | |
324 | ||
325 | new_val &= ~mask; | |
326 | new_val |= val & mask; | |
327 | ||
328 | writel(new_val, ipcdev.gcr_mem_base + offset); | |
329 | ||
330 | new_val = readl(ipcdev.gcr_mem_base + offset); | |
331 | ||
332 | /* check whether the bit update is successful */ | |
333 | if ((new_val & mask) != (val & mask)) { | |
334 | ret = -EIO; | |
335 | goto gcr_ipc_unlock; | |
336 | } | |
337 | ||
338 | gcr_ipc_unlock: | |
6687aeb9 | 339 | spin_unlock(&ipcdev.gcr_lock); |
49670206 KS |
340 | return ret; |
341 | } | |
342 | EXPORT_SYMBOL_GPL(intel_pmc_gcr_update); | |
343 | ||
9d855d46 KS |
344 | static int update_no_reboot_bit(void *priv, bool set) |
345 | { | |
346 | u32 value = set ? PMC_CFG_NO_REBOOT_EN : PMC_CFG_NO_REBOOT_DIS; | |
347 | ||
348 | return intel_pmc_gcr_update(PMC_GCR_PMC_CFG_REG, | |
349 | PMC_CFG_NO_REBOOT_MASK, value); | |
350 | } | |
351 | ||
0a8b8353 | 352 | static int intel_pmc_ipc_check_status(void) |
353 | { | |
354 | int status; | |
355 | int ret = 0; | |
356 | ||
357 | if (ipcdev.irq_mode) { | |
358 | if (0 == wait_for_completion_timeout( | |
359 | &ipcdev.cmd_complete, IPC_MAX_SEC * HZ)) | |
360 | ret = -ETIMEDOUT; | |
361 | } else { | |
362 | int loop_count = IPC_LOOP_CNT; | |
363 | ||
364 | while ((ipc_read_status() & IPC_STATUS_BUSY) && --loop_count) | |
365 | udelay(1); | |
366 | if (loop_count == 0) | |
367 | ret = -ETIMEDOUT; | |
368 | } | |
369 | ||
370 | status = ipc_read_status(); | |
371 | if (ret == -ETIMEDOUT) { | |
372 | dev_err(ipcdev.dev, | |
373 | "IPC timed out, TS=0x%x, CMD=0x%x\n", | |
374 | status, ipcdev.cmd); | |
375 | return ret; | |
376 | } | |
377 | ||
378 | if (status & IPC_STATUS_ERR) { | |
379 | int i; | |
380 | ||
381 | ret = -EIO; | |
382 | i = (status >> IPC_CMD_SIZE) & 0xFF; | |
383 | if (i < ARRAY_SIZE(ipc_err_sources)) | |
384 | dev_err(ipcdev.dev, | |
385 | "IPC failed: %s, STS=0x%x, CMD=0x%x\n", | |
386 | ipc_err_sources[i], status, ipcdev.cmd); | |
387 | else | |
388 | dev_err(ipcdev.dev, | |
389 | "IPC failed: unknown, STS=0x%x, CMD=0x%x\n", | |
390 | status, ipcdev.cmd); | |
391 | if ((i == IPC_ERR_UNSIGNEDKERNEL) || (i == IPC_ERR_EMSECURITY)) | |
392 | ret = -EACCES; | |
393 | } | |
394 | ||
395 | return ret; | |
396 | } | |
397 | ||
02941007 | 398 | /** |
399 | * intel_pmc_ipc_simple_command() - Simple IPC command | |
400 | * @cmd: IPC command code. | |
401 | * @sub: IPC command sub type. | |
402 | * | |
403 | * Send a simple IPC command to PMC when don't need to specify | |
404 | * input/output data and source/dest pointers. | |
405 | * | |
406 | * Return: an IPC error code or 0 on success. | |
0a8b8353 | 407 | */ |
408 | int intel_pmc_ipc_simple_command(int cmd, int sub) | |
409 | { | |
410 | int ret; | |
411 | ||
412 | mutex_lock(&ipclock); | |
413 | if (ipcdev.dev == NULL) { | |
414 | mutex_unlock(&ipclock); | |
415 | return -ENODEV; | |
416 | } | |
417 | ipc_send_command(sub << IPC_CMD_SUBCMD | cmd); | |
418 | ret = intel_pmc_ipc_check_status(); | |
419 | mutex_unlock(&ipclock); | |
420 | ||
421 | return ret; | |
422 | } | |
423 | EXPORT_SYMBOL_GPL(intel_pmc_ipc_simple_command); | |
424 | ||
02941007 | 425 | /** |
426 | * intel_pmc_ipc_raw_cmd() - IPC command with data and pointers | |
427 | * @cmd: IPC command code. | |
428 | * @sub: IPC command sub type. | |
429 | * @in: input data of this IPC command. | |
430 | * @inlen: input data length in bytes. | |
431 | * @out: output data of this IPC command. | |
432 | * @outlen: output data length in dwords. | |
433 | * @sptr: data writing to SPTR register. | |
434 | * @dptr: data writing to DPTR register. | |
435 | * | |
436 | * Send an IPC command to PMC with input/output data and source/dest pointers. | |
437 | * | |
438 | * Return: an IPC error code or 0 on success. | |
0a8b8353 | 439 | */ |
440 | int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen, u32 *out, | |
441 | u32 outlen, u32 dptr, u32 sptr) | |
442 | { | |
443 | u32 wbuf[4] = { 0 }; | |
444 | int ret; | |
445 | int i; | |
446 | ||
447 | if (inlen > IPC_DATA_BUFFER_SIZE || outlen > IPC_DATA_BUFFER_SIZE / 4) | |
448 | return -EINVAL; | |
449 | ||
450 | mutex_lock(&ipclock); | |
451 | if (ipcdev.dev == NULL) { | |
452 | mutex_unlock(&ipclock); | |
453 | return -ENODEV; | |
454 | } | |
455 | memcpy(wbuf, in, inlen); | |
456 | writel(dptr, ipcdev.ipc_base + IPC_DPTR); | |
457 | writel(sptr, ipcdev.ipc_base + IPC_SPTR); | |
458 | /* The input data register is 32bit register and inlen is in Byte */ | |
459 | for (i = 0; i < ((inlen + 3) / 4); i++) | |
460 | ipc_data_writel(wbuf[i], 4 * i); | |
461 | ipc_send_command((inlen << IPC_CMD_SIZE) | | |
462 | (sub << IPC_CMD_SUBCMD) | cmd); | |
463 | ret = intel_pmc_ipc_check_status(); | |
464 | if (!ret) { | |
465 | /* out is read from 32bit register and outlen is in 32bit */ | |
466 | for (i = 0; i < outlen; i++) | |
467 | *out++ = ipc_data_readl(4 * i); | |
468 | } | |
469 | mutex_unlock(&ipclock); | |
470 | ||
471 | return ret; | |
472 | } | |
473 | EXPORT_SYMBOL_GPL(intel_pmc_ipc_raw_cmd); | |
474 | ||
02941007 | 475 | /** |
476 | * intel_pmc_ipc_command() - IPC command with input/output data | |
477 | * @cmd: IPC command code. | |
478 | * @sub: IPC command sub type. | |
479 | * @in: input data of this IPC command. | |
480 | * @inlen: input data length in bytes. | |
481 | * @out: output data of this IPC command. | |
482 | * @outlen: output data length in dwords. | |
483 | * | |
484 | * Send an IPC command to PMC with input/output data. | |
485 | * | |
486 | * Return: an IPC error code or 0 on success. | |
0a8b8353 | 487 | */ |
488 | int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen, | |
489 | u32 *out, u32 outlen) | |
490 | { | |
491 | return intel_pmc_ipc_raw_cmd(cmd, sub, in, inlen, out, outlen, 0, 0); | |
492 | } | |
493 | EXPORT_SYMBOL_GPL(intel_pmc_ipc_command); | |
494 | ||
495 | static irqreturn_t ioc(int irq, void *dev_id) | |
496 | { | |
497 | int status; | |
498 | ||
499 | if (ipcdev.irq_mode) { | |
500 | status = ipc_read_status(); | |
501 | writel(status | IPC_STATUS_IRQ, ipcdev.ipc_base + IPC_STATUS); | |
502 | } | |
503 | complete(&ipcdev.cmd_complete); | |
504 | ||
505 | return IRQ_HANDLED; | |
506 | } | |
507 | ||
508 | static int ipc_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |
509 | { | |
83beee5c | 510 | struct intel_pmc_ipc_dev *pmc = &ipcdev; |
0a8b8353 | 511 | int ret; |
0a8b8353 | 512 | |
83beee5c KS |
513 | /* Only one PMC is supported */ |
514 | if (pmc->dev) | |
515 | return -EBUSY; | |
0a8b8353 | 516 | |
83beee5c KS |
517 | pmc->irq_mode = IPC_TRIGGER_MODE_IRQ; |
518 | ||
6687aeb9 KS |
519 | spin_lock_init(&ipcdev.gcr_lock); |
520 | ||
83beee5c | 521 | ret = pcim_enable_device(pdev); |
0a8b8353 | 522 | if (ret) |
523 | return ret; | |
524 | ||
83beee5c | 525 | ret = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev)); |
0a8b8353 | 526 | if (ret) |
527 | return ret; | |
528 | ||
83beee5c | 529 | init_completion(&pmc->cmd_complete); |
0a8b8353 | 530 | |
83beee5c | 531 | pmc->ipc_base = pcim_iomap_table(pdev)[0]; |
0a8b8353 | 532 | |
83beee5c KS |
533 | ret = devm_request_irq(&pdev->dev, pdev->irq, ioc, 0, "intel_pmc_ipc", |
534 | pmc); | |
535 | if (ret) { | |
0a8b8353 | 536 | dev_err(&pdev->dev, "Failed to request irq\n"); |
83beee5c | 537 | return ret; |
0a8b8353 | 538 | } |
539 | ||
83beee5c | 540 | pmc->dev = &pdev->dev; |
0a8b8353 | 541 | |
83beee5c | 542 | pci_set_drvdata(pdev, pmc); |
0a8b8353 | 543 | |
83beee5c | 544 | return 0; |
0a8b8353 | 545 | } |
546 | ||
547 | static const struct pci_device_id ipc_pci_ids[] = { | |
548 | {PCI_VDEVICE(INTEL, 0x0a94), 0}, | |
549 | {PCI_VDEVICE(INTEL, 0x1a94), 0}, | |
23e775db | 550 | {PCI_VDEVICE(INTEL, 0x5a94), 0}, |
0a8b8353 | 551 | { 0,} |
552 | }; | |
553 | MODULE_DEVICE_TABLE(pci, ipc_pci_ids); | |
554 | ||
555 | static struct pci_driver ipc_pci_driver = { | |
556 | .name = "intel_pmc_ipc", | |
557 | .id_table = ipc_pci_ids, | |
558 | .probe = ipc_pci_probe, | |
0a8b8353 | 559 | }; |
560 | ||
561 | static ssize_t intel_pmc_ipc_simple_cmd_store(struct device *dev, | |
562 | struct device_attribute *attr, | |
563 | const char *buf, size_t count) | |
564 | { | |
565 | int subcmd; | |
566 | int cmd; | |
567 | int ret; | |
568 | ||
569 | ret = sscanf(buf, "%d %d", &cmd, &subcmd); | |
570 | if (ret != 2) { | |
571 | dev_err(dev, "Error args\n"); | |
572 | return -EINVAL; | |
573 | } | |
574 | ||
575 | ret = intel_pmc_ipc_simple_command(cmd, subcmd); | |
576 | if (ret) { | |
577 | dev_err(dev, "command %d error with %d\n", cmd, ret); | |
578 | return ret; | |
579 | } | |
580 | return (ssize_t)count; | |
581 | } | |
582 | ||
583 | static ssize_t intel_pmc_ipc_northpeak_store(struct device *dev, | |
584 | struct device_attribute *attr, | |
585 | const char *buf, size_t count) | |
586 | { | |
587 | unsigned long val; | |
588 | int subcmd; | |
589 | int ret; | |
590 | ||
591 | if (kstrtoul(buf, 0, &val)) | |
592 | return -EINVAL; | |
593 | ||
594 | if (val) | |
595 | subcmd = 1; | |
596 | else | |
597 | subcmd = 0; | |
598 | ret = intel_pmc_ipc_simple_command(PMC_IPC_NORTHPEAK_CTRL, subcmd); | |
599 | if (ret) { | |
600 | dev_err(dev, "command north %d error with %d\n", subcmd, ret); | |
601 | return ret; | |
602 | } | |
603 | return (ssize_t)count; | |
604 | } | |
605 | ||
606 | static DEVICE_ATTR(simplecmd, S_IWUSR, | |
607 | NULL, intel_pmc_ipc_simple_cmd_store); | |
608 | static DEVICE_ATTR(northpeak, S_IWUSR, | |
609 | NULL, intel_pmc_ipc_northpeak_store); | |
610 | ||
611 | static struct attribute *intel_ipc_attrs[] = { | |
612 | &dev_attr_northpeak.attr, | |
613 | &dev_attr_simplecmd.attr, | |
614 | NULL | |
615 | }; | |
616 | ||
617 | static const struct attribute_group intel_ipc_group = { | |
618 | .attrs = intel_ipc_attrs, | |
619 | }; | |
620 | ||
8cc7fb4a QZ |
621 | static struct resource punit_res_array[] = { |
622 | /* Punit BIOS */ | |
623 | { | |
624 | .flags = IORESOURCE_MEM, | |
625 | }, | |
626 | { | |
627 | .flags = IORESOURCE_MEM, | |
628 | }, | |
629 | /* Punit ISP */ | |
630 | { | |
631 | .flags = IORESOURCE_MEM, | |
632 | }, | |
633 | { | |
634 | .flags = IORESOURCE_MEM, | |
635 | }, | |
636 | /* Punit GTD */ | |
0a8b8353 | 637 | { |
638 | .flags = IORESOURCE_MEM, | |
639 | }, | |
640 | { | |
641 | .flags = IORESOURCE_MEM, | |
642 | }, | |
643 | }; | |
644 | ||
645 | #define TCO_RESOURCE_ACPI_IO 0 | |
646 | #define TCO_RESOURCE_SMI_EN_IO 1 | |
647 | #define TCO_RESOURCE_GCR_MEM 2 | |
648 | static struct resource tco_res[] = { | |
649 | /* ACPI - TCO */ | |
650 | { | |
651 | .flags = IORESOURCE_IO, | |
652 | }, | |
653 | /* ACPI - SMI */ | |
654 | { | |
655 | .flags = IORESOURCE_IO, | |
656 | }, | |
0a8b8353 | 657 | }; |
658 | ||
420b54de | 659 | static struct itco_wdt_platform_data tco_info = { |
0a8b8353 | 660 | .name = "Apollo Lake SoC", |
334da2d6 | 661 | .version = 5, |
9d855d46 KS |
662 | .no_reboot_priv = &ipcdev, |
663 | .update_no_reboot_bit = update_no_reboot_bit, | |
0a8b8353 | 664 | }; |
665 | ||
48c19170 SKC |
666 | #define TELEMETRY_RESOURCE_PUNIT_SSRAM 0 |
667 | #define TELEMETRY_RESOURCE_PMC_SSRAM 1 | |
668 | static struct resource telemetry_res[] = { | |
669 | /*Telemetry*/ | |
670 | { | |
671 | .flags = IORESOURCE_MEM, | |
672 | }, | |
673 | { | |
674 | .flags = IORESOURCE_MEM, | |
675 | }, | |
676 | }; | |
677 | ||
0a8b8353 | 678 | static int ipc_create_punit_device(void) |
679 | { | |
680 | struct platform_device *pdev; | |
ea1a76ba AL |
681 | const struct platform_device_info pdevinfo = { |
682 | .parent = ipcdev.dev, | |
683 | .name = PUNIT_DEVICE_NAME, | |
684 | .id = -1, | |
685 | .res = punit_res_array, | |
af6c7e1f | 686 | .num_res = ipcdev.punit_res_count, |
ea1a76ba AL |
687 | }; |
688 | ||
689 | pdev = platform_device_register_full(&pdevinfo); | |
690 | if (IS_ERR(pdev)) | |
691 | return PTR_ERR(pdev); | |
0a8b8353 | 692 | |
0a8b8353 | 693 | ipcdev.punit_dev = pdev; |
694 | ||
695 | return 0; | |
0a8b8353 | 696 | } |
697 | ||
698 | static int ipc_create_tco_device(void) | |
699 | { | |
700 | struct platform_device *pdev; | |
701 | struct resource *res; | |
ea1a76ba AL |
702 | const struct platform_device_info pdevinfo = { |
703 | .parent = ipcdev.dev, | |
704 | .name = TCO_DEVICE_NAME, | |
705 | .id = -1, | |
706 | .res = tco_res, | |
707 | .num_res = ARRAY_SIZE(tco_res), | |
708 | .data = &tco_info, | |
709 | .size_data = sizeof(tco_info), | |
710 | }; | |
0a8b8353 | 711 | |
712 | res = tco_res + TCO_RESOURCE_ACPI_IO; | |
b78fb51b | 713 | res->start = ipcdev.acpi_io_base + TCO_BASE_OFFSET; |
0a8b8353 | 714 | res->end = res->start + TCO_REGS_SIZE - 1; |
715 | ||
716 | res = tco_res + TCO_RESOURCE_SMI_EN_IO; | |
b78fb51b | 717 | res->start = ipcdev.acpi_io_base + SMI_EN_OFFSET; |
0a8b8353 | 718 | res->end = res->start + SMI_EN_SIZE - 1; |
719 | ||
ea1a76ba AL |
720 | pdev = platform_device_register_full(&pdevinfo); |
721 | if (IS_ERR(pdev)) | |
722 | return PTR_ERR(pdev); | |
0a8b8353 | 723 | |
0a8b8353 | 724 | ipcdev.tco_dev = pdev; |
725 | ||
726 | return 0; | |
0a8b8353 | 727 | } |
728 | ||
48c19170 SKC |
729 | static int ipc_create_telemetry_device(void) |
730 | { | |
731 | struct platform_device *pdev; | |
732 | struct resource *res; | |
ea1a76ba AL |
733 | const struct platform_device_info pdevinfo = { |
734 | .parent = ipcdev.dev, | |
735 | .name = TELEMETRY_DEVICE_NAME, | |
736 | .id = -1, | |
737 | .res = telemetry_res, | |
738 | .num_res = ARRAY_SIZE(telemetry_res), | |
739 | }; | |
48c19170 SKC |
740 | |
741 | res = telemetry_res + TELEMETRY_RESOURCE_PUNIT_SSRAM; | |
742 | res->start = ipcdev.telem_punit_ssram_base; | |
743 | res->end = res->start + ipcdev.telem_punit_ssram_size - 1; | |
744 | ||
745 | res = telemetry_res + TELEMETRY_RESOURCE_PMC_SSRAM; | |
746 | res->start = ipcdev.telem_pmc_ssram_base; | |
747 | res->end = res->start + ipcdev.telem_pmc_ssram_size - 1; | |
748 | ||
ea1a76ba AL |
749 | pdev = platform_device_register_full(&pdevinfo); |
750 | if (IS_ERR(pdev)) | |
751 | return PTR_ERR(pdev); | |
48c19170 | 752 | |
48c19170 SKC |
753 | ipcdev.telemetry_dev = pdev; |
754 | ||
755 | return 0; | |
48c19170 SKC |
756 | } |
757 | ||
0a8b8353 | 758 | static int ipc_create_pmc_devices(void) |
759 | { | |
760 | int ret; | |
761 | ||
bba6529e MW |
762 | /* If we have ACPI based watchdog use that instead */ |
763 | if (!acpi_has_watchdog()) { | |
764 | ret = ipc_create_tco_device(); | |
765 | if (ret) { | |
766 | dev_err(ipcdev.dev, "Failed to add tco platform device\n"); | |
767 | return ret; | |
768 | } | |
0a8b8353 | 769 | } |
bba6529e | 770 | |
0a8b8353 | 771 | ret = ipc_create_punit_device(); |
772 | if (ret) { | |
773 | dev_err(ipcdev.dev, "Failed to add punit platform device\n"); | |
774 | platform_device_unregister(ipcdev.tco_dev); | |
e61985d0 | 775 | return ret; |
0a8b8353 | 776 | } |
48c19170 SKC |
777 | |
778 | if (!ipcdev.telem_res_inval) { | |
779 | ret = ipc_create_telemetry_device(); | |
e61985d0 | 780 | if (ret) { |
48c19170 SKC |
781 | dev_warn(ipcdev.dev, |
782 | "Failed to add telemetry platform device\n"); | |
e61985d0 JC |
783 | platform_device_unregister(ipcdev.punit_dev); |
784 | platform_device_unregister(ipcdev.tco_dev); | |
785 | } | |
48c19170 SKC |
786 | } |
787 | ||
0a8b8353 | 788 | return ret; |
789 | } | |
790 | ||
791 | static int ipc_plat_get_res(struct platform_device *pdev) | |
792 | { | |
af6c7e1f | 793 | struct resource *res, *punit_res = punit_res_array; |
0a8b8353 | 794 | void __iomem *addr; |
795 | int size; | |
796 | ||
797 | res = platform_get_resource(pdev, IORESOURCE_IO, | |
798 | PLAT_RESOURCE_ACPI_IO_INDEX); | |
799 | if (!res) { | |
800 | dev_err(&pdev->dev, "Failed to get io resource\n"); | |
801 | return -ENXIO; | |
802 | } | |
803 | size = resource_size(res); | |
b78fb51b | 804 | ipcdev.acpi_io_base = res->start; |
0a8b8353 | 805 | ipcdev.acpi_io_size = size; |
8cc7fb4a | 806 | dev_info(&pdev->dev, "io res: %pR\n", res); |
0a8b8353 | 807 | |
af6c7e1f AS |
808 | ipcdev.punit_res_count = 0; |
809 | ||
5d071633 | 810 | /* This is index 0 to cover BIOS data register */ |
0a8b8353 | 811 | res = platform_get_resource(pdev, IORESOURCE_MEM, |
8cc7fb4a | 812 | PLAT_RESOURCE_BIOS_DATA_INDEX); |
0a8b8353 | 813 | if (!res) { |
8cc7fb4a | 814 | dev_err(&pdev->dev, "Failed to get res of punit BIOS data\n"); |
0a8b8353 | 815 | return -ENXIO; |
816 | } | |
af6c7e1f | 817 | punit_res[ipcdev.punit_res_count++] = *res; |
8cc7fb4a | 818 | dev_info(&pdev->dev, "punit BIOS data res: %pR\n", res); |
0a8b8353 | 819 | |
5d071633 | 820 | /* This is index 1 to cover BIOS interface register */ |
0a8b8353 | 821 | res = platform_get_resource(pdev, IORESOURCE_MEM, |
8cc7fb4a | 822 | PLAT_RESOURCE_BIOS_IFACE_INDEX); |
0a8b8353 | 823 | if (!res) { |
8cc7fb4a | 824 | dev_err(&pdev->dev, "Failed to get res of punit BIOS iface\n"); |
0a8b8353 | 825 | return -ENXIO; |
826 | } | |
af6c7e1f | 827 | punit_res[ipcdev.punit_res_count++] = *res; |
8cc7fb4a QZ |
828 | dev_info(&pdev->dev, "punit BIOS interface res: %pR\n", res); |
829 | ||
5d071633 | 830 | /* This is index 2 to cover ISP data register, optional */ |
8cc7fb4a QZ |
831 | res = platform_get_resource(pdev, IORESOURCE_MEM, |
832 | PLAT_RESOURCE_ISP_DATA_INDEX); | |
5d071633 | 833 | if (res) { |
af6c7e1f | 834 | punit_res[ipcdev.punit_res_count++] = *res; |
5d071633 | 835 | dev_info(&pdev->dev, "punit ISP data res: %pR\n", res); |
8cc7fb4a | 836 | } |
8cc7fb4a | 837 | |
5d071633 | 838 | /* This is index 3 to cover ISP interface register, optional */ |
8cc7fb4a QZ |
839 | res = platform_get_resource(pdev, IORESOURCE_MEM, |
840 | PLAT_RESOURCE_ISP_IFACE_INDEX); | |
5d071633 | 841 | if (res) { |
af6c7e1f | 842 | punit_res[ipcdev.punit_res_count++] = *res; |
5d071633 | 843 | dev_info(&pdev->dev, "punit ISP interface res: %pR\n", res); |
8cc7fb4a | 844 | } |
8cc7fb4a | 845 | |
5d071633 | 846 | /* This is index 4 to cover GTD data register, optional */ |
8cc7fb4a QZ |
847 | res = platform_get_resource(pdev, IORESOURCE_MEM, |
848 | PLAT_RESOURCE_GTD_DATA_INDEX); | |
5d071633 | 849 | if (res) { |
af6c7e1f | 850 | punit_res[ipcdev.punit_res_count++] = *res; |
5d071633 | 851 | dev_info(&pdev->dev, "punit GTD data res: %pR\n", res); |
8cc7fb4a | 852 | } |
8cc7fb4a | 853 | |
5d071633 | 854 | /* This is index 5 to cover GTD interface register, optional */ |
8cc7fb4a QZ |
855 | res = platform_get_resource(pdev, IORESOURCE_MEM, |
856 | PLAT_RESOURCE_GTD_IFACE_INDEX); | |
5d071633 | 857 | if (res) { |
af6c7e1f | 858 | punit_res[ipcdev.punit_res_count++] = *res; |
5d071633 | 859 | dev_info(&pdev->dev, "punit GTD interface res: %pR\n", res); |
8cc7fb4a | 860 | } |
0a8b8353 | 861 | |
862 | res = platform_get_resource(pdev, IORESOURCE_MEM, | |
863 | PLAT_RESOURCE_IPC_INDEX); | |
864 | if (!res) { | |
865 | dev_err(&pdev->dev, "Failed to get ipc resource\n"); | |
866 | return -ENXIO; | |
867 | } | |
76062b4a | 868 | size = PLAT_RESOURCE_IPC_SIZE + PLAT_RESOURCE_GCR_SIZE; |
83beee5c KS |
869 | res->end = res->start + size - 1; |
870 | ||
871 | addr = devm_ioremap_resource(&pdev->dev, res); | |
872 | if (IS_ERR(addr)) | |
873 | return PTR_ERR(addr); | |
76062b4a | 874 | |
0a8b8353 | 875 | ipcdev.ipc_base = addr; |
876 | ||
49670206 | 877 | ipcdev.gcr_mem_base = addr + PLAT_RESOURCE_GCR_OFFSET; |
8cc7fb4a | 878 | dev_info(&pdev->dev, "ipc res: %pR\n", res); |
0a8b8353 | 879 | |
48c19170 SKC |
880 | ipcdev.telem_res_inval = 0; |
881 | res = platform_get_resource(pdev, IORESOURCE_MEM, | |
882 | PLAT_RESOURCE_TELEM_SSRAM_INDEX); | |
883 | if (!res) { | |
884 | dev_err(&pdev->dev, "Failed to get telemetry ssram resource\n"); | |
885 | ipcdev.telem_res_inval = 1; | |
886 | } else { | |
887 | ipcdev.telem_punit_ssram_base = res->start + | |
888 | TELEM_PUNIT_SSRAM_OFFSET; | |
889 | ipcdev.telem_punit_ssram_size = TELEM_SSRAM_SIZE; | |
890 | ipcdev.telem_pmc_ssram_base = res->start + | |
891 | TELEM_PMC_SSRAM_OFFSET; | |
892 | ipcdev.telem_pmc_ssram_size = TELEM_SSRAM_SIZE; | |
893 | dev_info(&pdev->dev, "telemetry ssram res: %pR\n", res); | |
894 | } | |
895 | ||
0a8b8353 | 896 | return 0; |
897 | } | |
898 | ||
76062b4a SM |
899 | /** |
900 | * intel_pmc_s0ix_counter_read() - Read S0ix residency. | |
901 | * @data: Out param that contains current S0ix residency count. | |
902 | * | |
903 | * Return: an error code or 0 on success. | |
904 | */ | |
905 | int intel_pmc_s0ix_counter_read(u64 *data) | |
906 | { | |
907 | u64 deep, shlw; | |
908 | ||
909 | if (!ipcdev.has_gcr_regs) | |
910 | return -EACCES; | |
911 | ||
62a7b9c8 KS |
912 | deep = gcr_data_readq(PMC_GCR_TELEM_DEEP_S0IX_REG); |
913 | shlw = gcr_data_readq(PMC_GCR_TELEM_SHLW_S0IX_REG); | |
76062b4a SM |
914 | |
915 | *data = S0IX_RESIDENCY_IN_USECS(deep, shlw); | |
916 | ||
917 | return 0; | |
918 | } | |
919 | EXPORT_SYMBOL_GPL(intel_pmc_s0ix_counter_read); | |
920 | ||
0a8b8353 | 921 | #ifdef CONFIG_ACPI |
922 | static const struct acpi_device_id ipc_acpi_ids[] = { | |
923 | { "INT34D2", 0}, | |
924 | { } | |
925 | }; | |
926 | MODULE_DEVICE_TABLE(acpi, ipc_acpi_ids); | |
927 | #endif | |
928 | ||
929 | static int ipc_plat_probe(struct platform_device *pdev) | |
930 | { | |
0a8b8353 | 931 | int ret; |
932 | ||
933 | ipcdev.dev = &pdev->dev; | |
934 | ipcdev.irq_mode = IPC_TRIGGER_MODE_IRQ; | |
935 | init_completion(&ipcdev.cmd_complete); | |
6687aeb9 | 936 | spin_lock_init(&ipcdev.gcr_lock); |
0a8b8353 | 937 | |
938 | ipcdev.irq = platform_get_irq(pdev, 0); | |
939 | if (ipcdev.irq < 0) { | |
940 | dev_err(&pdev->dev, "Failed to get irq\n"); | |
941 | return -EINVAL; | |
942 | } | |
943 | ||
944 | ret = ipc_plat_get_res(pdev); | |
945 | if (ret) { | |
946 | dev_err(&pdev->dev, "Failed to request resource\n"); | |
947 | return ret; | |
948 | } | |
949 | ||
950 | ret = ipc_create_pmc_devices(); | |
951 | if (ret) { | |
952 | dev_err(&pdev->dev, "Failed to create pmc devices\n"); | |
83beee5c | 953 | return ret; |
0a8b8353 | 954 | } |
955 | ||
83beee5c KS |
956 | if (devm_request_irq(&pdev->dev, ipcdev.irq, ioc, IRQF_NO_SUSPEND, |
957 | "intel_pmc_ipc", &ipcdev)) { | |
0a8b8353 | 958 | dev_err(&pdev->dev, "Failed to request irq\n"); |
959 | ret = -EBUSY; | |
960 | goto err_irq; | |
961 | } | |
962 | ||
963 | ret = sysfs_create_group(&pdev->dev.kobj, &intel_ipc_group); | |
964 | if (ret) { | |
965 | dev_err(&pdev->dev, "Failed to create sysfs group %d\n", | |
966 | ret); | |
967 | goto err_sys; | |
968 | } | |
969 | ||
76062b4a SM |
970 | ipcdev.has_gcr_regs = true; |
971 | ||
0a8b8353 | 972 | return 0; |
973 | err_sys: | |
83beee5c | 974 | devm_free_irq(&pdev->dev, ipcdev.irq, &ipcdev); |
0a8b8353 | 975 | err_irq: |
976 | platform_device_unregister(ipcdev.tco_dev); | |
977 | platform_device_unregister(ipcdev.punit_dev); | |
48c19170 | 978 | platform_device_unregister(ipcdev.telemetry_dev); |
83beee5c | 979 | |
0a8b8353 | 980 | return ret; |
981 | } | |
982 | ||
983 | static int ipc_plat_remove(struct platform_device *pdev) | |
984 | { | |
0a8b8353 | 985 | sysfs_remove_group(&pdev->dev.kobj, &intel_ipc_group); |
83beee5c | 986 | devm_free_irq(&pdev->dev, ipcdev.irq, &ipcdev); |
0a8b8353 | 987 | platform_device_unregister(ipcdev.tco_dev); |
988 | platform_device_unregister(ipcdev.punit_dev); | |
48c19170 | 989 | platform_device_unregister(ipcdev.telemetry_dev); |
0a8b8353 | 990 | ipcdev.dev = NULL; |
991 | return 0; | |
992 | } | |
993 | ||
994 | static struct platform_driver ipc_plat_driver = { | |
995 | .remove = ipc_plat_remove, | |
996 | .probe = ipc_plat_probe, | |
997 | .driver = { | |
998 | .name = "pmc-ipc-plat", | |
999 | .acpi_match_table = ACPI_PTR(ipc_acpi_ids), | |
1000 | }, | |
1001 | }; | |
1002 | ||
1003 | static int __init intel_pmc_ipc_init(void) | |
1004 | { | |
1005 | int ret; | |
1006 | ||
1007 | ret = platform_driver_register(&ipc_plat_driver); | |
1008 | if (ret) { | |
1009 | pr_err("Failed to register PMC ipc platform driver\n"); | |
1010 | return ret; | |
1011 | } | |
1012 | ret = pci_register_driver(&ipc_pci_driver); | |
1013 | if (ret) { | |
1014 | pr_err("Failed to register PMC ipc pci driver\n"); | |
1015 | platform_driver_unregister(&ipc_plat_driver); | |
1016 | return ret; | |
1017 | } | |
1018 | return ret; | |
1019 | } | |
1020 | ||
1021 | static void __exit intel_pmc_ipc_exit(void) | |
1022 | { | |
1023 | pci_unregister_driver(&ipc_pci_driver); | |
1024 | platform_driver_unregister(&ipc_plat_driver); | |
1025 | } | |
1026 | ||
1027 | MODULE_AUTHOR("Zha Qipeng <qipeng.zha@intel.com>"); | |
1028 | MODULE_DESCRIPTION("Intel PMC IPC driver"); | |
ad51f287 | 1029 | MODULE_LICENSE("GPL v2"); |
0a8b8353 | 1030 | |
1031 | /* Some modules are dependent on this, so init earlier */ | |
1032 | fs_initcall(intel_pmc_ipc_init); | |
1033 | module_exit(intel_pmc_ipc_exit); |