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9a58a333 SD |
1 | /* |
2 | * intel_scu_ipc.c: Driver for the Intel SCU IPC mechanism | |
3 | * | |
4 | * (C) Copyright 2008-2010 Intel Corporation | |
5 | * Author: Sreedhara DS (sreedhara.ds@intel.com) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | * | |
c8440336 | 12 | * SCU running in ARC processor communicates with other entity running in IA |
9a58a333 SD |
13 | * core through IPC mechanism which in turn messaging between IA core ad SCU. |
14 | * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and | |
15 | * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with | |
16 | * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC) | |
17 | * along with other APIs. | |
18 | */ | |
19 | #include <linux/delay.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/init.h> | |
edbaa603 | 22 | #include <linux/device.h> |
9a58a333 SD |
23 | #include <linux/pm.h> |
24 | #include <linux/pci.h> | |
25 | #include <linux/interrupt.h> | |
209009b2 | 26 | #include <linux/sfi.h> |
7c52d551 | 27 | #include <linux/module.h> |
14d10f0a | 28 | #include <asm/mrst.h> |
9a58a333 SD |
29 | #include <asm/intel_scu_ipc.h> |
30 | ||
31 | /* IPC defines the following message types */ | |
32 | #define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */ | |
33 | #define IPCMSG_BATTERY 0xEF /* Coulomb Counter Accumulator */ | |
34 | #define IPCMSG_FW_UPDATE 0xFE /* Firmware update */ | |
35 | #define IPCMSG_PCNTRL 0xFF /* Power controller unit read/write */ | |
36 | #define IPCMSG_FW_REVISION 0xF4 /* Get firmware revision */ | |
37 | ||
38 | /* Command id associated with message IPCMSG_PCNTRL */ | |
39 | #define IPC_CMD_PCNTRL_W 0 /* Register write */ | |
40 | #define IPC_CMD_PCNTRL_R 1 /* Register read */ | |
41 | #define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */ | |
42 | ||
9a58a333 SD |
43 | /* |
44 | * IPC register summary | |
45 | * | |
46 | * IPC register blocks are memory mapped at fixed address of 0xFF11C000 | |
47 | * To read or write information to the SCU, driver writes to IPC-1 memory | |
48 | * mapped registers (base address 0xFF11C000). The following is the IPC | |
49 | * mechanism | |
50 | * | |
51 | * 1. IA core cDMI interface claims this transaction and converts it to a | |
52 | * Transaction Layer Packet (TLP) message which is sent across the cDMI. | |
53 | * | |
54 | * 2. South Complex cDMI block receives this message and writes it to | |
55 | * the IPC-1 register block, causing an interrupt to the SCU | |
56 | * | |
57 | * 3. SCU firmware decodes this interrupt and IPC message and the appropriate | |
58 | * message handler is called within firmware. | |
59 | */ | |
60 | ||
61 | #define IPC_BASE_ADDR 0xFF11C000 /* IPC1 base register address */ | |
62 | #define IPC_MAX_ADDR 0x100 /* Maximum IPC regisers */ | |
51cd525d AV |
63 | #define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */ |
64 | #define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */ | |
9a58a333 SD |
65 | #define IPC_I2C_BASE 0xFF12B000 /* I2C control register base address */ |
66 | #define IPC_I2C_MAX_ADDR 0x10 /* Maximum I2C regisers */ | |
67 | ||
68 | static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id); | |
69 | static void ipc_remove(struct pci_dev *pdev); | |
70 | ||
71 | struct intel_scu_ipc_dev { | |
72 | struct pci_dev *pdev; | |
73 | void __iomem *ipc_base; | |
74 | void __iomem *i2c_base; | |
75 | }; | |
76 | ||
77 | static struct intel_scu_ipc_dev ipcdev; /* Only one for now */ | |
78 | ||
14d10f0a | 79 | static int platform; /* Platform type */ |
9a58a333 SD |
80 | |
81 | /* | |
82 | * IPC Read Buffer (Read Only): | |
83 | * 16 byte buffer for receiving data from SCU, if IPC command | |
84 | * processing results in response data | |
85 | */ | |
86 | #define IPC_READ_BUFFER 0x90 | |
87 | ||
88 | #define IPC_I2C_CNTRL_ADDR 0 | |
89 | #define I2C_DATA_ADDR 0x04 | |
90 | ||
91 | static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */ | |
92 | ||
93 | /* | |
94 | * Command Register (Write Only): | |
95 | * A write to this register results in an interrupt to the SCU core processor | |
96 | * Format: | |
97 | * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)| | |
98 | */ | |
99 | static inline void ipc_command(u32 cmd) /* Send ipc command */ | |
100 | { | |
101 | writel(cmd, ipcdev.ipc_base); | |
102 | } | |
103 | ||
104 | /* | |
105 | * IPC Write Buffer (Write Only): | |
106 | * 16-byte buffer for sending data associated with IPC command to | |
107 | * SCU. Size of the data is specified in the IPC_COMMAND_REG register | |
108 | */ | |
109 | static inline void ipc_data_writel(u32 data, u32 offset) /* Write ipc data */ | |
110 | { | |
111 | writel(data, ipcdev.ipc_base + 0x80 + offset); | |
112 | } | |
113 | ||
9a58a333 SD |
114 | /* |
115 | * Status Register (Read Only): | |
116 | * Driver will read this register to get the ready/busy status of the IPC | |
117 | * block and error status of the IPC command that was just processed by SCU | |
118 | * Format: | |
119 | * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)| | |
120 | */ | |
121 | ||
122 | static inline u8 ipc_read_status(void) | |
123 | { | |
124 | return __raw_readl(ipcdev.ipc_base + 0x04); | |
125 | } | |
126 | ||
127 | static inline u8 ipc_data_readb(u32 offset) /* Read ipc byte data */ | |
128 | { | |
129 | return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset); | |
130 | } | |
131 | ||
e3359fd5 | 132 | static inline u32 ipc_data_readl(u32 offset) /* Read ipc u32 data */ |
9a58a333 SD |
133 | { |
134 | return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset); | |
135 | } | |
136 | ||
137 | static inline int busy_loop(void) /* Wait till scu status is busy */ | |
138 | { | |
139 | u32 status = 0; | |
140 | u32 loop_count = 0; | |
141 | ||
142 | status = ipc_read_status(); | |
143 | while (status & 1) { | |
144 | udelay(1); /* scu processing time is in few u secods */ | |
145 | status = ipc_read_status(); | |
146 | loop_count++; | |
147 | /* break if scu doesn't reset busy bit after huge retry */ | |
148 | if (loop_count > 100000) { | |
149 | dev_err(&ipcdev.pdev->dev, "IPC timed out"); | |
150 | return -ETIMEDOUT; | |
151 | } | |
152 | } | |
77e01d6d HL |
153 | if ((status >> 1) & 1) |
154 | return -EIO; | |
155 | ||
156 | return 0; | |
9a58a333 SD |
157 | } |
158 | ||
159 | /* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */ | |
160 | static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id) | |
161 | { | |
215c330f | 162 | int i, nc, bytes, d; |
9a58a333 | 163 | u32 offset = 0; |
ecb5646c | 164 | int err; |
e3359fd5 | 165 | u8 cbuf[IPC_WWBUF_SIZE] = { }; |
9a58a333 SD |
166 | u32 *wbuf = (u32 *)&cbuf; |
167 | ||
168 | mutex_lock(&ipclock); | |
e3359fd5 | 169 | |
ed6f2b4d AV |
170 | memset(cbuf, 0, sizeof(cbuf)); |
171 | ||
9a58a333 SD |
172 | if (ipcdev.pdev == NULL) { |
173 | mutex_unlock(&ipclock); | |
174 | return -ENODEV; | |
175 | } | |
176 | ||
9dd3adeb | 177 | if (platform != MRST_CPU_CHIP_PENWELL) { |
6c8d0fdb | 178 | bytes = 0; |
215c330f HL |
179 | d = 0; |
180 | for (i = 0; i < count; i++) { | |
6c8d0fdb AR |
181 | cbuf[bytes++] = addr[i]; |
182 | cbuf[bytes++] = addr[i] >> 8; | |
9a58a333 | 183 | if (id != IPC_CMD_PCNTRL_R) |
215c330f | 184 | cbuf[bytes++] = data[d++]; |
6c8d0fdb | 185 | if (id == IPC_CMD_PCNTRL_M) |
215c330f | 186 | cbuf[bytes++] = data[d++]; |
9a58a333 | 187 | } |
215c330f | 188 | for (i = 0; i < bytes; i += 4) |
6c8d0fdb AR |
189 | ipc_data_writel(wbuf[i/4], i); |
190 | ipc_command(bytes << 16 | id << 12 | 0 << 8 | op); | |
9a58a333 | 191 | } else { |
e3359fd5 SD |
192 | for (nc = 0; nc < count; nc++, offset += 2) { |
193 | cbuf[offset] = addr[nc]; | |
194 | cbuf[offset + 1] = addr[nc] >> 8; | |
9a58a333 | 195 | } |
9a58a333 | 196 | |
e3359fd5 SD |
197 | if (id == IPC_CMD_PCNTRL_R) { |
198 | for (nc = 0, offset = 0; nc < count; nc++, offset += 4) | |
199 | ipc_data_writel(wbuf[nc], offset); | |
200 | ipc_command((count*2) << 16 | id << 12 | 0 << 8 | op); | |
201 | } else if (id == IPC_CMD_PCNTRL_W) { | |
202 | for (nc = 0; nc < count; nc++, offset += 1) | |
203 | cbuf[offset] = data[nc]; | |
204 | for (nc = 0, offset = 0; nc < count; nc++, offset += 4) | |
205 | ipc_data_writel(wbuf[nc], offset); | |
206 | ipc_command((count*3) << 16 | id << 12 | 0 << 8 | op); | |
207 | } else if (id == IPC_CMD_PCNTRL_M) { | |
208 | cbuf[offset] = data[0]; | |
209 | cbuf[offset + 1] = data[1]; | |
210 | ipc_data_writel(wbuf[0], 0); /* Write wbuff */ | |
211 | ipc_command(4 << 16 | id << 12 | 0 << 8 | op); | |
212 | } | |
213 | } | |
9a58a333 SD |
214 | |
215 | err = busy_loop(); | |
9a58a333 SD |
216 | if (id == IPC_CMD_PCNTRL_R) { /* Read rbuf */ |
217 | /* Workaround: values are read as 0 without memcpy_fromio */ | |
e3359fd5 | 218 | memcpy_fromio(cbuf, ipcdev.ipc_base + 0x90, 16); |
9dd3adeb | 219 | if (platform != MRST_CPU_CHIP_PENWELL) { |
9a58a333 SD |
220 | for (nc = 0, offset = 2; nc < count; nc++, offset += 3) |
221 | data[nc] = ipc_data_readb(offset); | |
222 | } else { | |
223 | for (nc = 0; nc < count; nc++) | |
224 | data[nc] = ipc_data_readb(nc); | |
225 | } | |
226 | } | |
227 | mutex_unlock(&ipclock); | |
228 | return err; | |
229 | } | |
230 | ||
231 | /** | |
232 | * intel_scu_ipc_ioread8 - read a word via the SCU | |
233 | * @addr: register on SCU | |
234 | * @data: return pointer for read byte | |
235 | * | |
236 | * Read a single register. Returns 0 on success or an error code. All | |
237 | * locking between SCU accesses is handled for the caller. | |
238 | * | |
239 | * This function may sleep. | |
240 | */ | |
241 | int intel_scu_ipc_ioread8(u16 addr, u8 *data) | |
242 | { | |
243 | return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); | |
244 | } | |
245 | EXPORT_SYMBOL(intel_scu_ipc_ioread8); | |
246 | ||
247 | /** | |
248 | * intel_scu_ipc_ioread16 - read a word via the SCU | |
249 | * @addr: register on SCU | |
250 | * @data: return pointer for read word | |
251 | * | |
252 | * Read a register pair. Returns 0 on success or an error code. All | |
253 | * locking between SCU accesses is handled for the caller. | |
254 | * | |
255 | * This function may sleep. | |
256 | */ | |
257 | int intel_scu_ipc_ioread16(u16 addr, u16 *data) | |
258 | { | |
259 | u16 x[2] = {addr, addr + 1 }; | |
260 | return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); | |
261 | } | |
262 | EXPORT_SYMBOL(intel_scu_ipc_ioread16); | |
263 | ||
264 | /** | |
265 | * intel_scu_ipc_ioread32 - read a dword via the SCU | |
266 | * @addr: register on SCU | |
267 | * @data: return pointer for read dword | |
268 | * | |
269 | * Read four registers. Returns 0 on success or an error code. All | |
270 | * locking between SCU accesses is handled for the caller. | |
271 | * | |
272 | * This function may sleep. | |
273 | */ | |
274 | int intel_scu_ipc_ioread32(u16 addr, u32 *data) | |
275 | { | |
276 | u16 x[4] = {addr, addr + 1, addr + 2, addr + 3}; | |
277 | return pwr_reg_rdwr(x, (u8 *)data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); | |
278 | } | |
279 | EXPORT_SYMBOL(intel_scu_ipc_ioread32); | |
280 | ||
281 | /** | |
282 | * intel_scu_ipc_iowrite8 - write a byte via the SCU | |
283 | * @addr: register on SCU | |
284 | * @data: byte to write | |
285 | * | |
286 | * Write a single register. Returns 0 on success or an error code. All | |
287 | * locking between SCU accesses is handled for the caller. | |
288 | * | |
289 | * This function may sleep. | |
290 | */ | |
291 | int intel_scu_ipc_iowrite8(u16 addr, u8 data) | |
292 | { | |
293 | return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); | |
294 | } | |
295 | EXPORT_SYMBOL(intel_scu_ipc_iowrite8); | |
296 | ||
297 | /** | |
298 | * intel_scu_ipc_iowrite16 - write a word via the SCU | |
299 | * @addr: register on SCU | |
300 | * @data: word to write | |
301 | * | |
302 | * Write two registers. Returns 0 on success or an error code. All | |
303 | * locking between SCU accesses is handled for the caller. | |
304 | * | |
305 | * This function may sleep. | |
306 | */ | |
307 | int intel_scu_ipc_iowrite16(u16 addr, u16 data) | |
308 | { | |
309 | u16 x[2] = {addr, addr + 1 }; | |
310 | return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); | |
311 | } | |
312 | EXPORT_SYMBOL(intel_scu_ipc_iowrite16); | |
313 | ||
314 | /** | |
315 | * intel_scu_ipc_iowrite32 - write a dword via the SCU | |
316 | * @addr: register on SCU | |
317 | * @data: dword to write | |
318 | * | |
319 | * Write four registers. Returns 0 on success or an error code. All | |
320 | * locking between SCU accesses is handled for the caller. | |
321 | * | |
322 | * This function may sleep. | |
323 | */ | |
324 | int intel_scu_ipc_iowrite32(u16 addr, u32 data) | |
325 | { | |
326 | u16 x[4] = {addr, addr + 1, addr + 2, addr + 3}; | |
327 | return pwr_reg_rdwr(x, (u8 *)&data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); | |
328 | } | |
329 | EXPORT_SYMBOL(intel_scu_ipc_iowrite32); | |
330 | ||
331 | /** | |
332 | * intel_scu_ipc_readvv - read a set of registers | |
333 | * @addr: register list | |
334 | * @data: bytes to return | |
335 | * @len: length of array | |
336 | * | |
337 | * Read registers. Returns 0 on success or an error code. All | |
338 | * locking between SCU accesses is handled for the caller. | |
339 | * | |
340 | * The largest array length permitted by the hardware is 5 items. | |
341 | * | |
342 | * This function may sleep. | |
343 | */ | |
344 | int intel_scu_ipc_readv(u16 *addr, u8 *data, int len) | |
345 | { | |
346 | return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); | |
347 | } | |
348 | EXPORT_SYMBOL(intel_scu_ipc_readv); | |
349 | ||
350 | /** | |
351 | * intel_scu_ipc_writev - write a set of registers | |
352 | * @addr: register list | |
353 | * @data: bytes to write | |
354 | * @len: length of array | |
355 | * | |
356 | * Write registers. Returns 0 on success or an error code. All | |
357 | * locking between SCU accesses is handled for the caller. | |
358 | * | |
359 | * The largest array length permitted by the hardware is 5 items. | |
360 | * | |
361 | * This function may sleep. | |
362 | * | |
363 | */ | |
364 | int intel_scu_ipc_writev(u16 *addr, u8 *data, int len) | |
365 | { | |
366 | return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); | |
367 | } | |
368 | EXPORT_SYMBOL(intel_scu_ipc_writev); | |
369 | ||
370 | ||
371 | /** | |
372 | * intel_scu_ipc_update_register - r/m/w a register | |
373 | * @addr: register address | |
374 | * @bits: bits to update | |
375 | * @mask: mask of bits to update | |
376 | * | |
377 | * Read-modify-write power control unit register. The first data argument | |
378 | * must be register value and second is mask value | |
379 | * mask is a bitmap that indicates which bits to update. | |
380 | * 0 = masked. Don't modify this bit, 1 = modify this bit. | |
381 | * returns 0 on success or an error code. | |
382 | * | |
383 | * This function may sleep. Locking between SCU accesses is handled | |
384 | * for the caller. | |
385 | */ | |
386 | int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask) | |
387 | { | |
388 | u8 data[2] = { bits, mask }; | |
389 | return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M); | |
390 | } | |
391 | EXPORT_SYMBOL(intel_scu_ipc_update_register); | |
392 | ||
9a58a333 SD |
393 | /** |
394 | * intel_scu_ipc_simple_command - send a simple command | |
395 | * @cmd: command | |
396 | * @sub: sub type | |
397 | * | |
398 | * Issue a simple command to the SCU. Do not use this interface if | |
399 | * you must then access data as any data values may be overwritten | |
400 | * by another SCU access by the time this function returns. | |
401 | * | |
402 | * This function may sleep. Locking for SCU accesses is handled for | |
403 | * the caller. | |
404 | */ | |
405 | int intel_scu_ipc_simple_command(int cmd, int sub) | |
406 | { | |
ecb5646c | 407 | int err; |
9a58a333 SD |
408 | |
409 | mutex_lock(&ipclock); | |
410 | if (ipcdev.pdev == NULL) { | |
411 | mutex_unlock(&ipclock); | |
412 | return -ENODEV; | |
413 | } | |
b4fd4f89 | 414 | ipc_command(sub << 12 | cmd); |
9a58a333 SD |
415 | err = busy_loop(); |
416 | mutex_unlock(&ipclock); | |
417 | return err; | |
418 | } | |
419 | EXPORT_SYMBOL(intel_scu_ipc_simple_command); | |
420 | ||
421 | /** | |
422 | * intel_scu_ipc_command - command with data | |
423 | * @cmd: command | |
424 | * @sub: sub type | |
425 | * @in: input data | |
b4fd4f89 | 426 | * @inlen: input length in dwords |
9a58a333 | 427 | * @out: output data |
b4fd4f89 | 428 | * @outlein: output length in dwords |
9a58a333 SD |
429 | * |
430 | * Issue a command to the SCU which involves data transfers. Do the | |
431 | * data copies under the lock but leave it for the caller to interpret | |
432 | */ | |
433 | ||
434 | int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen, | |
435 | u32 *out, int outlen) | |
436 | { | |
ecb5646c | 437 | int i, err; |
9a58a333 SD |
438 | |
439 | mutex_lock(&ipclock); | |
440 | if (ipcdev.pdev == NULL) { | |
441 | mutex_unlock(&ipclock); | |
442 | return -ENODEV; | |
443 | } | |
444 | ||
445 | for (i = 0; i < inlen; i++) | |
446 | ipc_data_writel(*in++, 4 * i); | |
447 | ||
5aa06930 | 448 | ipc_command((inlen << 16) | (sub << 12) | cmd); |
9a58a333 SD |
449 | err = busy_loop(); |
450 | ||
451 | for (i = 0; i < outlen; i++) | |
452 | *out++ = ipc_data_readl(4 * i); | |
453 | ||
454 | mutex_unlock(&ipclock); | |
455 | return err; | |
456 | } | |
457 | EXPORT_SYMBOL(intel_scu_ipc_command); | |
458 | ||
459 | /*I2C commands */ | |
460 | #define IPC_I2C_WRITE 1 /* I2C Write command */ | |
461 | #define IPC_I2C_READ 2 /* I2C Read command */ | |
462 | ||
463 | /** | |
464 | * intel_scu_ipc_i2c_cntrl - I2C read/write operations | |
465 | * @addr: I2C address + command bits | |
466 | * @data: data to read/write | |
467 | * | |
468 | * Perform an an I2C read/write operation via the SCU. All locking is | |
469 | * handled for the caller. This function may sleep. | |
470 | * | |
471 | * Returns an error code or 0 on success. | |
472 | * | |
473 | * This has to be in the IPC driver for the locking. | |
474 | */ | |
475 | int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data) | |
476 | { | |
477 | u32 cmd = 0; | |
478 | ||
479 | mutex_lock(&ipclock); | |
b4fd4f89 SD |
480 | if (ipcdev.pdev == NULL) { |
481 | mutex_unlock(&ipclock); | |
482 | return -ENODEV; | |
483 | } | |
9a58a333 SD |
484 | cmd = (addr >> 24) & 0xFF; |
485 | if (cmd == IPC_I2C_READ) { | |
486 | writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR); | |
487 | /* Write not getting updated without delay */ | |
488 | mdelay(1); | |
489 | *data = readl(ipcdev.i2c_base + I2C_DATA_ADDR); | |
490 | } else if (cmd == IPC_I2C_WRITE) { | |
32e2f63b | 491 | writel(*data, ipcdev.i2c_base + I2C_DATA_ADDR); |
9a58a333 SD |
492 | mdelay(1); |
493 | writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR); | |
494 | } else { | |
495 | dev_err(&ipcdev.pdev->dev, | |
496 | "intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd); | |
497 | ||
498 | mutex_unlock(&ipclock); | |
5369c02d | 499 | return -EIO; |
9a58a333 SD |
500 | } |
501 | mutex_unlock(&ipclock); | |
502 | return 0; | |
503 | } | |
504 | EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl); | |
505 | ||
506 | #define IPC_FW_LOAD_ADDR 0xFFFC0000 /* Storage location for FW image */ | |
507 | #define IPC_FW_UPDATE_MBOX_ADDR 0xFFFFDFF4 /* Mailbox between ipc and scu */ | |
508 | #define IPC_MAX_FW_SIZE 262144 /* 256K storage size for loading the FW image */ | |
509 | #define IPC_FW_MIP_HEADER_SIZE 2048 /* Firmware MIP header size */ | |
510 | /* IPC inform SCU to get ready for update process */ | |
511 | #define IPC_CMD_FW_UPDATE_READY 0x10FE | |
512 | /* IPC inform SCU to go for update process */ | |
513 | #define IPC_CMD_FW_UPDATE_GO 0x20FE | |
514 | /* Status code for fw update */ | |
515 | #define IPC_FW_UPDATE_SUCCESS 0x444f4e45 /* Status code 'DONE' */ | |
516 | #define IPC_FW_UPDATE_BADN 0x4241444E /* Status code 'BADN' */ | |
517 | #define IPC_FW_TXHIGH 0x54784849 /* Status code 'IPC_FW_TXHIGH' */ | |
518 | #define IPC_FW_TXLOW 0x54784c4f /* Status code 'IPC_FW_TXLOW' */ | |
519 | ||
520 | struct fw_update_mailbox { | |
521 | u32 status; | |
522 | u32 scu_flag; | |
523 | u32 driver_flag; | |
524 | }; | |
525 | ||
526 | ||
527 | /** | |
528 | * intel_scu_ipc_fw_update - Firmware update utility | |
529 | * @buffer: firmware buffer | |
530 | * @length: size of firmware buffer | |
531 | * | |
532 | * This function provides an interface to load the firmware into | |
533 | * the SCU. Returns 0 on success or -1 on failure | |
534 | */ | |
535 | int intel_scu_ipc_fw_update(u8 *buffer, u32 length) | |
536 | { | |
537 | void __iomem *fw_update_base; | |
538 | struct fw_update_mailbox __iomem *mailbox = NULL; | |
539 | int retry_cnt = 0; | |
540 | u32 status; | |
541 | ||
542 | mutex_lock(&ipclock); | |
543 | fw_update_base = ioremap_nocache(IPC_FW_LOAD_ADDR, (128*1024)); | |
544 | if (fw_update_base == NULL) { | |
545 | mutex_unlock(&ipclock); | |
546 | return -ENOMEM; | |
547 | } | |
548 | mailbox = ioremap_nocache(IPC_FW_UPDATE_MBOX_ADDR, | |
549 | sizeof(struct fw_update_mailbox)); | |
550 | if (mailbox == NULL) { | |
551 | iounmap(fw_update_base); | |
552 | mutex_unlock(&ipclock); | |
553 | return -ENOMEM; | |
554 | } | |
555 | ||
556 | ipc_command(IPC_CMD_FW_UPDATE_READY); | |
557 | ||
558 | /* Intitialize mailbox */ | |
559 | writel(0, &mailbox->status); | |
560 | writel(0, &mailbox->scu_flag); | |
561 | writel(0, &mailbox->driver_flag); | |
562 | ||
563 | /* Driver copies the 2KB MIP header to SRAM at 0xFFFC0000*/ | |
564 | memcpy_toio(fw_update_base, buffer, 0x800); | |
565 | ||
566 | /* Driver sends "FW Update" IPC command (CMD_ID 0xFE; MSG_ID 0x02). | |
567 | * Upon receiving this command, SCU will write the 2K MIP header | |
568 | * from 0xFFFC0000 into NAND. | |
569 | * SCU will write a status code into the Mailbox, and then set scu_flag. | |
570 | */ | |
571 | ||
572 | ipc_command(IPC_CMD_FW_UPDATE_GO); | |
573 | ||
574 | /*Driver stalls until scu_flag is set */ | |
575 | while (readl(&mailbox->scu_flag) != 1) { | |
576 | rmb(); | |
577 | mdelay(1); | |
578 | } | |
579 | ||
580 | /* Driver checks Mailbox status. | |
581 | * If the status is 'BADN', then abort (bad NAND). | |
582 | * If the status is 'IPC_FW_TXLOW', then continue. | |
583 | */ | |
584 | while (readl(&mailbox->status) != IPC_FW_TXLOW) { | |
585 | rmb(); | |
586 | mdelay(10); | |
587 | } | |
588 | mdelay(10); | |
589 | ||
590 | update_retry: | |
591 | if (retry_cnt > 5) | |
592 | goto update_end; | |
593 | ||
594 | if (readl(&mailbox->status) != IPC_FW_TXLOW) | |
595 | goto update_end; | |
596 | buffer = buffer + 0x800; | |
597 | memcpy_toio(fw_update_base, buffer, 0x20000); | |
598 | writel(1, &mailbox->driver_flag); | |
599 | while (readl(&mailbox->scu_flag) == 1) { | |
600 | rmb(); | |
601 | mdelay(1); | |
602 | } | |
603 | ||
604 | /* check for 'BADN' */ | |
605 | if (readl(&mailbox->status) == IPC_FW_UPDATE_BADN) | |
606 | goto update_end; | |
607 | ||
608 | while (readl(&mailbox->status) != IPC_FW_TXHIGH) { | |
609 | rmb(); | |
610 | mdelay(10); | |
611 | } | |
612 | mdelay(10); | |
613 | ||
614 | if (readl(&mailbox->status) != IPC_FW_TXHIGH) | |
615 | goto update_end; | |
616 | ||
617 | buffer = buffer + 0x20000; | |
618 | memcpy_toio(fw_update_base, buffer, 0x20000); | |
619 | writel(0, &mailbox->driver_flag); | |
620 | ||
621 | while (mailbox->scu_flag == 0) { | |
622 | rmb(); | |
623 | mdelay(1); | |
624 | } | |
625 | ||
626 | /* check for 'BADN' */ | |
627 | if (readl(&mailbox->status) == IPC_FW_UPDATE_BADN) | |
628 | goto update_end; | |
629 | ||
630 | if (readl(&mailbox->status) == IPC_FW_TXLOW) { | |
631 | ++retry_cnt; | |
632 | goto update_retry; | |
633 | } | |
634 | ||
635 | update_end: | |
636 | status = readl(&mailbox->status); | |
637 | ||
638 | iounmap(fw_update_base); | |
639 | iounmap(mailbox); | |
640 | mutex_unlock(&ipclock); | |
641 | ||
642 | if (status == IPC_FW_UPDATE_SUCCESS) | |
643 | return 0; | |
5369c02d | 644 | return -EIO; |
9a58a333 SD |
645 | } |
646 | EXPORT_SYMBOL(intel_scu_ipc_fw_update); | |
647 | ||
648 | /* | |
649 | * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1 | |
650 | * When ioc bit is set to 1, caller api must wait for interrupt handler called | |
651 | * which in turn unlocks the caller api. Currently this is not used | |
652 | * | |
653 | * This is edge triggered so we need take no action to clear anything | |
654 | */ | |
655 | static irqreturn_t ioc(int irq, void *dev_id) | |
656 | { | |
657 | return IRQ_HANDLED; | |
658 | } | |
659 | ||
660 | /** | |
661 | * ipc_probe - probe an Intel SCU IPC | |
662 | * @dev: the PCI device matching | |
663 | * @id: entry in the match table | |
664 | * | |
665 | * Enable and install an intel SCU IPC. This appears in the PCI space | |
666 | * but uses some hard coded addresses as well. | |
667 | */ | |
668 | static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
669 | { | |
670 | int err; | |
671 | resource_size_t pci_resource; | |
672 | ||
673 | if (ipcdev.pdev) /* We support only one SCU */ | |
674 | return -EBUSY; | |
675 | ||
676 | ipcdev.pdev = pci_dev_get(dev); | |
677 | ||
678 | err = pci_enable_device(dev); | |
679 | if (err) | |
680 | return err; | |
681 | ||
682 | err = pci_request_regions(dev, "intel_scu_ipc"); | |
683 | if (err) | |
684 | return err; | |
685 | ||
686 | pci_resource = pci_resource_start(dev, 0); | |
687 | if (!pci_resource) | |
688 | return -ENOMEM; | |
689 | ||
690 | if (request_irq(dev->irq, ioc, 0, "intel_scu_ipc", &ipcdev)) | |
691 | return -EBUSY; | |
692 | ||
693 | ipcdev.ipc_base = ioremap_nocache(IPC_BASE_ADDR, IPC_MAX_ADDR); | |
694 | if (!ipcdev.ipc_base) | |
695 | return -ENOMEM; | |
696 | ||
697 | ipcdev.i2c_base = ioremap_nocache(IPC_I2C_BASE, IPC_I2C_MAX_ADDR); | |
698 | if (!ipcdev.i2c_base) { | |
699 | iounmap(ipcdev.ipc_base); | |
700 | return -ENOMEM; | |
701 | } | |
1da4b1c6 FT |
702 | |
703 | intel_scu_devices_create(); | |
704 | ||
9a58a333 SD |
705 | return 0; |
706 | } | |
707 | ||
708 | /** | |
709 | * ipc_remove - remove a bound IPC device | |
710 | * @pdev: PCI device | |
711 | * | |
712 | * In practice the SCU is not removable but this function is also | |
713 | * called for each device on a module unload or cleanup which is the | |
714 | * path that will get used. | |
715 | * | |
716 | * Free up the mappings and release the PCI resources | |
717 | */ | |
718 | static void ipc_remove(struct pci_dev *pdev) | |
719 | { | |
720 | free_irq(pdev->irq, &ipcdev); | |
721 | pci_release_regions(pdev); | |
722 | pci_dev_put(ipcdev.pdev); | |
723 | iounmap(ipcdev.ipc_base); | |
724 | iounmap(ipcdev.i2c_base); | |
725 | ipcdev.pdev = NULL; | |
1da4b1c6 | 726 | intel_scu_devices_destroy(); |
9a58a333 SD |
727 | } |
728 | ||
daa77696 | 729 | static DEFINE_PCI_DEVICE_TABLE(pci_ids) = { |
9a58a333 | 730 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080e)}, |
e3359fd5 | 731 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x082a)}, |
9a58a333 SD |
732 | { 0,} |
733 | }; | |
734 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
735 | ||
736 | static struct pci_driver ipc_driver = { | |
737 | .name = "intel_scu_ipc", | |
738 | .id_table = pci_ids, | |
739 | .probe = ipc_probe, | |
740 | .remove = ipc_remove, | |
741 | }; | |
742 | ||
743 | ||
744 | static int __init intel_scu_ipc_init(void) | |
745 | { | |
9dd3adeb AC |
746 | platform = mrst_identify_cpu(); |
747 | if (platform == 0) | |
748 | return -ENODEV; | |
9a58a333 SD |
749 | return pci_register_driver(&ipc_driver); |
750 | } | |
751 | ||
752 | static void __exit intel_scu_ipc_exit(void) | |
753 | { | |
754 | pci_unregister_driver(&ipc_driver); | |
755 | } | |
756 | ||
757 | MODULE_AUTHOR("Sreedhara DS <sreedhara.ds@intel.com>"); | |
758 | MODULE_DESCRIPTION("Intel SCU IPC driver"); | |
759 | MODULE_LICENSE("GPL"); | |
760 | ||
761 | module_init(intel_scu_ipc_init); | |
762 | module_exit(intel_scu_ipc_exit); |