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Commit | Line | Data |
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f6cc69f1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
2d281d81 JP |
2 | /* |
3 | * Intel Running Average Power Limit (RAPL) Driver | |
4 | * Copyright (c) 2013, Intel Corporation. | |
2d281d81 JP |
5 | */ |
6 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
7 | ||
8 | #include <linux/kernel.h> | |
9 | #include <linux/module.h> | |
10 | #include <linux/list.h> | |
11 | #include <linux/types.h> | |
12 | #include <linux/device.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/log2.h> | |
15 | #include <linux/bitmap.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/sysfs.h> | |
18 | #include <linux/cpu.h> | |
19 | #include <linux/powercap.h> | |
52b3672c | 20 | #include <linux/suspend.h> |
ff956826 | 21 | #include <linux/intel_rapl.h> |
2d281d81 | 22 | |
ff956826 | 23 | #include <asm/iosf_mbi.h> |
2d281d81 JP |
24 | #include <asm/processor.h> |
25 | #include <asm/cpu_device_id.h> | |
62d16733 | 26 | #include <asm/intel-family.h> |
2d281d81 | 27 | |
3521ba1c SP |
28 | /* Local defines */ |
29 | #define MSR_PLATFORM_POWER_LIMIT 0x0000065C | |
30 | ||
2d281d81 JP |
31 | /* bitmasks for RAPL MSRs, used by primitive access functions */ |
32 | #define ENERGY_STATUS_MASK 0xffffffff | |
33 | ||
34 | #define POWER_LIMIT1_MASK 0x7FFF | |
35 | #define POWER_LIMIT1_ENABLE BIT(15) | |
36 | #define POWER_LIMIT1_CLAMP BIT(16) | |
37 | ||
38 | #define POWER_LIMIT2_MASK (0x7FFFULL<<32) | |
39 | #define POWER_LIMIT2_ENABLE BIT_ULL(47) | |
40 | #define POWER_LIMIT2_CLAMP BIT_ULL(48) | |
41 | #define POWER_PACKAGE_LOCK BIT_ULL(63) | |
42 | #define POWER_PP_LOCK BIT(31) | |
43 | ||
44 | #define TIME_WINDOW1_MASK (0x7FULL<<17) | |
45 | #define TIME_WINDOW2_MASK (0x7FULL<<49) | |
46 | ||
47 | #define POWER_UNIT_OFFSET 0 | |
48 | #define POWER_UNIT_MASK 0x0F | |
49 | ||
50 | #define ENERGY_UNIT_OFFSET 0x08 | |
51 | #define ENERGY_UNIT_MASK 0x1F00 | |
52 | ||
53 | #define TIME_UNIT_OFFSET 0x10 | |
54 | #define TIME_UNIT_MASK 0xF0000 | |
55 | ||
56 | #define POWER_INFO_MAX_MASK (0x7fffULL<<32) | |
57 | #define POWER_INFO_MIN_MASK (0x7fffULL<<16) | |
58 | #define POWER_INFO_MAX_TIME_WIN_MASK (0x3fULL<<48) | |
59 | #define POWER_INFO_THERMAL_SPEC_MASK 0x7fff | |
60 | ||
61 | #define PERF_STATUS_THROTTLE_TIME_MASK 0xffffffff | |
62 | #define PP_POLICY_MASK 0x1F | |
63 | ||
64 | /* Non HW constants */ | |
65 | #define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */ | |
66 | #define RAPL_PRIMITIVE_DUMMY BIT(2) | |
67 | ||
2d281d81 JP |
68 | #define TIME_WINDOW_MAX_MSEC 40000 |
69 | #define TIME_WINDOW_MIN_MSEC 250 | |
d474a4d3 | 70 | #define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit */ |
2d281d81 JP |
71 | enum unit_type { |
72 | ARBITRARY_UNIT, /* no translation */ | |
73 | POWER_UNIT, | |
74 | ENERGY_UNIT, | |
75 | TIME_UNIT, | |
76 | }; | |
77 | ||
7ebf8eff ZR |
78 | /* private data for RAPL MSR Interface */ |
79 | static struct rapl_if_priv rapl_msr_priv; | |
80 | ||
2d281d81 | 81 | /* per domain data, some are optional */ |
2d281d81 JP |
82 | #define NR_RAW_PRIMITIVES (NR_RAPL_PRIMITIVES - 2) |
83 | ||
f14a1396 JP |
84 | struct msrl_action { |
85 | u32 msr_no; | |
86 | u64 clear_mask; | |
87 | u64 set_mask; | |
88 | int err; | |
89 | }; | |
2d281d81 JP |
90 | |
91 | #define DOMAIN_STATE_INACTIVE BIT(0) | |
92 | #define DOMAIN_STATE_POWER_LIMIT_SET BIT(1) | |
93 | #define DOMAIN_STATE_BIOS_LOCKED BIT(2) | |
94 | ||
2d281d81 JP |
95 | static const char pl1_name[] = "long_term"; |
96 | static const char pl2_name[] = "short_term"; | |
97 | ||
2d281d81 JP |
98 | #define power_zone_to_rapl_domain(_zone) \ |
99 | container_of(_zone, struct rapl_domain, power_zone) | |
100 | ||
087e9cba | 101 | struct rapl_defaults { |
51b63409 | 102 | u8 floor_freq_reg_addr; |
087e9cba JP |
103 | int (*check_unit)(struct rapl_package *rp, int cpu); |
104 | void (*set_floor_freq)(struct rapl_domain *rd, bool mode); | |
105 | u64 (*compute_time_window)(struct rapl_package *rp, u64 val, | |
106 | bool to_raw); | |
d474a4d3 | 107 | unsigned int dram_domain_energy_unit; |
087e9cba JP |
108 | }; |
109 | static struct rapl_defaults *rapl_defaults; | |
110 | ||
3c2c0845 | 111 | /* Sideband MBI registers */ |
51b63409 AT |
112 | #define IOSF_CPU_POWER_BUDGET_CTL_BYT (0x2) |
113 | #define IOSF_CPU_POWER_BUDGET_CTL_TNG (0xdf) | |
3c2c0845 | 114 | |
2d281d81 JP |
115 | #define PACKAGE_PLN_INT_SAVED BIT(0) |
116 | #define MAX_PRIM_NAME (32) | |
117 | ||
118 | /* per domain data. used to describe individual knobs such that access function | |
119 | * can be consolidated into one instead of many inline functions. | |
120 | */ | |
121 | struct rapl_primitive_info { | |
122 | const char *name; | |
123 | u64 mask; | |
124 | int shift; | |
f7c4e0c8 | 125 | enum rapl_domain_reg_id id; |
2d281d81 JP |
126 | enum unit_type unit; |
127 | u32 flag; | |
128 | }; | |
129 | ||
130 | #define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \ | |
131 | .name = #p, \ | |
132 | .mask = m, \ | |
133 | .shift = s, \ | |
134 | .id = i, \ | |
135 | .unit = u, \ | |
136 | .flag = f \ | |
137 | } | |
138 | ||
139 | static void rapl_init_domains(struct rapl_package *rp); | |
140 | static int rapl_read_data_raw(struct rapl_domain *rd, | |
141 | enum rapl_primitives prim, | |
142 | bool xlate, u64 *data); | |
143 | static int rapl_write_data_raw(struct rapl_domain *rd, | |
144 | enum rapl_primitives prim, | |
145 | unsigned long long value); | |
309557f5 | 146 | static u64 rapl_unit_xlate(struct rapl_domain *rd, |
d474a4d3 | 147 | enum unit_type type, u64 value, |
2d281d81 | 148 | int to_raw); |
309557f5 | 149 | static void package_power_limit_irq_save(struct rapl_package *rp); |
2d281d81 JP |
150 | |
151 | static LIST_HEAD(rapl_packages); /* guarded by CPU hotplug lock */ | |
152 | ||
153 | static const char * const rapl_domain_names[] = { | |
154 | "package", | |
155 | "core", | |
156 | "uncore", | |
157 | "dram", | |
3521ba1c | 158 | "psys", |
2d281d81 JP |
159 | }; |
160 | ||
2d281d81 | 161 | /* caller to ensure CPU hotplug lock is held */ |
7ebf8eff | 162 | static struct rapl_package *rapl_find_package_domain(int cpu, struct rapl_if_priv *priv) |
2d281d81 | 163 | { |
32fb480e | 164 | int id = topology_logical_die_id(cpu); |
2d281d81 JP |
165 | struct rapl_package *rp; |
166 | ||
167 | list_for_each_entry(rp, &rapl_packages, plist) { | |
7ebf8eff | 168 | if (rp->id == id && rp->priv->control_type == priv->control_type) |
2d281d81 JP |
169 | return rp; |
170 | } | |
171 | ||
172 | return NULL; | |
173 | } | |
174 | ||
2d281d81 JP |
175 | static int get_energy_counter(struct powercap_zone *power_zone, u64 *energy_raw) |
176 | { | |
177 | struct rapl_domain *rd; | |
178 | u64 energy_now; | |
179 | ||
180 | /* prevent CPU hotplug, make sure the RAPL domain does not go | |
181 | * away while reading the counter. | |
182 | */ | |
183 | get_online_cpus(); | |
184 | rd = power_zone_to_rapl_domain(power_zone); | |
185 | ||
186 | if (!rapl_read_data_raw(rd, ENERGY_COUNTER, true, &energy_now)) { | |
187 | *energy_raw = energy_now; | |
188 | put_online_cpus(); | |
189 | ||
190 | return 0; | |
191 | } | |
192 | put_online_cpus(); | |
193 | ||
194 | return -EIO; | |
195 | } | |
196 | ||
197 | static int get_max_energy_counter(struct powercap_zone *pcd_dev, u64 *energy) | |
198 | { | |
d474a4d3 JP |
199 | struct rapl_domain *rd = power_zone_to_rapl_domain(pcd_dev); |
200 | ||
309557f5 | 201 | *energy = rapl_unit_xlate(rd, ENERGY_UNIT, ENERGY_STATUS_MASK, 0); |
2d281d81 JP |
202 | return 0; |
203 | } | |
204 | ||
205 | static int release_zone(struct powercap_zone *power_zone) | |
206 | { | |
207 | struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone); | |
309557f5 | 208 | struct rapl_package *rp = rd->rp; |
2d281d81 JP |
209 | |
210 | /* package zone is the last zone of a package, we can free | |
211 | * memory here since all children has been unregistered. | |
212 | */ | |
213 | if (rd->id == RAPL_DOMAIN_PACKAGE) { | |
2d281d81 JP |
214 | kfree(rd); |
215 | rp->domains = NULL; | |
216 | } | |
217 | ||
218 | return 0; | |
219 | ||
220 | } | |
221 | ||
222 | static int find_nr_power_limit(struct rapl_domain *rd) | |
223 | { | |
e1399ba2 | 224 | int i, nr_pl = 0; |
2d281d81 JP |
225 | |
226 | for (i = 0; i < NR_POWER_LIMITS; i++) { | |
e1399ba2 JP |
227 | if (rd->rpl[i].name) |
228 | nr_pl++; | |
2d281d81 JP |
229 | } |
230 | ||
e1399ba2 | 231 | return nr_pl; |
2d281d81 JP |
232 | } |
233 | ||
234 | static int set_domain_enable(struct powercap_zone *power_zone, bool mode) | |
235 | { | |
236 | struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone); | |
2d281d81 JP |
237 | |
238 | if (rd->state & DOMAIN_STATE_BIOS_LOCKED) | |
239 | return -EACCES; | |
3c2c0845 | 240 | |
2d281d81 | 241 | get_online_cpus(); |
2d281d81 | 242 | rapl_write_data_raw(rd, PL1_ENABLE, mode); |
51b63409 AT |
243 | if (rapl_defaults->set_floor_freq) |
244 | rapl_defaults->set_floor_freq(rd, mode); | |
2d281d81 JP |
245 | put_online_cpus(); |
246 | ||
247 | return 0; | |
248 | } | |
249 | ||
250 | static int get_domain_enable(struct powercap_zone *power_zone, bool *mode) | |
251 | { | |
252 | struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone); | |
253 | u64 val; | |
254 | ||
255 | if (rd->state & DOMAIN_STATE_BIOS_LOCKED) { | |
256 | *mode = false; | |
257 | return 0; | |
258 | } | |
259 | get_online_cpus(); | |
260 | if (rapl_read_data_raw(rd, PL1_ENABLE, true, &val)) { | |
261 | put_online_cpus(); | |
262 | return -EIO; | |
263 | } | |
264 | *mode = val; | |
265 | put_online_cpus(); | |
266 | ||
267 | return 0; | |
268 | } | |
269 | ||
270 | /* per RAPL domain ops, in the order of rapl_domain_type */ | |
600c395b | 271 | static const struct powercap_zone_ops zone_ops[] = { |
2d281d81 JP |
272 | /* RAPL_DOMAIN_PACKAGE */ |
273 | { | |
274 | .get_energy_uj = get_energy_counter, | |
275 | .get_max_energy_range_uj = get_max_energy_counter, | |
276 | .release = release_zone, | |
277 | .set_enable = set_domain_enable, | |
278 | .get_enable = get_domain_enable, | |
279 | }, | |
280 | /* RAPL_DOMAIN_PP0 */ | |
281 | { | |
282 | .get_energy_uj = get_energy_counter, | |
283 | .get_max_energy_range_uj = get_max_energy_counter, | |
284 | .release = release_zone, | |
285 | .set_enable = set_domain_enable, | |
286 | .get_enable = get_domain_enable, | |
287 | }, | |
288 | /* RAPL_DOMAIN_PP1 */ | |
289 | { | |
290 | .get_energy_uj = get_energy_counter, | |
291 | .get_max_energy_range_uj = get_max_energy_counter, | |
292 | .release = release_zone, | |
293 | .set_enable = set_domain_enable, | |
294 | .get_enable = get_domain_enable, | |
295 | }, | |
296 | /* RAPL_DOMAIN_DRAM */ | |
297 | { | |
298 | .get_energy_uj = get_energy_counter, | |
299 | .get_max_energy_range_uj = get_max_energy_counter, | |
300 | .release = release_zone, | |
301 | .set_enable = set_domain_enable, | |
302 | .get_enable = get_domain_enable, | |
303 | }, | |
3521ba1c SP |
304 | /* RAPL_DOMAIN_PLATFORM */ |
305 | { | |
306 | .get_energy_uj = get_energy_counter, | |
307 | .get_max_energy_range_uj = get_max_energy_counter, | |
308 | .release = release_zone, | |
309 | .set_enable = set_domain_enable, | |
310 | .get_enable = get_domain_enable, | |
311 | }, | |
2d281d81 JP |
312 | }; |
313 | ||
e1399ba2 JP |
314 | |
315 | /* | |
316 | * Constraint index used by powercap can be different than power limit (PL) | |
317 | * index in that some PLs maybe missing due to non-existant MSRs. So we | |
318 | * need to convert here by finding the valid PLs only (name populated). | |
319 | */ | |
320 | static int contraint_to_pl(struct rapl_domain *rd, int cid) | |
321 | { | |
322 | int i, j; | |
323 | ||
324 | for (i = 0, j = 0; i < NR_POWER_LIMITS; i++) { | |
325 | if ((rd->rpl[i].name) && j++ == cid) { | |
326 | pr_debug("%s: index %d\n", __func__, i); | |
327 | return i; | |
328 | } | |
329 | } | |
cb43f81b | 330 | pr_err("Cannot find matching power limit for constraint %d\n", cid); |
e1399ba2 JP |
331 | |
332 | return -EINVAL; | |
333 | } | |
334 | ||
335 | static int set_power_limit(struct powercap_zone *power_zone, int cid, | |
2d281d81 JP |
336 | u64 power_limit) |
337 | { | |
338 | struct rapl_domain *rd; | |
339 | struct rapl_package *rp; | |
340 | int ret = 0; | |
e1399ba2 | 341 | int id; |
2d281d81 JP |
342 | |
343 | get_online_cpus(); | |
344 | rd = power_zone_to_rapl_domain(power_zone); | |
e1399ba2 | 345 | id = contraint_to_pl(rd, cid); |
cb43f81b JP |
346 | if (id < 0) { |
347 | ret = id; | |
348 | goto set_exit; | |
349 | } | |
e1399ba2 | 350 | |
309557f5 | 351 | rp = rd->rp; |
2d281d81 JP |
352 | |
353 | if (rd->state & DOMAIN_STATE_BIOS_LOCKED) { | |
354 | dev_warn(&power_zone->dev, "%s locked by BIOS, monitoring only\n", | |
355 | rd->name); | |
356 | ret = -EACCES; | |
357 | goto set_exit; | |
358 | } | |
359 | ||
360 | switch (rd->rpl[id].prim_id) { | |
361 | case PL1_ENABLE: | |
362 | rapl_write_data_raw(rd, POWER_LIMIT1, power_limit); | |
363 | break; | |
364 | case PL2_ENABLE: | |
365 | rapl_write_data_raw(rd, POWER_LIMIT2, power_limit); | |
366 | break; | |
367 | default: | |
368 | ret = -EINVAL; | |
369 | } | |
370 | if (!ret) | |
309557f5 | 371 | package_power_limit_irq_save(rp); |
2d281d81 JP |
372 | set_exit: |
373 | put_online_cpus(); | |
374 | return ret; | |
375 | } | |
376 | ||
e1399ba2 | 377 | static int get_current_power_limit(struct powercap_zone *power_zone, int cid, |
2d281d81 JP |
378 | u64 *data) |
379 | { | |
380 | struct rapl_domain *rd; | |
381 | u64 val; | |
382 | int prim; | |
383 | int ret = 0; | |
e1399ba2 | 384 | int id; |
2d281d81 JP |
385 | |
386 | get_online_cpus(); | |
387 | rd = power_zone_to_rapl_domain(power_zone); | |
e1399ba2 | 388 | id = contraint_to_pl(rd, cid); |
cb43f81b JP |
389 | if (id < 0) { |
390 | ret = id; | |
391 | goto get_exit; | |
392 | } | |
393 | ||
2d281d81 JP |
394 | switch (rd->rpl[id].prim_id) { |
395 | case PL1_ENABLE: | |
396 | prim = POWER_LIMIT1; | |
397 | break; | |
398 | case PL2_ENABLE: | |
399 | prim = POWER_LIMIT2; | |
400 | break; | |
401 | default: | |
402 | put_online_cpus(); | |
403 | return -EINVAL; | |
404 | } | |
405 | if (rapl_read_data_raw(rd, prim, true, &val)) | |
406 | ret = -EIO; | |
407 | else | |
408 | *data = val; | |
409 | ||
cb43f81b | 410 | get_exit: |
2d281d81 JP |
411 | put_online_cpus(); |
412 | ||
413 | return ret; | |
414 | } | |
415 | ||
e1399ba2 | 416 | static int set_time_window(struct powercap_zone *power_zone, int cid, |
2d281d81 JP |
417 | u64 window) |
418 | { | |
419 | struct rapl_domain *rd; | |
420 | int ret = 0; | |
e1399ba2 | 421 | int id; |
2d281d81 JP |
422 | |
423 | get_online_cpus(); | |
424 | rd = power_zone_to_rapl_domain(power_zone); | |
e1399ba2 | 425 | id = contraint_to_pl(rd, cid); |
cb43f81b JP |
426 | if (id < 0) { |
427 | ret = id; | |
428 | goto set_time_exit; | |
429 | } | |
e1399ba2 | 430 | |
2d281d81 JP |
431 | switch (rd->rpl[id].prim_id) { |
432 | case PL1_ENABLE: | |
433 | rapl_write_data_raw(rd, TIME_WINDOW1, window); | |
434 | break; | |
435 | case PL2_ENABLE: | |
436 | rapl_write_data_raw(rd, TIME_WINDOW2, window); | |
437 | break; | |
438 | default: | |
439 | ret = -EINVAL; | |
440 | } | |
cb43f81b JP |
441 | |
442 | set_time_exit: | |
2d281d81 JP |
443 | put_online_cpus(); |
444 | return ret; | |
445 | } | |
446 | ||
e1399ba2 | 447 | static int get_time_window(struct powercap_zone *power_zone, int cid, u64 *data) |
2d281d81 JP |
448 | { |
449 | struct rapl_domain *rd; | |
450 | u64 val; | |
451 | int ret = 0; | |
e1399ba2 | 452 | int id; |
2d281d81 JP |
453 | |
454 | get_online_cpus(); | |
455 | rd = power_zone_to_rapl_domain(power_zone); | |
e1399ba2 | 456 | id = contraint_to_pl(rd, cid); |
cb43f81b JP |
457 | if (id < 0) { |
458 | ret = id; | |
459 | goto get_time_exit; | |
460 | } | |
e1399ba2 | 461 | |
2d281d81 JP |
462 | switch (rd->rpl[id].prim_id) { |
463 | case PL1_ENABLE: | |
464 | ret = rapl_read_data_raw(rd, TIME_WINDOW1, true, &val); | |
465 | break; | |
466 | case PL2_ENABLE: | |
467 | ret = rapl_read_data_raw(rd, TIME_WINDOW2, true, &val); | |
468 | break; | |
469 | default: | |
470 | put_online_cpus(); | |
471 | return -EINVAL; | |
472 | } | |
473 | if (!ret) | |
474 | *data = val; | |
cb43f81b JP |
475 | |
476 | get_time_exit: | |
2d281d81 JP |
477 | put_online_cpus(); |
478 | ||
479 | return ret; | |
480 | } | |
481 | ||
e1399ba2 | 482 | static const char *get_constraint_name(struct powercap_zone *power_zone, int cid) |
2d281d81 | 483 | { |
2d281d81 | 484 | struct rapl_domain *rd; |
e1399ba2 | 485 | int id; |
2d281d81 JP |
486 | |
487 | rd = power_zone_to_rapl_domain(power_zone); | |
e1399ba2 JP |
488 | id = contraint_to_pl(rd, cid); |
489 | if (id >= 0) | |
490 | return rd->rpl[id].name; | |
2d281d81 | 491 | |
e1399ba2 | 492 | return NULL; |
2d281d81 JP |
493 | } |
494 | ||
495 | ||
496 | static int get_max_power(struct powercap_zone *power_zone, int id, | |
497 | u64 *data) | |
498 | { | |
499 | struct rapl_domain *rd; | |
500 | u64 val; | |
501 | int prim; | |
502 | int ret = 0; | |
503 | ||
504 | get_online_cpus(); | |
505 | rd = power_zone_to_rapl_domain(power_zone); | |
506 | switch (rd->rpl[id].prim_id) { | |
507 | case PL1_ENABLE: | |
508 | prim = THERMAL_SPEC_POWER; | |
509 | break; | |
510 | case PL2_ENABLE: | |
511 | prim = MAX_POWER; | |
512 | break; | |
513 | default: | |
514 | put_online_cpus(); | |
515 | return -EINVAL; | |
516 | } | |
517 | if (rapl_read_data_raw(rd, prim, true, &val)) | |
518 | ret = -EIO; | |
519 | else | |
520 | *data = val; | |
521 | ||
522 | put_online_cpus(); | |
523 | ||
524 | return ret; | |
525 | } | |
526 | ||
600c395b | 527 | static const struct powercap_zone_constraint_ops constraint_ops = { |
2d281d81 JP |
528 | .set_power_limit_uw = set_power_limit, |
529 | .get_power_limit_uw = get_current_power_limit, | |
530 | .set_time_window_us = set_time_window, | |
531 | .get_time_window_us = get_time_window, | |
532 | .get_max_power_uw = get_max_power, | |
533 | .get_name = get_constraint_name, | |
534 | }; | |
535 | ||
536 | /* called after domain detection and package level data are set */ | |
537 | static void rapl_init_domains(struct rapl_package *rp) | |
538 | { | |
539 | int i; | |
540 | struct rapl_domain *rd = rp->domains; | |
541 | ||
542 | for (i = 0; i < RAPL_DOMAIN_MAX; i++) { | |
543 | unsigned int mask = rp->domain_map & (1 << i); | |
544 | switch (mask) { | |
545 | case BIT(RAPL_DOMAIN_PACKAGE): | |
546 | rd->name = rapl_domain_names[RAPL_DOMAIN_PACKAGE]; | |
547 | rd->id = RAPL_DOMAIN_PACKAGE; | |
8310e820 ZR |
548 | rd->regs[RAPL_DOMAIN_REG_LIMIT] = MSR_PKG_POWER_LIMIT; |
549 | rd->regs[RAPL_DOMAIN_REG_STATUS] = MSR_PKG_ENERGY_STATUS; | |
550 | rd->regs[RAPL_DOMAIN_REG_PERF] = MSR_PKG_PERF_STATUS; | |
551 | rd->regs[RAPL_DOMAIN_REG_POLICY] = 0; | |
552 | rd->regs[RAPL_DOMAIN_REG_INFO] = MSR_PKG_POWER_INFO; | |
2d281d81 JP |
553 | rd->rpl[0].prim_id = PL1_ENABLE; |
554 | rd->rpl[0].name = pl1_name; | |
555 | rd->rpl[1].prim_id = PL2_ENABLE; | |
556 | rd->rpl[1].name = pl2_name; | |
557 | break; | |
558 | case BIT(RAPL_DOMAIN_PP0): | |
559 | rd->name = rapl_domain_names[RAPL_DOMAIN_PP0]; | |
560 | rd->id = RAPL_DOMAIN_PP0; | |
8310e820 ZR |
561 | rd->regs[RAPL_DOMAIN_REG_LIMIT] = MSR_PP0_POWER_LIMIT; |
562 | rd->regs[RAPL_DOMAIN_REG_STATUS] = MSR_PP0_ENERGY_STATUS; | |
563 | rd->regs[RAPL_DOMAIN_REG_PERF] = 0; | |
564 | rd->regs[RAPL_DOMAIN_REG_POLICY] = MSR_PP0_POLICY; | |
565 | rd->regs[RAPL_DOMAIN_REG_INFO] = 0; | |
2d281d81 JP |
566 | rd->rpl[0].prim_id = PL1_ENABLE; |
567 | rd->rpl[0].name = pl1_name; | |
568 | break; | |
569 | case BIT(RAPL_DOMAIN_PP1): | |
570 | rd->name = rapl_domain_names[RAPL_DOMAIN_PP1]; | |
571 | rd->id = RAPL_DOMAIN_PP1; | |
8310e820 ZR |
572 | rd->regs[RAPL_DOMAIN_REG_LIMIT] = MSR_PP1_POWER_LIMIT; |
573 | rd->regs[RAPL_DOMAIN_REG_STATUS] = MSR_PP1_ENERGY_STATUS; | |
574 | rd->regs[RAPL_DOMAIN_REG_PERF] = 0; | |
575 | rd->regs[RAPL_DOMAIN_REG_POLICY] = MSR_PP1_POLICY; | |
576 | rd->regs[RAPL_DOMAIN_REG_INFO] = 0; | |
2d281d81 JP |
577 | rd->rpl[0].prim_id = PL1_ENABLE; |
578 | rd->rpl[0].name = pl1_name; | |
579 | break; | |
580 | case BIT(RAPL_DOMAIN_DRAM): | |
581 | rd->name = rapl_domain_names[RAPL_DOMAIN_DRAM]; | |
582 | rd->id = RAPL_DOMAIN_DRAM; | |
8310e820 ZR |
583 | rd->regs[RAPL_DOMAIN_REG_LIMIT] = MSR_DRAM_POWER_LIMIT; |
584 | rd->regs[RAPL_DOMAIN_REG_STATUS] = MSR_DRAM_ENERGY_STATUS; | |
585 | rd->regs[RAPL_DOMAIN_REG_PERF] = MSR_DRAM_PERF_STATUS; | |
586 | rd->regs[RAPL_DOMAIN_REG_POLICY] = 0; | |
587 | rd->regs[RAPL_DOMAIN_REG_INFO] = MSR_DRAM_POWER_INFO; | |
2d281d81 JP |
588 | rd->rpl[0].prim_id = PL1_ENABLE; |
589 | rd->rpl[0].name = pl1_name; | |
d474a4d3 JP |
590 | rd->domain_energy_unit = |
591 | rapl_defaults->dram_domain_energy_unit; | |
592 | if (rd->domain_energy_unit) | |
593 | pr_info("DRAM domain energy unit %dpj\n", | |
594 | rd->domain_energy_unit); | |
2d281d81 JP |
595 | break; |
596 | } | |
597 | if (mask) { | |
309557f5 | 598 | rd->rp = rp; |
2d281d81 JP |
599 | rd++; |
600 | } | |
601 | } | |
602 | } | |
603 | ||
309557f5 JP |
604 | static u64 rapl_unit_xlate(struct rapl_domain *rd, enum unit_type type, |
605 | u64 value, int to_raw) | |
2d281d81 | 606 | { |
3c2c0845 | 607 | u64 units = 1; |
309557f5 | 608 | struct rapl_package *rp = rd->rp; |
d474a4d3 | 609 | u64 scale = 1; |
2d281d81 | 610 | |
2d281d81 JP |
611 | switch (type) { |
612 | case POWER_UNIT: | |
3c2c0845 | 613 | units = rp->power_unit; |
2d281d81 JP |
614 | break; |
615 | case ENERGY_UNIT: | |
d474a4d3 JP |
616 | scale = ENERGY_UNIT_SCALE; |
617 | /* per domain unit takes precedence */ | |
cb43f81b | 618 | if (rd->domain_energy_unit) |
d474a4d3 JP |
619 | units = rd->domain_energy_unit; |
620 | else | |
621 | units = rp->energy_unit; | |
2d281d81 JP |
622 | break; |
623 | case TIME_UNIT: | |
3c2c0845 | 624 | return rapl_defaults->compute_time_window(rp, value, to_raw); |
2d281d81 JP |
625 | case ARBITRARY_UNIT: |
626 | default: | |
627 | return value; | |
628 | }; | |
629 | ||
630 | if (to_raw) | |
d474a4d3 | 631 | return div64_u64(value, units) * scale; |
3c2c0845 JP |
632 | |
633 | value *= units; | |
634 | ||
d474a4d3 | 635 | return div64_u64(value, scale); |
2d281d81 JP |
636 | } |
637 | ||
638 | /* in the order of enum rapl_primitives */ | |
639 | static struct rapl_primitive_info rpi[] = { | |
640 | /* name, mask, shift, msr index, unit divisor */ | |
641 | PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0, | |
f7c4e0c8 | 642 | RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0), |
2d281d81 | 643 | PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0, |
f7c4e0c8 | 644 | RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), |
2d281d81 | 645 | PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32, |
f7c4e0c8 | 646 | RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), |
2d281d81 | 647 | PRIMITIVE_INFO_INIT(FW_LOCK, POWER_PP_LOCK, 31, |
f7c4e0c8 | 648 | RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), |
2d281d81 | 649 | PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15, |
f7c4e0c8 | 650 | RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), |
2d281d81 | 651 | PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16, |
f7c4e0c8 | 652 | RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), |
2d281d81 | 653 | PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47, |
f7c4e0c8 | 654 | RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), |
2d281d81 | 655 | PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48, |
f7c4e0c8 | 656 | RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), |
2d281d81 | 657 | PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17, |
f7c4e0c8 | 658 | RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), |
2d281d81 | 659 | PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49, |
f7c4e0c8 | 660 | RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), |
2d281d81 | 661 | PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, POWER_INFO_THERMAL_SPEC_MASK, |
f7c4e0c8 | 662 | 0, RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), |
2d281d81 | 663 | PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32, |
f7c4e0c8 | 664 | RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), |
2d281d81 | 665 | PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16, |
f7c4e0c8 | 666 | RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), |
2d281d81 | 667 | PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, POWER_INFO_MAX_TIME_WIN_MASK, 48, |
f7c4e0c8 | 668 | RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0), |
2d281d81 | 669 | PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK, 0, |
f7c4e0c8 | 670 | RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0), |
2d281d81 | 671 | PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0, |
f7c4e0c8 | 672 | RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0), |
2d281d81 JP |
673 | /* non-hardware */ |
674 | PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, POWER_UNIT, | |
675 | RAPL_PRIMITIVE_DERIVED), | |
676 | {NULL, 0, 0, 0}, | |
677 | }; | |
678 | ||
679 | /* Read primitive data based on its related struct rapl_primitive_info. | |
680 | * if xlate flag is set, return translated data based on data units, i.e. | |
681 | * time, energy, and power. | |
682 | * RAPL MSRs are non-architectual and are laid out not consistently across | |
683 | * domains. Here we use primitive info to allow writing consolidated access | |
684 | * functions. | |
685 | * For a given primitive, it is processed by MSR mask and shift. Unit conversion | |
686 | * is pre-assigned based on RAPL unit MSRs read at init time. | |
687 | * 63-------------------------- 31--------------------------- 0 | |
688 | * | xxxxx (mask) | | |
689 | * | |<- shift ----------------| | |
690 | * 63-------------------------- 31--------------------------- 0 | |
691 | */ | |
692 | static int rapl_read_data_raw(struct rapl_domain *rd, | |
693 | enum rapl_primitives prim, | |
694 | bool xlate, u64 *data) | |
695 | { | |
696 | u64 value, final; | |
697 | u32 msr; | |
698 | struct rapl_primitive_info *rp = &rpi[prim]; | |
699 | int cpu; | |
700 | ||
701 | if (!rp->name || rp->flag & RAPL_PRIMITIVE_DUMMY) | |
702 | return -EINVAL; | |
703 | ||
f7c4e0c8 | 704 | msr = rd->regs[rp->id]; |
2d281d81 JP |
705 | if (!msr) |
706 | return -EINVAL; | |
323ee64a JP |
707 | |
708 | cpu = rd->rp->lead_cpu; | |
2d281d81 JP |
709 | |
710 | /* special-case package domain, which uses a different bit*/ | |
711 | if (prim == FW_LOCK && rd->id == RAPL_DOMAIN_PACKAGE) { | |
712 | rp->mask = POWER_PACKAGE_LOCK; | |
713 | rp->shift = 63; | |
714 | } | |
715 | /* non-hardware data are collected by the polling thread */ | |
716 | if (rp->flag & RAPL_PRIMITIVE_DERIVED) { | |
717 | *data = rd->rdd.primitives[prim]; | |
718 | return 0; | |
719 | } | |
720 | ||
721 | if (rdmsrl_safe_on_cpu(cpu, msr, &value)) { | |
722 | pr_debug("failed to read msr 0x%x on cpu %d\n", msr, cpu); | |
723 | return -EIO; | |
724 | } | |
725 | ||
726 | final = value & rp->mask; | |
727 | final = final >> rp->shift; | |
728 | if (xlate) | |
309557f5 | 729 | *data = rapl_unit_xlate(rd, rp->unit, final, 0); |
2d281d81 JP |
730 | else |
731 | *data = final; | |
732 | ||
733 | return 0; | |
734 | } | |
735 | ||
f14a1396 JP |
736 | |
737 | static int msrl_update_safe(u32 msr_no, u64 clear_mask, u64 set_mask) | |
738 | { | |
739 | int err; | |
740 | u64 val; | |
741 | ||
742 | err = rdmsrl_safe(msr_no, &val); | |
743 | if (err) | |
744 | goto out; | |
745 | ||
746 | val &= ~clear_mask; | |
747 | val |= set_mask; | |
748 | ||
749 | err = wrmsrl_safe(msr_no, val); | |
750 | ||
751 | out: | |
752 | return err; | |
753 | } | |
754 | ||
755 | static void msrl_update_func(void *info) | |
756 | { | |
757 | struct msrl_action *ma = info; | |
758 | ||
759 | ma->err = msrl_update_safe(ma->msr_no, ma->clear_mask, ma->set_mask); | |
760 | } | |
761 | ||
2d281d81 JP |
762 | /* Similar use of primitive info in the read counterpart */ |
763 | static int rapl_write_data_raw(struct rapl_domain *rd, | |
764 | enum rapl_primitives prim, | |
765 | unsigned long long value) | |
766 | { | |
2d281d81 JP |
767 | struct rapl_primitive_info *rp = &rpi[prim]; |
768 | int cpu; | |
f14a1396 JP |
769 | u64 bits; |
770 | struct msrl_action ma; | |
771 | int ret; | |
2d281d81 | 772 | |
323ee64a | 773 | cpu = rd->rp->lead_cpu; |
309557f5 | 774 | bits = rapl_unit_xlate(rd, rp->unit, value, 1); |
edbdabc6 AL |
775 | bits <<= rp->shift; |
776 | bits &= rp->mask; | |
777 | ||
f14a1396 JP |
778 | memset(&ma, 0, sizeof(ma)); |
779 | ||
f7c4e0c8 | 780 | ma.msr_no = rd->regs[rp->id]; |
f14a1396 JP |
781 | ma.clear_mask = rp->mask; |
782 | ma.set_mask = bits; | |
783 | ||
784 | ret = smp_call_function_single(cpu, msrl_update_func, &ma, 1); | |
785 | if (ret) | |
786 | WARN_ON_ONCE(ret); | |
787 | else | |
788 | ret = ma.err; | |
789 | ||
790 | return ret; | |
2d281d81 JP |
791 | } |
792 | ||
3c2c0845 JP |
793 | /* |
794 | * Raw RAPL data stored in MSRs are in certain scales. We need to | |
795 | * convert them into standard units based on the units reported in | |
796 | * the RAPL unit MSRs. This is specific to CPUs as the method to | |
797 | * calculate units differ on different CPUs. | |
798 | * We convert the units to below format based on CPUs. | |
799 | * i.e. | |
d474a4d3 | 800 | * energy unit: picoJoules : Represented in picoJoules by default |
3c2c0845 JP |
801 | * power unit : microWatts : Represented in milliWatts by default |
802 | * time unit : microseconds: Represented in seconds by default | |
803 | */ | |
804 | static int rapl_check_unit_core(struct rapl_package *rp, int cpu) | |
2d281d81 JP |
805 | { |
806 | u64 msr_val; | |
807 | u32 value; | |
808 | ||
809 | if (rdmsrl_safe_on_cpu(cpu, MSR_RAPL_POWER_UNIT, &msr_val)) { | |
810 | pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n", | |
811 | MSR_RAPL_POWER_UNIT, cpu); | |
812 | return -ENODEV; | |
813 | } | |
814 | ||
2d281d81 | 815 | value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET; |
d474a4d3 | 816 | rp->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << value); |
2d281d81 JP |
817 | |
818 | value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET; | |
3c2c0845 | 819 | rp->power_unit = 1000000 / (1 << value); |
2d281d81 JP |
820 | |
821 | value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET; | |
3c2c0845 | 822 | rp->time_unit = 1000000 / (1 << value); |
2d281d81 | 823 | |
9ea7612c ZR |
824 | pr_debug("Core CPU %s energy=%dpJ, time=%dus, power=%duW\n", |
825 | rp->name, rp->energy_unit, rp->time_unit, rp->power_unit); | |
2d281d81 JP |
826 | |
827 | return 0; | |
828 | } | |
829 | ||
3c2c0845 JP |
830 | static int rapl_check_unit_atom(struct rapl_package *rp, int cpu) |
831 | { | |
832 | u64 msr_val; | |
833 | u32 value; | |
834 | ||
835 | if (rdmsrl_safe_on_cpu(cpu, MSR_RAPL_POWER_UNIT, &msr_val)) { | |
836 | pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n", | |
837 | MSR_RAPL_POWER_UNIT, cpu); | |
838 | return -ENODEV; | |
839 | } | |
840 | value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET; | |
d474a4d3 | 841 | rp->energy_unit = ENERGY_UNIT_SCALE * 1 << value; |
3c2c0845 JP |
842 | |
843 | value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET; | |
844 | rp->power_unit = (1 << value) * 1000; | |
845 | ||
846 | value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET; | |
847 | rp->time_unit = 1000000 / (1 << value); | |
848 | ||
9ea7612c ZR |
849 | pr_debug("Atom %s energy=%dpJ, time=%dus, power=%duW\n", |
850 | rp->name, rp->energy_unit, rp->time_unit, rp->power_unit); | |
3c2c0845 JP |
851 | |
852 | return 0; | |
853 | } | |
854 | ||
f14a1396 JP |
855 | static void power_limit_irq_save_cpu(void *info) |
856 | { | |
857 | u32 l, h = 0; | |
858 | struct rapl_package *rp = (struct rapl_package *)info; | |
859 | ||
860 | /* save the state of PLN irq mask bit before disabling it */ | |
861 | rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h); | |
862 | if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED)) { | |
863 | rp->power_limit_irq = l & PACKAGE_THERM_INT_PLN_ENABLE; | |
864 | rp->power_limit_irq |= PACKAGE_PLN_INT_SAVED; | |
865 | } | |
866 | l &= ~PACKAGE_THERM_INT_PLN_ENABLE; | |
867 | wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); | |
868 | } | |
869 | ||
3c2c0845 | 870 | |
2d281d81 JP |
871 | /* REVISIT: |
872 | * When package power limit is set artificially low by RAPL, LVT | |
873 | * thermal interrupt for package power limit should be ignored | |
874 | * since we are not really exceeding the real limit. The intention | |
875 | * is to avoid excessive interrupts while we are trying to save power. | |
876 | * A useful feature might be routing the package_power_limit interrupt | |
877 | * to userspace via eventfd. once we have a usecase, this is simple | |
878 | * to do by adding an atomic notifier. | |
879 | */ | |
880 | ||
309557f5 | 881 | static void package_power_limit_irq_save(struct rapl_package *rp) |
2d281d81 | 882 | { |
f14a1396 JP |
883 | if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN)) |
884 | return; | |
885 | ||
323ee64a | 886 | smp_call_function_single(rp->lead_cpu, power_limit_irq_save_cpu, rp, 1); |
f14a1396 JP |
887 | } |
888 | ||
58705069 TG |
889 | /* |
890 | * Restore per package power limit interrupt enable state. Called from cpu | |
891 | * hotplug code on package removal. | |
892 | */ | |
893 | static void package_power_limit_irq_restore(struct rapl_package *rp) | |
f14a1396 | 894 | { |
58705069 TG |
895 | u32 l, h; |
896 | ||
897 | if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN)) | |
898 | return; | |
899 | ||
900 | /* irq enable state not saved, nothing to restore */ | |
901 | if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED)) | |
902 | return; | |
f14a1396 JP |
903 | |
904 | rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h); | |
905 | ||
906 | if (rp->power_limit_irq & PACKAGE_THERM_INT_PLN_ENABLE) | |
907 | l |= PACKAGE_THERM_INT_PLN_ENABLE; | |
908 | else | |
909 | l &= ~PACKAGE_THERM_INT_PLN_ENABLE; | |
910 | ||
911 | wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); | |
2d281d81 JP |
912 | } |
913 | ||
3c2c0845 JP |
914 | static void set_floor_freq_default(struct rapl_domain *rd, bool mode) |
915 | { | |
916 | int nr_powerlimit = find_nr_power_limit(rd); | |
917 | ||
918 | /* always enable clamp such that p-state can go below OS requested | |
919 | * range. power capping priority over guranteed frequency. | |
920 | */ | |
921 | rapl_write_data_raw(rd, PL1_CLAMP, mode); | |
922 | ||
923 | /* some domains have pl2 */ | |
924 | if (nr_powerlimit > 1) { | |
925 | rapl_write_data_raw(rd, PL2_ENABLE, mode); | |
926 | rapl_write_data_raw(rd, PL2_CLAMP, mode); | |
927 | } | |
928 | } | |
929 | ||
930 | static void set_floor_freq_atom(struct rapl_domain *rd, bool enable) | |
931 | { | |
932 | static u32 power_ctrl_orig_val; | |
933 | u32 mdata; | |
934 | ||
51b63409 AT |
935 | if (!rapl_defaults->floor_freq_reg_addr) { |
936 | pr_err("Invalid floor frequency config register\n"); | |
937 | return; | |
938 | } | |
939 | ||
3c2c0845 | 940 | if (!power_ctrl_orig_val) |
4077a387 AS |
941 | iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_CR_READ, |
942 | rapl_defaults->floor_freq_reg_addr, | |
943 | &power_ctrl_orig_val); | |
3c2c0845 JP |
944 | mdata = power_ctrl_orig_val; |
945 | if (enable) { | |
946 | mdata &= ~(0x7f << 8); | |
947 | mdata |= 1 << 8; | |
948 | } | |
4077a387 AS |
949 | iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_CR_WRITE, |
950 | rapl_defaults->floor_freq_reg_addr, mdata); | |
3c2c0845 JP |
951 | } |
952 | ||
953 | static u64 rapl_compute_time_window_core(struct rapl_package *rp, u64 value, | |
954 | bool to_raw) | |
955 | { | |
956 | u64 f, y; /* fraction and exp. used for time unit */ | |
957 | ||
958 | /* | |
959 | * Special processing based on 2^Y*(1+F/4), refer | |
960 | * to Intel Software Developer's manual Vol.3B: CH 14.9.3. | |
961 | */ | |
962 | if (!to_raw) { | |
963 | f = (value & 0x60) >> 5; | |
964 | y = value & 0x1f; | |
965 | value = (1 << y) * (4 + f) * rp->time_unit / 4; | |
966 | } else { | |
967 | do_div(value, rp->time_unit); | |
968 | y = ilog2(value); | |
969 | f = div64_u64(4 * (value - (1 << y)), 1 << y); | |
970 | value = (y & 0x1f) | ((f & 0x3) << 5); | |
971 | } | |
972 | return value; | |
973 | } | |
974 | ||
975 | static u64 rapl_compute_time_window_atom(struct rapl_package *rp, u64 value, | |
976 | bool to_raw) | |
977 | { | |
978 | /* | |
979 | * Atom time unit encoding is straight forward val * time_unit, | |
980 | * where time_unit is default to 1 sec. Never 0. | |
981 | */ | |
982 | if (!to_raw) | |
983 | return (value) ? value *= rp->time_unit : rp->time_unit; | |
984 | else | |
985 | value = div64_u64(value, rp->time_unit); | |
986 | ||
987 | return value; | |
988 | } | |
989 | ||
087e9cba | 990 | static const struct rapl_defaults rapl_defaults_core = { |
51b63409 | 991 | .floor_freq_reg_addr = 0, |
3c2c0845 JP |
992 | .check_unit = rapl_check_unit_core, |
993 | .set_floor_freq = set_floor_freq_default, | |
994 | .compute_time_window = rapl_compute_time_window_core, | |
087e9cba JP |
995 | }; |
996 | ||
d474a4d3 JP |
997 | static const struct rapl_defaults rapl_defaults_hsw_server = { |
998 | .check_unit = rapl_check_unit_core, | |
999 | .set_floor_freq = set_floor_freq_default, | |
1000 | .compute_time_window = rapl_compute_time_window_core, | |
1001 | .dram_domain_energy_unit = 15300, | |
1002 | }; | |
1003 | ||
51b63409 AT |
1004 | static const struct rapl_defaults rapl_defaults_byt = { |
1005 | .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_BYT, | |
1006 | .check_unit = rapl_check_unit_atom, | |
1007 | .set_floor_freq = set_floor_freq_atom, | |
1008 | .compute_time_window = rapl_compute_time_window_atom, | |
1009 | }; | |
1010 | ||
1011 | static const struct rapl_defaults rapl_defaults_tng = { | |
1012 | .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_TNG, | |
3c2c0845 JP |
1013 | .check_unit = rapl_check_unit_atom, |
1014 | .set_floor_freq = set_floor_freq_atom, | |
1015 | .compute_time_window = rapl_compute_time_window_atom, | |
087e9cba JP |
1016 | }; |
1017 | ||
51b63409 AT |
1018 | static const struct rapl_defaults rapl_defaults_ann = { |
1019 | .floor_freq_reg_addr = 0, | |
1020 | .check_unit = rapl_check_unit_atom, | |
1021 | .set_floor_freq = NULL, | |
1022 | .compute_time_window = rapl_compute_time_window_atom, | |
1023 | }; | |
1024 | ||
1025 | static const struct rapl_defaults rapl_defaults_cht = { | |
1026 | .floor_freq_reg_addr = 0, | |
1027 | .check_unit = rapl_check_unit_atom, | |
1028 | .set_floor_freq = NULL, | |
1029 | .compute_time_window = rapl_compute_time_window_atom, | |
1030 | }; | |
1031 | ||
ea85dbca | 1032 | static const struct x86_cpu_id rapl_ids[] __initconst = { |
17ed1518 AS |
1033 | INTEL_CPU_FAM6(SANDYBRIDGE, rapl_defaults_core), |
1034 | INTEL_CPU_FAM6(SANDYBRIDGE_X, rapl_defaults_core), | |
1035 | ||
1036 | INTEL_CPU_FAM6(IVYBRIDGE, rapl_defaults_core), | |
1037 | INTEL_CPU_FAM6(IVYBRIDGE_X, rapl_defaults_core), | |
1038 | ||
1039 | INTEL_CPU_FAM6(HASWELL_CORE, rapl_defaults_core), | |
1040 | INTEL_CPU_FAM6(HASWELL_ULT, rapl_defaults_core), | |
1041 | INTEL_CPU_FAM6(HASWELL_GT3E, rapl_defaults_core), | |
1042 | INTEL_CPU_FAM6(HASWELL_X, rapl_defaults_hsw_server), | |
1043 | ||
1044 | INTEL_CPU_FAM6(BROADWELL_CORE, rapl_defaults_core), | |
1045 | INTEL_CPU_FAM6(BROADWELL_GT3E, rapl_defaults_core), | |
1046 | INTEL_CPU_FAM6(BROADWELL_XEON_D, rapl_defaults_core), | |
1047 | INTEL_CPU_FAM6(BROADWELL_X, rapl_defaults_hsw_server), | |
1048 | ||
1049 | INTEL_CPU_FAM6(SKYLAKE_DESKTOP, rapl_defaults_core), | |
1050 | INTEL_CPU_FAM6(SKYLAKE_MOBILE, rapl_defaults_core), | |
1051 | INTEL_CPU_FAM6(SKYLAKE_X, rapl_defaults_hsw_server), | |
1052 | INTEL_CPU_FAM6(KABYLAKE_MOBILE, rapl_defaults_core), | |
1053 | INTEL_CPU_FAM6(KABYLAKE_DESKTOP, rapl_defaults_core), | |
1054 | INTEL_CPU_FAM6(CANNONLAKE_MOBILE, rapl_defaults_core), | |
ba6f3ec1 | 1055 | INTEL_CPU_FAM6(ICELAKE_MOBILE, rapl_defaults_core), |
17ed1518 | 1056 | |
c05f3642 | 1057 | INTEL_CPU_FAM6(ATOM_SILVERMONT, rapl_defaults_byt), |
17ed1518 | 1058 | INTEL_CPU_FAM6(ATOM_AIRMONT, rapl_defaults_cht), |
c05f3642 LT |
1059 | INTEL_CPU_FAM6(ATOM_SILVERMONT_MID, rapl_defaults_tng), |
1060 | INTEL_CPU_FAM6(ATOM_AIRMONT_MID, rapl_defaults_ann), | |
17ed1518 | 1061 | INTEL_CPU_FAM6(ATOM_GOLDMONT, rapl_defaults_core), |
c05f3642 LT |
1062 | INTEL_CPU_FAM6(ATOM_GOLDMONT_PLUS, rapl_defaults_core), |
1063 | INTEL_CPU_FAM6(ATOM_GOLDMONT_X, rapl_defaults_core), | |
df7f8e00 | 1064 | INTEL_CPU_FAM6(ATOM_TREMONT_X, rapl_defaults_core), |
17ed1518 AS |
1065 | |
1066 | INTEL_CPU_FAM6(XEON_PHI_KNL, rapl_defaults_hsw_server), | |
1067 | INTEL_CPU_FAM6(XEON_PHI_KNM, rapl_defaults_hsw_server), | |
2d281d81 JP |
1068 | {} |
1069 | }; | |
1070 | MODULE_DEVICE_TABLE(x86cpu, rapl_ids); | |
1071 | ||
bed5ab63 TG |
1072 | /* Read once for all raw primitive data for domains */ |
1073 | static void rapl_update_domain_data(struct rapl_package *rp) | |
2d281d81 JP |
1074 | { |
1075 | int dmn, prim; | |
1076 | u64 val; | |
2d281d81 | 1077 | |
bed5ab63 | 1078 | for (dmn = 0; dmn < rp->nr_domains; dmn++) { |
9ea7612c | 1079 | pr_debug("update %s domain %s data\n", rp->name, |
bed5ab63 TG |
1080 | rp->domains[dmn].name); |
1081 | /* exclude non-raw primitives */ | |
1082 | for (prim = 0; prim < NR_RAW_PRIMITIVES; prim++) { | |
1083 | if (!rapl_read_data_raw(&rp->domains[dmn], prim, | |
1084 | rpi[prim].unit, &val)) | |
1085 | rp->domains[dmn].rdd.primitives[prim] = val; | |
2d281d81 JP |
1086 | } |
1087 | } | |
1088 | ||
1089 | } | |
1090 | ||
58705069 | 1091 | static void rapl_unregister_powercap(void) |
2d281d81 | 1092 | { |
7ebf8eff ZR |
1093 | if (&rapl_msr_priv.platform_rapl_domain) { |
1094 | powercap_unregister_zone(rapl_msr_priv.control_type, | |
1095 | &rapl_msr_priv.platform_rapl_domain->power_zone); | |
1096 | kfree(rapl_msr_priv.platform_rapl_domain); | |
3521ba1c | 1097 | } |
7ebf8eff | 1098 | powercap_unregister_control_type(rapl_msr_priv.control_type); |
2d281d81 JP |
1099 | } |
1100 | ||
1101 | static int rapl_package_register_powercap(struct rapl_package *rp) | |
1102 | { | |
1103 | struct rapl_domain *rd; | |
2d281d81 | 1104 | struct powercap_zone *power_zone = NULL; |
01857cf7 | 1105 | int nr_pl, ret; |
bed5ab63 TG |
1106 | |
1107 | /* Update the domain data of the new package */ | |
1108 | rapl_update_domain_data(rp); | |
2d281d81 JP |
1109 | |
1110 | /* first we register package domain as the parent zone*/ | |
1111 | for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { | |
1112 | if (rd->id == RAPL_DOMAIN_PACKAGE) { | |
1113 | nr_pl = find_nr_power_limit(rd); | |
9ea7612c | 1114 | pr_debug("register package domain %s\n", rp->name); |
2d281d81 | 1115 | power_zone = powercap_register_zone(&rd->power_zone, |
7ebf8eff | 1116 | rp->priv->control_type, |
9ea7612c | 1117 | rp->name, NULL, |
2d281d81 JP |
1118 | &zone_ops[rd->id], |
1119 | nr_pl, | |
1120 | &constraint_ops); | |
1121 | if (IS_ERR(power_zone)) { | |
9ea7612c ZR |
1122 | pr_debug("failed to register power zone %s\n", |
1123 | rp->name); | |
bed5ab63 | 1124 | return PTR_ERR(power_zone); |
2d281d81 JP |
1125 | } |
1126 | /* track parent zone in per package/socket data */ | |
1127 | rp->power_zone = power_zone; | |
1128 | /* done, only one package domain per socket */ | |
1129 | break; | |
1130 | } | |
1131 | } | |
1132 | if (!power_zone) { | |
1133 | pr_err("no package domain found, unknown topology!\n"); | |
bed5ab63 | 1134 | return -ENODEV; |
2d281d81 JP |
1135 | } |
1136 | /* now register domains as children of the socket/package*/ | |
1137 | for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { | |
1138 | if (rd->id == RAPL_DOMAIN_PACKAGE) | |
1139 | continue; | |
1140 | /* number of power limits per domain varies */ | |
1141 | nr_pl = find_nr_power_limit(rd); | |
1142 | power_zone = powercap_register_zone(&rd->power_zone, | |
7ebf8eff | 1143 | rp->priv->control_type, rd->name, |
2d281d81 JP |
1144 | rp->power_zone, |
1145 | &zone_ops[rd->id], nr_pl, | |
1146 | &constraint_ops); | |
1147 | ||
1148 | if (IS_ERR(power_zone)) { | |
9ea7612c ZR |
1149 | pr_debug("failed to register power_zone, %s:%s\n", |
1150 | rp->name, rd->name); | |
2d281d81 JP |
1151 | ret = PTR_ERR(power_zone); |
1152 | goto err_cleanup; | |
1153 | } | |
1154 | } | |
bed5ab63 | 1155 | return 0; |
2d281d81 | 1156 | |
2d281d81 | 1157 | err_cleanup: |
58705069 TG |
1158 | /* |
1159 | * Clean up previously initialized domains within the package if we | |
2d281d81 JP |
1160 | * failed after the first domain setup. |
1161 | */ | |
1162 | while (--rd >= rp->domains) { | |
9ea7612c | 1163 | pr_debug("unregister %s domain %s\n", rp->name, rd->name); |
7ebf8eff | 1164 | powercap_unregister_zone(rp->priv->control_type, &rd->power_zone); |
2d281d81 JP |
1165 | } |
1166 | ||
1167 | return ret; | |
1168 | } | |
1169 | ||
58705069 | 1170 | static int __init rapl_register_psys(void) |
3521ba1c SP |
1171 | { |
1172 | struct rapl_domain *rd; | |
1173 | struct powercap_zone *power_zone; | |
1174 | u64 val; | |
1175 | ||
1176 | if (rdmsrl_safe_on_cpu(0, MSR_PLATFORM_ENERGY_STATUS, &val) || !val) | |
1177 | return -ENODEV; | |
1178 | ||
1179 | if (rdmsrl_safe_on_cpu(0, MSR_PLATFORM_POWER_LIMIT, &val) || !val) | |
1180 | return -ENODEV; | |
1181 | ||
1182 | rd = kzalloc(sizeof(*rd), GFP_KERNEL); | |
1183 | if (!rd) | |
1184 | return -ENOMEM; | |
1185 | ||
1186 | rd->name = rapl_domain_names[RAPL_DOMAIN_PLATFORM]; | |
1187 | rd->id = RAPL_DOMAIN_PLATFORM; | |
8310e820 ZR |
1188 | rd->regs[RAPL_DOMAIN_REG_LIMIT] = MSR_PLATFORM_POWER_LIMIT; |
1189 | rd->regs[RAPL_DOMAIN_REG_STATUS] = MSR_PLATFORM_ENERGY_STATUS; | |
3521ba1c SP |
1190 | rd->rpl[0].prim_id = PL1_ENABLE; |
1191 | rd->rpl[0].name = pl1_name; | |
1192 | rd->rpl[1].prim_id = PL2_ENABLE; | |
1193 | rd->rpl[1].name = pl2_name; | |
7ebf8eff | 1194 | rd->rp = rapl_find_package_domain(0, &rapl_msr_priv); |
3521ba1c | 1195 | |
7ebf8eff | 1196 | power_zone = powercap_register_zone(&rd->power_zone, rapl_msr_priv.control_type, |
3521ba1c SP |
1197 | "psys", NULL, |
1198 | &zone_ops[RAPL_DOMAIN_PLATFORM], | |
1199 | 2, &constraint_ops); | |
1200 | ||
1201 | if (IS_ERR(power_zone)) { | |
1202 | kfree(rd); | |
1203 | return PTR_ERR(power_zone); | |
1204 | } | |
1205 | ||
7ebf8eff | 1206 | rapl_msr_priv.platform_rapl_domain = rd; |
3521ba1c SP |
1207 | |
1208 | return 0; | |
1209 | } | |
1210 | ||
58705069 | 1211 | static int __init rapl_register_powercap(void) |
2d281d81 | 1212 | { |
7ebf8eff ZR |
1213 | rapl_msr_priv.control_type = powercap_register_control_type(NULL, "intel-rapl", NULL); |
1214 | if (IS_ERR(rapl_msr_priv.control_type)) { | |
2d281d81 | 1215 | pr_debug("failed to register powercap control_type.\n"); |
7ebf8eff | 1216 | return PTR_ERR(rapl_msr_priv.control_type); |
2d281d81 | 1217 | } |
58705069 | 1218 | return 0; |
2d281d81 JP |
1219 | } |
1220 | ||
1221 | static int rapl_check_domain(int cpu, int domain) | |
1222 | { | |
1223 | unsigned msr; | |
9d31c676 | 1224 | u64 val = 0; |
2d281d81 JP |
1225 | |
1226 | switch (domain) { | |
1227 | case RAPL_DOMAIN_PACKAGE: | |
1228 | msr = MSR_PKG_ENERGY_STATUS; | |
1229 | break; | |
1230 | case RAPL_DOMAIN_PP0: | |
1231 | msr = MSR_PP0_ENERGY_STATUS; | |
1232 | break; | |
1233 | case RAPL_DOMAIN_PP1: | |
1234 | msr = MSR_PP1_ENERGY_STATUS; | |
1235 | break; | |
1236 | case RAPL_DOMAIN_DRAM: | |
1237 | msr = MSR_DRAM_ENERGY_STATUS; | |
1238 | break; | |
3521ba1c SP |
1239 | case RAPL_DOMAIN_PLATFORM: |
1240 | /* PSYS(PLATFORM) is not a CPU domain, so avoid printng error */ | |
1241 | return -EINVAL; | |
2d281d81 JP |
1242 | default: |
1243 | pr_err("invalid domain id %d\n", domain); | |
1244 | return -EINVAL; | |
1245 | } | |
9d31c676 JP |
1246 | /* make sure domain counters are available and contains non-zero |
1247 | * values, otherwise skip it. | |
7b874772 | 1248 | */ |
9d31c676 JP |
1249 | if (rdmsrl_safe_on_cpu(cpu, msr, &val) || !val) |
1250 | return -ENODEV; | |
2d281d81 | 1251 | |
9d31c676 | 1252 | return 0; |
2d281d81 JP |
1253 | } |
1254 | ||
e1399ba2 JP |
1255 | |
1256 | /* | |
1257 | * Check if power limits are available. Two cases when they are not available: | |
1258 | * 1. Locked by BIOS, in this case we still provide read-only access so that | |
1259 | * users can see what limit is set by the BIOS. | |
1260 | * 2. Some CPUs make some domains monitoring only which means PLx MSRs may not | |
1261 | * exist at all. In this case, we do not show the contraints in powercap. | |
1262 | * | |
1263 | * Called after domains are detected and initialized. | |
1264 | */ | |
1265 | static void rapl_detect_powerlimit(struct rapl_domain *rd) | |
1266 | { | |
1267 | u64 val64; | |
1268 | int i; | |
1269 | ||
1270 | /* check if the domain is locked by BIOS, ignore if MSR doesn't exist */ | |
1271 | if (!rapl_read_data_raw(rd, FW_LOCK, false, &val64)) { | |
1272 | if (val64) { | |
9ea7612c ZR |
1273 | pr_info("RAPL %s domain %s locked by BIOS\n", |
1274 | rd->rp->name, rd->name); | |
e1399ba2 JP |
1275 | rd->state |= DOMAIN_STATE_BIOS_LOCKED; |
1276 | } | |
1277 | } | |
1278 | /* check if power limit MSRs exists, otherwise domain is monitoring only */ | |
1279 | for (i = 0; i < NR_POWER_LIMITS; i++) { | |
1280 | int prim = rd->rpl[i].prim_id; | |
1281 | if (rapl_read_data_raw(rd, prim, false, &val64)) | |
1282 | rd->rpl[i].name = NULL; | |
1283 | } | |
1284 | } | |
1285 | ||
2d281d81 JP |
1286 | /* Detect active and valid domains for the given CPU, caller must |
1287 | * ensure the CPU belongs to the targeted package and CPU hotlug is disabled. | |
1288 | */ | |
1289 | static int rapl_detect_domains(struct rapl_package *rp, int cpu) | |
1290 | { | |
2d281d81 | 1291 | struct rapl_domain *rd; |
58705069 | 1292 | int i; |
2d281d81 JP |
1293 | |
1294 | for (i = 0; i < RAPL_DOMAIN_MAX; i++) { | |
1295 | /* use physical package id to read counters */ | |
fcdf1797 | 1296 | if (!rapl_check_domain(cpu, i)) { |
2d281d81 | 1297 | rp->domain_map |= 1 << i; |
fcdf1797 JP |
1298 | pr_info("Found RAPL domain %s\n", rapl_domain_names[i]); |
1299 | } | |
2d281d81 JP |
1300 | } |
1301 | rp->nr_domains = bitmap_weight(&rp->domain_map, RAPL_DOMAIN_MAX); | |
1302 | if (!rp->nr_domains) { | |
9ea7612c | 1303 | pr_debug("no valid rapl domains found in %s\n", rp->name); |
58705069 | 1304 | return -ENODEV; |
2d281d81 | 1305 | } |
9ea7612c | 1306 | pr_debug("found %d domains on %s\n", rp->nr_domains, rp->name); |
2d281d81 JP |
1307 | |
1308 | rp->domains = kcalloc(rp->nr_domains + 1, sizeof(struct rapl_domain), | |
1309 | GFP_KERNEL); | |
58705069 TG |
1310 | if (!rp->domains) |
1311 | return -ENOMEM; | |
1312 | ||
2d281d81 JP |
1313 | rapl_init_domains(rp); |
1314 | ||
e1399ba2 JP |
1315 | for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) |
1316 | rapl_detect_powerlimit(rd); | |
1317 | ||
2d281d81 JP |
1318 | return 0; |
1319 | } | |
1320 | ||
1321 | /* called from CPU hotplug notifier, hotplug lock held */ | |
1322 | static void rapl_remove_package(struct rapl_package *rp) | |
1323 | { | |
1324 | struct rapl_domain *rd, *rd_package = NULL; | |
1325 | ||
58705069 TG |
1326 | package_power_limit_irq_restore(rp); |
1327 | ||
2d281d81 | 1328 | for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { |
58705069 TG |
1329 | rapl_write_data_raw(rd, PL1_ENABLE, 0); |
1330 | rapl_write_data_raw(rd, PL1_CLAMP, 0); | |
1331 | if (find_nr_power_limit(rd) > 1) { | |
1332 | rapl_write_data_raw(rd, PL2_ENABLE, 0); | |
1333 | rapl_write_data_raw(rd, PL2_CLAMP, 0); | |
1334 | } | |
2d281d81 JP |
1335 | if (rd->id == RAPL_DOMAIN_PACKAGE) { |
1336 | rd_package = rd; | |
1337 | continue; | |
1338 | } | |
9ea7612c ZR |
1339 | pr_debug("remove package, undo power limit on %s: %s\n", |
1340 | rp->name, rd->name); | |
7ebf8eff | 1341 | powercap_unregister_zone(rp->priv->control_type, &rd->power_zone); |
2d281d81 JP |
1342 | } |
1343 | /* do parent zone last */ | |
7ebf8eff | 1344 | powercap_unregister_zone(rp->priv->control_type, &rd_package->power_zone); |
2d281d81 JP |
1345 | list_del(&rp->plist); |
1346 | kfree(rp); | |
1347 | } | |
1348 | ||
1349 | /* called from CPU hotplug notifier, hotplug lock held */ | |
7ebf8eff | 1350 | static struct rapl_package *rapl_add_package(int cpu, struct rapl_if_priv *priv) |
2d281d81 | 1351 | { |
32fb480e | 1352 | int id = topology_logical_die_id(cpu); |
2d281d81 | 1353 | struct rapl_package *rp; |
9ea7612c | 1354 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
b4005e92 | 1355 | int ret; |
2d281d81 | 1356 | |
2d281d81 JP |
1357 | rp = kzalloc(sizeof(struct rapl_package), GFP_KERNEL); |
1358 | if (!rp) | |
b4005e92 | 1359 | return ERR_PTR(-ENOMEM); |
2d281d81 JP |
1360 | |
1361 | /* add the new package to the list */ | |
aadf7b38 | 1362 | rp->id = id; |
323ee64a | 1363 | rp->lead_cpu = cpu; |
7ebf8eff | 1364 | rp->priv = priv; |
323ee64a | 1365 | |
9ea7612c ZR |
1366 | if (topology_max_die_per_package() > 1) |
1367 | snprintf(rp->name, PACKAGE_DOMAIN_NAME_LENGTH, | |
1368 | "package-%d-die-%d", c->phys_proc_id, c->cpu_die_id); | |
1369 | else | |
1370 | snprintf(rp->name, PACKAGE_DOMAIN_NAME_LENGTH, "package-%d", | |
1371 | c->phys_proc_id); | |
1372 | ||
2d281d81 JP |
1373 | /* check if the package contains valid domains */ |
1374 | if (rapl_detect_domains(rp, cpu) || | |
3c2c0845 | 1375 | rapl_defaults->check_unit(rp, cpu)) { |
2d281d81 JP |
1376 | ret = -ENODEV; |
1377 | goto err_free_package; | |
1378 | } | |
a74f4367 TG |
1379 | ret = rapl_package_register_powercap(rp); |
1380 | if (!ret) { | |
2d281d81 JP |
1381 | INIT_LIST_HEAD(&rp->plist); |
1382 | list_add(&rp->plist, &rapl_packages); | |
b4005e92 | 1383 | return rp; |
2d281d81 JP |
1384 | } |
1385 | ||
1386 | err_free_package: | |
1387 | kfree(rp->domains); | |
1388 | kfree(rp); | |
b4005e92 | 1389 | return ERR_PTR(ret); |
2d281d81 JP |
1390 | } |
1391 | ||
1392 | /* Handles CPU hotplug on multi-socket systems. | |
1393 | * If a CPU goes online as the first CPU of the physical package | |
1394 | * we add the RAPL package to the system. Similarly, when the last | |
1395 | * CPU of the package is removed, we remove the RAPL package and its | |
1396 | * associated domains. Cooling devices are handled accordingly at | |
1397 | * per-domain level. | |
1398 | */ | |
5e4dc791 SAS |
1399 | static int rapl_cpu_online(unsigned int cpu) |
1400 | { | |
1401 | struct rapl_package *rp; | |
5e4dc791 | 1402 | |
7ebf8eff | 1403 | rp = rapl_find_package_domain(cpu, &rapl_msr_priv); |
b4005e92 | 1404 | if (!rp) { |
7ebf8eff | 1405 | rp = rapl_add_package(cpu, &rapl_msr_priv); |
b4005e92 TG |
1406 | if (IS_ERR(rp)) |
1407 | return PTR_ERR(rp); | |
58705069 | 1408 | } |
b4005e92 TG |
1409 | cpumask_set_cpu(cpu, &rp->cpumask); |
1410 | return 0; | |
5e4dc791 SAS |
1411 | } |
1412 | ||
1413 | static int rapl_cpu_down_prep(unsigned int cpu) | |
2d281d81 | 1414 | { |
2d281d81 | 1415 | struct rapl_package *rp; |
323ee64a | 1416 | int lead_cpu; |
2d281d81 | 1417 | |
7ebf8eff | 1418 | rp = rapl_find_package_domain(cpu, &rapl_msr_priv); |
5e4dc791 SAS |
1419 | if (!rp) |
1420 | return 0; | |
b4005e92 TG |
1421 | |
1422 | cpumask_clear_cpu(cpu, &rp->cpumask); | |
1423 | lead_cpu = cpumask_first(&rp->cpumask); | |
1424 | if (lead_cpu >= nr_cpu_ids) | |
5e4dc791 | 1425 | rapl_remove_package(rp); |
b4005e92 TG |
1426 | else if (rp->lead_cpu == cpu) |
1427 | rp->lead_cpu = lead_cpu; | |
5e4dc791 | 1428 | return 0; |
2d281d81 JP |
1429 | } |
1430 | ||
52b3672c ZH |
1431 | static void power_limit_state_save(void) |
1432 | { | |
1433 | struct rapl_package *rp; | |
1434 | struct rapl_domain *rd; | |
1435 | int nr_pl, ret, i; | |
1436 | ||
1437 | get_online_cpus(); | |
1438 | list_for_each_entry(rp, &rapl_packages, plist) { | |
1439 | if (!rp->power_zone) | |
1440 | continue; | |
1441 | rd = power_zone_to_rapl_domain(rp->power_zone); | |
1442 | nr_pl = find_nr_power_limit(rd); | |
1443 | for (i = 0; i < nr_pl; i++) { | |
1444 | switch (rd->rpl[i].prim_id) { | |
1445 | case PL1_ENABLE: | |
1446 | ret = rapl_read_data_raw(rd, | |
1447 | POWER_LIMIT1, | |
1448 | true, | |
1449 | &rd->rpl[i].last_power_limit); | |
1450 | if (ret) | |
1451 | rd->rpl[i].last_power_limit = 0; | |
1452 | break; | |
1453 | case PL2_ENABLE: | |
1454 | ret = rapl_read_data_raw(rd, | |
1455 | POWER_LIMIT2, | |
1456 | true, | |
1457 | &rd->rpl[i].last_power_limit); | |
1458 | if (ret) | |
1459 | rd->rpl[i].last_power_limit = 0; | |
1460 | break; | |
1461 | } | |
1462 | } | |
1463 | } | |
1464 | put_online_cpus(); | |
1465 | } | |
1466 | ||
1467 | static void power_limit_state_restore(void) | |
1468 | { | |
1469 | struct rapl_package *rp; | |
1470 | struct rapl_domain *rd; | |
1471 | int nr_pl, i; | |
1472 | ||
1473 | get_online_cpus(); | |
1474 | list_for_each_entry(rp, &rapl_packages, plist) { | |
1475 | if (!rp->power_zone) | |
1476 | continue; | |
1477 | rd = power_zone_to_rapl_domain(rp->power_zone); | |
1478 | nr_pl = find_nr_power_limit(rd); | |
1479 | for (i = 0; i < nr_pl; i++) { | |
1480 | switch (rd->rpl[i].prim_id) { | |
1481 | case PL1_ENABLE: | |
1482 | if (rd->rpl[i].last_power_limit) | |
1483 | rapl_write_data_raw(rd, | |
1484 | POWER_LIMIT1, | |
1485 | rd->rpl[i].last_power_limit); | |
1486 | break; | |
1487 | case PL2_ENABLE: | |
1488 | if (rd->rpl[i].last_power_limit) | |
1489 | rapl_write_data_raw(rd, | |
1490 | POWER_LIMIT2, | |
1491 | rd->rpl[i].last_power_limit); | |
1492 | break; | |
1493 | } | |
1494 | } | |
1495 | } | |
1496 | put_online_cpus(); | |
1497 | } | |
1498 | ||
1499 | static int rapl_pm_callback(struct notifier_block *nb, | |
1500 | unsigned long mode, void *_unused) | |
1501 | { | |
1502 | switch (mode) { | |
1503 | case PM_SUSPEND_PREPARE: | |
1504 | power_limit_state_save(); | |
1505 | break; | |
1506 | case PM_POST_SUSPEND: | |
1507 | power_limit_state_restore(); | |
1508 | break; | |
1509 | } | |
1510 | return NOTIFY_OK; | |
1511 | } | |
1512 | ||
1513 | static struct notifier_block rapl_pm_notifier = { | |
1514 | .notifier_call = rapl_pm_callback, | |
1515 | }; | |
1516 | ||
2d281d81 JP |
1517 | static int __init rapl_init(void) |
1518 | { | |
087e9cba | 1519 | const struct x86_cpu_id *id; |
58705069 | 1520 | int ret; |
2d281d81 | 1521 | |
087e9cba JP |
1522 | id = x86_match_cpu(rapl_ids); |
1523 | if (!id) { | |
2d281d81 JP |
1524 | pr_err("driver does not support CPU family %d model %d\n", |
1525 | boot_cpu_data.x86, boot_cpu_data.x86_model); | |
1526 | ||
1527 | return -ENODEV; | |
1528 | } | |
009f225e | 1529 | |
087e9cba JP |
1530 | rapl_defaults = (struct rapl_defaults *)id->driver_data; |
1531 | ||
58705069 | 1532 | ret = rapl_register_powercap(); |
2d281d81 | 1533 | if (ret) |
58705069 | 1534 | return ret; |
2d281d81 | 1535 | |
58705069 TG |
1536 | ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powercap/rapl:online", |
1537 | rapl_cpu_online, rapl_cpu_down_prep); | |
5e4dc791 SAS |
1538 | if (ret < 0) |
1539 | goto err_unreg; | |
7ebf8eff | 1540 | rapl_msr_priv.pcap_rapl_online = ret; |
58705069 TG |
1541 | |
1542 | /* Don't bail out if PSys is not supported */ | |
1543 | rapl_register_psys(); | |
52b3672c ZH |
1544 | |
1545 | ret = register_pm_notifier(&rapl_pm_notifier); | |
1546 | if (ret) | |
1547 | goto err_unreg_all; | |
1548 | ||
5e4dc791 SAS |
1549 | return 0; |
1550 | ||
52b3672c | 1551 | err_unreg_all: |
7ebf8eff | 1552 | cpuhp_remove_state(rapl_msr_priv.pcap_rapl_online); |
52b3672c | 1553 | |
5e4dc791 SAS |
1554 | err_unreg: |
1555 | rapl_unregister_powercap(); | |
2d281d81 JP |
1556 | return ret; |
1557 | } | |
1558 | ||
1559 | static void __exit rapl_exit(void) | |
1560 | { | |
52b3672c | 1561 | unregister_pm_notifier(&rapl_pm_notifier); |
7ebf8eff | 1562 | cpuhp_remove_state(rapl_msr_priv.pcap_rapl_online); |
2d281d81 | 1563 | rapl_unregister_powercap(); |
2d281d81 JP |
1564 | } |
1565 | ||
1566 | module_init(rapl_init); | |
1567 | module_exit(rapl_exit); | |
1568 | ||
1569 | MODULE_DESCRIPTION("Driver for Intel RAPL (Running Average Power Limit)"); | |
1570 | MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>"); | |
1571 | MODULE_LICENSE("GPL v2"); |