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powercap/rapl: reduce ipi calls
[mirror_ubuntu-bionic-kernel.git] / drivers / powercap / intel_rapl.c
CommitLineData
2d281d81
JP		 1/*
2 * Intel Running Average Power Limit (RAPL) Driver
3 * Copyright (c) 2013, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.
16 *
17 */
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/list.h>
23#include <linux/types.h>
24#include <linux/device.h>
25#include <linux/slab.h>
26#include <linux/log2.h>
27#include <linux/bitmap.h>
28#include <linux/delay.h>
29#include <linux/sysfs.h>
30#include <linux/cpu.h>
31#include <linux/powercap.h>
3c2c0845 32#include <asm/iosf_mbi.h>
2d281d81
JP		 33
34#include <asm/processor.h>
35#include <asm/cpu_device_id.h>
36
37/* bitmasks for RAPL MSRs, used by primitive access functions */
38#define ENERGY_STATUS_MASK 0xffffffff
39
40#define POWER_LIMIT1_MASK 0x7FFF
41#define POWER_LIMIT1_ENABLE BIT(15)
42#define POWER_LIMIT1_CLAMP BIT(16)
43
44#define POWER_LIMIT2_MASK (0x7FFFULL<<32)
45#define POWER_LIMIT2_ENABLE BIT_ULL(47)
46#define POWER_LIMIT2_CLAMP BIT_ULL(48)
47#define POWER_PACKAGE_LOCK BIT_ULL(63)
48#define POWER_PP_LOCK BIT(31)
49
50#define TIME_WINDOW1_MASK (0x7FULL<<17)
51#define TIME_WINDOW2_MASK (0x7FULL<<49)
52
53#define POWER_UNIT_OFFSET 0
54#define POWER_UNIT_MASK 0x0F
55
56#define ENERGY_UNIT_OFFSET 0x08
57#define ENERGY_UNIT_MASK 0x1F00
58
59#define TIME_UNIT_OFFSET 0x10
60#define TIME_UNIT_MASK 0xF0000
61
62#define POWER_INFO_MAX_MASK (0x7fffULL<<32)
63#define POWER_INFO_MIN_MASK (0x7fffULL<<16)
64#define POWER_INFO_MAX_TIME_WIN_MASK (0x3fULL<<48)
65#define POWER_INFO_THERMAL_SPEC_MASK 0x7fff
66
67#define PERF_STATUS_THROTTLE_TIME_MASK 0xffffffff
68#define PP_POLICY_MASK 0x1F
69
70/* Non HW constants */
71#define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */
72#define RAPL_PRIMITIVE_DUMMY BIT(2)
73
2d281d81
JP		 74#define TIME_WINDOW_MAX_MSEC 40000
75#define TIME_WINDOW_MIN_MSEC 250
d474a4d3 76#define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit */
2d281d81
JP		 77enum unit_type {
78 ARBITRARY_UNIT, /* no translation */
79 POWER_UNIT,
80 ENERGY_UNIT,
81 TIME_UNIT,
82};
83
84enum rapl_domain_type {
85 RAPL_DOMAIN_PACKAGE, /* entire package/socket */
86 RAPL_DOMAIN_PP0, /* core power plane */
87 RAPL_DOMAIN_PP1, /* graphics uncore */
88 RAPL_DOMAIN_DRAM,/* DRAM control_type */
89 RAPL_DOMAIN_MAX,
90};
91
92enum rapl_domain_msr_id {
93 RAPL_DOMAIN_MSR_LIMIT,
94 RAPL_DOMAIN_MSR_STATUS,
95 RAPL_DOMAIN_MSR_PERF,
96 RAPL_DOMAIN_MSR_POLICY,
97 RAPL_DOMAIN_MSR_INFO,
98 RAPL_DOMAIN_MSR_MAX,
99};
100
101/* per domain data, some are optional */
102enum rapl_primitives {
103 ENERGY_COUNTER,
104 POWER_LIMIT1,
105 POWER_LIMIT2,
106 FW_LOCK,
107
108 PL1_ENABLE, /* power limit 1, aka long term */
109 PL1_CLAMP, /* allow frequency to go below OS request */
110 PL2_ENABLE, /* power limit 2, aka short term, instantaneous */
111 PL2_CLAMP,
112
113 TIME_WINDOW1, /* long term */
114 TIME_WINDOW2, /* short term */
115 THERMAL_SPEC_POWER,
116 MAX_POWER,
117
118 MIN_POWER,
119 MAX_TIME_WINDOW,
120 THROTTLED_TIME,
121 PRIORITY_LEVEL,
122
123 /* below are not raw primitive data */
124 AVERAGE_POWER,
125 NR_RAPL_PRIMITIVES,
126};
127
128#define NR_RAW_PRIMITIVES (NR_RAPL_PRIMITIVES - 2)
129
130/* Can be expanded to include events, etc.*/
131struct rapl_domain_data {
132 u64 primitives[NR_RAPL_PRIMITIVES];
133 unsigned long timestamp;
134};
135
f14a1396
JP		 136struct msrl_action {
137 u32 msr_no;
138 u64 clear_mask;
139 u64 set_mask;
140 int err;
141};
2d281d81
JP		 142
143#define DOMAIN_STATE_INACTIVE BIT(0)
144#define DOMAIN_STATE_POWER_LIMIT_SET BIT(1)
145#define DOMAIN_STATE_BIOS_LOCKED BIT(2)
146
147#define NR_POWER_LIMITS (2)
148struct rapl_power_limit {
149 struct powercap_zone_constraint *constraint;
150 int prim_id; /* primitive ID used to enable */
151 struct rapl_domain *domain;
152 const char *name;
153};
154
155static const char pl1_name[] = "long_term";
156static const char pl2_name[] = "short_term";
157
158struct rapl_domain {
159 const char *name;
160 enum rapl_domain_type id;
161 int msrs[RAPL_DOMAIN_MSR_MAX];
162 struct powercap_zone power_zone;
163 struct rapl_domain_data rdd;
164 struct rapl_power_limit rpl[NR_POWER_LIMITS];
165 u64 attr_map; /* track capabilities */
166 unsigned int state;
d474a4d3 167 unsigned int domain_energy_unit;
2d281d81
JP		 168 int package_id;
169};
170#define power_zone_to_rapl_domain(_zone) \
171 container_of(_zone, struct rapl_domain, power_zone)
172
173
174/* Each physical package contains multiple domains, these are the common
175 * data across RAPL domains within a package.
176 */
177struct rapl_package {
178 unsigned int id; /* physical package/socket id */
179 unsigned int nr_domains;
180 unsigned long domain_map; /* bit map of active domains */
3c2c0845
JP		 181 unsigned int power_unit;
182 unsigned int energy_unit;
183 unsigned int time_unit;
2d281d81
JP		 184 struct rapl_domain *domains; /* array of domains, sized at runtime */
185 struct powercap_zone *power_zone; /* keep track of parent zone */
186 int nr_cpus; /* active cpus on the package, topology info is lost during
187 * cpu hotplug. so we have to track ourselves.
188 */
189 unsigned long power_limit_irq; /* keep track of package power limit
190 * notify interrupt enable status.
191 */
192 struct list_head plist;
193};
087e9cba
JP		 194
195struct rapl_defaults {
51b63409 196 u8 floor_freq_reg_addr;
087e9cba
JP		 197 int (*check_unit)(struct rapl_package *rp, int cpu);
198 void (*set_floor_freq)(struct rapl_domain *rd, bool mode);
199 u64 (*compute_time_window)(struct rapl_package *rp, u64 val,
200 bool to_raw);
d474a4d3 201 unsigned int dram_domain_energy_unit;
087e9cba
JP		 202};
203static struct rapl_defaults *rapl_defaults;
204
3c2c0845 205/* Sideband MBI registers */
51b63409
AT		 206#define IOSF_CPU_POWER_BUDGET_CTL_BYT (0x2)
207#define IOSF_CPU_POWER_BUDGET_CTL_TNG (0xdf)
3c2c0845 208
2d281d81
JP		 209#define PACKAGE_PLN_INT_SAVED BIT(0)
210#define MAX_PRIM_NAME (32)
211
212/* per domain data. used to describe individual knobs such that access function
213 * can be consolidated into one instead of many inline functions.
214 */
215struct rapl_primitive_info {
216 const char *name;
217 u64 mask;
218 int shift;
219 enum rapl_domain_msr_id id;
220 enum unit_type unit;
221 u32 flag;
222};
223
224#define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \
225 .name = #p, \
226 .mask = m, \
227 .shift = s, \
228 .id = i, \
229 .unit = u, \
230 .flag = f \
231 }
232
233static void rapl_init_domains(struct rapl_package *rp);
234static int rapl_read_data_raw(struct rapl_domain *rd,
235 enum rapl_primitives prim,
236 bool xlate, u64 *data);
237static int rapl_write_data_raw(struct rapl_domain *rd,
238 enum rapl_primitives prim,
239 unsigned long long value);
d474a4d3
JP		 240static u64 rapl_unit_xlate(struct rapl_domain *rd, int package,
241 enum unit_type type, u64 value,
2d281d81
JP		 242 int to_raw);
243static void package_power_limit_irq_save(int package_id);
244
245static LIST_HEAD(rapl_packages); /* guarded by CPU hotplug lock */
246
247static const char * const rapl_domain_names[] = {
248 "package",
249 "core",
250 "uncore",
251 "dram",
252};
253
254static struct powercap_control_type *control_type; /* PowerCap Controller */
255
256/* caller to ensure CPU hotplug lock is held */
257static struct rapl_package *find_package_by_id(int id)
258{
259 struct rapl_package *rp;
260
261 list_for_each_entry(rp, &rapl_packages, plist) {
262 if (rp->id == id)
263 return rp;
264 }
265
266 return NULL;
267}
268
269/* caller to ensure CPU hotplug lock is held */
270static int find_active_cpu_on_package(int package_id)
271{
272 int i;
273
274 for_each_online_cpu(i) {
275 if (topology_physical_package_id(i) == package_id)
276 return i;
277 }
278 /* all CPUs on this package are offline */
279
280 return -ENODEV;
281}
282
283/* caller must hold cpu hotplug lock */
284static void rapl_cleanup_data(void)
285{
286 struct rapl_package *p, *tmp;
287
288 list_for_each_entry_safe(p, tmp, &rapl_packages, plist) {
289 kfree(p->domains);
290 list_del(&p->plist);
291 kfree(p);
292 }
293}
294
295static int get_energy_counter(struct powercap_zone *power_zone, u64 *energy_raw)
296{
297 struct rapl_domain *rd;
298 u64 energy_now;
299
300 /* prevent CPU hotplug, make sure the RAPL domain does not go
301 * away while reading the counter.
302 */
303 get_online_cpus();
304 rd = power_zone_to_rapl_domain(power_zone);
305
306 if (!rapl_read_data_raw(rd, ENERGY_COUNTER, true, &energy_now)) {
307 *energy_raw = energy_now;
308 put_online_cpus();
309
310 return 0;
311 }
312 put_online_cpus();
313
314 return -EIO;
315}
316
317static int get_max_energy_counter(struct powercap_zone *pcd_dev, u64 *energy)
318{
d474a4d3
JP		 319 struct rapl_domain *rd = power_zone_to_rapl_domain(pcd_dev);
320
321 *energy = rapl_unit_xlate(rd, 0, ENERGY_UNIT, ENERGY_STATUS_MASK, 0);
2d281d81
JP		 322 return 0;
323}
324
325static int release_zone(struct powercap_zone *power_zone)
326{
327 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
328 struct rapl_package *rp;
329
330 /* package zone is the last zone of a package, we can free
331 * memory here since all children has been unregistered.
332 */
333 if (rd->id == RAPL_DOMAIN_PACKAGE) {
334 rp = find_package_by_id(rd->package_id);
335 if (!rp) {
336 dev_warn(&power_zone->dev, "no package id %s\n",
337 rd->name);
338 return -ENODEV;
339 }
340 kfree(rd);
341 rp->domains = NULL;
342 }
343
344 return 0;
345
346}
347
348static int find_nr_power_limit(struct rapl_domain *rd)
349{
350 int i;
351
352 for (i = 0; i < NR_POWER_LIMITS; i++) {
353 if (rd->rpl[i].name == NULL)
354 break;
355 }
356
357 return i;
358}
359
360static int set_domain_enable(struct powercap_zone *power_zone, bool mode)
361{
362 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
2d281d81
JP		 363
364 if (rd->state & DOMAIN_STATE_BIOS_LOCKED)
365 return -EACCES;
3c2c0845 366
2d281d81 367 get_online_cpus();
2d281d81 368 rapl_write_data_raw(rd, PL1_ENABLE, mode);
51b63409
AT		 369 if (rapl_defaults->set_floor_freq)
370 rapl_defaults->set_floor_freq(rd, mode);
2d281d81
JP		 371 put_online_cpus();
372
373 return 0;
374}
375
376static int get_domain_enable(struct powercap_zone *power_zone, bool *mode)
377{
378 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
379 u64 val;
380
381 if (rd->state & DOMAIN_STATE_BIOS_LOCKED) {
382 *mode = false;
383 return 0;
384 }
385 get_online_cpus();
386 if (rapl_read_data_raw(rd, PL1_ENABLE, true, &val)) {
387 put_online_cpus();
388 return -EIO;
389 }
390 *mode = val;
391 put_online_cpus();
392
393 return 0;
394}
395
396/* per RAPL domain ops, in the order of rapl_domain_type */
600c395b 397static const struct powercap_zone_ops zone_ops[] = {
2d281d81
JP		 398 /* RAPL_DOMAIN_PACKAGE */
399 {
400 .get_energy_uj = get_energy_counter,
401 .get_max_energy_range_uj = get_max_energy_counter,
402 .release = release_zone,
403 .set_enable = set_domain_enable,
404 .get_enable = get_domain_enable,
405 },
406 /* RAPL_DOMAIN_PP0 */
407 {
408 .get_energy_uj = get_energy_counter,
409 .get_max_energy_range_uj = get_max_energy_counter,
410 .release = release_zone,
411 .set_enable = set_domain_enable,
412 .get_enable = get_domain_enable,
413 },
414 /* RAPL_DOMAIN_PP1 */
415 {
416 .get_energy_uj = get_energy_counter,
417 .get_max_energy_range_uj = get_max_energy_counter,
418 .release = release_zone,
419 .set_enable = set_domain_enable,
420 .get_enable = get_domain_enable,
421 },
422 /* RAPL_DOMAIN_DRAM */
423 {
424 .get_energy_uj = get_energy_counter,
425 .get_max_energy_range_uj = get_max_energy_counter,
426 .release = release_zone,
427 .set_enable = set_domain_enable,
428 .get_enable = get_domain_enable,
429 },
430};
431
432static int set_power_limit(struct powercap_zone *power_zone, int id,
433 u64 power_limit)
434{
435 struct rapl_domain *rd;
436 struct rapl_package *rp;
437 int ret = 0;
438
439 get_online_cpus();
440 rd = power_zone_to_rapl_domain(power_zone);
441 rp = find_package_by_id(rd->package_id);
442 if (!rp) {
443 ret = -ENODEV;
444 goto set_exit;
445 }
446
447 if (rd->state & DOMAIN_STATE_BIOS_LOCKED) {
448 dev_warn(&power_zone->dev, "%s locked by BIOS, monitoring only\n",
449 rd->name);
450 ret = -EACCES;
451 goto set_exit;
452 }
453
454 switch (rd->rpl[id].prim_id) {
455 case PL1_ENABLE:
456 rapl_write_data_raw(rd, POWER_LIMIT1, power_limit);
457 break;
458 case PL2_ENABLE:
459 rapl_write_data_raw(rd, POWER_LIMIT2, power_limit);
460 break;
461 default:
462 ret = -EINVAL;
463 }
464 if (!ret)
465 package_power_limit_irq_save(rd->package_id);
466set_exit:
467 put_online_cpus();
468 return ret;
469}
470
471static int get_current_power_limit(struct powercap_zone *power_zone, int id,
472 u64 *data)
473{
474 struct rapl_domain *rd;
475 u64 val;
476 int prim;
477 int ret = 0;
478
479 get_online_cpus();
480 rd = power_zone_to_rapl_domain(power_zone);
481 switch (rd->rpl[id].prim_id) {
482 case PL1_ENABLE:
483 prim = POWER_LIMIT1;
484 break;
485 case PL2_ENABLE:
486 prim = POWER_LIMIT2;
487 break;
488 default:
489 put_online_cpus();
490 return -EINVAL;
491 }
492 if (rapl_read_data_raw(rd, prim, true, &val))
493 ret = -EIO;
494 else
495 *data = val;
496
497 put_online_cpus();
498
499 return ret;
500}
501
502static int set_time_window(struct powercap_zone *power_zone, int id,
503 u64 window)
504{
505 struct rapl_domain *rd;
506 int ret = 0;
507
508 get_online_cpus();
509 rd = power_zone_to_rapl_domain(power_zone);
510 switch (rd->rpl[id].prim_id) {
511 case PL1_ENABLE:
512 rapl_write_data_raw(rd, TIME_WINDOW1, window);
513 break;
514 case PL2_ENABLE:
515 rapl_write_data_raw(rd, TIME_WINDOW2, window);
516 break;
517 default:
518 ret = -EINVAL;
519 }
520 put_online_cpus();
521 return ret;
522}
523
524static int get_time_window(struct powercap_zone *power_zone, int id, u64 *data)
525{
526 struct rapl_domain *rd;
527 u64 val;
528 int ret = 0;
529
530 get_online_cpus();
531 rd = power_zone_to_rapl_domain(power_zone);
532 switch (rd->rpl[id].prim_id) {
533 case PL1_ENABLE:
534 ret = rapl_read_data_raw(rd, TIME_WINDOW1, true, &val);
535 break;
536 case PL2_ENABLE:
537 ret = rapl_read_data_raw(rd, TIME_WINDOW2, true, &val);
538 break;
539 default:
540 put_online_cpus();
541 return -EINVAL;
542 }
543 if (!ret)
544 *data = val;
545 put_online_cpus();
546
547 return ret;
548}
549
550static const char *get_constraint_name(struct powercap_zone *power_zone, int id)
551{
552 struct rapl_power_limit *rpl;
553 struct rapl_domain *rd;
554
555 rd = power_zone_to_rapl_domain(power_zone);
556 rpl = (struct rapl_power_limit *) &rd->rpl[id];
557
558 return rpl->name;
559}
560
561
562static int get_max_power(struct powercap_zone *power_zone, int id,
563 u64 *data)
564{
565 struct rapl_domain *rd;
566 u64 val;
567 int prim;
568 int ret = 0;
569
570 get_online_cpus();
571 rd = power_zone_to_rapl_domain(power_zone);
572 switch (rd->rpl[id].prim_id) {
573 case PL1_ENABLE:
574 prim = THERMAL_SPEC_POWER;
575 break;
576 case PL2_ENABLE:
577 prim = MAX_POWER;
578 break;
579 default:
580 put_online_cpus();
581 return -EINVAL;
582 }
583 if (rapl_read_data_raw(rd, prim, true, &val))
584 ret = -EIO;
585 else
586 *data = val;
587
588 put_online_cpus();
589
590 return ret;
591}
592
600c395b 593static const struct powercap_zone_constraint_ops constraint_ops = {
2d281d81
JP		 594 .set_power_limit_uw = set_power_limit,
595 .get_power_limit_uw = get_current_power_limit,
596 .set_time_window_us = set_time_window,
597 .get_time_window_us = get_time_window,
598 .get_max_power_uw = get_max_power,
599 .get_name = get_constraint_name,
600};
601
602/* called after domain detection and package level data are set */
603static void rapl_init_domains(struct rapl_package *rp)
604{
605 int i;
606 struct rapl_domain *rd = rp->domains;
607
608 for (i = 0; i < RAPL_DOMAIN_MAX; i++) {
609 unsigned int mask = rp->domain_map & (1 << i);
610 switch (mask) {
611 case BIT(RAPL_DOMAIN_PACKAGE):
612 rd->name = rapl_domain_names[RAPL_DOMAIN_PACKAGE];
613 rd->id = RAPL_DOMAIN_PACKAGE;
614 rd->msrs[0] = MSR_PKG_POWER_LIMIT;
615 rd->msrs[1] = MSR_PKG_ENERGY_STATUS;
616 rd->msrs[2] = MSR_PKG_PERF_STATUS;
617 rd->msrs[3] = 0;
618 rd->msrs[4] = MSR_PKG_POWER_INFO;
619 rd->rpl[0].prim_id = PL1_ENABLE;
620 rd->rpl[0].name = pl1_name;
621 rd->rpl[1].prim_id = PL2_ENABLE;
622 rd->rpl[1].name = pl2_name;
623 break;
624 case BIT(RAPL_DOMAIN_PP0):
625 rd->name = rapl_domain_names[RAPL_DOMAIN_PP0];
626 rd->id = RAPL_DOMAIN_PP0;
627 rd->msrs[0] = MSR_PP0_POWER_LIMIT;
628 rd->msrs[1] = MSR_PP0_ENERGY_STATUS;
629 rd->msrs[2] = 0;
630 rd->msrs[3] = MSR_PP0_POLICY;
631 rd->msrs[4] = 0;
632 rd->rpl[0].prim_id = PL1_ENABLE;
633 rd->rpl[0].name = pl1_name;
634 break;
635 case BIT(RAPL_DOMAIN_PP1):
636 rd->name = rapl_domain_names[RAPL_DOMAIN_PP1];
637 rd->id = RAPL_DOMAIN_PP1;
638 rd->msrs[0] = MSR_PP1_POWER_LIMIT;
639 rd->msrs[1] = MSR_PP1_ENERGY_STATUS;
640 rd->msrs[2] = 0;
641 rd->msrs[3] = MSR_PP1_POLICY;
642 rd->msrs[4] = 0;
643 rd->rpl[0].prim_id = PL1_ENABLE;
644 rd->rpl[0].name = pl1_name;
645 break;
646 case BIT(RAPL_DOMAIN_DRAM):
647 rd->name = rapl_domain_names[RAPL_DOMAIN_DRAM];
648 rd->id = RAPL_DOMAIN_DRAM;
649 rd->msrs[0] = MSR_DRAM_POWER_LIMIT;
650 rd->msrs[1] = MSR_DRAM_ENERGY_STATUS;
651 rd->msrs[2] = MSR_DRAM_PERF_STATUS;
652 rd->msrs[3] = 0;
653 rd->msrs[4] = MSR_DRAM_POWER_INFO;
654 rd->rpl[0].prim_id = PL1_ENABLE;
655 rd->rpl[0].name = pl1_name;
d474a4d3
JP		 656 rd->domain_energy_unit =
657 rapl_defaults->dram_domain_energy_unit;
658 if (rd->domain_energy_unit)
659 pr_info("DRAM domain energy unit %dpj\n",
660 rd->domain_energy_unit);
2d281d81
JP		 661 break;
662 }
663 if (mask) {
664 rd->package_id = rp->id;
665 rd++;
666 }
667 }
668}
669
d474a4d3
JP		 670static u64 rapl_unit_xlate(struct rapl_domain *rd, int package,
671 enum unit_type type, u64 value,
2d281d81
JP		 672 int to_raw)
673{
3c2c0845 674 u64 units = 1;
2d281d81 675 struct rapl_package *rp;
d474a4d3 676 u64 scale = 1;
2d281d81
JP		 677
678 rp = find_package_by_id(package);
679 if (!rp)
680 return value;
681
682 switch (type) {
683 case POWER_UNIT:
3c2c0845 684 units = rp->power_unit;
2d281d81
JP		 685 break;
686 case ENERGY_UNIT:
d474a4d3
JP		 687 scale = ENERGY_UNIT_SCALE;
688 /* per domain unit takes precedence */
689 if (rd && rd->domain_energy_unit)
690 units = rd->domain_energy_unit;
691 else
692 units = rp->energy_unit;
2d281d81
JP		 693 break;
694 case TIME_UNIT:
3c2c0845 695 return rapl_defaults->compute_time_window(rp, value, to_raw);
2d281d81
JP		 696 case ARBITRARY_UNIT:
697 default:
698 return value;
699 };
700
701 if (to_raw)
d474a4d3 702 return div64_u64(value, units) * scale;
3c2c0845
JP		 703
704 value *= units;
705
d474a4d3 706 return div64_u64(value, scale);
2d281d81
JP		 707}
708
709/* in the order of enum rapl_primitives */
710static struct rapl_primitive_info rpi[] = {
711 /* name, mask, shift, msr index, unit divisor */
712 PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0,
713 RAPL_DOMAIN_MSR_STATUS, ENERGY_UNIT, 0),
714 PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0,
715 RAPL_DOMAIN_MSR_LIMIT, POWER_UNIT, 0),
716 PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32,
717 RAPL_DOMAIN_MSR_LIMIT, POWER_UNIT, 0),
718 PRIMITIVE_INFO_INIT(FW_LOCK, POWER_PP_LOCK, 31,
719 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
720 PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15,
721 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
722 PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16,
723 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
724 PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47,
725 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
726 PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48,
727 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
728 PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17,
729 RAPL_DOMAIN_MSR_LIMIT, TIME_UNIT, 0),
730 PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49,
731 RAPL_DOMAIN_MSR_LIMIT, TIME_UNIT, 0),
732 PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, POWER_INFO_THERMAL_SPEC_MASK,
733 0, RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0),
734 PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32,
735 RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0),
736 PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16,
737 RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0),
738 PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, POWER_INFO_MAX_TIME_WIN_MASK, 48,
739 RAPL_DOMAIN_MSR_INFO, TIME_UNIT, 0),
740 PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK, 0,
741 RAPL_DOMAIN_MSR_PERF, TIME_UNIT, 0),
742 PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0,
743 RAPL_DOMAIN_MSR_POLICY, ARBITRARY_UNIT, 0),
744 /* non-hardware */
745 PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, POWER_UNIT,
746 RAPL_PRIMITIVE_DERIVED),
747 {NULL, 0, 0, 0},
748};
749
750/* Read primitive data based on its related struct rapl_primitive_info.
751 * if xlate flag is set, return translated data based on data units, i.e.
752 * time, energy, and power.
753 * RAPL MSRs are non-architectual and are laid out not consistently across
754 * domains. Here we use primitive info to allow writing consolidated access
755 * functions.
756 * For a given primitive, it is processed by MSR mask and shift. Unit conversion
757 * is pre-assigned based on RAPL unit MSRs read at init time.
758 * 63-------------------------- 31--------------------------- 0
759 * | xxxxx (mask) |
760 * | |<- shift ----------------|
761 * 63-------------------------- 31--------------------------- 0
762 */
763static int rapl_read_data_raw(struct rapl_domain *rd,
764 enum rapl_primitives prim,
765 bool xlate, u64 *data)
766{
767 u64 value, final;
768 u32 msr;
769 struct rapl_primitive_info *rp = &rpi[prim];
770 int cpu;
771
772 if (!rp->name || rp->flag & RAPL_PRIMITIVE_DUMMY)
773 return -EINVAL;
774
775 msr = rd->msrs[rp->id];
776 if (!msr)
777 return -EINVAL;
778 /* use physical package id to look up active cpus */
779 cpu = find_active_cpu_on_package(rd->package_id);
780 if (cpu < 0)
781 return cpu;
782
783 /* special-case package domain, which uses a different bit*/
784 if (prim == FW_LOCK && rd->id == RAPL_DOMAIN_PACKAGE) {
785 rp->mask = POWER_PACKAGE_LOCK;
786 rp->shift = 63;
787 }
788 /* non-hardware data are collected by the polling thread */
789 if (rp->flag & RAPL_PRIMITIVE_DERIVED) {
790 *data = rd->rdd.primitives[prim];
791 return 0;
792 }
793
794 if (rdmsrl_safe_on_cpu(cpu, msr, &value)) {
795 pr_debug("failed to read msr 0x%x on cpu %d\n", msr, cpu);
796 return -EIO;
797 }
798
799 final = value & rp->mask;
800 final = final >> rp->shift;
801 if (xlate)
d474a4d3 802 *data = rapl_unit_xlate(rd, rd->package_id, rp->unit, final, 0);
2d281d81
JP		 803 else
804 *data = final;
805
806 return 0;
807}
808
f14a1396
JP		 809
810static int msrl_update_safe(u32 msr_no, u64 clear_mask, u64 set_mask)
811{
812 int err;
813 u64 val;
814
815 err = rdmsrl_safe(msr_no, &val);
816 if (err)
817 goto out;
818
819 val &= ~clear_mask;
820 val |= set_mask;
821
822 err = wrmsrl_safe(msr_no, val);
823
824out:
825 return err;
826}
827
828static void msrl_update_func(void *info)
829{
830 struct msrl_action *ma = info;
831
832 ma->err = msrl_update_safe(ma->msr_no, ma->clear_mask, ma->set_mask);
833}
834
2d281d81
JP		 835/* Similar use of primitive info in the read counterpart */
836static int rapl_write_data_raw(struct rapl_domain *rd,
837 enum rapl_primitives prim,
838 unsigned long long value)
839{
2d281d81
JP		 840 struct rapl_primitive_info *rp = &rpi[prim];
841 int cpu;
f14a1396
JP		 842 u64 bits;
843 struct msrl_action ma;
844 int ret;
2d281d81
JP		 845
846 cpu = find_active_cpu_on_package(rd->package_id);
847 if (cpu < 0)
848 return cpu;
2d281d81 849
f14a1396
JP		 850 bits = rapl_unit_xlate(rd, rd->package_id, rp->unit, value, 1);
851 bits |= bits << rp->shift;
852 memset(&ma, 0, sizeof(ma));
853
854 ma.msr_no = rd->msrs[rp->id];
855 ma.clear_mask = rp->mask;
856 ma.set_mask = bits;
857
858 ret = smp_call_function_single(cpu, msrl_update_func, &ma, 1);
859 if (ret)
860 WARN_ON_ONCE(ret);
861 else
862 ret = ma.err;
863
864 return ret;
2d281d81
JP		 865}
866
3c2c0845
JP		 867/*
868 * Raw RAPL data stored in MSRs are in certain scales. We need to
869 * convert them into standard units based on the units reported in
870 * the RAPL unit MSRs. This is specific to CPUs as the method to
871 * calculate units differ on different CPUs.
872 * We convert the units to below format based on CPUs.
873 * i.e.
d474a4d3 874 * energy unit: picoJoules : Represented in picoJoules by default
3c2c0845
JP		 875 * power unit : microWatts : Represented in milliWatts by default
876 * time unit : microseconds: Represented in seconds by default
877 */
878static int rapl_check_unit_core(struct rapl_package *rp, int cpu)
2d281d81
JP		 879{
880 u64 msr_val;
881 u32 value;
882
883 if (rdmsrl_safe_on_cpu(cpu, MSR_RAPL_POWER_UNIT, &msr_val)) {
884 pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n",
885 MSR_RAPL_POWER_UNIT, cpu);
886 return -ENODEV;
887 }
888
2d281d81 889 value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
d474a4d3 890 rp->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << value);
2d281d81
JP		 891
892 value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
3c2c0845 893 rp->power_unit = 1000000 / (1 << value);
2d281d81
JP		 894
895 value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
3c2c0845 896 rp->time_unit = 1000000 / (1 << value);
2d281d81 897
d474a4d3 898 pr_debug("Core CPU package %d energy=%dpJ, time=%dus, power=%duW\n",
3c2c0845 899 rp->id, rp->energy_unit, rp->time_unit, rp->power_unit);
2d281d81
JP		 900
901 return 0;
902}
903
3c2c0845
JP		 904static int rapl_check_unit_atom(struct rapl_package *rp, int cpu)
905{
906 u64 msr_val;
907 u32 value;
908
909 if (rdmsrl_safe_on_cpu(cpu, MSR_RAPL_POWER_UNIT, &msr_val)) {
910 pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n",
911 MSR_RAPL_POWER_UNIT, cpu);
912 return -ENODEV;
913 }
914 value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
d474a4d3 915 rp->energy_unit = ENERGY_UNIT_SCALE * 1 << value;
3c2c0845
JP		 916
917 value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
918 rp->power_unit = (1 << value) * 1000;
919
920 value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
921 rp->time_unit = 1000000 / (1 << value);
922
d474a4d3 923 pr_debug("Atom package %d energy=%dpJ, time=%dus, power=%duW\n",
3c2c0845
JP		 924 rp->id, rp->energy_unit, rp->time_unit, rp->power_unit);
925
926 return 0;
927}
928
f14a1396
JP		 929static void power_limit_irq_save_cpu(void *info)
930{
931 u32 l, h = 0;
932 struct rapl_package *rp = (struct rapl_package *)info;
933
934 /* save the state of PLN irq mask bit before disabling it */
935 rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h);
936 if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED)) {
937 rp->power_limit_irq = l & PACKAGE_THERM_INT_PLN_ENABLE;
938 rp->power_limit_irq |= PACKAGE_PLN_INT_SAVED;
939 }
940 l &= ~PACKAGE_THERM_INT_PLN_ENABLE;
941 wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
942}
943
3c2c0845 944
2d281d81
JP		 945/* REVISIT:
946 * When package power limit is set artificially low by RAPL, LVT
947 * thermal interrupt for package power limit should be ignored
948 * since we are not really exceeding the real limit. The intention
949 * is to avoid excessive interrupts while we are trying to save power.
950 * A useful feature might be routing the package_power_limit interrupt
951 * to userspace via eventfd. once we have a usecase, this is simple
952 * to do by adding an atomic notifier.
953 */
954
955static void package_power_limit_irq_save(int package_id)
956{
2d281d81
JP		 957 int cpu;
958 struct rapl_package *rp;
959
960 rp = find_package_by_id(package_id);
961 if (!rp)
962 return;
963
964 if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN))
965 return;
966
967 cpu = find_active_cpu_on_package(package_id);
968 if (cpu < 0)
969 return;
f14a1396
JP		 970 if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN))
971 return;
972
973 smp_call_function_single(cpu, power_limit_irq_save_cpu, rp, 1);
974}
975
976static void power_limit_irq_restore_cpu(void *info)
977{
978 u32 l, h = 0;
979 struct rapl_package *rp = (struct rapl_package *)info;
980
981 rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h);
982
983 if (rp->power_limit_irq & PACKAGE_THERM_INT_PLN_ENABLE)
984 l |= PACKAGE_THERM_INT_PLN_ENABLE;
985 else
986 l &= ~PACKAGE_THERM_INT_PLN_ENABLE;
987
988 wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
2d281d81
JP		 989}
990
991/* restore per package power limit interrupt enable state */
992static void package_power_limit_irq_restore(int package_id)
993{
2d281d81
JP		 994 int cpu;
995 struct rapl_package *rp;
996
997 rp = find_package_by_id(package_id);
998 if (!rp)
999 return;
1000
1001 if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN))
1002 return;
1003
1004 cpu = find_active_cpu_on_package(package_id);
1005 if (cpu < 0)
1006 return;
1007
1008 /* irq enable state not saved, nothing to restore */
1009 if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED))
1010 return;
2d281d81 1011
f14a1396 1012 smp_call_function_single(cpu, power_limit_irq_restore_cpu, rp, 1);
2d281d81
JP		 1013}
1014
3c2c0845
JP		 1015static void set_floor_freq_default(struct rapl_domain *rd, bool mode)
1016{
1017 int nr_powerlimit = find_nr_power_limit(rd);
1018
1019 /* always enable clamp such that p-state can go below OS requested
1020 * range. power capping priority over guranteed frequency.
1021 */
1022 rapl_write_data_raw(rd, PL1_CLAMP, mode);
1023
1024 /* some domains have pl2 */
1025 if (nr_powerlimit > 1) {
1026 rapl_write_data_raw(rd, PL2_ENABLE, mode);
1027 rapl_write_data_raw(rd, PL2_CLAMP, mode);
1028 }
1029}
1030
1031static void set_floor_freq_atom(struct rapl_domain *rd, bool enable)
1032{
1033 static u32 power_ctrl_orig_val;
1034 u32 mdata;
1035
51b63409
AT		 1036 if (!rapl_defaults->floor_freq_reg_addr) {
1037 pr_err("Invalid floor frequency config register\n");
1038 return;
1039 }
1040
3c2c0845 1041 if (!power_ctrl_orig_val)
4077a387
AS		 1042 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_CR_READ,
1043 rapl_defaults->floor_freq_reg_addr,
1044 &power_ctrl_orig_val);
3c2c0845
JP		 1045 mdata = power_ctrl_orig_val;
1046 if (enable) {
1047 mdata &= ~(0x7f << 8);
1048 mdata |= 1 << 8;
1049 }
4077a387
AS		 1050 iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_CR_WRITE,
1051 rapl_defaults->floor_freq_reg_addr, mdata);
3c2c0845
JP		 1052}
1053
1054static u64 rapl_compute_time_window_core(struct rapl_package *rp, u64 value,
1055 bool to_raw)
1056{
1057 u64 f, y; /* fraction and exp. used for time unit */
1058
1059 /*
1060 * Special processing based on 2^Y*(1+F/4), refer
1061 * to Intel Software Developer's manual Vol.3B: CH 14.9.3.
1062 */
1063 if (!to_raw) {
1064 f = (value & 0x60) >> 5;
1065 y = value & 0x1f;
1066 value = (1 << y) * (4 + f) * rp->time_unit / 4;
1067 } else {
1068 do_div(value, rp->time_unit);
1069 y = ilog2(value);
1070 f = div64_u64(4 * (value - (1 << y)), 1 << y);
1071 value = (y & 0x1f) | ((f & 0x3) << 5);
1072 }
1073 return value;
1074}
1075
1076static u64 rapl_compute_time_window_atom(struct rapl_package *rp, u64 value,
1077 bool to_raw)
1078{
1079 /*
1080 * Atom time unit encoding is straight forward val * time_unit,
1081 * where time_unit is default to 1 sec. Never 0.
1082 */
1083 if (!to_raw)
1084 return (value) ? value *= rp->time_unit : rp->time_unit;
1085 else
1086 value = div64_u64(value, rp->time_unit);
1087
1088 return value;
1089}
1090
087e9cba 1091static const struct rapl_defaults rapl_defaults_core = {
51b63409 1092 .floor_freq_reg_addr = 0,
3c2c0845
JP		 1093 .check_unit = rapl_check_unit_core,
1094 .set_floor_freq = set_floor_freq_default,
1095 .compute_time_window = rapl_compute_time_window_core,
087e9cba
JP		 1096};
1097
d474a4d3
JP		 1098static const struct rapl_defaults rapl_defaults_hsw_server = {
1099 .check_unit = rapl_check_unit_core,
1100 .set_floor_freq = set_floor_freq_default,
1101 .compute_time_window = rapl_compute_time_window_core,
1102 .dram_domain_energy_unit = 15300,
1103};
1104
51b63409
AT		 1105static const struct rapl_defaults rapl_defaults_byt = {
1106 .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_BYT,
1107 .check_unit = rapl_check_unit_atom,
1108 .set_floor_freq = set_floor_freq_atom,
1109 .compute_time_window = rapl_compute_time_window_atom,
1110};
1111
1112static const struct rapl_defaults rapl_defaults_tng = {
1113 .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_TNG,
3c2c0845
JP		 1114 .check_unit = rapl_check_unit_atom,
1115 .set_floor_freq = set_floor_freq_atom,
1116 .compute_time_window = rapl_compute_time_window_atom,
087e9cba
JP		 1117};
1118
51b63409
AT		 1119static const struct rapl_defaults rapl_defaults_ann = {
1120 .floor_freq_reg_addr = 0,
1121 .check_unit = rapl_check_unit_atom,
1122 .set_floor_freq = NULL,
1123 .compute_time_window = rapl_compute_time_window_atom,
1124};
1125
1126static const struct rapl_defaults rapl_defaults_cht = {
1127 .floor_freq_reg_addr = 0,
1128 .check_unit = rapl_check_unit_atom,
1129 .set_floor_freq = NULL,
1130 .compute_time_window = rapl_compute_time_window_atom,
1131};
1132
087e9cba
JP		 1133#define RAPL_CPU(_model, _ops) { \
1134 .vendor = X86_VENDOR_INTEL, \
1135 .family = 6, \
1136 .model = _model, \
1137 .driver_data = (kernel_ulong_t)&_ops, \
1138 }
1139
ea85dbca 1140static const struct x86_cpu_id rapl_ids[] __initconst = {
087e9cba
JP		 1141 RAPL_CPU(0x2a, rapl_defaults_core),/* Sandy Bridge */
1142 RAPL_CPU(0x2d, rapl_defaults_core),/* Sandy Bridge EP */
51b63409 1143 RAPL_CPU(0x37, rapl_defaults_byt),/* Valleyview */
087e9cba
JP		 1144 RAPL_CPU(0x3a, rapl_defaults_core),/* Ivy Bridge */
1145 RAPL_CPU(0x3c, rapl_defaults_core),/* Haswell */
1146 RAPL_CPU(0x3d, rapl_defaults_core),/* Broadwell */
d474a4d3 1147 RAPL_CPU(0x3f, rapl_defaults_hsw_server),/* Haswell servers */
34dfa36c 1148 RAPL_CPU(0x4f, rapl_defaults_hsw_server),/* Broadwell servers */
087e9cba 1149 RAPL_CPU(0x45, rapl_defaults_core),/* Haswell ULT */
4e0bec9e 1150 RAPL_CPU(0x47, rapl_defaults_core),/* Broadwell-H */
5fa0fa4b 1151 RAPL_CPU(0x4E, rapl_defaults_core),/* Skylake */
51b63409
AT		 1152 RAPL_CPU(0x4C, rapl_defaults_cht),/* Braswell/Cherryview */
1153 RAPL_CPU(0x4A, rapl_defaults_tng),/* Tangier */
d72be771 1154 RAPL_CPU(0x56, rapl_defaults_core),/* Future Xeon */
51b63409 1155 RAPL_CPU(0x5A, rapl_defaults_ann),/* Annidale */
89e7b255 1156 RAPL_CPU(0X5C, rapl_defaults_core),/* Broxton */
2cac1f70 1157 RAPL_CPU(0x5E, rapl_defaults_core),/* Skylake-H/S */
6f066d4d 1158 RAPL_CPU(0x57, rapl_defaults_hsw_server),/* Knights Landing */
2d281d81
JP		 1159 {}
1160};
1161MODULE_DEVICE_TABLE(x86cpu, rapl_ids);
1162
1163/* read once for all raw primitive data for all packages, domains */
1164static void rapl_update_domain_data(void)
1165{
1166 int dmn, prim;
1167 u64 val;
1168 struct rapl_package *rp;
1169
1170 list_for_each_entry(rp, &rapl_packages, plist) {
1171 for (dmn = 0; dmn < rp->nr_domains; dmn++) {
1172 pr_debug("update package %d domain %s data\n", rp->id,
1173 rp->domains[dmn].name);
1174 /* exclude non-raw primitives */
1175 for (prim = 0; prim < NR_RAW_PRIMITIVES; prim++)
1176 if (!rapl_read_data_raw(&rp->domains[dmn], prim,
1177 rpi[prim].unit,
1178 &val))
1179 rp->domains[dmn].rdd.primitives[prim] =
1180 val;
1181 }
1182 }
1183
1184}
1185
1186static int rapl_unregister_powercap(void)
1187{
1188 struct rapl_package *rp;
1189 struct rapl_domain *rd, *rd_package = NULL;
1190
1191 /* unregister all active rapl packages from the powercap layer,
1192 * hotplug lock held
1193 */
1194 list_for_each_entry(rp, &rapl_packages, plist) {
1195 package_power_limit_irq_restore(rp->id);
1196
1197 for (rd = rp->domains; rd < rp->domains + rp->nr_domains;
1198 rd++) {
1199 pr_debug("remove package, undo power limit on %d: %s\n",
1200 rp->id, rd->name);
1201 rapl_write_data_raw(rd, PL1_ENABLE, 0);
2d281d81 1202 rapl_write_data_raw(rd, PL1_CLAMP, 0);
5021282c
SI		 1203 if (find_nr_power_limit(rd) > 1) {
1204 rapl_write_data_raw(rd, PL2_ENABLE, 0);
1205 rapl_write_data_raw(rd, PL2_CLAMP, 0);
1206 }
2d281d81
JP		 1207 if (rd->id == RAPL_DOMAIN_PACKAGE) {
1208 rd_package = rd;
1209 continue;
1210 }
1211 powercap_unregister_zone(control_type, &rd->power_zone);
1212 }
1213 /* do the package zone last */
1214 if (rd_package)
1215 powercap_unregister_zone(control_type,
1216 &rd_package->power_zone);
1217 }
1218 powercap_unregister_control_type(control_type);
1219
1220 return 0;
1221}
1222
1223static int rapl_package_register_powercap(struct rapl_package *rp)
1224{
1225 struct rapl_domain *rd;
1226 int ret = 0;
1227 char dev_name[17]; /* max domain name = 7 + 1 + 8 for int + 1 for null*/
1228 struct powercap_zone *power_zone = NULL;
1229 int nr_pl;
1230
1231 /* first we register package domain as the parent zone*/
1232 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1233 if (rd->id == RAPL_DOMAIN_PACKAGE) {
1234 nr_pl = find_nr_power_limit(rd);
1235 pr_debug("register socket %d package domain %s\n",
1236 rp->id, rd->name);
1237 memset(dev_name, 0, sizeof(dev_name));
1238 snprintf(dev_name, sizeof(dev_name), "%s-%d",
1239 rd->name, rp->id);
1240 power_zone = powercap_register_zone(&rd->power_zone,
1241 control_type,
1242 dev_name, NULL,
1243 &zone_ops[rd->id],
1244 nr_pl,
1245 &constraint_ops);
1246 if (IS_ERR(power_zone)) {
1247 pr_debug("failed to register package, %d\n",
1248 rp->id);
1249 ret = PTR_ERR(power_zone);
1250 goto exit_package;
1251 }
1252 /* track parent zone in per package/socket data */
1253 rp->power_zone = power_zone;
1254 /* done, only one package domain per socket */
1255 break;
1256 }
1257 }
1258 if (!power_zone) {
1259 pr_err("no package domain found, unknown topology!\n");
1260 ret = -ENODEV;
1261 goto exit_package;
1262 }
1263 /* now register domains as children of the socket/package*/
1264 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1265 if (rd->id == RAPL_DOMAIN_PACKAGE)
1266 continue;
1267 /* number of power limits per domain varies */
1268 nr_pl = find_nr_power_limit(rd);
1269 power_zone = powercap_register_zone(&rd->power_zone,
1270 control_type, rd->name,
1271 rp->power_zone,
1272 &zone_ops[rd->id], nr_pl,
1273 &constraint_ops);
1274
1275 if (IS_ERR(power_zone)) {
1276 pr_debug("failed to register power_zone, %d:%s:%s\n",
1277 rp->id, rd->name, dev_name);
1278 ret = PTR_ERR(power_zone);
1279 goto err_cleanup;
1280 }
1281 }
1282
1283exit_package:
1284 return ret;
1285err_cleanup:
1286 /* clean up previously initialized domains within the package if we
1287 * failed after the first domain setup.
1288 */
1289 while (--rd >= rp->domains) {
1290 pr_debug("unregister package %d domain %s\n", rp->id, rd->name);
1291 powercap_unregister_zone(control_type, &rd->power_zone);
1292 }
1293
1294 return ret;
1295}
1296
1297static int rapl_register_powercap(void)
1298{
1299 struct rapl_domain *rd;
1300 struct rapl_package *rp;
1301 int ret = 0;
1302
1303 control_type = powercap_register_control_type(NULL, "intel-rapl", NULL);
1304 if (IS_ERR(control_type)) {
1305 pr_debug("failed to register powercap control_type.\n");
1306 return PTR_ERR(control_type);
1307 }
1308 /* read the initial data */
1309 rapl_update_domain_data();
1310 list_for_each_entry(rp, &rapl_packages, plist)
1311 if (rapl_package_register_powercap(rp))
1312 goto err_cleanup_package;
1313 return ret;
1314
1315err_cleanup_package:
1316 /* clean up previously initialized packages */
1317 list_for_each_entry_continue_reverse(rp, &rapl_packages, plist) {
1318 for (rd = rp->domains; rd < rp->domains + rp->nr_domains;
1319 rd++) {
1320 pr_debug("unregister zone/package %d, %s domain\n",
1321 rp->id, rd->name);
1322 powercap_unregister_zone(control_type, &rd->power_zone);
1323 }
1324 }
1325
1326 return ret;
1327}
1328
1329static int rapl_check_domain(int cpu, int domain)
1330{
1331 unsigned msr;
9d31c676 1332 u64 val = 0;
2d281d81
JP		 1333
1334 switch (domain) {
1335 case RAPL_DOMAIN_PACKAGE:
1336 msr = MSR_PKG_ENERGY_STATUS;
1337 break;
1338 case RAPL_DOMAIN_PP0:
1339 msr = MSR_PP0_ENERGY_STATUS;
1340 break;
1341 case RAPL_DOMAIN_PP1:
1342 msr = MSR_PP1_ENERGY_STATUS;
1343 break;
1344 case RAPL_DOMAIN_DRAM:
1345 msr = MSR_DRAM_ENERGY_STATUS;
1346 break;
1347 default:
1348 pr_err("invalid domain id %d\n", domain);
1349 return -EINVAL;
1350 }
9d31c676
JP		 1351 /* make sure domain counters are available and contains non-zero
1352 * values, otherwise skip it.
7b874772 1353 */
9d31c676
JP		 1354 if (rdmsrl_safe_on_cpu(cpu, msr, &val) || !val)
1355 return -ENODEV;
2d281d81 1356
9d31c676 1357 return 0;
2d281d81
JP		 1358}
1359
1360/* Detect active and valid domains for the given CPU, caller must
1361 * ensure the CPU belongs to the targeted package and CPU hotlug is disabled.
1362 */
1363static int rapl_detect_domains(struct rapl_package *rp, int cpu)
1364{
1365 int i;
1366 int ret = 0;
1367 struct rapl_domain *rd;
1368 u64 locked;
1369
1370 for (i = 0; i < RAPL_DOMAIN_MAX; i++) {
1371 /* use physical package id to read counters */
fcdf1797 1372 if (!rapl_check_domain(cpu, i)) {
2d281d81 1373 rp->domain_map |= 1 << i;
fcdf1797
JP		 1374 pr_info("Found RAPL domain %s\n", rapl_domain_names[i]);
1375 }
2d281d81
JP		 1376 }
1377 rp->nr_domains = bitmap_weight(&rp->domain_map, RAPL_DOMAIN_MAX);
1378 if (!rp->nr_domains) {
1379 pr_err("no valid rapl domains found in package %d\n", rp->id);
1380 ret = -ENODEV;
1381 goto done;
1382 }
1383 pr_debug("found %d domains on package %d\n", rp->nr_domains, rp->id);
1384
1385 rp->domains = kcalloc(rp->nr_domains + 1, sizeof(struct rapl_domain),
1386 GFP_KERNEL);
1387 if (!rp->domains) {
1388 ret = -ENOMEM;
1389 goto done;
1390 }
1391 rapl_init_domains(rp);
1392
1393 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1394 /* check if the domain is locked by BIOS */
79a21dbf
PB		 1395 ret = rapl_read_data_raw(rd, FW_LOCK, false, &locked);
1396 if (ret)
1397 return ret;
1398 if (locked) {
2d281d81
JP		 1399 pr_info("RAPL package %d domain %s locked by BIOS\n",
1400 rp->id, rd->name);
79a21dbf 1401 rd->state |= DOMAIN_STATE_BIOS_LOCKED;
2d281d81
JP		 1402 }
1403 }
1404
1405
1406done:
1407 return ret;
1408}
1409
1410static bool is_package_new(int package)
1411{
1412 struct rapl_package *rp;
1413
1414 /* caller prevents cpu hotplug, there will be no new packages added
1415 * or deleted while traversing the package list, no need for locking.
1416 */
1417 list_for_each_entry(rp, &rapl_packages, plist)
1418 if (package == rp->id)
1419 return false;
1420
1421 return true;
1422}
1423
1424/* RAPL interface can be made of a two-level hierarchy: package level and domain
1425 * level. We first detect the number of packages then domains of each package.
1426 * We have to consider the possiblity of CPU online/offline due to hotplug and
1427 * other scenarios.
1428 */
1429static int rapl_detect_topology(void)
1430{
1431 int i;
1432 int phy_package_id;
1433 struct rapl_package *new_package, *rp;
1434
1435 for_each_online_cpu(i) {
1436 phy_package_id = topology_physical_package_id(i);
1437 if (is_package_new(phy_package_id)) {
1438 new_package = kzalloc(sizeof(*rp), GFP_KERNEL);
1439 if (!new_package) {
1440 rapl_cleanup_data();
1441 return -ENOMEM;
1442 }
1443 /* add the new package to the list */
1444 new_package->id = phy_package_id;
1445 new_package->nr_cpus = 1;
1446
1447 /* check if the package contains valid domains */
1448 if (rapl_detect_domains(new_package, i) ||
3c2c0845 1449 rapl_defaults->check_unit(new_package, i)) {
2d281d81
JP		 1450 kfree(new_package->domains);
1451 kfree(new_package);
1452 /* free up the packages already initialized */
1453 rapl_cleanup_data();
1454 return -ENODEV;
1455 }
1456 INIT_LIST_HEAD(&new_package->plist);
1457 list_add(&new_package->plist, &rapl_packages);
1458 } else {
1459 rp = find_package_by_id(phy_package_id);
1460 if (rp)
1461 ++rp->nr_cpus;
1462 }
1463 }
1464
1465 return 0;
1466}
1467
1468/* called from CPU hotplug notifier, hotplug lock held */
1469static void rapl_remove_package(struct rapl_package *rp)
1470{
1471 struct rapl_domain *rd, *rd_package = NULL;
1472
1473 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1474 if (rd->id == RAPL_DOMAIN_PACKAGE) {
1475 rd_package = rd;
1476 continue;
1477 }
1478 pr_debug("remove package %d, %s domain\n", rp->id, rd->name);
1479 powercap_unregister_zone(control_type, &rd->power_zone);
1480 }
1481 /* do parent zone last */
1482 powercap_unregister_zone(control_type, &rd_package->power_zone);
1483 list_del(&rp->plist);
1484 kfree(rp);
1485}
1486
1487/* called from CPU hotplug notifier, hotplug lock held */
1488static int rapl_add_package(int cpu)
1489{
1490 int ret = 0;
1491 int phy_package_id;
1492 struct rapl_package *rp;
1493
1494 phy_package_id = topology_physical_package_id(cpu);
1495 rp = kzalloc(sizeof(struct rapl_package), GFP_KERNEL);
1496 if (!rp)
1497 return -ENOMEM;
1498
1499 /* add the new package to the list */
1500 rp->id = phy_package_id;
1501 rp->nr_cpus = 1;
1502 /* check if the package contains valid domains */
1503 if (rapl_detect_domains(rp, cpu) ||
3c2c0845 1504 rapl_defaults->check_unit(rp, cpu)) {
2d281d81
JP		 1505 ret = -ENODEV;
1506 goto err_free_package;
1507 }
1508 if (!rapl_package_register_powercap(rp)) {
1509 INIT_LIST_HEAD(&rp->plist);
1510 list_add(&rp->plist, &rapl_packages);
1511 return ret;
1512 }
1513
1514err_free_package:
1515 kfree(rp->domains);
1516 kfree(rp);
1517
1518 return ret;
1519}
1520
1521/* Handles CPU hotplug on multi-socket systems.
1522 * If a CPU goes online as the first CPU of the physical package
1523 * we add the RAPL package to the system. Similarly, when the last
1524 * CPU of the package is removed, we remove the RAPL package and its
1525 * associated domains. Cooling devices are handled accordingly at
1526 * per-domain level.
1527 */
1528static int rapl_cpu_callback(struct notifier_block *nfb,
1529 unsigned long action, void *hcpu)
1530{
1531 unsigned long cpu = (unsigned long)hcpu;
1532 int phy_package_id;
1533 struct rapl_package *rp;
1534
1535 phy_package_id = topology_physical_package_id(cpu);
1536 switch (action) {
1537 case CPU_ONLINE:
1538 case CPU_ONLINE_FROZEN:
1539 case CPU_DOWN_FAILED:
1540 case CPU_DOWN_FAILED_FROZEN:
1541 rp = find_package_by_id(phy_package_id);
1542 if (rp)
1543 ++rp->nr_cpus;
1544 else
1545 rapl_add_package(cpu);
1546 break;
1547 case CPU_DOWN_PREPARE:
1548 case CPU_DOWN_PREPARE_FROZEN:
1549 rp = find_package_by_id(phy_package_id);
1550 if (!rp)
1551 break;
1552 if (--rp->nr_cpus == 0)
1553 rapl_remove_package(rp);
1554 }
1555
1556 return NOTIFY_OK;
1557}
1558
1559static struct notifier_block rapl_cpu_notifier = {
1560 .notifier_call = rapl_cpu_callback,
1561};
1562
1563static int __init rapl_init(void)
1564{
1565 int ret = 0;
087e9cba 1566 const struct x86_cpu_id *id;
2d281d81 1567
087e9cba
JP		 1568 id = x86_match_cpu(rapl_ids);
1569 if (!id) {
2d281d81
JP		 1570 pr_err("driver does not support CPU family %d model %d\n",
1571 boot_cpu_data.x86, boot_cpu_data.x86_model);
1572
1573 return -ENODEV;
1574 }
009f225e 1575
087e9cba
JP		 1576 rapl_defaults = (struct rapl_defaults *)id->driver_data;
1577
009f225e
SB		 1578 cpu_notifier_register_begin();
1579
2d281d81
JP		 1580 /* prevent CPU hotplug during detection */
1581 get_online_cpus();
1582 ret = rapl_detect_topology();
1583 if (ret)
1584 goto done;
1585
1586 if (rapl_register_powercap()) {
1587 rapl_cleanup_data();
1588 ret = -ENODEV;
1589 goto done;
1590 }
009f225e 1591 __register_hotcpu_notifier(&rapl_cpu_notifier);
2d281d81
JP		 1592done:
1593 put_online_cpus();
009f225e 1594 cpu_notifier_register_done();
2d281d81
JP		 1595
1596 return ret;
1597}
1598
1599static void __exit rapl_exit(void)
1600{
009f225e 1601 cpu_notifier_register_begin();
2d281d81 1602 get_online_cpus();
009f225e 1603 __unregister_hotcpu_notifier(&rapl_cpu_notifier);
2d281d81
JP		 1604 rapl_unregister_powercap();
1605 rapl_cleanup_data();
1606 put_online_cpus();
009f225e 1607 cpu_notifier_register_done();
2d281d81
JP		 1608}
1609
1610module_init(rapl_init);
1611module_exit(rapl_exit);
1612
1613MODULE_DESCRIPTION("Driver for Intel RAPL (Running Average Power Limit)");
1614MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>");
1615MODULE_LICENSE("GPL v2");
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