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3a6ba7dc VC |
1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2 | /* idt8a340_reg.h | |
3 | * | |
4 | * Originally generated by regen.tcl on Thu Feb 14 19:23:44 PST 2019 | |
5 | * https://github.com/richardcochran/regen | |
6 | * | |
7 | * Hand modified to include some HW registers. | |
8 | * Based on 4.8.0, SCSR rev C commit a03c7ae5 | |
9 | */ | |
10 | #ifndef HAVE_IDT8A340_REG | |
11 | #define HAVE_IDT8A340_REG | |
12 | ||
13 | #define PAGE_ADDR_BASE 0x0000 | |
14 | #define PAGE_ADDR 0x00fc | |
15 | ||
16 | #define HW_REVISION 0x8180 | |
17 | #define REV_ID 0x007a | |
18 | ||
19 | #define HW_DPLL_0 (0x8a00) | |
20 | #define HW_DPLL_1 (0x8b00) | |
21 | #define HW_DPLL_2 (0x8c00) | |
22 | #define HW_DPLL_3 (0x8d00) | |
7ea5fda2 ML |
23 | #define HW_DPLL_4 (0x8e00) |
24 | #define HW_DPLL_5 (0x8f00) | |
25 | #define HW_DPLL_6 (0x9000) | |
26 | #define HW_DPLL_7 (0x9100) | |
3a6ba7dc VC |
27 | |
28 | #define HW_DPLL_TOD_SW_TRIG_ADDR__0 (0x080) | |
29 | #define HW_DPLL_TOD_CTRL_1 (0x089) | |
30 | #define HW_DPLL_TOD_CTRL_2 (0x08A) | |
31 | #define HW_DPLL_TOD_OVR__0 (0x098) | |
32 | #define HW_DPLL_TOD_OUT_0__0 (0x0B0) | |
33 | ||
34 | #define HW_Q0_Q1_CH_SYNC_CTRL_0 (0xa740) | |
35 | #define HW_Q0_Q1_CH_SYNC_CTRL_1 (0xa741) | |
36 | #define HW_Q2_Q3_CH_SYNC_CTRL_0 (0xa742) | |
37 | #define HW_Q2_Q3_CH_SYNC_CTRL_1 (0xa743) | |
38 | #define HW_Q4_Q5_CH_SYNC_CTRL_0 (0xa744) | |
39 | #define HW_Q4_Q5_CH_SYNC_CTRL_1 (0xa745) | |
40 | #define HW_Q6_Q7_CH_SYNC_CTRL_0 (0xa746) | |
41 | #define HW_Q6_Q7_CH_SYNC_CTRL_1 (0xa747) | |
42 | #define HW_Q8_CH_SYNC_CTRL_0 (0xa748) | |
43 | #define HW_Q8_CH_SYNC_CTRL_1 (0xa749) | |
44 | #define HW_Q9_CH_SYNC_CTRL_0 (0xa74a) | |
45 | #define HW_Q9_CH_SYNC_CTRL_1 (0xa74b) | |
46 | #define HW_Q10_CH_SYNC_CTRL_0 (0xa74c) | |
47 | #define HW_Q10_CH_SYNC_CTRL_1 (0xa74d) | |
48 | #define HW_Q11_CH_SYNC_CTRL_0 (0xa74e) | |
49 | #define HW_Q11_CH_SYNC_CTRL_1 (0xa74f) | |
50 | ||
51 | #define SYNC_SOURCE_DPLL0_TOD_PPS 0x14 | |
52 | #define SYNC_SOURCE_DPLL1_TOD_PPS 0x15 | |
53 | #define SYNC_SOURCE_DPLL2_TOD_PPS 0x16 | |
54 | #define SYNC_SOURCE_DPLL3_TOD_PPS 0x17 | |
55 | ||
56 | #define SYNCTRL1_MASTER_SYNC_RST BIT(7) | |
57 | #define SYNCTRL1_MASTER_SYNC_TRIG BIT(5) | |
58 | #define SYNCTRL1_TOD_SYNC_TRIG BIT(4) | |
59 | #define SYNCTRL1_FBDIV_FRAME_SYNC_TRIG BIT(3) | |
60 | #define SYNCTRL1_FBDIV_SYNC_TRIG BIT(2) | |
61 | #define SYNCTRL1_Q1_DIV_SYNC_TRIG BIT(1) | |
62 | #define SYNCTRL1_Q0_DIV_SYNC_TRIG BIT(0) | |
63 | ||
7ea5fda2 ML |
64 | #define HW_Q8_CTRL_SPARE (0xa7d4) |
65 | #define HW_Q11_CTRL_SPARE (0xa7ec) | |
66 | ||
67 | /** | |
68 | * Select FOD5 as sync_trigger for Q8 divider. | |
69 | * Transition from logic zero to one | |
70 | * sets trigger to sync Q8 divider. | |
71 | * | |
72 | * Unused when FOD4 is driving Q8 divider (normal operation). | |
73 | */ | |
74 | #define Q9_TO_Q8_SYNC_TRIG BIT(1) | |
75 | ||
76 | /** | |
77 | * Enable FOD5 as driver for clock and sync for Q8 divider. | |
78 | * Enable fanout buffer for FOD5. | |
79 | * | |
80 | * Unused when FOD4 is driving Q8 divider (normal operation). | |
81 | */ | |
82 | #define Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK (BIT(0) | BIT(2)) | |
83 | ||
84 | /** | |
85 | * Select FOD6 as sync_trigger for Q11 divider. | |
86 | * Transition from logic zero to one | |
87 | * sets trigger to sync Q11 divider. | |
88 | * | |
89 | * Unused when FOD7 is driving Q11 divider (normal operation). | |
90 | */ | |
91 | #define Q10_TO_Q11_SYNC_TRIG BIT(1) | |
92 | ||
93 | /** | |
94 | * Enable FOD6 as driver for clock and sync for Q11 divider. | |
95 | * Enable fanout buffer for FOD6. | |
96 | * | |
97 | * Unused when FOD7 is driving Q11 divider (normal operation). | |
98 | */ | |
99 | #define Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK (BIT(0) | BIT(2)) | |
100 | ||
3a6ba7dc VC |
101 | #define RESET_CTRL 0xc000 |
102 | #define SM_RESET 0x0012 | |
103 | #define SM_RESET_CMD 0x5A | |
104 | ||
105 | #define GENERAL_STATUS 0xc014 | |
106 | #define HW_REV_ID 0x000A | |
107 | #define BOND_ID 0x000B | |
108 | #define HW_CSR_ID 0x000C | |
109 | #define HW_IRQ_ID 0x000E | |
110 | ||
111 | #define MAJ_REL 0x0010 | |
112 | #define MIN_REL 0x0011 | |
113 | #define HOTFIX_REL 0x0012 | |
114 | ||
115 | #define PIPELINE_ID 0x0014 | |
116 | #define BUILD_ID 0x0018 | |
117 | ||
118 | #define JTAG_DEVICE_ID 0x001c | |
119 | #define PRODUCT_ID 0x001e | |
120 | ||
1ece2fbe VC |
121 | #define OTP_SCSR_CONFIG_SELECT 0x0022 |
122 | ||
3a6ba7dc VC |
123 | #define STATUS 0xc03c |
124 | #define USER_GPIO0_TO_7_STATUS 0x008a | |
125 | #define USER_GPIO8_TO_15_STATUS 0x008b | |
126 | ||
127 | #define GPIO_USER_CONTROL 0xc160 | |
128 | #define GPIO0_TO_7_OUT 0x0000 | |
129 | #define GPIO8_TO_15_OUT 0x0001 | |
130 | ||
131 | #define STICKY_STATUS_CLEAR 0xc164 | |
132 | ||
133 | #define GPIO_TOD_NOTIFICATION_CLEAR 0xc16c | |
134 | ||
135 | #define ALERT_CFG 0xc188 | |
136 | ||
137 | #define SYS_DPLL_XO 0xc194 | |
138 | ||
139 | #define SYS_APLL 0xc19c | |
140 | ||
141 | #define INPUT_0 0xc1b0 | |
142 | ||
143 | #define INPUT_1 0xc1c0 | |
144 | ||
145 | #define INPUT_2 0xc1d0 | |
146 | ||
147 | #define INPUT_3 0xc200 | |
148 | ||
149 | #define INPUT_4 0xc210 | |
150 | ||
151 | #define INPUT_5 0xc220 | |
152 | ||
153 | #define INPUT_6 0xc230 | |
154 | ||
155 | #define INPUT_7 0xc240 | |
156 | ||
157 | #define INPUT_8 0xc250 | |
158 | ||
159 | #define INPUT_9 0xc260 | |
160 | ||
161 | #define INPUT_10 0xc280 | |
162 | ||
163 | #define INPUT_11 0xc290 | |
164 | ||
165 | #define INPUT_12 0xc2a0 | |
166 | ||
167 | #define INPUT_13 0xc2b0 | |
168 | ||
169 | #define INPUT_14 0xc2c0 | |
170 | ||
171 | #define INPUT_15 0xc2d0 | |
172 | ||
173 | #define REF_MON_0 0xc2e0 | |
174 | ||
175 | #define REF_MON_1 0xc2ec | |
176 | ||
177 | #define REF_MON_2 0xc300 | |
178 | ||
179 | #define REF_MON_3 0xc30c | |
180 | ||
181 | #define REF_MON_4 0xc318 | |
182 | ||
183 | #define REF_MON_5 0xc324 | |
184 | ||
185 | #define REF_MON_6 0xc330 | |
186 | ||
187 | #define REF_MON_7 0xc33c | |
188 | ||
189 | #define REF_MON_8 0xc348 | |
190 | ||
191 | #define REF_MON_9 0xc354 | |
192 | ||
193 | #define REF_MON_10 0xc360 | |
194 | ||
195 | #define REF_MON_11 0xc36c | |
196 | ||
197 | #define REF_MON_12 0xc380 | |
198 | ||
199 | #define REF_MON_13 0xc38c | |
200 | ||
201 | #define REF_MON_14 0xc398 | |
202 | ||
203 | #define REF_MON_15 0xc3a4 | |
204 | ||
205 | #define DPLL_0 0xc3b0 | |
206 | #define DPLL_CTRL_REG_0 0x0002 | |
207 | #define DPLL_CTRL_REG_1 0x0003 | |
208 | #define DPLL_CTRL_REG_2 0x0004 | |
209 | #define DPLL_TOD_SYNC_CFG 0x0031 | |
210 | #define DPLL_COMBO_SLAVE_CFG_0 0x0032 | |
211 | #define DPLL_COMBO_SLAVE_CFG_1 0x0033 | |
212 | #define DPLL_SLAVE_REF_CFG 0x0034 | |
213 | #define DPLL_REF_MODE 0x0035 | |
214 | #define DPLL_PHASE_MEASUREMENT_CFG 0x0036 | |
215 | #define DPLL_MODE 0x0037 | |
216 | ||
217 | #define DPLL_1 0xc400 | |
218 | ||
219 | #define DPLL_2 0xc438 | |
220 | ||
221 | #define DPLL_3 0xc480 | |
222 | ||
223 | #define DPLL_4 0xc4b8 | |
224 | ||
225 | #define DPLL_5 0xc500 | |
226 | ||
227 | #define DPLL_6 0xc538 | |
228 | ||
229 | #define DPLL_7 0xc580 | |
230 | ||
231 | #define SYS_DPLL 0xc5b8 | |
232 | ||
233 | #define DPLL_CTRL_0 0xc600 | |
234 | #define DPLL_CTRL_DPLL_MANU_REF_CFG 0x0001 | |
7ea5fda2 | 235 | #define DPLL_CTRL_COMBO_MASTER_CFG 0x003a |
3a6ba7dc VC |
236 | |
237 | #define DPLL_CTRL_1 0xc63c | |
238 | ||
239 | #define DPLL_CTRL_2 0xc680 | |
240 | ||
241 | #define DPLL_CTRL_3 0xc6bc | |
242 | ||
243 | #define DPLL_CTRL_4 0xc700 | |
244 | ||
245 | #define DPLL_CTRL_5 0xc73c | |
246 | ||
247 | #define DPLL_CTRL_6 0xc780 | |
248 | ||
249 | #define DPLL_CTRL_7 0xc7bc | |
250 | ||
251 | #define SYS_DPLL_CTRL 0xc800 | |
252 | ||
253 | #define DPLL_PHASE_0 0xc818 | |
254 | ||
255 | /* Signed 42-bit FFO in units of 2^(-53) */ | |
256 | #define DPLL_WR_PHASE 0x0000 | |
257 | ||
258 | #define DPLL_PHASE_1 0xc81c | |
259 | ||
260 | #define DPLL_PHASE_2 0xc820 | |
261 | ||
262 | #define DPLL_PHASE_3 0xc824 | |
263 | ||
264 | #define DPLL_PHASE_4 0xc828 | |
265 | ||
266 | #define DPLL_PHASE_5 0xc82c | |
267 | ||
268 | #define DPLL_PHASE_6 0xc830 | |
269 | ||
270 | #define DPLL_PHASE_7 0xc834 | |
271 | ||
272 | #define DPLL_FREQ_0 0xc838 | |
273 | ||
274 | /* Signed 42-bit FFO in units of 2^(-53) */ | |
275 | #define DPLL_WR_FREQ 0x0000 | |
276 | ||
277 | #define DPLL_FREQ_1 0xc840 | |
278 | ||
279 | #define DPLL_FREQ_2 0xc848 | |
280 | ||
281 | #define DPLL_FREQ_3 0xc850 | |
282 | ||
283 | #define DPLL_FREQ_4 0xc858 | |
284 | ||
285 | #define DPLL_FREQ_5 0xc860 | |
286 | ||
287 | #define DPLL_FREQ_6 0xc868 | |
288 | ||
289 | #define DPLL_FREQ_7 0xc870 | |
290 | ||
291 | #define DPLL_PHASE_PULL_IN_0 0xc880 | |
292 | #define PULL_IN_OFFSET 0x0000 /* Signed 32 bit */ | |
293 | #define PULL_IN_SLOPE_LIMIT 0x0004 /* Unsigned 24 bit */ | |
294 | #define PULL_IN_CTRL 0x0007 | |
295 | ||
296 | #define DPLL_PHASE_PULL_IN_1 0xc888 | |
297 | ||
298 | #define DPLL_PHASE_PULL_IN_2 0xc890 | |
299 | ||
300 | #define DPLL_PHASE_PULL_IN_3 0xc898 | |
301 | ||
302 | #define DPLL_PHASE_PULL_IN_4 0xc8a0 | |
303 | ||
304 | #define DPLL_PHASE_PULL_IN_5 0xc8a8 | |
305 | ||
306 | #define DPLL_PHASE_PULL_IN_6 0xc8b0 | |
307 | ||
308 | #define DPLL_PHASE_PULL_IN_7 0xc8b8 | |
309 | ||
310 | #define GPIO_CFG 0xc8c0 | |
311 | #define GPIO_CFG_GBL 0x0000 | |
312 | ||
313 | #define GPIO_0 0xc8c2 | |
314 | #define GPIO_DCO_INC_DEC 0x0000 | |
315 | #define GPIO_OUT_CTRL_0 0x0001 | |
316 | #define GPIO_OUT_CTRL_1 0x0002 | |
317 | #define GPIO_TOD_TRIG 0x0003 | |
318 | #define GPIO_DPLL_INDICATOR 0x0004 | |
319 | #define GPIO_LOS_INDICATOR 0x0005 | |
320 | #define GPIO_REF_INPUT_DSQ_0 0x0006 | |
321 | #define GPIO_REF_INPUT_DSQ_1 0x0007 | |
322 | #define GPIO_REF_INPUT_DSQ_2 0x0008 | |
323 | #define GPIO_REF_INPUT_DSQ_3 0x0009 | |
324 | #define GPIO_MAN_CLK_SEL_0 0x000a | |
325 | #define GPIO_MAN_CLK_SEL_1 0x000b | |
326 | #define GPIO_MAN_CLK_SEL_2 0x000c | |
327 | #define GPIO_SLAVE 0x000d | |
328 | #define GPIO_ALERT_OUT_CFG 0x000e | |
329 | #define GPIO_TOD_NOTIFICATION_CFG 0x000f | |
330 | #define GPIO_CTRL 0x0010 | |
331 | ||
332 | #define GPIO_1 0xc8d4 | |
333 | ||
334 | #define GPIO_2 0xc8e6 | |
335 | ||
336 | #define GPIO_3 0xc900 | |
337 | ||
338 | #define GPIO_4 0xc912 | |
339 | ||
340 | #define GPIO_5 0xc924 | |
341 | ||
342 | #define GPIO_6 0xc936 | |
343 | ||
344 | #define GPIO_7 0xc948 | |
345 | ||
346 | #define GPIO_8 0xc95a | |
347 | ||
348 | #define GPIO_9 0xc980 | |
349 | ||
350 | #define GPIO_10 0xc992 | |
351 | ||
352 | #define GPIO_11 0xc9a4 | |
353 | ||
354 | #define GPIO_12 0xc9b6 | |
355 | ||
356 | #define GPIO_13 0xc9c8 | |
357 | ||
358 | #define GPIO_14 0xc9da | |
359 | ||
360 | #define GPIO_15 0xca00 | |
361 | ||
362 | #define OUT_DIV_MUX 0xca12 | |
363 | ||
364 | #define OUTPUT_0 0xca14 | |
365 | /* FOD frequency output divider value */ | |
366 | #define OUT_DIV 0x0000 | |
367 | #define OUT_DUTY_CYCLE_HIGH 0x0004 | |
368 | #define OUT_CTRL_0 0x0008 | |
369 | #define OUT_CTRL_1 0x0009 | |
370 | /* Phase adjustment in FOD cycles */ | |
371 | #define OUT_PHASE_ADJ 0x000c | |
372 | ||
373 | #define OUTPUT_1 0xca24 | |
374 | ||
375 | #define OUTPUT_2 0xca34 | |
376 | ||
377 | #define OUTPUT_3 0xca44 | |
378 | ||
379 | #define OUTPUT_4 0xca54 | |
380 | ||
381 | #define OUTPUT_5 0xca64 | |
382 | ||
383 | #define OUTPUT_6 0xca80 | |
384 | ||
385 | #define OUTPUT_7 0xca90 | |
386 | ||
387 | #define OUTPUT_8 0xcaa0 | |
388 | ||
389 | #define OUTPUT_9 0xcab0 | |
390 | ||
391 | #define OUTPUT_10 0xcac0 | |
392 | ||
393 | #define OUTPUT_11 0xcad0 | |
394 | ||
395 | #define SERIAL 0xcae0 | |
396 | ||
397 | #define PWM_ENCODER_0 0xcb00 | |
398 | ||
399 | #define PWM_ENCODER_1 0xcb08 | |
400 | ||
401 | #define PWM_ENCODER_2 0xcb10 | |
402 | ||
403 | #define PWM_ENCODER_3 0xcb18 | |
404 | ||
405 | #define PWM_ENCODER_4 0xcb20 | |
406 | ||
407 | #define PWM_ENCODER_5 0xcb28 | |
408 | ||
409 | #define PWM_ENCODER_6 0xcb30 | |
410 | ||
411 | #define PWM_ENCODER_7 0xcb38 | |
412 | ||
413 | #define PWM_DECODER_0 0xcb40 | |
414 | ||
415 | #define PWM_DECODER_1 0xcb48 | |
416 | ||
417 | #define PWM_DECODER_2 0xcb50 | |
418 | ||
419 | #define PWM_DECODER_3 0xcb58 | |
420 | ||
421 | #define PWM_DECODER_4 0xcb60 | |
422 | ||
423 | #define PWM_DECODER_5 0xcb68 | |
424 | ||
425 | #define PWM_DECODER_6 0xcb70 | |
426 | ||
427 | #define PWM_DECODER_7 0xcb80 | |
428 | ||
429 | #define PWM_DECODER_8 0xcb88 | |
430 | ||
431 | #define PWM_DECODER_9 0xcb90 | |
432 | ||
433 | #define PWM_DECODER_10 0xcb98 | |
434 | ||
435 | #define PWM_DECODER_11 0xcba0 | |
436 | ||
437 | #define PWM_DECODER_12 0xcba8 | |
438 | ||
439 | #define PWM_DECODER_13 0xcbb0 | |
440 | ||
441 | #define PWM_DECODER_14 0xcbb8 | |
442 | ||
443 | #define PWM_DECODER_15 0xcbc0 | |
444 | ||
445 | #define PWM_USER_DATA 0xcbc8 | |
446 | ||
447 | #define TOD_0 0xcbcc | |
448 | ||
449 | /* Enable TOD counter, output channel sync and even-PPS mode */ | |
450 | #define TOD_CFG 0x0000 | |
451 | ||
452 | #define TOD_1 0xcbce | |
453 | ||
454 | #define TOD_2 0xcbd0 | |
455 | ||
456 | #define TOD_3 0xcbd2 | |
457 | ||
458 | ||
459 | #define TOD_WRITE_0 0xcc00 | |
460 | /* 8-bit subns, 32-bit ns, 48-bit seconds */ | |
461 | #define TOD_WRITE 0x0000 | |
462 | /* Counter increments after TOD write is completed */ | |
463 | #define TOD_WRITE_COUNTER 0x000c | |
464 | /* TOD write trigger configuration */ | |
465 | #define TOD_WRITE_SELECT_CFG_0 0x000d | |
466 | /* TOD write trigger selection */ | |
467 | #define TOD_WRITE_CMD 0x000f | |
468 | ||
469 | #define TOD_WRITE_1 0xcc10 | |
470 | ||
471 | #define TOD_WRITE_2 0xcc20 | |
472 | ||
473 | #define TOD_WRITE_3 0xcc30 | |
474 | ||
475 | #define TOD_READ_PRIMARY_0 0xcc40 | |
476 | /* 8-bit subns, 32-bit ns, 48-bit seconds */ | |
477 | #define TOD_READ_PRIMARY 0x0000 | |
478 | /* Counter increments after TOD write is completed */ | |
479 | #define TOD_READ_PRIMARY_COUNTER 0x000b | |
480 | /* Read trigger configuration */ | |
481 | #define TOD_READ_PRIMARY_SEL_CFG_0 0x000c | |
482 | /* Read trigger selection */ | |
483 | #define TOD_READ_PRIMARY_CMD 0x000e | |
484 | ||
485 | #define TOD_READ_PRIMARY_1 0xcc50 | |
486 | ||
487 | #define TOD_READ_PRIMARY_2 0xcc60 | |
488 | ||
489 | #define TOD_READ_PRIMARY_3 0xcc80 | |
490 | ||
491 | #define TOD_READ_SECONDARY_0 0xcc90 | |
492 | ||
493 | #define TOD_READ_SECONDARY_1 0xcca0 | |
494 | ||
495 | #define TOD_READ_SECONDARY_2 0xccb0 | |
496 | ||
497 | #define TOD_READ_SECONDARY_3 0xccc0 | |
498 | ||
499 | #define OUTPUT_TDC_CFG 0xccd0 | |
500 | ||
501 | #define OUTPUT_TDC_0 0xcd00 | |
502 | ||
503 | #define OUTPUT_TDC_1 0xcd08 | |
504 | ||
505 | #define OUTPUT_TDC_2 0xcd10 | |
506 | ||
507 | #define OUTPUT_TDC_3 0xcd18 | |
508 | ||
509 | #define INPUT_TDC 0xcd20 | |
510 | ||
511 | #define SCRATCH 0xcf50 | |
512 | ||
513 | #define EEPROM 0xcf68 | |
514 | ||
515 | #define OTP 0xcf70 | |
516 | ||
517 | #define BYTE 0xcf80 | |
518 | ||
519 | /* Bit definitions for the MAJ_REL register */ | |
520 | #define MAJOR_SHIFT (1) | |
521 | #define MAJOR_MASK (0x7f) | |
522 | #define PR_BUILD BIT(0) | |
523 | ||
524 | /* Bit definitions for the USER_GPIO0_TO_7_STATUS register */ | |
525 | #define GPIO0_LEVEL BIT(0) | |
526 | #define GPIO1_LEVEL BIT(1) | |
527 | #define GPIO2_LEVEL BIT(2) | |
528 | #define GPIO3_LEVEL BIT(3) | |
529 | #define GPIO4_LEVEL BIT(4) | |
530 | #define GPIO5_LEVEL BIT(5) | |
531 | #define GPIO6_LEVEL BIT(6) | |
532 | #define GPIO7_LEVEL BIT(7) | |
533 | ||
534 | /* Bit definitions for the USER_GPIO8_TO_15_STATUS register */ | |
535 | #define GPIO8_LEVEL BIT(0) | |
536 | #define GPIO9_LEVEL BIT(1) | |
537 | #define GPIO10_LEVEL BIT(2) | |
538 | #define GPIO11_LEVEL BIT(3) | |
539 | #define GPIO12_LEVEL BIT(4) | |
540 | #define GPIO13_LEVEL BIT(5) | |
541 | #define GPIO14_LEVEL BIT(6) | |
542 | #define GPIO15_LEVEL BIT(7) | |
543 | ||
544 | /* Bit definitions for the GPIO0_TO_7_OUT register */ | |
545 | #define GPIO0_DRIVE_LEVEL BIT(0) | |
546 | #define GPIO1_DRIVE_LEVEL BIT(1) | |
547 | #define GPIO2_DRIVE_LEVEL BIT(2) | |
548 | #define GPIO3_DRIVE_LEVEL BIT(3) | |
549 | #define GPIO4_DRIVE_LEVEL BIT(4) | |
550 | #define GPIO5_DRIVE_LEVEL BIT(5) | |
551 | #define GPIO6_DRIVE_LEVEL BIT(6) | |
552 | #define GPIO7_DRIVE_LEVEL BIT(7) | |
553 | ||
554 | /* Bit definitions for the GPIO8_TO_15_OUT register */ | |
555 | #define GPIO8_DRIVE_LEVEL BIT(0) | |
556 | #define GPIO9_DRIVE_LEVEL BIT(1) | |
557 | #define GPIO10_DRIVE_LEVEL BIT(2) | |
558 | #define GPIO11_DRIVE_LEVEL BIT(3) | |
559 | #define GPIO12_DRIVE_LEVEL BIT(4) | |
560 | #define GPIO13_DRIVE_LEVEL BIT(5) | |
561 | #define GPIO14_DRIVE_LEVEL BIT(6) | |
562 | #define GPIO15_DRIVE_LEVEL BIT(7) | |
563 | ||
564 | /* Bit definitions for the DPLL_TOD_SYNC_CFG register */ | |
565 | #define TOD_SYNC_SOURCE_SHIFT (1) | |
566 | #define TOD_SYNC_SOURCE_MASK (0x3) | |
567 | #define TOD_SYNC_EN BIT(0) | |
568 | ||
569 | /* Bit definitions for the DPLL_MODE register */ | |
570 | #define WRITE_TIMER_MODE BIT(6) | |
571 | #define PLL_MODE_SHIFT (3) | |
572 | #define PLL_MODE_MASK (0x7) | |
573 | #define STATE_MODE_SHIFT (0) | |
574 | #define STATE_MODE_MASK (0x7) | |
575 | ||
576 | /* Bit definitions for the GPIO_CFG_GBL register */ | |
577 | #define SUPPLY_MODE_SHIFT (0) | |
578 | #define SUPPLY_MODE_MASK (0x3) | |
579 | ||
580 | /* Bit definitions for the GPIO_DCO_INC_DEC register */ | |
581 | #define INCDEC_DPLL_INDEX_SHIFT (0) | |
582 | #define INCDEC_DPLL_INDEX_MASK (0x7) | |
583 | ||
584 | /* Bit definitions for the GPIO_OUT_CTRL_0 register */ | |
585 | #define CTRL_OUT_0 BIT(0) | |
586 | #define CTRL_OUT_1 BIT(1) | |
587 | #define CTRL_OUT_2 BIT(2) | |
588 | #define CTRL_OUT_3 BIT(3) | |
589 | #define CTRL_OUT_4 BIT(4) | |
590 | #define CTRL_OUT_5 BIT(5) | |
591 | #define CTRL_OUT_6 BIT(6) | |
592 | #define CTRL_OUT_7 BIT(7) | |
593 | ||
594 | /* Bit definitions for the GPIO_OUT_CTRL_1 register */ | |
595 | #define CTRL_OUT_8 BIT(0) | |
596 | #define CTRL_OUT_9 BIT(1) | |
597 | #define CTRL_OUT_10 BIT(2) | |
598 | #define CTRL_OUT_11 BIT(3) | |
599 | #define CTRL_OUT_12 BIT(4) | |
600 | #define CTRL_OUT_13 BIT(5) | |
601 | #define CTRL_OUT_14 BIT(6) | |
602 | #define CTRL_OUT_15 BIT(7) | |
603 | ||
604 | /* Bit definitions for the GPIO_TOD_TRIG register */ | |
605 | #define TOD_TRIG_0 BIT(0) | |
606 | #define TOD_TRIG_1 BIT(1) | |
607 | #define TOD_TRIG_2 BIT(2) | |
608 | #define TOD_TRIG_3 BIT(3) | |
609 | ||
610 | /* Bit definitions for the GPIO_DPLL_INDICATOR register */ | |
611 | #define IND_DPLL_INDEX_SHIFT (0) | |
612 | #define IND_DPLL_INDEX_MASK (0x7) | |
613 | ||
614 | /* Bit definitions for the GPIO_LOS_INDICATOR register */ | |
615 | #define REFMON_INDEX_SHIFT (0) | |
616 | #define REFMON_INDEX_MASK (0xf) | |
617 | /* Active level of LOS indicator, 0=low 1=high */ | |
618 | #define ACTIVE_LEVEL BIT(4) | |
619 | ||
620 | /* Bit definitions for the GPIO_REF_INPUT_DSQ_0 register */ | |
621 | #define DSQ_INP_0 BIT(0) | |
622 | #define DSQ_INP_1 BIT(1) | |
623 | #define DSQ_INP_2 BIT(2) | |
624 | #define DSQ_INP_3 BIT(3) | |
625 | #define DSQ_INP_4 BIT(4) | |
626 | #define DSQ_INP_5 BIT(5) | |
627 | #define DSQ_INP_6 BIT(6) | |
628 | #define DSQ_INP_7 BIT(7) | |
629 | ||
630 | /* Bit definitions for the GPIO_REF_INPUT_DSQ_1 register */ | |
631 | #define DSQ_INP_8 BIT(0) | |
632 | #define DSQ_INP_9 BIT(1) | |
633 | #define DSQ_INP_10 BIT(2) | |
634 | #define DSQ_INP_11 BIT(3) | |
635 | #define DSQ_INP_12 BIT(4) | |
636 | #define DSQ_INP_13 BIT(5) | |
637 | #define DSQ_INP_14 BIT(6) | |
638 | #define DSQ_INP_15 BIT(7) | |
639 | ||
640 | /* Bit definitions for the GPIO_REF_INPUT_DSQ_2 register */ | |
641 | #define DSQ_DPLL_0 BIT(0) | |
642 | #define DSQ_DPLL_1 BIT(1) | |
643 | #define DSQ_DPLL_2 BIT(2) | |
644 | #define DSQ_DPLL_3 BIT(3) | |
645 | #define DSQ_DPLL_4 BIT(4) | |
646 | #define DSQ_DPLL_5 BIT(5) | |
647 | #define DSQ_DPLL_6 BIT(6) | |
648 | #define DSQ_DPLL_7 BIT(7) | |
649 | ||
650 | /* Bit definitions for the GPIO_REF_INPUT_DSQ_3 register */ | |
651 | #define DSQ_DPLL_SYS BIT(0) | |
652 | #define GPIO_DSQ_LEVEL BIT(1) | |
653 | ||
654 | /* Bit definitions for the GPIO_TOD_NOTIFICATION_CFG register */ | |
655 | #define DPLL_TOD_SHIFT (0) | |
656 | #define DPLL_TOD_MASK (0x3) | |
657 | #define TOD_READ_SECONDARY BIT(2) | |
658 | #define GPIO_ASSERT_LEVEL BIT(3) | |
659 | ||
660 | /* Bit definitions for the GPIO_CTRL register */ | |
661 | #define GPIO_FUNCTION_EN BIT(0) | |
662 | #define GPIO_CMOS_OD_MODE BIT(1) | |
663 | #define GPIO_CONTROL_DIR BIT(2) | |
664 | #define GPIO_PU_PD_MODE BIT(3) | |
665 | #define GPIO_FUNCTION_SHIFT (4) | |
666 | #define GPIO_FUNCTION_MASK (0xf) | |
667 | ||
668 | /* Bit definitions for the OUT_CTRL_1 register */ | |
669 | #define OUT_SYNC_DISABLE BIT(7) | |
670 | #define SQUELCH_VALUE BIT(6) | |
671 | #define SQUELCH_DISABLE BIT(5) | |
672 | #define PAD_VDDO_SHIFT (2) | |
673 | #define PAD_VDDO_MASK (0x7) | |
674 | #define PAD_CMOSDRV_SHIFT (0) | |
675 | #define PAD_CMOSDRV_MASK (0x3) | |
676 | ||
677 | /* Bit definitions for the TOD_CFG register */ | |
678 | #define TOD_EVEN_PPS_MODE BIT(2) | |
679 | #define TOD_OUT_SYNC_ENABLE BIT(1) | |
680 | #define TOD_ENABLE BIT(0) | |
681 | ||
682 | /* Bit definitions for the TOD_WRITE_SELECT_CFG_0 register */ | |
683 | #define WR_PWM_DECODER_INDEX_SHIFT (4) | |
684 | #define WR_PWM_DECODER_INDEX_MASK (0xf) | |
685 | #define WR_REF_INDEX_SHIFT (0) | |
686 | #define WR_REF_INDEX_MASK (0xf) | |
687 | ||
688 | /* Bit definitions for the TOD_WRITE_CMD register */ | |
689 | #define TOD_WRITE_SELECTION_SHIFT (0) | |
690 | #define TOD_WRITE_SELECTION_MASK (0xf) | |
7ea5fda2 ML |
691 | /* 4.8.7 */ |
692 | #define TOD_WRITE_TYPE_SHIFT (4) | |
693 | #define TOD_WRITE_TYPE_MASK (0x3) | |
3a6ba7dc VC |
694 | |
695 | /* Bit definitions for the TOD_READ_PRIMARY_SEL_CFG_0 register */ | |
696 | #define RD_PWM_DECODER_INDEX_SHIFT (4) | |
697 | #define RD_PWM_DECODER_INDEX_MASK (0xf) | |
698 | #define RD_REF_INDEX_SHIFT (0) | |
699 | #define RD_REF_INDEX_MASK (0xf) | |
700 | ||
701 | /* Bit definitions for the TOD_READ_PRIMARY_CMD register */ | |
702 | #define TOD_READ_TRIGGER_MODE BIT(4) | |
703 | #define TOD_READ_TRIGGER_SHIFT (0) | |
704 | #define TOD_READ_TRIGGER_MASK (0xf) | |
705 | ||
7ea5fda2 ML |
706 | /* Bit definitions for the DPLL_CTRL_COMBO_MASTER_CFG register */ |
707 | #define COMBO_MASTER_HOLD BIT(0) | |
708 | ||
3a6ba7dc | 709 | #endif |