[mirror_ubuntu-jammy-kernel.git] / drivers / ptp / ptp_clockmatrix.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and
 * synchronization devices.
 *
 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
 */
#ifndef PTP_IDTCLOCKMATRIX_H
#define PTP_IDTCLOCKMATRIX_H

#include <linux/ktime.h>

#include "idt8a340_reg.h"

#define FW_FILENAME	"idtcm.bin"
#define MAX_TOD		(4)
#define MAX_PLL		(8)
#define MAX_OUTPUT	(12)

#define MAX_ABS_WRITE_PHASE_PICOSECONDS (107374182350LL)

#define TOD_MASK_ADDR		(0xFFA5)
#define DEFAULT_TOD_MASK	(0x04)

#define SET_U16_LSB(orig, val8) (orig = (0xff00 & (orig)) | (val8))
#define SET_U16_MSB(orig, val8) (orig = (0x00ff & (orig)) | (val8 << 8))

#define TOD0_PTP_PLL_ADDR		(0xFFA8)
#define TOD1_PTP_PLL_ADDR		(0xFFA9)
#define TOD2_PTP_PLL_ADDR		(0xFFAA)
#define TOD3_PTP_PLL_ADDR		(0xFFAB)

#define TOD0_OUT_ALIGN_MASK_ADDR	(0xFFB0)
#define TOD1_OUT_ALIGN_MASK_ADDR	(0xFFB2)
#define TOD2_OUT_ALIGN_MASK_ADDR	(0xFFB4)
#define TOD3_OUT_ALIGN_MASK_ADDR	(0xFFB6)

#define DEFAULT_OUTPUT_MASK_PLL0	(0x003)
#define DEFAULT_OUTPUT_MASK_PLL1	(0x00c)
#define DEFAULT_OUTPUT_MASK_PLL2	(0x030)
#define DEFAULT_OUTPUT_MASK_PLL3	(0x0c0)

#define DEFAULT_TOD0_PTP_PLL		(0)
#define DEFAULT_TOD1_PTP_PLL		(1)
#define DEFAULT_TOD2_PTP_PLL		(2)
#define DEFAULT_TOD3_PTP_PLL		(3)

#define POST_SM_RESET_DELAY_MS			(3000)
#define PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED	(150000)
#define PHASE_PULL_IN_THRESHOLD_NS		(15000)
#define TOD_WRITE_OVERHEAD_COUNT_MAX		(2)
#define TOD_BYTE_COUNT				(11)

#define LOCK_TIMEOUT_MS			(2000)
#define LOCK_POLL_INTERVAL_MS		(10)

#define PEROUT_ENABLE_OUTPUT_MASK	(0xdeadbeef)

#define IDTCM_MAX_WRITE_COUNT		(512)

#define FULL_FW_CFG_BYTES		(SCRATCH - GPIO_USER_CONTROL)
#define FULL_FW_CFG_SKIPPED_BYTES	(((SCRATCH >> 7) \
					  - (GPIO_USER_CONTROL >> 7)) \
					 * 4) /* 4 bytes skipped every 0x80 */

/* Values of DPLL_N.DPLL_MODE.PLL_MODE */
enum pll_mode {
	PLL_MODE_MIN = 0,
	PLL_MODE_NORMAL = PLL_MODE_MIN,
	PLL_MODE_WRITE_PHASE = 1,
	PLL_MODE_WRITE_FREQUENCY = 2,
	PLL_MODE_GPIO_INC_DEC = 3,
	PLL_MODE_SYNTHESIS = 4,
	PLL_MODE_PHASE_MEASUREMENT = 5,
	PLL_MODE_DISABLED = 6,
	PLL_MODE_MAX = PLL_MODE_DISABLED,
};

enum hw_tod_write_trig_sel {
	HW_TOD_WR_TRIG_SEL_MIN = 0,
	HW_TOD_WR_TRIG_SEL_MSB = HW_TOD_WR_TRIG_SEL_MIN,
	HW_TOD_WR_TRIG_SEL_RESERVED = 1,
	HW_TOD_WR_TRIG_SEL_TOD_PPS = 2,
	HW_TOD_WR_TRIG_SEL_IRIGB_PPS = 3,
	HW_TOD_WR_TRIG_SEL_PWM_PPS = 4,
	HW_TOD_WR_TRIG_SEL_GPIO = 5,
	HW_TOD_WR_TRIG_SEL_FOD_SYNC = 6,
	WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_FOD_SYNC,
};

/* 4.8.7 only */
enum scsr_tod_write_trig_sel {
	SCSR_TOD_WR_TRIG_SEL_DISABLE = 0,
	SCSR_TOD_WR_TRIG_SEL_IMMEDIATE = 1,
	SCSR_TOD_WR_TRIG_SEL_REFCLK = 2,
	SCSR_TOD_WR_TRIG_SEL_PWMPPS = 3,
	SCSR_TOD_WR_TRIG_SEL_TODPPS = 4,
	SCSR_TOD_WR_TRIG_SEL_SYNCFOD = 5,
	SCSR_TOD_WR_TRIG_SEL_GPIO = 6,
	SCSR_TOD_WR_TRIG_SEL_MAX = SCSR_TOD_WR_TRIG_SEL_GPIO,
};

/* 4.8.7 only */
enum scsr_tod_write_type_sel {
	SCSR_TOD_WR_TYPE_SEL_ABSOLUTE = 0,
	SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS = 1,
	SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS = 2,
	SCSR_TOD_WR_TYPE_SEL_MAX = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS,
};

/* Values STATUS.DPLL_SYS_STATUS.DPLL_SYS_STATE */
enum dpll_state {
	DPLL_STATE_MIN = 0,
	DPLL_STATE_FREERUN = DPLL_STATE_MIN,
	DPLL_STATE_LOCKACQ = 1,
	DPLL_STATE_LOCKREC = 2,
	DPLL_STATE_LOCKED = 3,
	DPLL_STATE_HOLDOVER = 4,
	DPLL_STATE_OPEN_LOOP = 5,
	DPLL_STATE_MAX = DPLL_STATE_OPEN_LOOP,
};

struct idtcm;

struct idtcm_channel {
	struct ptp_clock_info	caps;
	struct ptp_clock	*ptp_clock;
	struct idtcm		*idtcm;
	u16			dpll_phase;
	u16			dpll_freq;
	u16			dpll_n;
	u16			dpll_ctrl_n;
	u16			dpll_phase_pull_in;
	u16			tod_read_primary;
	u16			tod_write;
	u16			tod_n;
	u16			hw_dpll_n;
	enum pll_mode		pll_mode;
	u8			pll;
	u16			output_mask;
	u8			output_phase_adj[MAX_OUTPUT][4];
};

struct idtcm {
	struct idtcm_channel	channel[MAX_TOD];
	struct i2c_client	*client;
	u8			page_offset;
	u8			tod_mask;
	char			version[16];
	u8			deprecated;

	/* Overhead calculation for adjtime */
	u8			calculate_overhead_flag;
	s64			tod_write_overhead_ns;
	ktime_t			start_time;

	/* Protects I2C read/modify/write registers from concurrent access */
	struct mutex		reg_lock;
};

struct idtcm_fwrc {
	u8 hiaddr;
	u8 loaddr;
	u8 value;
	u8 reserved;
} __packed;

#endif /* PTP_IDTCLOCKMATRIX_H */
Commit	Line	Data
3a6ba7dc VC	1	/* SPDX-License-Identifier: GPL-2.0+ */
	2	/*
	3	* PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and
	4	* synchronization devices.
	5	*
	6	* Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
	7	*/
	8	#ifndef PTP_IDTCLOCKMATRIX_H
	9	#define PTP_IDTCLOCKMATRIX_H
	10
	11	#include <linux/ktime.h>
	12
	13	#include "idt8a340_reg.h"
	14
	15	#define FW_FILENAME "idtcm.bin"
7ea5fda2 ML	16	#define MAX_TOD (4)
7ea5fda2 ML	17	#define MAX_PLL (8)
7260d1c8	18	#define MAX_OUTPUT (12)
3a6ba7dc	19
425d2b1c VC	20	#define MAX_ABS_WRITE_PHASE_PICOSECONDS (107374182350LL)
425d2b1c VC	21
7ea5fda2 ML	22	#define TOD_MASK_ADDR (0xFFA5)
7ea5fda2 ML	23	#define DEFAULT_TOD_MASK (0x04)
3a6ba7dc VC	24
	25	#define SET_U16_LSB(orig, val8) (orig = (0xff00 & (orig)) \| (val8))
	26	#define SET_U16_MSB(orig, val8) (orig = (0x00ff & (orig)) \| (val8 << 8))
	27
7ea5fda2 ML	28	#define TOD0_PTP_PLL_ADDR (0xFFA8)
	29	#define TOD1_PTP_PLL_ADDR (0xFFA9)
	30	#define TOD2_PTP_PLL_ADDR (0xFFAA)
	31	#define TOD3_PTP_PLL_ADDR (0xFFAB)
	32
	33	#define TOD0_OUT_ALIGN_MASK_ADDR (0xFFB0)
	34	#define TOD1_OUT_ALIGN_MASK_ADDR (0xFFB2)
	35	#define TOD2_OUT_ALIGN_MASK_ADDR (0xFFB4)
	36	#define TOD3_OUT_ALIGN_MASK_ADDR (0xFFB6)
3a6ba7dc VC	37
	38	#define DEFAULT_OUTPUT_MASK_PLL0 (0x003)
	39	#define DEFAULT_OUTPUT_MASK_PLL1 (0x00c)
	40	#define DEFAULT_OUTPUT_MASK_PLL2 (0x030)
	41	#define DEFAULT_OUTPUT_MASK_PLL3 (0x0c0)
	42
7ea5fda2 ML	43	#define DEFAULT_TOD0_PTP_PLL (0)
	44	#define DEFAULT_TOD1_PTP_PLL (1)
	45	#define DEFAULT_TOD2_PTP_PLL (2)
	46	#define DEFAULT_TOD3_PTP_PLL (3)
	47
da948233 ML	48	#define POST_SM_RESET_DELAY_MS (3000)
	49	#define PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED (150000)
	50	#define PHASE_PULL_IN_THRESHOLD_NS (15000)
	51	#define TOD_WRITE_OVERHEAD_COUNT_MAX (2)
	52	#define TOD_BYTE_COUNT (11)
7ea5fda2	53
797d3186 VC	54	#define LOCK_TIMEOUT_MS (2000)
	55	#define LOCK_POLL_INTERVAL_MS (10)
	56
251f4fe2	57	#define PEROUT_ENABLE_OUTPUT_MASK (0xdeadbeef)
7ea5fda2	58
251f4fe2 ML	59	#define IDTCM_MAX_WRITE_COUNT (512)
	60
	61	#define FULL_FW_CFG_BYTES (SCRATCH - GPIO_USER_CONTROL)
	62	#define FULL_FW_CFG_SKIPPED_BYTES (((SCRATCH >> 7) \
	63	- (GPIO_USER_CONTROL >> 7)) \
	64	* 4) /* 4 bytes skipped every 0x80 */
957ff427	65
3a6ba7dc VC	66	/* Values of DPLL_N.DPLL_MODE.PLL_MODE */
	67	enum pll_mode {
	68	PLL_MODE_MIN = 0,
	69	PLL_MODE_NORMAL = PLL_MODE_MIN,
	70	PLL_MODE_WRITE_PHASE = 1,
	71	PLL_MODE_WRITE_FREQUENCY = 2,
	72	PLL_MODE_GPIO_INC_DEC = 3,
	73	PLL_MODE_SYNTHESIS = 4,
	74	PLL_MODE_PHASE_MEASUREMENT = 5,
7ea5fda2 ML	75	PLL_MODE_DISABLED = 6,
7ea5fda2 ML	76	PLL_MODE_MAX = PLL_MODE_DISABLED,
3a6ba7dc VC	77	};
	78
	79	enum hw_tod_write_trig_sel {
	80	HW_TOD_WR_TRIG_SEL_MIN = 0,
	81	HW_TOD_WR_TRIG_SEL_MSB = HW_TOD_WR_TRIG_SEL_MIN,
	82	HW_TOD_WR_TRIG_SEL_RESERVED = 1,
	83	HW_TOD_WR_TRIG_SEL_TOD_PPS = 2,
	84	HW_TOD_WR_TRIG_SEL_IRIGB_PPS = 3,
	85	HW_TOD_WR_TRIG_SEL_PWM_PPS = 4,
	86	HW_TOD_WR_TRIG_SEL_GPIO = 5,
	87	HW_TOD_WR_TRIG_SEL_FOD_SYNC = 6,
	88	WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_FOD_SYNC,
	89	};
	90
7ea5fda2 ML	91	/* 4.8.7 only */
	92	enum scsr_tod_write_trig_sel {
	93	SCSR_TOD_WR_TRIG_SEL_DISABLE = 0,
	94	SCSR_TOD_WR_TRIG_SEL_IMMEDIATE = 1,
	95	SCSR_TOD_WR_TRIG_SEL_REFCLK = 2,
	96	SCSR_TOD_WR_TRIG_SEL_PWMPPS = 3,
	97	SCSR_TOD_WR_TRIG_SEL_TODPPS = 4,
	98	SCSR_TOD_WR_TRIG_SEL_SYNCFOD = 5,
	99	SCSR_TOD_WR_TRIG_SEL_GPIO = 6,
	100	SCSR_TOD_WR_TRIG_SEL_MAX = SCSR_TOD_WR_TRIG_SEL_GPIO,
	101	};
	102
	103	/* 4.8.7 only */
	104	enum scsr_tod_write_type_sel {
	105	SCSR_TOD_WR_TYPE_SEL_ABSOLUTE = 0,
	106	SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS = 1,
	107	SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS = 2,
	108	SCSR_TOD_WR_TYPE_SEL_MAX = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS,
	109	};
	110
797d3186 VC	111	/* Values STATUS.DPLL_SYS_STATUS.DPLL_SYS_STATE */
	112	enum dpll_state {
	113	DPLL_STATE_MIN = 0,
	114	DPLL_STATE_FREERUN = DPLL_STATE_MIN,
	115	DPLL_STATE_LOCKACQ = 1,
	116	DPLL_STATE_LOCKREC = 2,
	117	DPLL_STATE_LOCKED = 3,
	118	DPLL_STATE_HOLDOVER = 4,
	119	DPLL_STATE_OPEN_LOOP = 5,
	120	DPLL_STATE_MAX = DPLL_STATE_OPEN_LOOP,
	121	};
	122
3a6ba7dc VC	123	struct idtcm;
	124
	125	struct idtcm_channel {
	126	struct ptp_clock_info caps;
	127	struct ptp_clock *ptp_clock;
	128	struct idtcm *idtcm;
	129	u16 dpll_phase;
	130	u16 dpll_freq;
	131	u16 dpll_n;
	132	u16 dpll_ctrl_n;
	133	u16 dpll_phase_pull_in;
	134	u16 tod_read_primary;
	135	u16 tod_write;
	136	u16 tod_n;
	137	u16 hw_dpll_n;
	138	enum pll_mode pll_mode;
7ea5fda2	139	u8 pll;
3a6ba7dc	140	u16 output_mask;
7260d1c8	141	u8 output_phase_adj[MAX_OUTPUT][4];
3a6ba7dc VC	142	};
	143
	144	struct idtcm {
7ea5fda2	145	struct idtcm_channel channel[MAX_TOD];
3a6ba7dc VC	146	struct i2c_client *client;
3a6ba7dc VC	147	u8 page_offset;
7ea5fda2 ML	148	u8 tod_mask;
7ea5fda2 ML	149	char version[16];
da948233	150	u8 deprecated;
3a6ba7dc VC	151
	152	/* Overhead calculation for adjtime */
	153	u8 calculate_overhead_flag;
	154	s64 tod_write_overhead_ns;
	155	ktime_t start_time;
	156
	157	/* Protects I2C read/modify/write registers from concurrent access */
	158	struct mutex reg_lock;
	159	};
	160
	161	struct idtcm_fwrc {
	162	u8 hiaddr;
	163	u8 loaddr;
	164	u8 value;
	165	u8 reserved;
	166	} __packed;
	167
	168	#endif /* PTP_IDTCLOCKMATRIX_H */