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57a10d8c ML |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // | |
3 | // Copyright (C) 2018 Integrated Device Technology, Inc | |
4 | // | |
5 | ||
6 | #define pr_fmt(fmt) "IDT_82p33xxx: " fmt | |
7 | ||
8 | #include <linux/firmware.h> | |
9 | #include <linux/i2c.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/ptp_clock_kernel.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/timekeeping.h> | |
15 | #include <linux/bitops.h> | |
16 | ||
17 | #include "ptp_private.h" | |
18 | #include "ptp_idt82p33.h" | |
19 | ||
20 | MODULE_DESCRIPTION("Driver for IDT 82p33xxx clock devices"); | |
21 | MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>"); | |
22 | MODULE_VERSION("1.0"); | |
23 | MODULE_LICENSE("GPL"); | |
e014ae39 | 24 | MODULE_FIRMWARE(FW_FILENAME); |
57a10d8c ML |
25 | |
26 | /* Module Parameters */ | |
d30e1c3d | 27 | static u32 sync_tod_timeout = SYNC_TOD_TIMEOUT_SEC; |
57a10d8c ML |
28 | module_param(sync_tod_timeout, uint, 0); |
29 | MODULE_PARM_DESC(sync_tod_timeout, | |
30 | "duration in second to keep SYNC_TOD on (set to 0 to keep it always on)"); | |
31 | ||
d30e1c3d | 32 | static u32 phase_snap_threshold = SNAP_THRESHOLD_NS; |
57a10d8c ML |
33 | module_param(phase_snap_threshold, uint, 0); |
34 | MODULE_PARM_DESC(phase_snap_threshold, | |
35 | "threshold (150000ns by default) below which adjtime would ignore"); | |
36 | ||
37 | static void idt82p33_byte_array_to_timespec(struct timespec64 *ts, | |
38 | u8 buf[TOD_BYTE_COUNT]) | |
39 | { | |
40 | time64_t sec; | |
41 | s32 nsec; | |
42 | u8 i; | |
43 | ||
44 | nsec = buf[3]; | |
45 | for (i = 0; i < 3; i++) { | |
46 | nsec <<= 8; | |
47 | nsec |= buf[2 - i]; | |
48 | } | |
49 | ||
50 | sec = buf[9]; | |
51 | for (i = 0; i < 5; i++) { | |
52 | sec <<= 8; | |
53 | sec |= buf[8 - i]; | |
54 | } | |
55 | ||
56 | ts->tv_sec = sec; | |
57 | ts->tv_nsec = nsec; | |
58 | } | |
59 | ||
60 | static void idt82p33_timespec_to_byte_array(struct timespec64 const *ts, | |
61 | u8 buf[TOD_BYTE_COUNT]) | |
62 | { | |
63 | time64_t sec; | |
64 | s32 nsec; | |
65 | u8 i; | |
66 | ||
67 | nsec = ts->tv_nsec; | |
68 | sec = ts->tv_sec; | |
69 | ||
70 | for (i = 0; i < 4; i++) { | |
71 | buf[i] = nsec & 0xff; | |
72 | nsec >>= 8; | |
73 | } | |
74 | ||
75 | for (i = 4; i < TOD_BYTE_COUNT; i++) { | |
76 | buf[i] = sec & 0xff; | |
77 | sec >>= 8; | |
78 | } | |
79 | } | |
80 | ||
81 | static int idt82p33_xfer(struct idt82p33 *idt82p33, | |
82 | unsigned char regaddr, | |
83 | unsigned char *buf, | |
84 | unsigned int count, | |
85 | int write) | |
86 | { | |
87 | struct i2c_client *client = idt82p33->client; | |
88 | struct i2c_msg msg[2]; | |
89 | int cnt; | |
90 | ||
91 | msg[0].addr = client->addr; | |
92 | msg[0].flags = 0; | |
93 | msg[0].len = 1; | |
94 | msg[0].buf = ®addr; | |
95 | ||
96 | msg[1].addr = client->addr; | |
97 | msg[1].flags = write ? 0 : I2C_M_RD; | |
98 | msg[1].len = count; | |
99 | msg[1].buf = buf; | |
100 | ||
101 | cnt = i2c_transfer(client->adapter, msg, 2); | |
102 | if (cnt < 0) { | |
103 | dev_err(&client->dev, "i2c_transfer returned %d\n", cnt); | |
104 | return cnt; | |
105 | } else if (cnt != 2) { | |
106 | dev_err(&client->dev, | |
107 | "i2c_transfer sent only %d of %d messages\n", cnt, 2); | |
108 | return -EIO; | |
109 | } | |
110 | return 0; | |
111 | } | |
112 | ||
113 | static int idt82p33_page_offset(struct idt82p33 *idt82p33, unsigned char val) | |
114 | { | |
115 | int err; | |
116 | ||
117 | if (idt82p33->page_offset == val) | |
118 | return 0; | |
119 | ||
120 | err = idt82p33_xfer(idt82p33, PAGE_ADDR, &val, sizeof(val), 1); | |
121 | if (err) | |
122 | dev_err(&idt82p33->client->dev, | |
123 | "failed to set page offset %d\n", val); | |
124 | else | |
125 | idt82p33->page_offset = val; | |
126 | ||
127 | return err; | |
128 | } | |
129 | ||
130 | static int idt82p33_rdwr(struct idt82p33 *idt82p33, unsigned int regaddr, | |
131 | unsigned char *buf, unsigned int count, bool write) | |
132 | { | |
133 | u8 offset, page; | |
134 | int err; | |
135 | ||
136 | page = _PAGE(regaddr); | |
137 | offset = _OFFSET(regaddr); | |
138 | ||
139 | err = idt82p33_page_offset(idt82p33, page); | |
140 | if (err) | |
141 | goto out; | |
142 | ||
143 | err = idt82p33_xfer(idt82p33, offset, buf, count, write); | |
144 | out: | |
145 | return err; | |
146 | } | |
147 | ||
148 | static int idt82p33_read(struct idt82p33 *idt82p33, unsigned int regaddr, | |
149 | unsigned char *buf, unsigned int count) | |
150 | { | |
151 | return idt82p33_rdwr(idt82p33, regaddr, buf, count, false); | |
152 | } | |
153 | ||
154 | static int idt82p33_write(struct idt82p33 *idt82p33, unsigned int regaddr, | |
155 | unsigned char *buf, unsigned int count) | |
156 | { | |
157 | return idt82p33_rdwr(idt82p33, regaddr, buf, count, true); | |
158 | } | |
159 | ||
160 | static int idt82p33_dpll_set_mode(struct idt82p33_channel *channel, | |
161 | enum pll_mode mode) | |
162 | { | |
163 | struct idt82p33 *idt82p33 = channel->idt82p33; | |
164 | u8 dpll_mode; | |
165 | int err; | |
166 | ||
167 | if (channel->pll_mode == mode) | |
168 | return 0; | |
169 | ||
170 | err = idt82p33_read(idt82p33, channel->dpll_mode_cnfg, | |
171 | &dpll_mode, sizeof(dpll_mode)); | |
172 | if (err) | |
173 | return err; | |
174 | ||
175 | dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT); | |
176 | ||
177 | dpll_mode |= (mode << PLL_MODE_SHIFT); | |
178 | ||
179 | err = idt82p33_write(idt82p33, channel->dpll_mode_cnfg, | |
180 | &dpll_mode, sizeof(dpll_mode)); | |
181 | if (err) | |
182 | return err; | |
183 | ||
184 | channel->pll_mode = dpll_mode; | |
185 | ||
186 | return 0; | |
187 | } | |
188 | ||
189 | static int _idt82p33_gettime(struct idt82p33_channel *channel, | |
190 | struct timespec64 *ts) | |
191 | { | |
192 | struct idt82p33 *idt82p33 = channel->idt82p33; | |
193 | u8 buf[TOD_BYTE_COUNT]; | |
194 | u8 trigger; | |
195 | int err; | |
196 | ||
197 | trigger = TOD_TRIGGER(HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG, | |
198 | HW_TOD_RD_TRIG_SEL_LSB_TOD_STS); | |
199 | ||
200 | ||
201 | err = idt82p33_write(idt82p33, channel->dpll_tod_trigger, | |
202 | &trigger, sizeof(trigger)); | |
203 | ||
204 | if (err) | |
205 | return err; | |
206 | ||
207 | if (idt82p33->calculate_overhead_flag) | |
208 | idt82p33->start_time = ktime_get_raw(); | |
209 | ||
210 | err = idt82p33_read(idt82p33, channel->dpll_tod_sts, buf, sizeof(buf)); | |
211 | ||
212 | if (err) | |
213 | return err; | |
214 | ||
215 | idt82p33_byte_array_to_timespec(ts, buf); | |
216 | ||
217 | return 0; | |
218 | } | |
219 | ||
220 | /* | |
221 | * TOD Trigger: | |
222 | * Bits[7:4] Write 0x9, MSB write | |
223 | * Bits[3:0] Read 0x9, LSB read | |
224 | */ | |
225 | ||
226 | static int _idt82p33_settime(struct idt82p33_channel *channel, | |
227 | struct timespec64 const *ts) | |
228 | { | |
229 | struct idt82p33 *idt82p33 = channel->idt82p33; | |
230 | struct timespec64 local_ts = *ts; | |
231 | char buf[TOD_BYTE_COUNT]; | |
232 | s64 dynamic_overhead_ns; | |
233 | unsigned char trigger; | |
234 | int err; | |
235 | u8 i; | |
236 | ||
237 | trigger = TOD_TRIGGER(HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG, | |
238 | HW_TOD_RD_TRIG_SEL_LSB_TOD_STS); | |
239 | ||
240 | err = idt82p33_write(idt82p33, channel->dpll_tod_trigger, | |
241 | &trigger, sizeof(trigger)); | |
242 | ||
243 | if (err) | |
244 | return err; | |
245 | ||
246 | if (idt82p33->calculate_overhead_flag) { | |
247 | dynamic_overhead_ns = ktime_to_ns(ktime_get_raw()) | |
248 | - ktime_to_ns(idt82p33->start_time); | |
249 | ||
250 | timespec64_add_ns(&local_ts, dynamic_overhead_ns); | |
251 | ||
252 | idt82p33->calculate_overhead_flag = 0; | |
253 | } | |
254 | ||
255 | idt82p33_timespec_to_byte_array(&local_ts, buf); | |
256 | ||
257 | /* | |
258 | * Store the new time value. | |
259 | */ | |
260 | for (i = 0; i < TOD_BYTE_COUNT; i++) { | |
261 | err = idt82p33_write(idt82p33, channel->dpll_tod_cnfg + i, | |
262 | &buf[i], sizeof(buf[i])); | |
263 | if (err) | |
264 | return err; | |
265 | } | |
266 | ||
267 | return err; | |
268 | } | |
269 | ||
270 | static int _idt82p33_adjtime(struct idt82p33_channel *channel, s64 delta_ns) | |
271 | { | |
272 | struct idt82p33 *idt82p33 = channel->idt82p33; | |
273 | struct timespec64 ts; | |
274 | s64 now_ns; | |
275 | int err; | |
276 | ||
277 | idt82p33->calculate_overhead_flag = 1; | |
278 | ||
279 | err = _idt82p33_gettime(channel, &ts); | |
280 | ||
281 | if (err) | |
282 | return err; | |
283 | ||
284 | now_ns = timespec64_to_ns(&ts); | |
285 | now_ns += delta_ns + idt82p33->tod_write_overhead_ns; | |
286 | ||
287 | ts = ns_to_timespec64(now_ns); | |
288 | ||
289 | err = _idt82p33_settime(channel, &ts); | |
290 | ||
291 | return err; | |
292 | } | |
293 | ||
294 | static int _idt82p33_adjfine(struct idt82p33_channel *channel, long scaled_ppm) | |
295 | { | |
296 | struct idt82p33 *idt82p33 = channel->idt82p33; | |
297 | unsigned char buf[5] = {0}; | |
298 | int neg_adj = 0; | |
299 | int err, i; | |
300 | s64 fcw; | |
301 | ||
302 | if (scaled_ppm == channel->current_freq_ppb) | |
303 | return 0; | |
304 | ||
305 | /* | |
306 | * Frequency Control Word unit is: 1.68 * 10^-10 ppm | |
307 | * | |
308 | * adjfreq: | |
309 | * ppb * 10^9 | |
310 | * FCW = ---------- | |
311 | * 168 | |
312 | * | |
313 | * adjfine: | |
314 | * scaled_ppm * 5^12 | |
315 | * FCW = ------------- | |
316 | * 168 * 2^4 | |
317 | */ | |
318 | if (scaled_ppm < 0) { | |
319 | neg_adj = 1; | |
320 | scaled_ppm = -scaled_ppm; | |
321 | } | |
322 | ||
323 | fcw = scaled_ppm * 244140625ULL; | |
324 | fcw = div_u64(fcw, 2688); | |
325 | ||
326 | if (neg_adj) | |
327 | fcw = -fcw; | |
328 | ||
329 | for (i = 0; i < 5; i++) { | |
330 | buf[i] = fcw & 0xff; | |
331 | fcw >>= 8; | |
332 | } | |
333 | ||
334 | err = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO); | |
335 | ||
336 | if (err) | |
337 | return err; | |
338 | ||
339 | err = idt82p33_write(idt82p33, channel->dpll_freq_cnfg, | |
340 | buf, sizeof(buf)); | |
341 | ||
342 | if (err == 0) | |
343 | channel->current_freq_ppb = scaled_ppm; | |
344 | ||
345 | return err; | |
346 | } | |
347 | ||
348 | static int idt82p33_measure_one_byte_write_overhead( | |
349 | struct idt82p33_channel *channel, s64 *overhead_ns) | |
350 | { | |
351 | struct idt82p33 *idt82p33 = channel->idt82p33; | |
352 | ktime_t start, stop; | |
353 | s64 total_ns; | |
354 | u8 trigger; | |
355 | int err; | |
356 | u8 i; | |
357 | ||
358 | total_ns = 0; | |
359 | *overhead_ns = 0; | |
360 | trigger = TOD_TRIGGER(HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG, | |
361 | HW_TOD_RD_TRIG_SEL_LSB_TOD_STS); | |
362 | ||
363 | for (i = 0; i < MAX_MEASURMENT_COUNT; i++) { | |
364 | ||
365 | start = ktime_get_raw(); | |
366 | ||
367 | err = idt82p33_write(idt82p33, channel->dpll_tod_trigger, | |
368 | &trigger, sizeof(trigger)); | |
369 | ||
370 | stop = ktime_get_raw(); | |
371 | ||
372 | if (err) | |
373 | return err; | |
374 | ||
375 | total_ns += ktime_to_ns(stop) - ktime_to_ns(start); | |
376 | } | |
377 | ||
378 | *overhead_ns = div_s64(total_ns, MAX_MEASURMENT_COUNT); | |
379 | ||
380 | return err; | |
381 | } | |
382 | ||
383 | static int idt82p33_measure_tod_write_9_byte_overhead( | |
384 | struct idt82p33_channel *channel) | |
385 | { | |
386 | struct idt82p33 *idt82p33 = channel->idt82p33; | |
387 | u8 buf[TOD_BYTE_COUNT]; | |
388 | ktime_t start, stop; | |
389 | s64 total_ns; | |
390 | int err = 0; | |
391 | u8 i, j; | |
392 | ||
393 | total_ns = 0; | |
394 | idt82p33->tod_write_overhead_ns = 0; | |
395 | ||
396 | for (i = 0; i < MAX_MEASURMENT_COUNT; i++) { | |
397 | ||
398 | start = ktime_get_raw(); | |
399 | ||
400 | /* Need one less byte for applicable overhead */ | |
401 | for (j = 0; j < (TOD_BYTE_COUNT - 1); j++) { | |
402 | err = idt82p33_write(idt82p33, | |
403 | channel->dpll_tod_cnfg + i, | |
404 | &buf[i], sizeof(buf[i])); | |
405 | if (err) | |
406 | return err; | |
407 | } | |
408 | ||
409 | stop = ktime_get_raw(); | |
410 | ||
411 | total_ns += ktime_to_ns(stop) - ktime_to_ns(start); | |
412 | } | |
413 | ||
414 | idt82p33->tod_write_overhead_ns = div_s64(total_ns, | |
415 | MAX_MEASURMENT_COUNT); | |
416 | ||
417 | return err; | |
418 | } | |
419 | ||
420 | static int idt82p33_measure_settime_gettime_gap_overhead( | |
421 | struct idt82p33_channel *channel, s64 *overhead_ns) | |
422 | { | |
423 | struct timespec64 ts1 = {0, 0}; | |
424 | struct timespec64 ts2; | |
425 | int err; | |
426 | ||
427 | *overhead_ns = 0; | |
428 | ||
429 | err = _idt82p33_settime(channel, &ts1); | |
430 | ||
431 | if (err) | |
432 | return err; | |
433 | ||
434 | err = _idt82p33_gettime(channel, &ts2); | |
435 | ||
436 | if (!err) | |
437 | *overhead_ns = timespec64_to_ns(&ts2) - timespec64_to_ns(&ts1); | |
438 | ||
439 | return err; | |
440 | } | |
441 | ||
442 | static int idt82p33_measure_tod_write_overhead(struct idt82p33_channel *channel) | |
443 | { | |
444 | s64 trailing_overhead_ns, one_byte_write_ns, gap_ns; | |
445 | struct idt82p33 *idt82p33 = channel->idt82p33; | |
446 | int err; | |
447 | ||
448 | idt82p33->tod_write_overhead_ns = 0; | |
449 | ||
450 | err = idt82p33_measure_settime_gettime_gap_overhead(channel, &gap_ns); | |
451 | ||
e014ae39 ML |
452 | if (err) { |
453 | dev_err(&idt82p33->client->dev, | |
454 | "Failed in %s with err %d!\n", __func__, err); | |
57a10d8c | 455 | return err; |
e014ae39 | 456 | } |
57a10d8c ML |
457 | |
458 | err = idt82p33_measure_one_byte_write_overhead(channel, | |
459 | &one_byte_write_ns); | |
460 | ||
461 | if (err) | |
462 | return err; | |
463 | ||
464 | err = idt82p33_measure_tod_write_9_byte_overhead(channel); | |
465 | ||
466 | if (err) | |
467 | return err; | |
468 | ||
469 | trailing_overhead_ns = gap_ns - (2 * one_byte_write_ns); | |
470 | ||
471 | idt82p33->tod_write_overhead_ns -= trailing_overhead_ns; | |
472 | ||
473 | return err; | |
474 | } | |
475 | ||
476 | static int idt82p33_check_and_set_masks(struct idt82p33 *idt82p33, | |
477 | u8 page, | |
478 | u8 offset, | |
479 | u8 val) | |
480 | { | |
481 | int err = 0; | |
482 | ||
483 | if (page == PLLMASK_ADDR_HI && offset == PLLMASK_ADDR_LO) { | |
484 | if ((val & 0xfc) || !(val & 0x3)) { | |
485 | dev_err(&idt82p33->client->dev, | |
486 | "Invalid PLL mask 0x%hhx\n", val); | |
487 | err = -EINVAL; | |
488 | } else { | |
489 | idt82p33->pll_mask = val; | |
490 | } | |
491 | } else if (page == PLL0_OUTMASK_ADDR_HI && | |
492 | offset == PLL0_OUTMASK_ADDR_LO) { | |
493 | idt82p33->channel[0].output_mask = val; | |
494 | } else if (page == PLL1_OUTMASK_ADDR_HI && | |
495 | offset == PLL1_OUTMASK_ADDR_LO) { | |
496 | idt82p33->channel[1].output_mask = val; | |
497 | } | |
498 | ||
499 | return err; | |
500 | } | |
501 | ||
502 | static void idt82p33_display_masks(struct idt82p33 *idt82p33) | |
503 | { | |
504 | u8 mask, i; | |
505 | ||
506 | dev_info(&idt82p33->client->dev, | |
507 | "pllmask = 0x%02x\n", idt82p33->pll_mask); | |
508 | ||
509 | for (i = 0; i < MAX_PHC_PLL; i++) { | |
510 | mask = 1 << i; | |
511 | ||
512 | if (mask & idt82p33->pll_mask) | |
513 | dev_info(&idt82p33->client->dev, | |
514 | "PLL%d output_mask = 0x%04x\n", | |
515 | i, idt82p33->channel[i].output_mask); | |
516 | } | |
517 | } | |
518 | ||
519 | static int idt82p33_sync_tod(struct idt82p33_channel *channel, bool enable) | |
520 | { | |
521 | struct idt82p33 *idt82p33 = channel->idt82p33; | |
522 | u8 sync_cnfg; | |
523 | int err; | |
524 | ||
e014ae39 ML |
525 | /* Turn it off after sync_tod_timeout seconds */ |
526 | if (enable && sync_tod_timeout) | |
527 | ptp_schedule_worker(channel->ptp_clock, | |
528 | sync_tod_timeout * HZ); | |
57a10d8c ML |
529 | |
530 | err = idt82p33_read(idt82p33, channel->dpll_sync_cnfg, | |
531 | &sync_cnfg, sizeof(sync_cnfg)); | |
532 | if (err) | |
533 | return err; | |
534 | ||
535 | sync_cnfg &= ~SYNC_TOD; | |
57a10d8c ML |
536 | if (enable) |
537 | sync_cnfg |= SYNC_TOD; | |
538 | ||
e014ae39 ML |
539 | return idt82p33_write(idt82p33, channel->dpll_sync_cnfg, |
540 | &sync_cnfg, sizeof(sync_cnfg)); | |
57a10d8c ML |
541 | } |
542 | ||
e014ae39 | 543 | static long idt82p33_sync_tod_work_handler(struct ptp_clock_info *ptp) |
57a10d8c ML |
544 | { |
545 | struct idt82p33_channel *channel = | |
e014ae39 | 546 | container_of(ptp, struct idt82p33_channel, caps); |
57a10d8c ML |
547 | struct idt82p33 *idt82p33 = channel->idt82p33; |
548 | ||
549 | mutex_lock(&idt82p33->reg_lock); | |
550 | ||
551 | (void)idt82p33_sync_tod(channel, false); | |
552 | ||
553 | mutex_unlock(&idt82p33->reg_lock); | |
e014ae39 ML |
554 | |
555 | /* Return a negative value here to not reschedule */ | |
556 | return -1; | |
57a10d8c ML |
557 | } |
558 | ||
e014ae39 ML |
559 | static int idt82p33_output_enable(struct idt82p33_channel *channel, |
560 | bool enable, unsigned int outn) | |
57a10d8c ML |
561 | { |
562 | struct idt82p33 *idt82p33 = channel->idt82p33; | |
57a10d8c | 563 | int err; |
e014ae39 ML |
564 | u8 val; |
565 | ||
566 | err = idt82p33_read(idt82p33, OUT_MUX_CNFG(outn), &val, sizeof(val)); | |
567 | if (err) | |
568 | return err; | |
569 | if (enable) | |
570 | val &= ~SQUELCH_ENABLE; | |
571 | else | |
572 | val |= SQUELCH_ENABLE; | |
573 | ||
574 | return idt82p33_write(idt82p33, OUT_MUX_CNFG(outn), &val, sizeof(val)); | |
575 | } | |
576 | ||
577 | static int idt82p33_output_mask_enable(struct idt82p33_channel *channel, | |
578 | bool enable) | |
579 | { | |
580 | u16 mask; | |
581 | int err; | |
582 | u8 outn; | |
57a10d8c ML |
583 | |
584 | mask = channel->output_mask; | |
585 | outn = 0; | |
586 | ||
587 | while (mask) { | |
588 | if (mask & 0x1) { | |
e014ae39 | 589 | err = idt82p33_output_enable(channel, enable, outn); |
57a10d8c ML |
590 | if (err) |
591 | return err; | |
592 | } | |
e014ae39 | 593 | |
57a10d8c ML |
594 | mask >>= 0x1; |
595 | outn++; | |
596 | } | |
597 | ||
598 | return 0; | |
599 | } | |
600 | ||
e014ae39 ML |
601 | static int idt82p33_perout_enable(struct idt82p33_channel *channel, |
602 | bool enable, | |
603 | struct ptp_perout_request *perout) | |
604 | { | |
605 | unsigned int flags = perout->flags; | |
606 | ||
607 | /* Enable/disable output based on output_mask */ | |
608 | if (flags == PEROUT_ENABLE_OUTPUT_MASK) | |
609 | return idt82p33_output_mask_enable(channel, enable); | |
610 | ||
611 | /* Enable/disable individual output instead */ | |
612 | return idt82p33_output_enable(channel, enable, perout->index); | |
613 | } | |
614 | ||
57a10d8c ML |
615 | static int idt82p33_enable_tod(struct idt82p33_channel *channel) |
616 | { | |
617 | struct idt82p33 *idt82p33 = channel->idt82p33; | |
618 | struct timespec64 ts = {0, 0}; | |
619 | int err; | |
620 | u8 val; | |
621 | ||
622 | val = 0; | |
623 | err = idt82p33_write(idt82p33, channel->dpll_input_mode_cnfg, | |
624 | &val, sizeof(val)); | |
625 | if (err) | |
626 | return err; | |
627 | ||
57a10d8c ML |
628 | err = idt82p33_measure_tod_write_overhead(channel); |
629 | ||
e014ae39 ML |
630 | if (err) { |
631 | dev_err(&idt82p33->client->dev, | |
632 | "Failed in %s with err %d!\n", __func__, err); | |
57a10d8c | 633 | return err; |
e014ae39 | 634 | } |
57a10d8c ML |
635 | |
636 | err = _idt82p33_settime(channel, &ts); | |
637 | ||
638 | if (err) | |
639 | return err; | |
640 | ||
641 | return idt82p33_sync_tod(channel, true); | |
642 | } | |
643 | ||
644 | static void idt82p33_ptp_clock_unregister_all(struct idt82p33 *idt82p33) | |
645 | { | |
646 | struct idt82p33_channel *channel; | |
647 | u8 i; | |
648 | ||
649 | for (i = 0; i < MAX_PHC_PLL; i++) { | |
650 | ||
651 | channel = &idt82p33->channel[i]; | |
652 | ||
e014ae39 | 653 | if (channel->ptp_clock) |
57a10d8c | 654 | ptp_clock_unregister(channel->ptp_clock); |
57a10d8c ML |
655 | } |
656 | } | |
657 | ||
658 | static int idt82p33_enable(struct ptp_clock_info *ptp, | |
659 | struct ptp_clock_request *rq, int on) | |
660 | { | |
661 | struct idt82p33_channel *channel = | |
662 | container_of(ptp, struct idt82p33_channel, caps); | |
663 | struct idt82p33 *idt82p33 = channel->idt82p33; | |
664 | int err; | |
665 | ||
666 | err = -EOPNOTSUPP; | |
667 | ||
668 | mutex_lock(&idt82p33->reg_lock); | |
669 | ||
670 | if (rq->type == PTP_CLK_REQ_PEROUT) { | |
671 | if (!on) | |
e014ae39 ML |
672 | err = idt82p33_perout_enable(channel, false, |
673 | &rq->perout); | |
57a10d8c ML |
674 | /* Only accept a 1-PPS aligned to the second. */ |
675 | else if (rq->perout.start.nsec || rq->perout.period.sec != 1 || | |
676 | rq->perout.period.nsec) { | |
677 | err = -ERANGE; | |
678 | } else | |
e014ae39 ML |
679 | err = idt82p33_perout_enable(channel, true, |
680 | &rq->perout); | |
57a10d8c ML |
681 | } |
682 | ||
683 | mutex_unlock(&idt82p33->reg_lock); | |
684 | ||
685 | return err; | |
686 | } | |
687 | ||
e014ae39 ML |
688 | static int idt82p33_adjwritephase(struct ptp_clock_info *ptp, s32 offset_ns) |
689 | { | |
690 | struct idt82p33_channel *channel = | |
691 | container_of(ptp, struct idt82p33_channel, caps); | |
692 | struct idt82p33 *idt82p33 = channel->idt82p33; | |
693 | s64 offset_regval, offset_fs; | |
694 | u8 val[4] = {0}; | |
695 | int err; | |
696 | ||
697 | offset_fs = (s64)(-offset_ns) * 1000000; | |
698 | ||
699 | if (offset_fs > WRITE_PHASE_OFFSET_LIMIT) | |
700 | offset_fs = WRITE_PHASE_OFFSET_LIMIT; | |
701 | else if (offset_fs < -WRITE_PHASE_OFFSET_LIMIT) | |
702 | offset_fs = -WRITE_PHASE_OFFSET_LIMIT; | |
703 | ||
704 | /* Convert from phaseoffset_fs to register value */ | |
705 | offset_regval = div_s64(offset_fs * 1000, IDT_T0DPLL_PHASE_RESOL); | |
706 | ||
707 | val[0] = offset_regval & 0xFF; | |
708 | val[1] = (offset_regval >> 8) & 0xFF; | |
709 | val[2] = (offset_regval >> 16) & 0xFF; | |
710 | val[3] = (offset_regval >> 24) & 0x1F; | |
711 | val[3] |= PH_OFFSET_EN; | |
712 | ||
713 | mutex_lock(&idt82p33->reg_lock); | |
714 | ||
715 | err = idt82p33_dpll_set_mode(channel, PLL_MODE_WPH); | |
716 | if (err) { | |
717 | dev_err(&idt82p33->client->dev, | |
718 | "Failed in %s with err %d!\n", __func__, err); | |
719 | goto out; | |
720 | } | |
721 | ||
722 | err = idt82p33_write(idt82p33, channel->dpll_phase_cnfg, val, | |
723 | sizeof(val)); | |
724 | ||
725 | out: | |
726 | mutex_unlock(&idt82p33->reg_lock); | |
727 | return err; | |
728 | } | |
729 | ||
57a10d8c ML |
730 | static int idt82p33_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) |
731 | { | |
732 | struct idt82p33_channel *channel = | |
733 | container_of(ptp, struct idt82p33_channel, caps); | |
734 | struct idt82p33 *idt82p33 = channel->idt82p33; | |
735 | int err; | |
736 | ||
737 | mutex_lock(&idt82p33->reg_lock); | |
738 | err = _idt82p33_adjfine(channel, scaled_ppm); | |
e014ae39 ML |
739 | if (err) |
740 | dev_err(&idt82p33->client->dev, | |
741 | "Failed in %s with err %d!\n", __func__, err); | |
57a10d8c ML |
742 | mutex_unlock(&idt82p33->reg_lock); |
743 | ||
744 | return err; | |
745 | } | |
746 | ||
747 | static int idt82p33_adjtime(struct ptp_clock_info *ptp, s64 delta_ns) | |
748 | { | |
749 | struct idt82p33_channel *channel = | |
750 | container_of(ptp, struct idt82p33_channel, caps); | |
751 | struct idt82p33 *idt82p33 = channel->idt82p33; | |
752 | int err; | |
753 | ||
754 | mutex_lock(&idt82p33->reg_lock); | |
755 | ||
756 | if (abs(delta_ns) < phase_snap_threshold) { | |
757 | mutex_unlock(&idt82p33->reg_lock); | |
758 | return 0; | |
759 | } | |
760 | ||
761 | err = _idt82p33_adjtime(channel, delta_ns); | |
762 | ||
763 | if (err) { | |
764 | mutex_unlock(&idt82p33->reg_lock); | |
e014ae39 ML |
765 | dev_err(&idt82p33->client->dev, |
766 | "Adjtime failed in %s with err %d!\n", __func__, err); | |
57a10d8c ML |
767 | return err; |
768 | } | |
769 | ||
770 | err = idt82p33_sync_tod(channel, true); | |
e014ae39 ML |
771 | if (err) |
772 | dev_err(&idt82p33->client->dev, | |
773 | "Sync_tod failed in %s with err %d!\n", __func__, err); | |
57a10d8c ML |
774 | |
775 | mutex_unlock(&idt82p33->reg_lock); | |
776 | ||
777 | return err; | |
778 | } | |
779 | ||
780 | static int idt82p33_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) | |
781 | { | |
782 | struct idt82p33_channel *channel = | |
783 | container_of(ptp, struct idt82p33_channel, caps); | |
784 | struct idt82p33 *idt82p33 = channel->idt82p33; | |
785 | int err; | |
786 | ||
787 | mutex_lock(&idt82p33->reg_lock); | |
788 | err = _idt82p33_gettime(channel, ts); | |
e014ae39 ML |
789 | if (err) |
790 | dev_err(&idt82p33->client->dev, | |
791 | "Failed in %s with err %d!\n", __func__, err); | |
57a10d8c ML |
792 | mutex_unlock(&idt82p33->reg_lock); |
793 | ||
794 | return err; | |
795 | } | |
796 | ||
797 | static int idt82p33_settime(struct ptp_clock_info *ptp, | |
798 | const struct timespec64 *ts) | |
799 | { | |
800 | struct idt82p33_channel *channel = | |
801 | container_of(ptp, struct idt82p33_channel, caps); | |
802 | struct idt82p33 *idt82p33 = channel->idt82p33; | |
803 | int err; | |
804 | ||
805 | mutex_lock(&idt82p33->reg_lock); | |
806 | err = _idt82p33_settime(channel, ts); | |
e014ae39 ML |
807 | if (err) |
808 | dev_err(&idt82p33->client->dev, | |
809 | "Failed in %s with err %d!\n", __func__, err); | |
57a10d8c ML |
810 | mutex_unlock(&idt82p33->reg_lock); |
811 | ||
812 | return err; | |
813 | } | |
814 | ||
815 | static int idt82p33_channel_init(struct idt82p33_channel *channel, int index) | |
816 | { | |
817 | switch (index) { | |
818 | case 0: | |
819 | channel->dpll_tod_cnfg = DPLL1_TOD_CNFG; | |
820 | channel->dpll_tod_trigger = DPLL1_TOD_TRIGGER; | |
821 | channel->dpll_tod_sts = DPLL1_TOD_STS; | |
822 | channel->dpll_mode_cnfg = DPLL1_OPERATING_MODE_CNFG; | |
823 | channel->dpll_freq_cnfg = DPLL1_HOLDOVER_FREQ_CNFG; | |
824 | channel->dpll_phase_cnfg = DPLL1_PHASE_OFFSET_CNFG; | |
825 | channel->dpll_sync_cnfg = DPLL1_SYNC_EDGE_CNFG; | |
826 | channel->dpll_input_mode_cnfg = DPLL1_INPUT_MODE_CNFG; | |
827 | break; | |
828 | case 1: | |
829 | channel->dpll_tod_cnfg = DPLL2_TOD_CNFG; | |
830 | channel->dpll_tod_trigger = DPLL2_TOD_TRIGGER; | |
831 | channel->dpll_tod_sts = DPLL2_TOD_STS; | |
832 | channel->dpll_mode_cnfg = DPLL2_OPERATING_MODE_CNFG; | |
833 | channel->dpll_freq_cnfg = DPLL2_HOLDOVER_FREQ_CNFG; | |
834 | channel->dpll_phase_cnfg = DPLL2_PHASE_OFFSET_CNFG; | |
835 | channel->dpll_sync_cnfg = DPLL2_SYNC_EDGE_CNFG; | |
836 | channel->dpll_input_mode_cnfg = DPLL2_INPUT_MODE_CNFG; | |
837 | break; | |
838 | default: | |
839 | return -EINVAL; | |
840 | } | |
841 | ||
57a10d8c ML |
842 | channel->current_freq_ppb = 0; |
843 | ||
844 | return 0; | |
845 | } | |
846 | ||
847 | static void idt82p33_caps_init(struct ptp_clock_info *caps) | |
848 | { | |
849 | caps->owner = THIS_MODULE; | |
850 | caps->max_adj = 92000; | |
e014ae39 ML |
851 | caps->n_per_out = 11; |
852 | caps->adjphase = idt82p33_adjwritephase; | |
57a10d8c ML |
853 | caps->adjfine = idt82p33_adjfine; |
854 | caps->adjtime = idt82p33_adjtime; | |
855 | caps->gettime64 = idt82p33_gettime; | |
856 | caps->settime64 = idt82p33_settime; | |
857 | caps->enable = idt82p33_enable; | |
e014ae39 | 858 | caps->do_aux_work = idt82p33_sync_tod_work_handler; |
57a10d8c ML |
859 | } |
860 | ||
861 | static int idt82p33_enable_channel(struct idt82p33 *idt82p33, u32 index) | |
862 | { | |
863 | struct idt82p33_channel *channel; | |
864 | int err; | |
865 | ||
866 | if (!(index < MAX_PHC_PLL)) | |
867 | return -EINVAL; | |
868 | ||
869 | channel = &idt82p33->channel[index]; | |
870 | ||
871 | err = idt82p33_channel_init(channel, index); | |
e014ae39 ML |
872 | if (err) { |
873 | dev_err(&idt82p33->client->dev, | |
874 | "Channel_init failed in %s with err %d!\n", | |
875 | __func__, err); | |
57a10d8c | 876 | return err; |
e014ae39 | 877 | } |
57a10d8c ML |
878 | |
879 | channel->idt82p33 = idt82p33; | |
880 | ||
881 | idt82p33_caps_init(&channel->caps); | |
882 | snprintf(channel->caps.name, sizeof(channel->caps.name), | |
883 | "IDT 82P33 PLL%u", index); | |
57a10d8c ML |
884 | |
885 | channel->ptp_clock = ptp_clock_register(&channel->caps, NULL); | |
886 | ||
887 | if (IS_ERR(channel->ptp_clock)) { | |
888 | err = PTR_ERR(channel->ptp_clock); | |
889 | channel->ptp_clock = NULL; | |
890 | return err; | |
891 | } | |
892 | ||
893 | if (!channel->ptp_clock) | |
894 | return -ENOTSUPP; | |
895 | ||
e014ae39 ML |
896 | err = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO); |
897 | if (err) { | |
898 | dev_err(&idt82p33->client->dev, | |
899 | "Dpll_set_mode failed in %s with err %d!\n", | |
900 | __func__, err); | |
901 | return err; | |
902 | } | |
903 | ||
904 | err = idt82p33_enable_tod(channel); | |
905 | if (err) { | |
906 | dev_err(&idt82p33->client->dev, | |
907 | "Enable_tod failed in %s with err %d!\n", | |
908 | __func__, err); | |
909 | return err; | |
910 | } | |
911 | ||
57a10d8c ML |
912 | dev_info(&idt82p33->client->dev, "PLL%d registered as ptp%d\n", |
913 | index, channel->ptp_clock->index); | |
914 | ||
915 | return 0; | |
916 | } | |
917 | ||
918 | static int idt82p33_load_firmware(struct idt82p33 *idt82p33) | |
919 | { | |
920 | const struct firmware *fw; | |
921 | struct idt82p33_fwrc *rec; | |
922 | u8 loaddr, page, val; | |
923 | int err; | |
924 | s32 len; | |
925 | ||
926 | dev_dbg(&idt82p33->client->dev, | |
927 | "requesting firmware '%s'\n", FW_FILENAME); | |
928 | ||
929 | err = request_firmware(&fw, FW_FILENAME, &idt82p33->client->dev); | |
930 | ||
e014ae39 ML |
931 | if (err) { |
932 | dev_err(&idt82p33->client->dev, | |
933 | "Failed in %s with err %d!\n", __func__, err); | |
57a10d8c | 934 | return err; |
e014ae39 | 935 | } |
57a10d8c ML |
936 | |
937 | dev_dbg(&idt82p33->client->dev, "firmware size %zu bytes\n", fw->size); | |
938 | ||
939 | rec = (struct idt82p33_fwrc *) fw->data; | |
940 | ||
941 | for (len = fw->size; len > 0; len -= sizeof(*rec)) { | |
942 | ||
943 | if (rec->reserved) { | |
944 | dev_err(&idt82p33->client->dev, | |
945 | "bad firmware, reserved field non-zero\n"); | |
946 | err = -EINVAL; | |
947 | } else { | |
948 | val = rec->value; | |
949 | loaddr = rec->loaddr; | |
950 | page = rec->hiaddr; | |
951 | ||
952 | rec++; | |
953 | ||
954 | err = idt82p33_check_and_set_masks(idt82p33, page, | |
955 | loaddr, val); | |
956 | } | |
957 | ||
958 | if (err == 0) { | |
959 | /* maximum 8 pages */ | |
960 | if (page >= PAGE_NUM) | |
961 | continue; | |
962 | ||
963 | /* Page size 128, last 4 bytes of page skipped */ | |
964 | if (((loaddr > 0x7b) && (loaddr <= 0x7f)) | |
6033cebd | 965 | || loaddr > 0xfb) |
57a10d8c ML |
966 | continue; |
967 | ||
968 | err = idt82p33_write(idt82p33, _ADDR(page, loaddr), | |
969 | &val, sizeof(val)); | |
970 | } | |
971 | ||
972 | if (err) | |
973 | goto out; | |
974 | } | |
975 | ||
976 | idt82p33_display_masks(idt82p33); | |
977 | out: | |
978 | release_firmware(fw); | |
979 | return err; | |
980 | } | |
981 | ||
982 | ||
983 | static int idt82p33_probe(struct i2c_client *client, | |
984 | const struct i2c_device_id *id) | |
985 | { | |
986 | struct idt82p33 *idt82p33; | |
987 | int err; | |
988 | u8 i; | |
989 | ||
990 | (void)id; | |
991 | ||
992 | idt82p33 = devm_kzalloc(&client->dev, | |
993 | sizeof(struct idt82p33), GFP_KERNEL); | |
994 | if (!idt82p33) | |
995 | return -ENOMEM; | |
996 | ||
997 | mutex_init(&idt82p33->reg_lock); | |
998 | ||
999 | idt82p33->client = client; | |
1000 | idt82p33->page_offset = 0xff; | |
1001 | idt82p33->tod_write_overhead_ns = 0; | |
1002 | idt82p33->calculate_overhead_flag = 0; | |
1003 | idt82p33->pll_mask = DEFAULT_PLL_MASK; | |
1004 | idt82p33->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0; | |
1005 | idt82p33->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1; | |
1006 | ||
1007 | mutex_lock(&idt82p33->reg_lock); | |
1008 | ||
1009 | err = idt82p33_load_firmware(idt82p33); | |
1010 | ||
1011 | if (err) | |
1012 | dev_warn(&idt82p33->client->dev, | |
1013 | "loading firmware failed with %d\n", err); | |
1014 | ||
1015 | if (idt82p33->pll_mask) { | |
1016 | for (i = 0; i < MAX_PHC_PLL; i++) { | |
1017 | if (idt82p33->pll_mask & (1 << i)) { | |
1018 | err = idt82p33_enable_channel(idt82p33, i); | |
e014ae39 ML |
1019 | if (err) { |
1020 | dev_err(&idt82p33->client->dev, | |
1021 | "Failed in %s with err %d!\n", | |
1022 | __func__, err); | |
57a10d8c | 1023 | break; |
e014ae39 | 1024 | } |
57a10d8c ML |
1025 | } |
1026 | } | |
1027 | } else { | |
1028 | dev_err(&idt82p33->client->dev, | |
1029 | "no PLLs flagged as PHCs, nothing to do\n"); | |
1030 | err = -ENODEV; | |
1031 | } | |
1032 | ||
1033 | mutex_unlock(&idt82p33->reg_lock); | |
1034 | ||
1035 | if (err) { | |
1036 | idt82p33_ptp_clock_unregister_all(idt82p33); | |
1037 | return err; | |
1038 | } | |
1039 | ||
1040 | i2c_set_clientdata(client, idt82p33); | |
1041 | ||
1042 | return 0; | |
1043 | } | |
1044 | ||
1045 | static int idt82p33_remove(struct i2c_client *client) | |
1046 | { | |
1047 | struct idt82p33 *idt82p33 = i2c_get_clientdata(client); | |
1048 | ||
1049 | idt82p33_ptp_clock_unregister_all(idt82p33); | |
1050 | mutex_destroy(&idt82p33->reg_lock); | |
1051 | ||
1052 | return 0; | |
1053 | } | |
1054 | ||
1055 | #ifdef CONFIG_OF | |
1056 | static const struct of_device_id idt82p33_dt_id[] = { | |
1057 | { .compatible = "idt,82p33810" }, | |
1058 | { .compatible = "idt,82p33813" }, | |
1059 | { .compatible = "idt,82p33814" }, | |
1060 | { .compatible = "idt,82p33831" }, | |
1061 | { .compatible = "idt,82p33910" }, | |
1062 | { .compatible = "idt,82p33913" }, | |
1063 | { .compatible = "idt,82p33914" }, | |
1064 | { .compatible = "idt,82p33931" }, | |
1065 | {}, | |
1066 | }; | |
1067 | MODULE_DEVICE_TABLE(of, idt82p33_dt_id); | |
1068 | #endif | |
1069 | ||
1070 | static const struct i2c_device_id idt82p33_i2c_id[] = { | |
1071 | { "idt82p33810", }, | |
1072 | { "idt82p33813", }, | |
1073 | { "idt82p33814", }, | |
1074 | { "idt82p33831", }, | |
1075 | { "idt82p33910", }, | |
1076 | { "idt82p33913", }, | |
1077 | { "idt82p33914", }, | |
1078 | { "idt82p33931", }, | |
1079 | {}, | |
1080 | }; | |
1081 | MODULE_DEVICE_TABLE(i2c, idt82p33_i2c_id); | |
1082 | ||
1083 | static struct i2c_driver idt82p33_driver = { | |
1084 | .driver = { | |
1085 | .of_match_table = of_match_ptr(idt82p33_dt_id), | |
1086 | .name = "idt82p33", | |
1087 | }, | |
1088 | .probe = idt82p33_probe, | |
1089 | .remove = idt82p33_remove, | |
1090 | .id_table = idt82p33_i2c_id, | |
1091 | }; | |
1092 | ||
1093 | module_i2c_driver(idt82p33_driver); |