[mirror_ubuntu-jammy-kernel.git] / drivers / ptp / ptp_ixp46x.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * PTP 1588 clock using the IXP46X
 *
 * Copyright (C) 2010 OMICRON electronics GmbH
 */
#include <linux/device.h>
#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>

#include <linux/ptp_clock_kernel.h>
#include <mach/ixp46x_ts.h>

#define DRIVER		"ptp_ixp46x"
#define N_EXT_TS	2
#define MASTER_GPIO	8
#define MASTER_IRQ	25
#define SLAVE_GPIO	7
#define SLAVE_IRQ	24

struct ixp_clock {
	struct ixp46x_ts_regs *regs;
	struct ptp_clock *ptp_clock;
	struct ptp_clock_info caps;
	int exts0_enabled;
	int exts1_enabled;
};

DEFINE_SPINLOCK(register_lock);

/*
 * Register access functions
 */

static u64 ixp_systime_read(struct ixp46x_ts_regs *regs)
{
	u64 ns;
	u32 lo, hi;

	lo = __raw_readl(&regs->systime_lo);
	hi = __raw_readl(&regs->systime_hi);

	ns = ((u64) hi) << 32;
	ns |= lo;
	ns <<= TICKS_NS_SHIFT;

	return ns;
}

static void ixp_systime_write(struct ixp46x_ts_regs *regs, u64 ns)
{
	u32 hi, lo;

	ns >>= TICKS_NS_SHIFT;
	hi = ns >> 32;
	lo = ns & 0xffffffff;

	__raw_writel(lo, &regs->systime_lo);
	__raw_writel(hi, &regs->systime_hi);
}

/*
 * Interrupt service routine
 */

static irqreturn_t isr(int irq, void *priv)
{
	struct ixp_clock *ixp_clock = priv;
	struct ixp46x_ts_regs *regs = ixp_clock->regs;
	struct ptp_clock_event event;
	u32 ack = 0, lo, hi, val;

	val = __raw_readl(&regs->event);

	if (val & TSER_SNS) {
		ack |= TSER_SNS;
		if (ixp_clock->exts0_enabled) {
			hi = __raw_readl(&regs->asms_hi);
			lo = __raw_readl(&regs->asms_lo);
			event.type = PTP_CLOCK_EXTTS;
			event.index = 0;
			event.timestamp = ((u64) hi) << 32;
			event.timestamp |= lo;
			event.timestamp <<= TICKS_NS_SHIFT;
			ptp_clock_event(ixp_clock->ptp_clock, &event);
		}
	}

	if (val & TSER_SNM) {
		ack |= TSER_SNM;
		if (ixp_clock->exts1_enabled) {
			hi = __raw_readl(&regs->amms_hi);
			lo = __raw_readl(&regs->amms_lo);
			event.type = PTP_CLOCK_EXTTS;
			event.index = 1;
			event.timestamp = ((u64) hi) << 32;
			event.timestamp |= lo;
			event.timestamp <<= TICKS_NS_SHIFT;
			ptp_clock_event(ixp_clock->ptp_clock, &event);
		}
	}

	if (val & TTIPEND)
		ack |= TTIPEND; /* this bit seems to be always set */

	if (ack) {
		__raw_writel(ack, &regs->event);
		return IRQ_HANDLED;
	} else
		return IRQ_NONE;
}

/*
 * PTP clock operations
 */

static int ptp_ixp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
{
	u64 adj;
	u32 diff, addend;
	int neg_adj = 0;
	struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps);
	struct ixp46x_ts_regs *regs = ixp_clock->regs;

	if (ppb < 0) {
		neg_adj = 1;
		ppb = -ppb;
	}
	addend = DEFAULT_ADDEND;
	adj = addend;
	adj *= ppb;
	diff = div_u64(adj, 1000000000ULL);

	addend = neg_adj ? addend - diff : addend + diff;

	__raw_writel(addend, &regs->addend);

	return 0;
}

static int ptp_ixp_adjtime(struct ptp_clock_info *ptp, s64 delta)
{
	s64 now;
	unsigned long flags;
	struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps);
	struct ixp46x_ts_regs *regs = ixp_clock->regs;

	spin_lock_irqsave(&register_lock, flags);

	now = ixp_systime_read(regs);
	now += delta;
	ixp_systime_write(regs, now);

	spin_unlock_irqrestore(&register_lock, flags);

	return 0;
}

static int ptp_ixp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
{
	u64 ns;
	unsigned long flags;
	struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps);
	struct ixp46x_ts_regs *regs = ixp_clock->regs;

	spin_lock_irqsave(&register_lock, flags);

	ns = ixp_systime_read(regs);

	spin_unlock_irqrestore(&register_lock, flags);

	*ts = ns_to_timespec64(ns);
	return 0;
}

static int ptp_ixp_settime(struct ptp_clock_info *ptp,
			   const struct timespec64 *ts)
{
	u64 ns;
	unsigned long flags;
	struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps);
	struct ixp46x_ts_regs *regs = ixp_clock->regs;

	ns = timespec64_to_ns(ts);

	spin_lock_irqsave(&register_lock, flags);

	ixp_systime_write(regs, ns);

	spin_unlock_irqrestore(&register_lock, flags);

	return 0;
}

static int ptp_ixp_enable(struct ptp_clock_info *ptp,
			  struct ptp_clock_request *rq, int on)
{
	struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps);

	switch (rq->type) {
	case PTP_CLK_REQ_EXTTS:
		switch (rq->extts.index) {
		case 0:
			ixp_clock->exts0_enabled = on ? 1 : 0;
			break;
		case 1:
			ixp_clock->exts1_enabled = on ? 1 : 0;
			break;
		default:
			return -EINVAL;
		}
		return 0;
	default:
		break;
	}

	return -EOPNOTSUPP;
}

static const struct ptp_clock_info ptp_ixp_caps = {
	.owner		= THIS_MODULE,
	.name		= "IXP46X timer",
	.max_adj	= 66666655,
	.n_ext_ts	= N_EXT_TS,
	.n_pins		= 0,
	.pps		= 0,
	.adjfreq	= ptp_ixp_adjfreq,
	.adjtime	= ptp_ixp_adjtime,
	.gettime64	= ptp_ixp_gettime,
	.settime64	= ptp_ixp_settime,
	.enable		= ptp_ixp_enable,
};

/* module operations */

static struct ixp_clock ixp_clock;

static int setup_interrupt(int gpio)
{
	int irq;
	int err;

	err = gpio_request(gpio, "ixp4-ptp");
	if (err)
		return err;

	err = gpio_direction_input(gpio);
	if (err)
		return err;

	irq = gpio_to_irq(gpio);
	if (irq < 0)
		return irq;

	err = irq_set_irq_type(irq, IRQF_TRIGGER_FALLING);
	if (err) {
		pr_err("cannot set trigger type for irq %d\n", irq);
		return err;
	}

	err = request_irq(irq, isr, 0, DRIVER, &ixp_clock);
	if (err) {
		pr_err("request_irq failed for irq %d\n", irq);
		return err;
	}

	return irq;
}

static void __exit ptp_ixp_exit(void)
{
	free_irq(MASTER_IRQ, &ixp_clock);
	free_irq(SLAVE_IRQ, &ixp_clock);
	ixp46x_phc_index = -1;
	ptp_clock_unregister(ixp_clock.ptp_clock);
}

static int __init ptp_ixp_init(void)
{
	if (!cpu_is_ixp46x())
		return -ENODEV;

	ixp_clock.regs =
		(struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;

	ixp_clock.caps = ptp_ixp_caps;

	ixp_clock.ptp_clock = ptp_clock_register(&ixp_clock.caps, NULL);

	if (IS_ERR(ixp_clock.ptp_clock))
		return PTR_ERR(ixp_clock.ptp_clock);

	ixp46x_phc_index = ptp_clock_index(ixp_clock.ptp_clock);

	__raw_writel(DEFAULT_ADDEND, &ixp_clock.regs->addend);
	__raw_writel(1, &ixp_clock.regs->trgt_lo);
	__raw_writel(0, &ixp_clock.regs->trgt_hi);
	__raw_writel(TTIPEND, &ixp_clock.regs->event);

	if (MASTER_IRQ != setup_interrupt(MASTER_GPIO)) {
		pr_err("failed to setup gpio %d as irq\n", MASTER_GPIO);
		goto no_master;
	}
	if (SLAVE_IRQ != setup_interrupt(SLAVE_GPIO)) {
		pr_err("failed to setup gpio %d as irq\n", SLAVE_GPIO);
		goto no_slave;
	}

	return 0;
no_slave:
	free_irq(MASTER_IRQ, &ixp_clock);
no_master:
	ptp_clock_unregister(ixp_clock.ptp_clock);
	return -ENODEV;
}

module_init(ptp_ixp_init);
module_exit(ptp_ixp_exit);

MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
MODULE_DESCRIPTION("PTP clock using the IXP46X timer");
MODULE_LICENSE("GPL");
Commit	Line	Data
74ba9207	1	// SPDX-License-Identifier: GPL-2.0-or-later
32bd93e8 RC	2	/*
	3	* PTP 1588 clock using the IXP46X
	4	*
	5	* Copyright (C) 2010 OMICRON electronics GmbH
32bd93e8 RC	6	*/
	7	#include <linux/device.h>
	8	#include <linux/err.h>
	9	#include <linux/gpio.h>
	10	#include <linux/init.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/io.h>
	13	#include <linux/irq.h>
	14	#include <linux/kernel.h>
	15	#include <linux/module.h>
	16
	17	#include <linux/ptp_clock_kernel.h>
	18	#include <mach/ixp46x_ts.h>
	19
	20	#define DRIVER "ptp_ixp46x"
	21	#define N_EXT_TS 2
	22	#define MASTER_GPIO 8
	23	#define MASTER_IRQ 25
	24	#define SLAVE_GPIO 7
	25	#define SLAVE_IRQ 24
	26
	27	struct ixp_clock {
	28	struct ixp46x_ts_regs *regs;
	29	struct ptp_clock *ptp_clock;
	30	struct ptp_clock_info caps;
	31	int exts0_enabled;
	32	int exts1_enabled;
	33	};
	34
	35	DEFINE_SPINLOCK(register_lock);
	36
	37	/*
	38	* Register access functions
	39	*/
	40
	41	static u64 ixp_systime_read(struct ixp46x_ts_regs *regs)
	42	{
	43	u64 ns;
	44	u32 lo, hi;
	45
	46	lo = __raw_readl(&regs->systime_lo);
	47	hi = __raw_readl(&regs->systime_hi);
	48
	49	ns = ((u64) hi) << 32;
	50	ns \|= lo;
	51	ns <<= TICKS_NS_SHIFT;
	52
	53	return ns;
	54	}
	55
	56	static void ixp_systime_write(struct ixp46x_ts_regs *regs, u64 ns)
	57	{
	58	u32 hi, lo;
	59
	60	ns >>= TICKS_NS_SHIFT;
	61	hi = ns >> 32;
	62	lo = ns & 0xffffffff;
	63
	64	__raw_writel(lo, &regs->systime_lo);
	65	__raw_writel(hi, &regs->systime_hi);
	66	}
	67
	68	/*
	69	* Interrupt service routine
70	*/
71
72	static irqreturn_t isr(int irq, void *priv)
73	{
74	struct ixp_clock *ixp_clock = priv;
75	struct ixp46x_ts_regs *regs = ixp_clock->regs;
76	struct ptp_clock_event event;
77	u32 ack = 0, lo, hi, val;
78
79	val = __raw_readl(&regs->event);
80
81	if (val & TSER_SNS) {
82	ack \|= TSER_SNS;
83	if (ixp_clock->exts0_enabled) {
84	hi = __raw_readl(&regs->asms_hi);
85	lo = __raw_readl(&regs->asms_lo);
86	event.type = PTP_CLOCK_EXTTS;
87	event.index = 0;
88	event.timestamp = ((u64) hi) << 32;
89	event.timestamp \|= lo;
90	event.timestamp <<= TICKS_NS_SHIFT;
91	ptp_clock_event(ixp_clock->ptp_clock, &event);
92	}
93	}
94
95	if (val & TSER_SNM) {
96	ack \|= TSER_SNM;
97	if (ixp_clock->exts1_enabled) {
98	hi = __raw_readl(&regs->amms_hi);
99	lo = __raw_readl(&regs->amms_lo);
100	event.type = PTP_CLOCK_EXTTS;
101	event.index = 1;
102	event.timestamp = ((u64) hi) << 32;
103	event.timestamp \|= lo;
104	event.timestamp <<= TICKS_NS_SHIFT;
105	ptp_clock_event(ixp_clock->ptp_clock, &event);
106	}
107	}
108
109	if (val & TTIPEND)
110	ack \|= TTIPEND; /* this bit seems to be always set */
111
112	if (ack) {
113	__raw_writel(ack, &regs->event);
114	return IRQ_HANDLED;
115	} else
116	return IRQ_NONE;
117	}
118
119	/*
120	* PTP clock operations
121	*/
122
123	static int ptp_ixp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
124	{
125	u64 adj;
126	u32 diff, addend;
127	int neg_adj = 0;
128	struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps);
129	struct ixp46x_ts_regs *regs = ixp_clock->regs;
130
131	if (ppb < 0) {
132	neg_adj = 1;
133	ppb = -ppb;
134	}
135	addend = DEFAULT_ADDEND;
136	adj = addend;
137	adj *= ppb;
138	diff = div_u64(adj, 1000000000ULL);
139
140	addend = neg_adj ? addend - diff : addend + diff;
141
142	__raw_writel(addend, &regs->addend);
143
144	return 0;
145	}
146
147	static int ptp_ixp_adjtime(struct ptp_clock_info *ptp, s64 delta)
148	{
149	s64 now;
150	unsigned long flags;
151	struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps);
152	struct ixp46x_ts_regs *regs = ixp_clock->regs;
153
154	spin_lock_irqsave(&register_lock, flags);
155
156	now = ixp_systime_read(regs);
157	now += delta;
158	ixp_systime_write(regs, now);
159
160	spin_unlock_irqrestore(&register_lock, flags);
161
162	return 0;
163	}
164
1ca13de2	165	static int ptp_ixp_gettime(struct ptp_clock_info ptp, struct timespec64 ts)
32bd93e8 RC	166	{
32bd93e8 RC	167	u64 ns;
32bd93e8 RC	168	unsigned long flags;
	169	struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps);
	170	struct ixp46x_ts_regs *regs = ixp_clock->regs;
	171
	172	spin_lock_irqsave(&register_lock, flags);
	173
	174	ns = ixp_systime_read(regs);
	175
	176	spin_unlock_irqrestore(&register_lock, flags);
	177
b83ef507	178	*ts = ns_to_timespec64(ns);
32bd93e8 RC	179	return 0;
	180	}
	181
	182	static int ptp_ixp_settime(struct ptp_clock_info *ptp,
1ca13de2	183	const struct timespec64 *ts)
32bd93e8 RC	184	{
	185	u64 ns;
	186	unsigned long flags;
	187	struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps);
	188	struct ixp46x_ts_regs *regs = ixp_clock->regs;
	189
b83ef507	190	ns = timespec64_to_ns(ts);
32bd93e8 RC	191
	192	spin_lock_irqsave(&register_lock, flags);
	193
	194	ixp_systime_write(regs, ns);
	195
	196	spin_unlock_irqrestore(&register_lock, flags);
	197
	198	return 0;
	199	}
	200
	201	static int ptp_ixp_enable(struct ptp_clock_info *ptp,
	202	struct ptp_clock_request *rq, int on)
	203	{
	204	struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps);
	205
	206	switch (rq->type) {
	207	case PTP_CLK_REQ_EXTTS:
	208	switch (rq->extts.index) {
	209	case 0:
	210	ixp_clock->exts0_enabled = on ? 1 : 0;
	211	break;
	212	case 1:
	213	ixp_clock->exts1_enabled = on ? 1 : 0;
	214	break;
	215	default:
	216	return -EINVAL;
	217	}
	218	return 0;
	219	default:
	220	break;
	221	}
	222
	223	return -EOPNOTSUPP;
	224	}
	225
7d47e9a2	226	static const struct ptp_clock_info ptp_ixp_caps = {
32bd93e8 RC	227	.owner = THIS_MODULE,
	228	.name = "IXP46X timer",
	229	.max_adj = 66666655,
	230	.n_ext_ts = N_EXT_TS,
4986b4f0	231	.n_pins = 0,
32bd93e8 RC	232	.pps = 0,
	233	.adjfreq = ptp_ixp_adjfreq,
	234	.adjtime = ptp_ixp_adjtime,
1ca13de2 RC	235	.gettime64 = ptp_ixp_gettime,
1ca13de2 RC	236	.settime64 = ptp_ixp_settime,
32bd93e8 RC	237	.enable = ptp_ixp_enable,
	238	};
	239
	240	/* module operations */
	241
	242	static struct ixp_clock ixp_clock;
	243
	244	static int setup_interrupt(int gpio)
	245	{
	246	int irq;
dc6ab07d	247	int err;
32bd93e8	248
dc6ab07d LW	249	err = gpio_request(gpio, "ixp4-ptp");
	250	if (err)
	251	return err;
	252
	253	err = gpio_direction_input(gpio);
	254	if (err)
	255	return err;
32bd93e8 RC	256
32bd93e8 RC	257	irq = gpio_to_irq(gpio);
cf86799e AB	258	if (irq < 0)
cf86799e AB	259	return irq;
32bd93e8	260
cf86799e AB	261	err = irq_set_irq_type(irq, IRQF_TRIGGER_FALLING);
cf86799e AB	262	if (err) {
32bd93e8	263	pr_err("cannot set trigger type for irq %d\n", irq);
cf86799e	264	return err;
32bd93e8 RC	265	}
32bd93e8 RC	266
cf86799e AB	267	err = request_irq(irq, isr, 0, DRIVER, &ixp_clock);
cf86799e AB	268	if (err) {
32bd93e8	269	pr_err("request_irq failed for irq %d\n", irq);
cf86799e	270	return err;
32bd93e8 RC	271	}
	272
	273	return irq;
	274	}
	275
	276	static void __exit ptp_ixp_exit(void)
	277	{
	278	free_irq(MASTER_IRQ, &ixp_clock);
	279	free_irq(SLAVE_IRQ, &ixp_clock);
c1e6aaf0	280	ixp46x_phc_index = -1;
32bd93e8 RC	281	ptp_clock_unregister(ixp_clock.ptp_clock);
	282	}
	283
	284	static int __init ptp_ixp_init(void)
	285	{
	286	if (!cpu_is_ixp46x())
	287	return -ENODEV;
	288
	289	ixp_clock.regs =
	290	(struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
	291
	292	ixp_clock.caps = ptp_ixp_caps;
	293
1ef76158	294	ixp_clock.ptp_clock = ptp_clock_register(&ixp_clock.caps, NULL);
32bd93e8 RC	295
	296	if (IS_ERR(ixp_clock.ptp_clock))
	297	return PTR_ERR(ixp_clock.ptp_clock);
	298
c1e6aaf0	299	ixp46x_phc_index = ptp_clock_index(ixp_clock.ptp_clock);
509a7c25	300
32bd93e8 RC	301	__raw_writel(DEFAULT_ADDEND, &ixp_clock.regs->addend);
	302	__raw_writel(1, &ixp_clock.regs->trgt_lo);
	303	__raw_writel(0, &ixp_clock.regs->trgt_hi);
	304	__raw_writel(TTIPEND, &ixp_clock.regs->event);
	305
	306	if (MASTER_IRQ != setup_interrupt(MASTER_GPIO)) {
	307	pr_err("failed to setup gpio %d as irq\n", MASTER_GPIO);
	308	goto no_master;
	309	}
	310	if (SLAVE_IRQ != setup_interrupt(SLAVE_GPIO)) {
	311	pr_err("failed to setup gpio %d as irq\n", SLAVE_GPIO);
	312	goto no_slave;
	313	}
	314
	315	return 0;
	316	no_slave:
	317	free_irq(MASTER_IRQ, &ixp_clock);
	318	no_master:
	319	ptp_clock_unregister(ixp_clock.ptp_clock);
	320	return -ENODEV;
	321	}
	322
	323	module_init(ptp_ixp_init);
	324	module_exit(ptp_ixp_exit);
	325
c2ec3ff6	326	MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
32bd93e8 RC	327	MODULE_DESCRIPTION("PTP clock using the IXP46X timer");
32bd93e8 RC	328	MODULE_LICENSE("GPL");