[mirror_ubuntu-hirsute-kernel.git] / drivers / ptp / ptp_pch.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * PTP 1588 clock using the EG20T PCH
 *
 * Copyright (C) 2010 OMICRON electronics GmbH
 * Copyright (C) 2011-2012 LAPIS SEMICONDUCTOR Co., LTD.
 *
 * This code was derived from the IXP46X driver.
 */

#include <linux/device.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/ptp_clock_kernel.h>
#include <linux/slab.h>

#define STATION_ADDR_LEN	20
#define PCI_DEVICE_ID_PCH_1588	0x8819
#define IO_MEM_BAR 1

#define DEFAULT_ADDEND 0xA0000000
#define TICKS_NS_SHIFT  5
#define N_EXT_TS	2

enum pch_status {
	PCH_SUCCESS,
	PCH_INVALIDPARAM,
	PCH_NOTIMESTAMP,
	PCH_INTERRUPTMODEINUSE,
	PCH_FAILED,
	PCH_UNSUPPORTED,
};
/**
 * struct pch_ts_regs - IEEE 1588 registers
 */
struct pch_ts_regs {
	u32 control;
	u32 event;
	u32 addend;
	u32 accum;
	u32 test;
	u32 ts_compare;
	u32 rsystime_lo;
	u32 rsystime_hi;
	u32 systime_lo;
	u32 systime_hi;
	u32 trgt_lo;
	u32 trgt_hi;
	u32 asms_lo;
	u32 asms_hi;
	u32 amms_lo;
	u32 amms_hi;
	u32 ch_control;
	u32 ch_event;
	u32 tx_snap_lo;
	u32 tx_snap_hi;
	u32 rx_snap_lo;
	u32 rx_snap_hi;
	u32 src_uuid_lo;
	u32 src_uuid_hi;
	u32 can_status;
	u32 can_snap_lo;
	u32 can_snap_hi;
	u32 ts_sel;
	u32 ts_st[6];
	u32 reserve1[14];
	u32 stl_max_set_en;
	u32 stl_max_set;
	u32 reserve2[13];
	u32 srst;
};

#define PCH_TSC_RESET		(1 << 0)
#define PCH_TSC_TTM_MASK	(1 << 1)
#define PCH_TSC_ASMS_MASK	(1 << 2)
#define PCH_TSC_AMMS_MASK	(1 << 3)
#define PCH_TSC_PPSM_MASK	(1 << 4)
#define PCH_TSE_TTIPEND		(1 << 1)
#define PCH_TSE_SNS		(1 << 2)
#define PCH_TSE_SNM		(1 << 3)
#define PCH_TSE_PPS		(1 << 4)
#define PCH_CC_MM		(1 << 0)
#define PCH_CC_TA		(1 << 1)

#define PCH_CC_MODE_SHIFT	16
#define PCH_CC_MODE_MASK	0x001F0000
#define PCH_CC_VERSION		(1 << 31)
#define PCH_CE_TXS		(1 << 0)
#define PCH_CE_RXS		(1 << 1)
#define PCH_CE_OVR		(1 << 0)
#define PCH_CE_VAL		(1 << 1)
#define PCH_ECS_ETH		(1 << 0)

#define PCH_ECS_CAN		(1 << 1)
#define PCH_STATION_BYTES	6

#define PCH_IEEE1588_ETH	(1 << 0)
#define PCH_IEEE1588_CAN	(1 << 1)
/**
 * struct pch_dev - Driver private data
 */
struct pch_dev {
	struct pch_ts_regs __iomem *regs;
	struct ptp_clock *ptp_clock;
	struct ptp_clock_info caps;
	int exts0_enabled;
	int exts1_enabled;

	u32 mem_base;
	u32 mem_size;
	u32 irq;
	struct pci_dev *pdev;
	spinlock_t register_lock;
};

/**
 * struct pch_params - 1588 module parameter
 */
struct pch_params {
	u8 station[STATION_ADDR_LEN];
};

/* structure to hold the module parameters */
static struct pch_params pch_param = {
	"00:00:00:00:00:00"
};

/*
 * Register access functions
 */
static inline void pch_eth_enable_set(struct pch_dev *chip)
{
	u32 val;
	/* SET the eth_enable bit */
	val = ioread32(&chip->regs->ts_sel) | (PCH_ECS_ETH);
	iowrite32(val, (&chip->regs->ts_sel));
}

static u64 pch_systime_read(struct pch_ts_regs __iomem *regs)
{
	u64 ns;
	u32 lo, hi;

	lo = ioread32(&regs->systime_lo);
	hi = ioread32(&regs->systime_hi);

	ns = ((u64) hi) << 32;
	ns |= lo;
	ns <<= TICKS_NS_SHIFT;

	return ns;
}

static void pch_systime_write(struct pch_ts_regs __iomem *regs, u64 ns)
{
	u32 hi, lo;

	ns >>= TICKS_NS_SHIFT;
	hi = ns >> 32;
	lo = ns & 0xffffffff;

	iowrite32(lo, &regs->systime_lo);
	iowrite32(hi, &regs->systime_hi);
}

static inline void pch_block_reset(struct pch_dev *chip)
{
	u32 val;
	/* Reset Hardware Assist block */
	val = ioread32(&chip->regs->control) | PCH_TSC_RESET;
	iowrite32(val, (&chip->regs->control));
	val = val & ~PCH_TSC_RESET;
	iowrite32(val, (&chip->regs->control));
}

u32 pch_ch_control_read(struct pci_dev *pdev)
{
	struct pch_dev *chip = pci_get_drvdata(pdev);
	u32 val;

	val = ioread32(&chip->regs->ch_control);

	return val;
}
EXPORT_SYMBOL(pch_ch_control_read);

void pch_ch_control_write(struct pci_dev *pdev, u32 val)
{
	struct pch_dev *chip = pci_get_drvdata(pdev);

	iowrite32(val, (&chip->regs->ch_control));
}
EXPORT_SYMBOL(pch_ch_control_write);

u32 pch_ch_event_read(struct pci_dev *pdev)
{
	struct pch_dev *chip = pci_get_drvdata(pdev);
	u32 val;

	val = ioread32(&chip->regs->ch_event);

	return val;
}
EXPORT_SYMBOL(pch_ch_event_read);

void pch_ch_event_write(struct pci_dev *pdev, u32 val)
{
	struct pch_dev *chip = pci_get_drvdata(pdev);

	iowrite32(val, (&chip->regs->ch_event));
}
EXPORT_SYMBOL(pch_ch_event_write);

u32 pch_src_uuid_lo_read(struct pci_dev *pdev)
{
	struct pch_dev *chip = pci_get_drvdata(pdev);
	u32 val;

	val = ioread32(&chip->regs->src_uuid_lo);

	return val;
}
EXPORT_SYMBOL(pch_src_uuid_lo_read);

u32 pch_src_uuid_hi_read(struct pci_dev *pdev)
{
	struct pch_dev *chip = pci_get_drvdata(pdev);
	u32 val;

	val = ioread32(&chip->regs->src_uuid_hi);

	return val;
}
EXPORT_SYMBOL(pch_src_uuid_hi_read);

u64 pch_rx_snap_read(struct pci_dev *pdev)
{
	struct pch_dev *chip = pci_get_drvdata(pdev);
	u64 ns;
	u32 lo, hi;

	lo = ioread32(&chip->regs->rx_snap_lo);
	hi = ioread32(&chip->regs->rx_snap_hi);

	ns = ((u64) hi) << 32;
	ns |= lo;
	ns <<= TICKS_NS_SHIFT;

	return ns;
}
EXPORT_SYMBOL(pch_rx_snap_read);

u64 pch_tx_snap_read(struct pci_dev *pdev)
{
	struct pch_dev *chip = pci_get_drvdata(pdev);
	u64 ns;
	u32 lo, hi;

	lo = ioread32(&chip->regs->tx_snap_lo);
	hi = ioread32(&chip->regs->tx_snap_hi);

	ns = ((u64) hi) << 32;
	ns |= lo;
	ns <<= TICKS_NS_SHIFT;

	return ns;
}
EXPORT_SYMBOL(pch_tx_snap_read);

/* This function enables all 64 bits in system time registers [high & low].
This is a work-around for non continuous value in the SystemTime Register*/
static void pch_set_system_time_count(struct pch_dev *chip)
{
	iowrite32(0x01, &chip->regs->stl_max_set_en);
	iowrite32(0xFFFFFFFF, &chip->regs->stl_max_set);
	iowrite32(0x00, &chip->regs->stl_max_set_en);
}

static void pch_reset(struct pch_dev *chip)
{
	/* Reset Hardware Assist */
	pch_block_reset(chip);

	/* enable all 32 bits in system time registers */
	pch_set_system_time_count(chip);
}

/**
 * pch_set_station_address() - This API sets the station address used by
 *				    IEEE 1588 hardware when looking at PTP
 *				    traffic on the  ethernet interface
 * @addr:	dress which contain the column separated address to be used.
 */
int pch_set_station_address(u8 *addr, struct pci_dev *pdev)
{
	s32 i;
	struct pch_dev *chip = pci_get_drvdata(pdev);

	/* Verify the parameter */
	if ((chip->regs == NULL) || addr == (u8 *)NULL) {
		dev_err(&pdev->dev,
			"invalid params returning PCH_INVALIDPARAM\n");
		return PCH_INVALIDPARAM;
	}
	/* For all station address bytes */
	for (i = 0; i < PCH_STATION_BYTES; i++) {
		u32 val;
		s32 tmp;

		tmp = hex_to_bin(addr[i * 3]);
		if (tmp < 0) {
			dev_err(&pdev->dev,
				"invalid params returning PCH_INVALIDPARAM\n");
			return PCH_INVALIDPARAM;
		}
		val = tmp * 16;
		tmp = hex_to_bin(addr[(i * 3) + 1]);
		if (tmp < 0) {
			dev_err(&pdev->dev,
				"invalid params returning PCH_INVALIDPARAM\n");
			return PCH_INVALIDPARAM;
		}
		val += tmp;
		/* Expects ':' separated addresses */
		if ((i < 5) && (addr[(i * 3) + 2] != ':')) {
			dev_err(&pdev->dev,
				"invalid params returning PCH_INVALIDPARAM\n");
			return PCH_INVALIDPARAM;
		}

		/* Ideally we should set the address only after validating
							 entire string */
		dev_dbg(&pdev->dev, "invoking pch_station_set\n");
		iowrite32(val, &chip->regs->ts_st[i]);
	}
	return 0;
}
EXPORT_SYMBOL(pch_set_station_address);

/*
 * Interrupt service routine
 */
static irqreturn_t isr(int irq, void *priv)
{
	struct pch_dev *pch_dev = priv;
	struct pch_ts_regs __iomem *regs = pch_dev->regs;
	struct ptp_clock_event event;
	u32 ack = 0, lo, hi, val;

	val = ioread32(&regs->event);

	if (val & PCH_TSE_SNS) {
		ack |= PCH_TSE_SNS;
		if (pch_dev->exts0_enabled) {
			hi = ioread32(&regs->asms_hi);
			lo = ioread32(&regs->asms_lo);
			event.type = PTP_CLOCK_EXTTS;
			event.index = 0;
			event.timestamp = ((u64) hi) << 32;
			event.timestamp |= lo;
			event.timestamp <<= TICKS_NS_SHIFT;
			ptp_clock_event(pch_dev->ptp_clock, &event);
		}
	}

	if (val & PCH_TSE_SNM) {
		ack |= PCH_TSE_SNM;
		if (pch_dev->exts1_enabled) {
			hi = ioread32(&regs->amms_hi);
			lo = ioread32(&regs->amms_lo);
			event.type = PTP_CLOCK_EXTTS;
			event.index = 1;
			event.timestamp = ((u64) hi) << 32;
			event.timestamp |= lo;
			event.timestamp <<= TICKS_NS_SHIFT;
			ptp_clock_event(pch_dev->ptp_clock, &event);
		}
	}

	if (val & PCH_TSE_TTIPEND)
		ack |= PCH_TSE_TTIPEND; /* this bit seems to be always set */

	if (ack) {
		iowrite32(ack, &regs->event);
		return IRQ_HANDLED;
	} else
		return IRQ_NONE;
}

/*
 * PTP clock operations
 */

static int ptp_pch_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
{
	u64 adj;
	u32 diff, addend;
	int neg_adj = 0;
	struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
	struct pch_ts_regs __iomem *regs = pch_dev->regs;

	if (ppb < 0) {
		neg_adj = 1;
		ppb = -ppb;
	}
	addend = DEFAULT_ADDEND;
	adj = addend;
	adj *= ppb;
	diff = div_u64(adj, 1000000000ULL);

	addend = neg_adj ? addend - diff : addend + diff;

	iowrite32(addend, &regs->addend);

	return 0;
}

static int ptp_pch_adjtime(struct ptp_clock_info *ptp, s64 delta)
{
	s64 now;
	unsigned long flags;
	struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
	struct pch_ts_regs __iomem *regs = pch_dev->regs;

	spin_lock_irqsave(&pch_dev->register_lock, flags);
	now = pch_systime_read(regs);
	now += delta;
	pch_systime_write(regs, now);
	spin_unlock_irqrestore(&pch_dev->register_lock, flags);

	return 0;
}

static int ptp_pch_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
{
	u64 ns;
	unsigned long flags;
	struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
	struct pch_ts_regs __iomem *regs = pch_dev->regs;

	spin_lock_irqsave(&pch_dev->register_lock, flags);
	ns = pch_systime_read(regs);
	spin_unlock_irqrestore(&pch_dev->register_lock, flags);

	*ts = ns_to_timespec64(ns);
	return 0;
}

static int ptp_pch_settime(struct ptp_clock_info *ptp,
			   const struct timespec64 *ts)
{
	u64 ns;
	unsigned long flags;
	struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
	struct pch_ts_regs __iomem *regs = pch_dev->regs;

	ns = timespec64_to_ns(ts);

	spin_lock_irqsave(&pch_dev->register_lock, flags);
	pch_systime_write(regs, ns);
	spin_unlock_irqrestore(&pch_dev->register_lock, flags);

	return 0;
}

static int ptp_pch_enable(struct ptp_clock_info *ptp,
			  struct ptp_clock_request *rq, int on)
{
	struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);

	switch (rq->type) {
	case PTP_CLK_REQ_EXTTS:
		switch (rq->extts.index) {
		case 0:
			pch_dev->exts0_enabled = on ? 1 : 0;
			break;
		case 1:
			pch_dev->exts1_enabled = on ? 1 : 0;
			break;
		default:
			return -EINVAL;
		}
		return 0;
	default:
		break;
	}

	return -EOPNOTSUPP;
}

static const struct ptp_clock_info ptp_pch_caps = {
	.owner		= THIS_MODULE,
	.name		= "PCH timer",
	.max_adj	= 50000000,
	.n_ext_ts	= N_EXT_TS,
	.n_pins		= 0,
	.pps		= 0,
	.adjfreq	= ptp_pch_adjfreq,
	.adjtime	= ptp_pch_adjtime,
	.gettime64	= ptp_pch_gettime,
	.settime64	= ptp_pch_settime,
	.enable		= ptp_pch_enable,
};

#define pch_suspend NULL
#define pch_resume NULL

static void pch_remove(struct pci_dev *pdev)
{
	struct pch_dev *chip = pci_get_drvdata(pdev);

	ptp_clock_unregister(chip->ptp_clock);
	/* free the interrupt */
	if (pdev->irq != 0)
		free_irq(pdev->irq, chip);

	/* unmap the virtual IO memory space */
	if (chip->regs != NULL) {
		iounmap(chip->regs);
		chip->regs = NULL;
	}
	/* release the reserved IO memory space */
	if (chip->mem_base != 0) {
		release_mem_region(chip->mem_base, chip->mem_size);
		chip->mem_base = 0;
	}
	pci_disable_device(pdev);
	kfree(chip);
	dev_info(&pdev->dev, "complete\n");
}

static s32
pch_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
	s32 ret;
	unsigned long flags;
	struct pch_dev *chip;

	chip = kzalloc(sizeof(struct pch_dev), GFP_KERNEL);
	if (chip == NULL)
		return -ENOMEM;

	/* enable the 1588 pci device */
	ret = pci_enable_device(pdev);
	if (ret != 0) {
		dev_err(&pdev->dev, "could not enable the pci device\n");
		goto err_pci_en;
	}

	chip->mem_base = pci_resource_start(pdev, IO_MEM_BAR);
	if (!chip->mem_base) {
		dev_err(&pdev->dev, "could not locate IO memory address\n");
		ret = -ENODEV;
		goto err_pci_start;
	}

	/* retrieve the available length of the IO memory space */
	chip->mem_size = pci_resource_len(pdev, IO_MEM_BAR);

	/* allocate the memory for the device registers */
	if (!request_mem_region(chip->mem_base, chip->mem_size, "1588_regs")) {
		dev_err(&pdev->dev,
			"could not allocate register memory space\n");
		ret = -EBUSY;
		goto err_req_mem_region;
	}

	/* get the virtual address to the 1588 registers */
	chip->regs = ioremap(chip->mem_base, chip->mem_size);

	if (!chip->regs) {
		dev_err(&pdev->dev, "Could not get virtual address\n");
		ret = -ENOMEM;
		goto err_ioremap;
	}

	chip->caps = ptp_pch_caps;
	chip->ptp_clock = ptp_clock_register(&chip->caps, &pdev->dev);
	if (IS_ERR(chip->ptp_clock)) {
		ret = PTR_ERR(chip->ptp_clock);
		goto err_ptp_clock_reg;
	}

	spin_lock_init(&chip->register_lock);

	ret = request_irq(pdev->irq, &isr, IRQF_SHARED, KBUILD_MODNAME, chip);
	if (ret != 0) {
		dev_err(&pdev->dev, "failed to get irq %d\n", pdev->irq);
		goto err_req_irq;
	}

	/* indicate success */
	chip->irq = pdev->irq;
	chip->pdev = pdev;
	pci_set_drvdata(pdev, chip);

	spin_lock_irqsave(&chip->register_lock, flags);
	/* reset the ieee1588 h/w */
	pch_reset(chip);

	iowrite32(DEFAULT_ADDEND, &chip->regs->addend);
	iowrite32(1, &chip->regs->trgt_lo);
	iowrite32(0, &chip->regs->trgt_hi);
	iowrite32(PCH_TSE_TTIPEND, &chip->regs->event);

	pch_eth_enable_set(chip);

	if (strcmp(pch_param.station, "00:00:00:00:00:00") != 0) {
		if (pch_set_station_address(pch_param.station, pdev) != 0) {
			dev_err(&pdev->dev,
			"Invalid station address parameter\n"
			"Module loaded but station address not set correctly\n"
			);
		}
	}
	spin_unlock_irqrestore(&chip->register_lock, flags);
	return 0;

err_req_irq:
	ptp_clock_unregister(chip->ptp_clock);
err_ptp_clock_reg:
	iounmap(chip->regs);
	chip->regs = NULL;

err_ioremap:
	release_mem_region(chip->mem_base, chip->mem_size);

err_req_mem_region:
	chip->mem_base = 0;

err_pci_start:
	pci_disable_device(pdev);

err_pci_en:
	kfree(chip);
	dev_err(&pdev->dev, "probe failed(ret=0x%x)\n", ret);

	return ret;
}

static const struct pci_device_id pch_ieee1588_pcidev_id[] = {
	{
	  .vendor = PCI_VENDOR_ID_INTEL,
	  .device = PCI_DEVICE_ID_PCH_1588
	 },
	{0}
};

static SIMPLE_DEV_PM_OPS(pch_pm_ops, pch_suspend, pch_resume);

static struct pci_driver pch_driver = {
	.name = KBUILD_MODNAME,
	.id_table = pch_ieee1588_pcidev_id,
	.probe = pch_probe,
	.remove = pch_remove,
	.driver.pm = &pch_pm_ops,
};

static void __exit ptp_pch_exit(void)
{
	pci_unregister_driver(&pch_driver);
}

static s32 __init ptp_pch_init(void)
{
	s32 ret;

	/* register the driver with the pci core */
	ret = pci_register_driver(&pch_driver);

	return ret;
}

module_init(ptp_pch_init);
module_exit(ptp_pch_exit);

module_param_string(station,
		    pch_param.station, sizeof(pch_param.station), 0444);
MODULE_PARM_DESC(station,
	 "IEEE 1588 station address to use - colon separated hex values");

MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>");
MODULE_DESCRIPTION("PTP clock using the EG20T timer");
MODULE_LICENSE("GPL");
Commit	Line	Data
873e65bc	1	// SPDX-License-Identifier: GPL-2.0-only
863d08ec TS	2	/*
	3	* PTP 1588 clock using the EG20T PCH
	4	*
	5	* Copyright (C) 2010 OMICRON electronics GmbH
	6	* Copyright (C) 2011-2012 LAPIS SEMICONDUCTOR Co., LTD.
	7	*
	8	* This code was derived from the IXP46X driver.
863d08ec TS	9	*/
	10
	11	#include <linux/device.h>
	12	#include <linux/err.h>
	13	#include <linux/init.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/io.h>
	16	#include <linux/irq.h>
	17	#include <linux/kernel.h>
	18	#include <linux/module.h>
	19	#include <linux/pci.h>
	20	#include <linux/ptp_clock_kernel.h>
769b0daf	21	#include <linux/slab.h>
863d08ec TS	22
	23	#define STATION_ADDR_LEN 20
	24	#define PCI_DEVICE_ID_PCH_1588 0x8819
	25	#define IO_MEM_BAR 1
	26
	27	#define DEFAULT_ADDEND 0xA0000000
	28	#define TICKS_NS_SHIFT 5
	29	#define N_EXT_TS 2
	30
	31	enum pch_status {
	32	PCH_SUCCESS,
	33	PCH_INVALIDPARAM,
	34	PCH_NOTIMESTAMP,
	35	PCH_INTERRUPTMODEINUSE,
	36	PCH_FAILED,
	37	PCH_UNSUPPORTED,
	38	};
	39	/**
	40	* struct pch_ts_regs - IEEE 1588 registers
	41	*/
	42	struct pch_ts_regs {
	43	u32 control;
	44	u32 event;
	45	u32 addend;
	46	u32 accum;
	47	u32 test;
	48	u32 ts_compare;
	49	u32 rsystime_lo;
	50	u32 rsystime_hi;
	51	u32 systime_lo;
	52	u32 systime_hi;
	53	u32 trgt_lo;
	54	u32 trgt_hi;
	55	u32 asms_lo;
	56	u32 asms_hi;
	57	u32 amms_lo;
	58	u32 amms_hi;
	59	u32 ch_control;
	60	u32 ch_event;
	61	u32 tx_snap_lo;
	62	u32 tx_snap_hi;
	63	u32 rx_snap_lo;
	64	u32 rx_snap_hi;
	65	u32 src_uuid_lo;
	66	u32 src_uuid_hi;
	67	u32 can_status;
	68	u32 can_snap_lo;
	69	u32 can_snap_hi;
	70	u32 ts_sel;
	71	u32 ts_st[6];
	72	u32 reserve1[14];
	73	u32 stl_max_set_en;
	74	u32 stl_max_set;
	75	u32 reserve2[13];
	76	u32 srst;
	77	};
	78
	79	#define PCH_TSC_RESET (1 << 0)
	80	#define PCH_TSC_TTM_MASK (1 << 1)
	81	#define PCH_TSC_ASMS_MASK (1 << 2)
	82	#define PCH_TSC_AMMS_MASK (1 << 3)
	83	#define PCH_TSC_PPSM_MASK (1 << 4)
	84	#define PCH_TSE_TTIPEND (1 << 1)
	85	#define PCH_TSE_SNS (1 << 2)
86	#define PCH_TSE_SNM (1 << 3)
87	#define PCH_TSE_PPS (1 << 4)
88	#define PCH_CC_MM (1 << 0)
89	#define PCH_CC_TA (1 << 1)
90
91	#define PCH_CC_MODE_SHIFT 16
92	#define PCH_CC_MODE_MASK 0x001F0000
93	#define PCH_CC_VERSION (1 << 31)
94	#define PCH_CE_TXS (1 << 0)
95	#define PCH_CE_RXS (1 << 1)
96	#define PCH_CE_OVR (1 << 0)
97	#define PCH_CE_VAL (1 << 1)
98	#define PCH_ECS_ETH (1 << 0)
99
100	#define PCH_ECS_CAN (1 << 1)
101	#define PCH_STATION_BYTES 6
102
103	#define PCH_IEEE1588_ETH (1 << 0)
104	#define PCH_IEEE1588_CAN (1 << 1)
105	/**
106	* struct pch_dev - Driver private data
107	*/
108	struct pch_dev {
7d3ac5c7	109	struct pch_ts_regs __iomem *regs;
863d08ec TS	110	struct ptp_clock *ptp_clock;
	111	struct ptp_clock_info caps;
	112	int exts0_enabled;
	113	int exts1_enabled;
	114
	115	u32 mem_base;
	116	u32 mem_size;
	117	u32 irq;
	118	struct pci_dev *pdev;
	119	spinlock_t register_lock;
	120	};
	121
	122	/**
	123	* struct pch_params - 1588 module parameter
	124	*/
	125	struct pch_params {
	126	u8 station[STATION_ADDR_LEN];
	127	};
	128
	129	/* structure to hold the module parameters */
	130	static struct pch_params pch_param = {
	131	"00:00:00:00:00:00"
	132	};
	133
	134	/*
	135	* Register access functions
	136	*/
	137	static inline void pch_eth_enable_set(struct pch_dev *chip)
	138	{
	139	u32 val;
	140	/* SET the eth_enable bit */
	141	val = ioread32(&chip->regs->ts_sel) \| (PCH_ECS_ETH);
	142	iowrite32(val, (&chip->regs->ts_sel));
	143	}
	144
7d3ac5c7	145	static u64 pch_systime_read(struct pch_ts_regs __iomem *regs)
863d08ec TS	146	{
	147	u64 ns;
	148	u32 lo, hi;
	149
	150	lo = ioread32(&regs->systime_lo);
	151	hi = ioread32(&regs->systime_hi);
	152
	153	ns = ((u64) hi) << 32;
	154	ns \|= lo;
	155	ns <<= TICKS_NS_SHIFT;
	156
	157	return ns;
	158	}
	159
7d3ac5c7	160	static void pch_systime_write(struct pch_ts_regs __iomem *regs, u64 ns)
863d08ec TS	161	{
	162	u32 hi, lo;
	163
	164	ns >>= TICKS_NS_SHIFT;
	165	hi = ns >> 32;
	166	lo = ns & 0xffffffff;
	167
	168	iowrite32(lo, &regs->systime_lo);
	169	iowrite32(hi, &regs->systime_hi);
	170	}
	171
	172	static inline void pch_block_reset(struct pch_dev *chip)
	173	{
	174	u32 val;
	175	/* Reset Hardware Assist block */
	176	val = ioread32(&chip->regs->control) \| PCH_TSC_RESET;
	177	iowrite32(val, (&chip->regs->control));
	178	val = val & ~PCH_TSC_RESET;
	179	iowrite32(val, (&chip->regs->control));
	180	}
	181
	182	u32 pch_ch_control_read(struct pci_dev *pdev)
	183	{
	184	struct pch_dev *chip = pci_get_drvdata(pdev);
	185	u32 val;
	186
	187	val = ioread32(&chip->regs->ch_control);
	188
	189	return val;
	190	}
	191	EXPORT_SYMBOL(pch_ch_control_read);
	192
	193	void pch_ch_control_write(struct pci_dev *pdev, u32 val)
	194	{
	195	struct pch_dev *chip = pci_get_drvdata(pdev);
	196
	197	iowrite32(val, (&chip->regs->ch_control));
	198	}
	199	EXPORT_SYMBOL(pch_ch_control_write);
	200
	201	u32 pch_ch_event_read(struct pci_dev *pdev)
	202	{
	203	struct pch_dev *chip = pci_get_drvdata(pdev);
	204	u32 val;
	205
	206	val = ioread32(&chip->regs->ch_event);
	207
	208	return val;
	209	}
	210	EXPORT_SYMBOL(pch_ch_event_read);
	211
	212	void pch_ch_event_write(struct pci_dev *pdev, u32 val)
	213	{
	214	struct pch_dev *chip = pci_get_drvdata(pdev);
	215
	216	iowrite32(val, (&chip->regs->ch_event));
	217	}
	218	EXPORT_SYMBOL(pch_ch_event_write);
	219
	220	u32 pch_src_uuid_lo_read(struct pci_dev *pdev)
	221	{
	222	struct pch_dev *chip = pci_get_drvdata(pdev);
	223	u32 val;
	224
225	val = ioread32(&chip->regs->src_uuid_lo);
226
227	return val;
228	}
229	EXPORT_SYMBOL(pch_src_uuid_lo_read);
230
231	u32 pch_src_uuid_hi_read(struct pci_dev *pdev)
232	{
233	struct pch_dev *chip = pci_get_drvdata(pdev);
234	u32 val;
235
236	val = ioread32(&chip->regs->src_uuid_hi);
237
238	return val;
239	}
240	EXPORT_SYMBOL(pch_src_uuid_hi_read);
241
242	u64 pch_rx_snap_read(struct pci_dev *pdev)
243	{
244	struct pch_dev *chip = pci_get_drvdata(pdev);
245	u64 ns;
246	u32 lo, hi;
247
248	lo = ioread32(&chip->regs->rx_snap_lo);
249	hi = ioread32(&chip->regs->rx_snap_hi);
250
251	ns = ((u64) hi) << 32;
252	ns \|= lo;
d50566c7	253	ns <<= TICKS_NS_SHIFT;
863d08ec TS	254
	255	return ns;
	256	}
	257	EXPORT_SYMBOL(pch_rx_snap_read);
	258
	259	u64 pch_tx_snap_read(struct pci_dev *pdev)
	260	{
	261	struct pch_dev *chip = pci_get_drvdata(pdev);
	262	u64 ns;
	263	u32 lo, hi;
	264
	265	lo = ioread32(&chip->regs->tx_snap_lo);
	266	hi = ioread32(&chip->regs->tx_snap_hi);
	267
	268	ns = ((u64) hi) << 32;
	269	ns \|= lo;
d50566c7	270	ns <<= TICKS_NS_SHIFT;
863d08ec TS	271
	272	return ns;
	273	}
	274	EXPORT_SYMBOL(pch_tx_snap_read);
	275
	276	/* This function enables all 64 bits in system time registers [high & low].
	277	This is a work-around for non continuous value in the SystemTime Register*/
	278	static void pch_set_system_time_count(struct pch_dev *chip)
	279	{
	280	iowrite32(0x01, &chip->regs->stl_max_set_en);
	281	iowrite32(0xFFFFFFFF, &chip->regs->stl_max_set);
	282	iowrite32(0x00, &chip->regs->stl_max_set_en);
	283	}
	284
	285	static void pch_reset(struct pch_dev *chip)
	286	{
	287	/* Reset Hardware Assist */
	288	pch_block_reset(chip);
	289
	290	/* enable all 32 bits in system time registers */
	291	pch_set_system_time_count(chip);
	292	}
	293
	294	/**
	295	* pch_set_station_address() - This API sets the station address used by
	296	* IEEE 1588 hardware when looking at PTP
	297	* traffic on the ethernet interface
	298	* @addr: dress which contain the column separated address to be used.
	299	*/
17cdedf3	300	int pch_set_station_address(u8 addr, struct pci_dev pdev)
863d08ec TS	301	{
	302	s32 i;
	303	struct pch_dev *chip = pci_get_drvdata(pdev);
	304
	305	/* Verify the parameter */
7d3ac5c7	306	if ((chip->regs == NULL) \|\| addr == (u8 *)NULL) {
863d08ec TS	307	dev_err(&pdev->dev,
	308	"invalid params returning PCH_INVALIDPARAM\n");
	309	return PCH_INVALIDPARAM;
	310	}
	311	/* For all station address bytes */
	312	for (i = 0; i < PCH_STATION_BYTES; i++) {
	313	u32 val;
	314	s32 tmp;
	315
	316	tmp = hex_to_bin(addr[i * 3]);
	317	if (tmp < 0) {
	318	dev_err(&pdev->dev,
	319	"invalid params returning PCH_INVALIDPARAM\n");
	320	return PCH_INVALIDPARAM;
	321	}
	322	val = tmp * 16;
	323	tmp = hex_to_bin(addr[(i * 3) + 1]);
	324	if (tmp < 0) {
	325	dev_err(&pdev->dev,
	326	"invalid params returning PCH_INVALIDPARAM\n");
	327	return PCH_INVALIDPARAM;
	328	}
	329	val += tmp;
	330	/* Expects ':' separated addresses */
	331	if ((i < 5) && (addr[(i * 3) + 2] != ':')) {
	332	dev_err(&pdev->dev,
	333	"invalid params returning PCH_INVALIDPARAM\n");
	334	return PCH_INVALIDPARAM;
	335	}
	336
	337	/* Ideally we should set the address only after validating
	338	entire string */
	339	dev_dbg(&pdev->dev, "invoking pch_station_set\n");
	340	iowrite32(val, &chip->regs->ts_st[i]);
	341	}
	342	return 0;
	343	}
17cdedf3	344	EXPORT_SYMBOL(pch_set_station_address);
863d08ec TS	345
	346	/*
	347	* Interrupt service routine
	348	*/
	349	static irqreturn_t isr(int irq, void *priv)
	350	{
	351	struct pch_dev *pch_dev = priv;
7d3ac5c7	352	struct pch_ts_regs __iomem *regs = pch_dev->regs;
863d08ec TS	353	struct ptp_clock_event event;
	354	u32 ack = 0, lo, hi, val;
	355
	356	val = ioread32(&regs->event);
	357
	358	if (val & PCH_TSE_SNS) {
	359	ack \|= PCH_TSE_SNS;
	360	if (pch_dev->exts0_enabled) {
	361	hi = ioread32(&regs->asms_hi);
	362	lo = ioread32(&regs->asms_lo);
	363	event.type = PTP_CLOCK_EXTTS;
	364	event.index = 0;
	365	event.timestamp = ((u64) hi) << 32;
	366	event.timestamp \|= lo;
	367	event.timestamp <<= TICKS_NS_SHIFT;
	368	ptp_clock_event(pch_dev->ptp_clock, &event);
	369	}
	370	}
	371
	372	if (val & PCH_TSE_SNM) {
	373	ack \|= PCH_TSE_SNM;
	374	if (pch_dev->exts1_enabled) {
	375	hi = ioread32(&regs->amms_hi);
	376	lo = ioread32(&regs->amms_lo);
	377	event.type = PTP_CLOCK_EXTTS;
	378	event.index = 1;
	379	event.timestamp = ((u64) hi) << 32;
	380	event.timestamp \|= lo;
	381	event.timestamp <<= TICKS_NS_SHIFT;
	382	ptp_clock_event(pch_dev->ptp_clock, &event);
	383	}
	384	}
	385
	386	if (val & PCH_TSE_TTIPEND)
	387	ack \|= PCH_TSE_TTIPEND; /* this bit seems to be always set */
	388
	389	if (ack) {
	390	iowrite32(ack, &regs->event);
	391	return IRQ_HANDLED;
	392	} else
	393	return IRQ_NONE;
	394	}
	395
	396	/*
	397	* PTP clock operations
	398	*/
	399
	400	static int ptp_pch_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
	401	{
	402	u64 adj;
	403	u32 diff, addend;
	404	int neg_adj = 0;
	405	struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
7d3ac5c7	406	struct pch_ts_regs __iomem *regs = pch_dev->regs;
863d08ec TS	407
	408	if (ppb < 0) {
	409	neg_adj = 1;
	410	ppb = -ppb;
	411	}
	412	addend = DEFAULT_ADDEND;
	413	adj = addend;
	414	adj *= ppb;
	415	diff = div_u64(adj, 1000000000ULL);
	416
	417	addend = neg_adj ? addend - diff : addend + diff;
	418
	419	iowrite32(addend, &regs->addend);
	420
	421	return 0;
	422	}
	423
	424	static int ptp_pch_adjtime(struct ptp_clock_info *ptp, s64 delta)
	425	{
	426	s64 now;
	427	unsigned long flags;
	428	struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
7d3ac5c7	429	struct pch_ts_regs __iomem *regs = pch_dev->regs;
863d08ec TS	430
	431	spin_lock_irqsave(&pch_dev->register_lock, flags);
	432	now = pch_systime_read(regs);
	433	now += delta;
	434	pch_systime_write(regs, now);
	435	spin_unlock_irqrestore(&pch_dev->register_lock, flags);
	436
	437	return 0;
	438	}
	439
a043a729	440	static int ptp_pch_gettime(struct ptp_clock_info ptp, struct timespec64 ts)
863d08ec TS	441	{
863d08ec TS	442	u64 ns;
863d08ec TS	443	unsigned long flags;
863d08ec TS	444	struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
7d3ac5c7	445	struct pch_ts_regs __iomem *regs = pch_dev->regs;
863d08ec TS	446
	447	spin_lock_irqsave(&pch_dev->register_lock, flags);
	448	ns = pch_systime_read(regs);
	449	spin_unlock_irqrestore(&pch_dev->register_lock, flags);
	450
80e95f47	451	*ts = ns_to_timespec64(ns);
863d08ec TS	452	return 0;
	453	}
	454
	455	static int ptp_pch_settime(struct ptp_clock_info *ptp,
a043a729	456	const struct timespec64 *ts)
863d08ec TS	457	{
	458	u64 ns;
	459	unsigned long flags;
	460	struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
7d3ac5c7	461	struct pch_ts_regs __iomem *regs = pch_dev->regs;
863d08ec	462
80e95f47	463	ns = timespec64_to_ns(ts);
863d08ec TS	464
	465	spin_lock_irqsave(&pch_dev->register_lock, flags);
	466	pch_systime_write(regs, ns);
	467	spin_unlock_irqrestore(&pch_dev->register_lock, flags);
	468
	469	return 0;
	470	}
	471
	472	static int ptp_pch_enable(struct ptp_clock_info *ptp,
	473	struct ptp_clock_request *rq, int on)
	474	{
	475	struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
	476
	477	switch (rq->type) {
	478	case PTP_CLK_REQ_EXTTS:
	479	switch (rq->extts.index) {
	480	case 0:
	481	pch_dev->exts0_enabled = on ? 1 : 0;
	482	break;
	483	case 1:
	484	pch_dev->exts1_enabled = on ? 1 : 0;
	485	break;
	486	default:
	487	return -EINVAL;
	488	}
	489	return 0;
	490	default:
	491	break;
	492	}
	493
	494	return -EOPNOTSUPP;
	495	}
	496
7d47e9a2	497	static const struct ptp_clock_info ptp_pch_caps = {
863d08ec TS	498	.owner = THIS_MODULE,
	499	.name = "PCH timer",
	500	.max_adj = 50000000,
	501	.n_ext_ts = N_EXT_TS,
4986b4f0	502	.n_pins = 0,
863d08ec TS	503	.pps = 0,
	504	.adjfreq = ptp_pch_adjfreq,
	505	.adjtime = ptp_pch_adjtime,
a043a729 RC	506	.gettime64 = ptp_pch_gettime,
a043a729 RC	507	.settime64 = ptp_pch_settime,
863d08ec TS	508	.enable = ptp_pch_enable,
	509	};
	510
863d08ec TS	511	#define pch_suspend NULL
863d08ec TS	512	#define pch_resume NULL
863d08ec	513
b1f7c8cc	514	static void pch_remove(struct pci_dev *pdev)
863d08ec TS	515	{
	516	struct pch_dev *chip = pci_get_drvdata(pdev);
	517
	518	ptp_clock_unregister(chip->ptp_clock);
	519	/* free the interrupt */
	520	if (pdev->irq != 0)
	521	free_irq(pdev->irq, chip);
	522
	523	/* unmap the virtual IO memory space */
7d3ac5c7	524	if (chip->regs != NULL) {
863d08ec	525	iounmap(chip->regs);
7d3ac5c7	526	chip->regs = NULL;
863d08ec TS	527	}
	528	/* release the reserved IO memory space */
	529	if (chip->mem_base != 0) {
	530	release_mem_region(chip->mem_base, chip->mem_size);
	531	chip->mem_base = 0;
	532	}
	533	pci_disable_device(pdev);
	534	kfree(chip);
	535	dev_info(&pdev->dev, "complete\n");
	536	}
	537
5c0a4256	538	static s32
863d08ec TS	539	pch_probe(struct pci_dev pdev, const struct pci_device_id id)
	540	{
	541	s32 ret;
	542	unsigned long flags;
	543	struct pch_dev *chip;
	544
	545	chip = kzalloc(sizeof(struct pch_dev), GFP_KERNEL);
	546	if (chip == NULL)
	547	return -ENOMEM;
	548
	549	/* enable the 1588 pci device */
	550	ret = pci_enable_device(pdev);
	551	if (ret != 0) {
	552	dev_err(&pdev->dev, "could not enable the pci device\n");
	553	goto err_pci_en;
	554	}
	555
	556	chip->mem_base = pci_resource_start(pdev, IO_MEM_BAR);
	557	if (!chip->mem_base) {
	558	dev_err(&pdev->dev, "could not locate IO memory address\n");
	559	ret = -ENODEV;
	560	goto err_pci_start;
	561	}
	562
	563	/* retrieve the available length of the IO memory space */
	564	chip->mem_size = pci_resource_len(pdev, IO_MEM_BAR);
	565
	566	/* allocate the memory for the device registers */
	567	if (!request_mem_region(chip->mem_base, chip->mem_size, "1588_regs")) {
	568	dev_err(&pdev->dev,
	569	"could not allocate register memory space\n");
	570	ret = -EBUSY;
	571	goto err_req_mem_region;
	572	}
	573
	574	/* get the virtual address to the 1588 registers */
	575	chip->regs = ioremap(chip->mem_base, chip->mem_size);
	576
	577	if (!chip->regs) {
	578	dev_err(&pdev->dev, "Could not get virtual address\n");
	579	ret = -ENOMEM;
	580	goto err_ioremap;
	581	}
	582
	583	chip->caps = ptp_pch_caps;
1ef76158	584	chip->ptp_clock = ptp_clock_register(&chip->caps, &pdev->dev);
0d8c3e77 WY	585	if (IS_ERR(chip->ptp_clock)) {
	586	ret = PTR_ERR(chip->ptp_clock);
	587	goto err_ptp_clock_reg;
	588	}
863d08ec TS	589
	590	spin_lock_init(&chip->register_lock);
	591
	592	ret = request_irq(pdev->irq, &isr, IRQF_SHARED, KBUILD_MODNAME, chip);
	593	if (ret != 0) {
	594	dev_err(&pdev->dev, "failed to get irq %d\n", pdev->irq);
	595	goto err_req_irq;
	596	}
	597
	598	/* indicate success */
	599	chip->irq = pdev->irq;
	600	chip->pdev = pdev;
	601	pci_set_drvdata(pdev, chip);
	602
	603	spin_lock_irqsave(&chip->register_lock, flags);
	604	/* reset the ieee1588 h/w */
	605	pch_reset(chip);
	606
	607	iowrite32(DEFAULT_ADDEND, &chip->regs->addend);
	608	iowrite32(1, &chip->regs->trgt_lo);
	609	iowrite32(0, &chip->regs->trgt_hi);
	610	iowrite32(PCH_TSE_TTIPEND, &chip->regs->event);
863d08ec TS	611
	612	pch_eth_enable_set(chip);
	613
	614	if (strcmp(pch_param.station, "00:00:00:00:00:00") != 0) {
	615	if (pch_set_station_address(pch_param.station, pdev) != 0) {
	616	dev_err(&pdev->dev,
	617	"Invalid station address parameter\n"
	618	"Module loaded but station address not set correctly\n"
	619	);
	620	}
	621	}
	622	spin_unlock_irqrestore(&chip->register_lock, flags);
	623	return 0;
	624
	625	err_req_irq:
	626	ptp_clock_unregister(chip->ptp_clock);
0d8c3e77	627	err_ptp_clock_reg:
863d08ec	628	iounmap(chip->regs);
7d3ac5c7	629	chip->regs = NULL;
863d08ec TS	630
	631	err_ioremap:
	632	release_mem_region(chip->mem_base, chip->mem_size);
	633
	634	err_req_mem_region:
	635	chip->mem_base = 0;
	636
	637	err_pci_start:
	638	pci_disable_device(pdev);
	639
	640	err_pci_en:
	641	kfree(chip);
	642	dev_err(&pdev->dev, "probe failed(ret=0x%x)\n", ret);
	643
	644	return ret;
	645	}
	646
9baa3c34	647	static const struct pci_device_id pch_ieee1588_pcidev_id[] = {
863d08ec TS	648	{
	649	.vendor = PCI_VENDOR_ID_INTEL,
	650	.device = PCI_DEVICE_ID_PCH_1588
	651	},
	652	{0}
	653	};
	654
4b88b9ce VG	655	static SIMPLE_DEV_PM_OPS(pch_pm_ops, pch_suspend, pch_resume);
4b88b9ce VG	656
d8d78949	657	static struct pci_driver pch_driver = {
863d08ec TS	658	.name = KBUILD_MODNAME,
	659	.id_table = pch_ieee1588_pcidev_id,
	660	.probe = pch_probe,
	661	.remove = pch_remove,
4b88b9ce	662	.driver.pm = &pch_pm_ops,
863d08ec TS	663	};
	664
	665	static void __exit ptp_pch_exit(void)
	666	{
d8d78949	667	pci_unregister_driver(&pch_driver);
863d08ec TS	668	}
	669
	670	static s32 __init ptp_pch_init(void)
	671	{
	672	s32 ret;
	673
	674	/* register the driver with the pci core */
d8d78949	675	ret = pci_register_driver(&pch_driver);
863d08ec TS	676
	677	return ret;
	678	}
	679
	680	module_init(ptp_pch_init);
	681	module_exit(ptp_pch_exit);
	682
7d3ac5c7 S	683	module_param_string(station,
7d3ac5c7 S	684	pch_param.station, sizeof(pch_param.station), 0444);
863d08ec	685	MODULE_PARM_DESC(station,
55c31b5b	686	"IEEE 1588 station address to use - colon separated hex values");
863d08ec TS	687
	688	MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>");
	689	MODULE_DESCRIPTION("PTP clock using the EG20T timer");
	690	MODULE_LICENSE("GPL");