[mirror_ubuntu-zesty-kernel.git] / drivers / pwm / pwm-crc.c

/*
 * Copyright (C) 2015 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License version
 * 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * Author: Shobhit Kumar <shobhit.kumar@intel.com>
 */

#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/mfd/intel_soc_pmic.h>
#include <linux/pwm.h>

#define PWM0_CLK_DIV		0x4B
#define  PWM_OUTPUT_ENABLE	BIT(7)
#define  PWM_DIV_CLK_0		0x00 /* DIVIDECLK = BASECLK */
#define  PWM_DIV_CLK_100	0x63 /* DIVIDECLK = BASECLK/100 */
#define  PWM_DIV_CLK_128	0x7F /* DIVIDECLK = BASECLK/128 */

#define PWM0_DUTY_CYCLE		0x4E
#define BACKLIGHT_EN		0x51

#define PWM_MAX_LEVEL		0xFF

#define PWM_BASE_CLK		6000000  /* 6 MHz */
#define PWM_MAX_PERIOD_NS	21333    /* 46.875KHz */

/**
 * struct crystalcove_pwm - Crystal Cove PWM controller
 * @chip: the abstract pwm_chip structure.
 * @regmap: the regmap from the parent device.
 */
struct crystalcove_pwm {
	struct pwm_chip chip;
	struct regmap *regmap;
};

static inline struct crystalcove_pwm *to_crc_pwm(struct pwm_chip *pc)
{
	return container_of(pc, struct crystalcove_pwm, chip);
}

static int crc_pwm_enable(struct pwm_chip *c, struct pwm_device *pwm)
{
	struct crystalcove_pwm *crc_pwm = to_crc_pwm(c);

	regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 1);

	return 0;
}

static void crc_pwm_disable(struct pwm_chip *c, struct pwm_device *pwm)
{
	struct crystalcove_pwm *crc_pwm = to_crc_pwm(c);

	regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 0);
}

static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm,
			  int duty_ns, int period_ns)
{
	struct crystalcove_pwm *crc_pwm = to_crc_pwm(c);
	struct device *dev = crc_pwm->chip.dev;
	int level;

	if (period_ns > PWM_MAX_PERIOD_NS) {
		dev_err(dev, "un-supported period_ns\n");
		return -EINVAL;
	}

	if (pwm_get_period(pwm) != period_ns) {
		int clk_div;

		/* changing the clk divisor, need to disable fisrt */
		crc_pwm_disable(c, pwm);
		clk_div = PWM_BASE_CLK * period_ns / NSEC_PER_SEC;

		regmap_write(crc_pwm->regmap, PWM0_CLK_DIV,
					clk_div | PWM_OUTPUT_ENABLE);

		/* enable back */
		crc_pwm_enable(c, pwm);
	}

	/* change the pwm duty cycle */
	level = duty_ns * PWM_MAX_LEVEL / period_ns;
	regmap_write(crc_pwm->regmap, PWM0_DUTY_CYCLE, level);

	return 0;
}

static const struct pwm_ops crc_pwm_ops = {
	.config = crc_pwm_config,
	.enable = crc_pwm_enable,
	.disable = crc_pwm_disable,
};

static int crystalcove_pwm_probe(struct platform_device *pdev)
{
	struct crystalcove_pwm *pwm;
	struct device *dev = pdev->dev.parent;
	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);

	pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
	if (!pwm)
		return -ENOMEM;

	pwm->chip.dev = &pdev->dev;
	pwm->chip.ops = &crc_pwm_ops;
	pwm->chip.base = -1;
	pwm->chip.npwm = 1;

	/* get the PMIC regmap */
	pwm->regmap = pmic->regmap;

	platform_set_drvdata(pdev, pwm);

	return pwmchip_add(&pwm->chip);
}

static int crystalcove_pwm_remove(struct platform_device *pdev)
{
	struct crystalcove_pwm *pwm = platform_get_drvdata(pdev);

	return pwmchip_remove(&pwm->chip);
}

static struct platform_driver crystalcove_pwm_driver = {
	.probe = crystalcove_pwm_probe,
	.remove = crystalcove_pwm_remove,
	.driver = {
		.name = "crystal_cove_pwm",
	},
};

builtin_platform_driver(crystalcove_pwm_driver);
Commit	Line	Data
a3f37a10 SK	1	/*
	2	* Copyright (C) 2015 Intel Corporation. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License version
	6	* 2 as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* Author: Shobhit Kumar <shobhit.kumar@intel.com>
	14	*/
	15
	16	#include <linux/platform_device.h>
	17	#include <linux/regmap.h>
	18	#include <linux/mfd/intel_soc_pmic.h>
	19	#include <linux/pwm.h>
	20
	21	#define PWM0_CLK_DIV 0x4B
	22	#define PWM_OUTPUT_ENABLE BIT(7)
	23	#define PWM_DIV_CLK_0 0x00 /* DIVIDECLK = BASECLK */
	24	#define PWM_DIV_CLK_100 0x63 /* DIVIDECLK = BASECLK/100 */
	25	#define PWM_DIV_CLK_128 0x7F /* DIVIDECLK = BASECLK/128 */
	26
	27	#define PWM0_DUTY_CYCLE 0x4E
	28	#define BACKLIGHT_EN 0x51
	29
	30	#define PWM_MAX_LEVEL 0xFF
	31
	32	#define PWM_BASE_CLK 6000000 /* 6 MHz */
	33	#define PWM_MAX_PERIOD_NS 21333 /* 46.875KHz */
	34
	35	/**
	36	* struct crystalcove_pwm - Crystal Cove PWM controller
	37	* @chip: the abstract pwm_chip structure.
	38	* @regmap: the regmap from the parent device.
	39	*/
	40	struct crystalcove_pwm {
	41	struct pwm_chip chip;
	42	struct regmap *regmap;
	43	};
	44
	45	static inline struct crystalcove_pwm to_crc_pwm(struct pwm_chip pc)
	46	{
	47	return container_of(pc, struct crystalcove_pwm, chip);
	48	}
	49
	50	static int crc_pwm_enable(struct pwm_chip c, struct pwm_device pwm)
	51	{
	52	struct crystalcove_pwm *crc_pwm = to_crc_pwm(c);
	53
	54	regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 1);
	55
	56	return 0;
	57	}
	58
	59	static void crc_pwm_disable(struct pwm_chip c, struct pwm_device pwm)
	60	{
	61	struct crystalcove_pwm *crc_pwm = to_crc_pwm(c);
	62
	63	regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 0);
	64	}
65
66	static int crc_pwm_config(struct pwm_chip c, struct pwm_device pwm,
67	int duty_ns, int period_ns)
68	{
69	struct crystalcove_pwm *crc_pwm = to_crc_pwm(c);
70	struct device *dev = crc_pwm->chip.dev;
71	int level;
72
73	if (period_ns > PWM_MAX_PERIOD_NS) {
74	dev_err(dev, "un-supported period_ns\n");
75	return -EINVAL;
76	}
77
4b58896f	78	if (pwm_get_period(pwm) != period_ns) {
a3f37a10 SK	79	int clk_div;
	80
	81	/* changing the clk divisor, need to disable fisrt */
	82	crc_pwm_disable(c, pwm);
	83	clk_div = PWM_BASE_CLK * period_ns / NSEC_PER_SEC;
	84
	85	regmap_write(crc_pwm->regmap, PWM0_CLK_DIV,
	86	clk_div \| PWM_OUTPUT_ENABLE);
	87
	88	/* enable back */
	89	crc_pwm_enable(c, pwm);
	90	}
	91
	92	/* change the pwm duty cycle */
	93	level = duty_ns * PWM_MAX_LEVEL / period_ns;
	94	regmap_write(crc_pwm->regmap, PWM0_DUTY_CYCLE, level);
	95
	96	return 0;
	97	}
	98
	99	static const struct pwm_ops crc_pwm_ops = {
	100	.config = crc_pwm_config,
	101	.enable = crc_pwm_enable,
	102	.disable = crc_pwm_disable,
	103	};
	104
	105	static int crystalcove_pwm_probe(struct platform_device *pdev)
	106	{
	107	struct crystalcove_pwm *pwm;
	108	struct device *dev = pdev->dev.parent;
	109	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
	110
	111	pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
	112	if (!pwm)
	113	return -ENOMEM;
	114
	115	pwm->chip.dev = &pdev->dev;
	116	pwm->chip.ops = &crc_pwm_ops;
	117	pwm->chip.base = -1;
	118	pwm->chip.npwm = 1;
	119
	120	/* get the PMIC regmap */
	121	pwm->regmap = pmic->regmap;
	122
	123	platform_set_drvdata(pdev, pwm);
	124
	125	return pwmchip_add(&pwm->chip);
	126	}
	127
	128	static int crystalcove_pwm_remove(struct platform_device *pdev)
	129	{
	130	struct crystalcove_pwm *pwm = platform_get_drvdata(pdev);
	131
	132	return pwmchip_remove(&pwm->chip);
	133	}
	134
	135	static struct platform_driver crystalcove_pwm_driver = {
	136	.probe = crystalcove_pwm_probe,
	137	.remove = crystalcove_pwm_remove,
	138	.driver = {
	139	.name = "crystal_cove_pwm",
	140	},
	141	};
	142
143	builtin_platform_driver(crystalcove_pwm_driver);