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Commit | Line | Data |
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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
b505183b XL |
2 | /* |
3 | * Freescale FlexTimer Module (FTM) PWM Driver | |
4 | * | |
5 | * Copyright 2012-2013 Freescale Semiconductor, Inc. | |
b505183b XL |
6 | */ |
7 | ||
8 | #include <linux/clk.h> | |
9 | #include <linux/err.h> | |
10 | #include <linux/io.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/mutex.h> | |
14 | #include <linux/of_address.h> | |
db6c51ab | 15 | #include <linux/of_device.h> |
b505183b | 16 | #include <linux/platform_device.h> |
97d0b42e | 17 | #include <linux/pm.h> |
b505183b | 18 | #include <linux/pwm.h> |
42fa98a9 | 19 | #include <linux/regmap.h> |
b505183b | 20 | #include <linux/slab.h> |
e590eb40 | 21 | #include <linux/fsl/ftm.h> |
b505183b | 22 | |
cd6d92d2 | 23 | #define FTM_SC_CLK(c) (((c) + 1) << FTM_SC_CLK_MASK_SHIFT) |
b505183b XL |
24 | |
25 | enum fsl_pwm_clk { | |
26 | FSL_PWM_CLK_SYS, | |
27 | FSL_PWM_CLK_FIX, | |
28 | FSL_PWM_CLK_EXT, | |
29 | FSL_PWM_CLK_CNTEN, | |
30 | FSL_PWM_CLK_MAX | |
31 | }; | |
32 | ||
db6c51ab | 33 | struct fsl_ftm_soc { |
34 | bool has_enable_bits; | |
35 | }; | |
36 | ||
3479bbd1 PH |
37 | struct fsl_pwm_periodcfg { |
38 | enum fsl_pwm_clk clk_select; | |
39 | unsigned int clk_ps; | |
40 | unsigned int mod_period; | |
41 | }; | |
42 | ||
b505183b XL |
43 | struct fsl_pwm_chip { |
44 | struct pwm_chip chip; | |
b505183b | 45 | struct mutex lock; |
42fa98a9 | 46 | struct regmap *regmap; |
b505183b | 47 | |
3479bbd1 PH |
48 | /* This value is valid iff a pwm is running */ |
49 | struct fsl_pwm_periodcfg period; | |
b505183b | 50 | |
82a9c55a | 51 | struct clk *ipg_clk; |
b505183b | 52 | struct clk *clk[FSL_PWM_CLK_MAX]; |
db6c51ab | 53 | |
54 | const struct fsl_ftm_soc *soc; | |
b505183b XL |
55 | }; |
56 | ||
57 | static inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip) | |
58 | { | |
59 | return container_of(chip, struct fsl_pwm_chip, chip); | |
60 | } | |
61 | ||
a2a28229 PH |
62 | static void ftm_clear_write_protection(struct fsl_pwm_chip *fpc) |
63 | { | |
64 | u32 val; | |
65 | ||
66 | regmap_read(fpc->regmap, FTM_FMS, &val); | |
67 | if (val & FTM_FMS_WPEN) | |
68 | regmap_update_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS, | |
69 | FTM_MODE_WPDIS); | |
70 | } | |
71 | ||
72 | static void ftm_set_write_protection(struct fsl_pwm_chip *fpc) | |
73 | { | |
74 | regmap_update_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN, FTM_FMS_WPEN); | |
75 | } | |
76 | ||
3479bbd1 PH |
77 | static bool fsl_pwm_periodcfg_are_equal(const struct fsl_pwm_periodcfg *a, |
78 | const struct fsl_pwm_periodcfg *b) | |
79 | { | |
80 | if (a->clk_select != b->clk_select) | |
81 | return false; | |
82 | if (a->clk_ps != b->clk_ps) | |
83 | return false; | |
84 | if (a->mod_period != b->mod_period) | |
85 | return false; | |
86 | return true; | |
87 | } | |
88 | ||
b505183b XL |
89 | static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) |
90 | { | |
db6c51ab | 91 | int ret; |
b505183b XL |
92 | struct fsl_pwm_chip *fpc = to_fsl_chip(chip); |
93 | ||
db6c51ab | 94 | ret = clk_prepare_enable(fpc->ipg_clk); |
95 | if (!ret && fpc->soc->has_enable_bits) { | |
96 | mutex_lock(&fpc->lock); | |
97 | regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16), | |
98 | BIT(pwm->hwpwm + 16)); | |
99 | mutex_unlock(&fpc->lock); | |
100 | } | |
101 | ||
102 | return ret; | |
b505183b XL |
103 | } |
104 | ||
105 | static void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) | |
106 | { | |
107 | struct fsl_pwm_chip *fpc = to_fsl_chip(chip); | |
108 | ||
db6c51ab | 109 | if (fpc->soc->has_enable_bits) { |
110 | mutex_lock(&fpc->lock); | |
111 | regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16), | |
112 | 0); | |
113 | mutex_unlock(&fpc->lock); | |
114 | } | |
115 | ||
82a9c55a | 116 | clk_disable_unprepare(fpc->ipg_clk); |
b505183b XL |
117 | } |
118 | ||
3479bbd1 PH |
119 | static unsigned int fsl_pwm_ticks_to_ns(struct fsl_pwm_chip *fpc, |
120 | unsigned int ticks) | |
b505183b | 121 | { |
3479bbd1 PH |
122 | unsigned long rate; |
123 | unsigned long long exval; | |
124 | ||
125 | rate = clk_get_rate(fpc->clk[fpc->period.clk_select]); | |
126 | exval = ticks; | |
127 | exval *= 1000000000UL; | |
128 | do_div(exval, rate >> fpc->period.clk_ps); | |
129 | return exval; | |
b505183b XL |
130 | } |
131 | ||
3479bbd1 PH |
132 | static bool fsl_pwm_calculate_period_clk(struct fsl_pwm_chip *fpc, |
133 | unsigned int period_ns, | |
134 | enum fsl_pwm_clk index, | |
135 | struct fsl_pwm_periodcfg *periodcfg | |
136 | ) | |
b505183b | 137 | { |
3479bbd1 PH |
138 | unsigned long long c; |
139 | unsigned int ps; | |
b505183b | 140 | |
3479bbd1 | 141 | c = clk_get_rate(fpc->clk[index]); |
b505183b XL |
142 | c = c * period_ns; |
143 | do_div(c, 1000000000UL); | |
144 | ||
3479bbd1 PH |
145 | if (c == 0) |
146 | return false; | |
b505183b | 147 | |
3479bbd1 PH |
148 | for (ps = 0; ps < 8 ; ++ps, c >>= 1) { |
149 | if (c <= 0x10000) { | |
150 | periodcfg->clk_select = index; | |
151 | periodcfg->clk_ps = ps; | |
152 | periodcfg->mod_period = c - 1; | |
153 | return true; | |
154 | } | |
b505183b | 155 | } |
3479bbd1 | 156 | return false; |
b505183b XL |
157 | } |
158 | ||
3479bbd1 PH |
159 | static bool fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc, |
160 | unsigned int period_ns, | |
161 | struct fsl_pwm_periodcfg *periodcfg) | |
b505183b XL |
162 | { |
163 | enum fsl_pwm_clk m0, m1; | |
3479bbd1 PH |
164 | unsigned long fix_rate, ext_rate; |
165 | bool ret; | |
b505183b | 166 | |
3479bbd1 PH |
167 | ret = fsl_pwm_calculate_period_clk(fpc, period_ns, FSL_PWM_CLK_SYS, |
168 | periodcfg); | |
169 | if (ret) | |
170 | return true; | |
b505183b XL |
171 | |
172 | fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]); | |
173 | ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]); | |
174 | ||
175 | if (fix_rate > ext_rate) { | |
176 | m0 = FSL_PWM_CLK_FIX; | |
177 | m1 = FSL_PWM_CLK_EXT; | |
178 | } else { | |
179 | m0 = FSL_PWM_CLK_EXT; | |
180 | m1 = FSL_PWM_CLK_FIX; | |
181 | } | |
182 | ||
3479bbd1 PH |
183 | ret = fsl_pwm_calculate_period_clk(fpc, period_ns, m0, periodcfg); |
184 | if (ret) | |
185 | return true; | |
b505183b | 186 | |
3479bbd1 | 187 | return fsl_pwm_calculate_period_clk(fpc, period_ns, m1, periodcfg); |
b505183b XL |
188 | } |
189 | ||
3479bbd1 PH |
190 | static unsigned int fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc, |
191 | unsigned int duty_ns) | |
b505183b | 192 | { |
42fa98a9 | 193 | unsigned long long duty; |
b505183b | 194 | |
3479bbd1 PH |
195 | unsigned int period = fpc->period.mod_period + 1; |
196 | unsigned int period_ns = fsl_pwm_ticks_to_ns(fpc, period); | |
197 | ||
198 | duty = (unsigned long long)duty_ns * period; | |
b505183b XL |
199 | do_div(duty, period_ns); |
200 | ||
3479bbd1 | 201 | return (unsigned int)duty; |
b505183b XL |
202 | } |
203 | ||
3479bbd1 PH |
204 | static bool fsl_pwm_is_any_pwm_enabled(struct fsl_pwm_chip *fpc, |
205 | struct pwm_device *pwm) | |
b505183b | 206 | { |
3479bbd1 | 207 | u32 val; |
b505183b | 208 | |
3479bbd1 PH |
209 | regmap_read(fpc->regmap, FTM_OUTMASK, &val); |
210 | if (~val & 0xFF) | |
211 | return true; | |
212 | else | |
213 | return false; | |
214 | } | |
215 | ||
216 | static bool fsl_pwm_is_other_pwm_enabled(struct fsl_pwm_chip *fpc, | |
217 | struct pwm_device *pwm) | |
218 | { | |
219 | u32 val; | |
b505183b | 220 | |
3479bbd1 PH |
221 | regmap_read(fpc->regmap, FTM_OUTMASK, &val); |
222 | if (~(val | BIT(pwm->hwpwm)) & 0xFF) | |
223 | return true; | |
224 | else | |
225 | return false; | |
226 | } | |
227 | ||
228 | static int fsl_pwm_apply_config(struct fsl_pwm_chip *fpc, | |
229 | struct pwm_device *pwm, | |
71523d18 | 230 | const struct pwm_state *newstate) |
3479bbd1 PH |
231 | { |
232 | unsigned int duty; | |
233 | u32 reg_polarity; | |
b505183b | 234 | |
3479bbd1 PH |
235 | struct fsl_pwm_periodcfg periodcfg; |
236 | bool do_write_period = false; | |
237 | ||
238 | if (!fsl_pwm_calculate_period(fpc, newstate->period, &periodcfg)) { | |
239 | dev_err(fpc->chip.dev, "failed to calculate new period\n"); | |
240 | return -EINVAL; | |
241 | } | |
242 | ||
243 | if (!fsl_pwm_is_any_pwm_enabled(fpc, pwm)) | |
244 | do_write_period = true; | |
b505183b XL |
245 | /* |
246 | * The Freescale FTM controller supports only a single period for | |
3479bbd1 PH |
247 | * all PWM channels, therefore verify if the newly computed period |
248 | * is different than the current period being used. In such case | |
249 | * we allow to change the period only if no other pwm is running. | |
b505183b | 250 | */ |
3479bbd1 PH |
251 | else if (!fsl_pwm_periodcfg_are_equal(&fpc->period, &periodcfg)) { |
252 | if (fsl_pwm_is_other_pwm_enabled(fpc, pwm)) { | |
253 | dev_err(fpc->chip.dev, | |
254 | "Cannot change period for PWM %u, disable other PWMs first\n", | |
255 | pwm->hwpwm); | |
256 | return -EBUSY; | |
b505183b | 257 | } |
3479bbd1 PH |
258 | if (fpc->period.clk_select != periodcfg.clk_select) { |
259 | int ret; | |
260 | enum fsl_pwm_clk oldclk = fpc->period.clk_select; | |
261 | enum fsl_pwm_clk newclk = periodcfg.clk_select; | |
262 | ||
263 | ret = clk_prepare_enable(fpc->clk[newclk]); | |
264 | if (ret) | |
265 | return ret; | |
266 | clk_disable_unprepare(fpc->clk[oldclk]); | |
267 | } | |
268 | do_write_period = true; | |
b505183b XL |
269 | } |
270 | ||
a2a28229 | 271 | ftm_clear_write_protection(fpc); |
b505183b | 272 | |
3479bbd1 PH |
273 | if (do_write_period) { |
274 | regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK, | |
275 | FTM_SC_CLK(periodcfg.clk_select)); | |
42fa98a9 | 276 | regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK, |
3479bbd1 PH |
277 | periodcfg.clk_ps); |
278 | regmap_write(fpc->regmap, FTM_MOD, periodcfg.mod_period); | |
b505183b | 279 | |
3479bbd1 | 280 | fpc->period = periodcfg; |
b505183b XL |
281 | } |
282 | ||
3479bbd1 | 283 | duty = fsl_pwm_calculate_duty(fpc, newstate->duty_cycle); |
b505183b | 284 | |
42fa98a9 XL |
285 | regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm), |
286 | FTM_CSC_MSB | FTM_CSC_ELSB); | |
287 | regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty); | |
b505183b | 288 | |
3479bbd1 PH |
289 | reg_polarity = 0; |
290 | if (newstate->polarity == PWM_POLARITY_INVERSED) | |
291 | reg_polarity = BIT(pwm->hwpwm); | |
b505183b | 292 | |
3479bbd1 | 293 | regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity); |
b505183b | 294 | |
a2a28229 | 295 | ftm_set_write_protection(fpc); |
b505183b XL |
296 | |
297 | return 0; | |
298 | } | |
299 | ||
3479bbd1 | 300 | static int fsl_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
71523d18 | 301 | const struct pwm_state *newstate) |
b505183b XL |
302 | { |
303 | struct fsl_pwm_chip *fpc = to_fsl_chip(chip); | |
3479bbd1 PH |
304 | struct pwm_state *oldstate = &pwm->state; |
305 | int ret = 0; | |
b505183b | 306 | |
3479bbd1 PH |
307 | /* |
308 | * oldstate to newstate : action | |
309 | * | |
310 | * disabled to disabled : ignore | |
311 | * enabled to disabled : disable | |
312 | * enabled to enabled : update settings | |
313 | * disabled to enabled : update settings + enable | |
314 | */ | |
b505183b | 315 | |
3479bbd1 | 316 | mutex_lock(&fpc->lock); |
b505183b | 317 | |
3479bbd1 PH |
318 | if (!newstate->enabled) { |
319 | if (oldstate->enabled) { | |
320 | regmap_update_bits(fpc->regmap, FTM_OUTMASK, | |
321 | BIT(pwm->hwpwm), BIT(pwm->hwpwm)); | |
322 | clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]); | |
323 | clk_disable_unprepare(fpc->clk[fpc->period.clk_select]); | |
324 | } | |
b505183b | 325 | |
3479bbd1 PH |
326 | goto end_mutex; |
327 | } | |
b505183b | 328 | |
3479bbd1 PH |
329 | ret = fsl_pwm_apply_config(fpc, pwm, newstate); |
330 | if (ret) | |
331 | goto end_mutex; | |
332 | ||
333 | /* check if need to enable */ | |
334 | if (!oldstate->enabled) { | |
335 | ret = clk_prepare_enable(fpc->clk[fpc->period.clk_select]); | |
336 | if (ret) | |
3d25025c | 337 | goto end_mutex; |
3479bbd1 PH |
338 | |
339 | ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]); | |
340 | if (ret) { | |
341 | clk_disable_unprepare(fpc->clk[fpc->period.clk_select]); | |
3d25025c | 342 | goto end_mutex; |
3479bbd1 | 343 | } |
b505183b | 344 | |
3479bbd1 PH |
345 | regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm), |
346 | 0); | |
347 | } | |
b505183b | 348 | |
3479bbd1 | 349 | end_mutex: |
b505183b | 350 | mutex_unlock(&fpc->lock); |
3479bbd1 | 351 | return ret; |
b505183b XL |
352 | } |
353 | ||
354 | static const struct pwm_ops fsl_pwm_ops = { | |
355 | .request = fsl_pwm_request, | |
356 | .free = fsl_pwm_free, | |
3479bbd1 | 357 | .apply = fsl_pwm_apply, |
b505183b XL |
358 | .owner = THIS_MODULE, |
359 | }; | |
360 | ||
361 | static int fsl_pwm_init(struct fsl_pwm_chip *fpc) | |
362 | { | |
363 | int ret; | |
364 | ||
82a9c55a | 365 | ret = clk_prepare_enable(fpc->ipg_clk); |
b505183b XL |
366 | if (ret) |
367 | return ret; | |
368 | ||
42fa98a9 XL |
369 | regmap_write(fpc->regmap, FTM_CNTIN, 0x00); |
370 | regmap_write(fpc->regmap, FTM_OUTINIT, 0x00); | |
371 | regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF); | |
b505183b | 372 | |
82a9c55a | 373 | clk_disable_unprepare(fpc->ipg_clk); |
b505183b XL |
374 | |
375 | return 0; | |
376 | } | |
377 | ||
49599cf6 XL |
378 | static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg) |
379 | { | |
380 | switch (reg) { | |
a2a28229 PH |
381 | case FTM_FMS: |
382 | case FTM_MODE: | |
49599cf6 XL |
383 | case FTM_CNT: |
384 | return true; | |
385 | } | |
386 | return false; | |
387 | } | |
388 | ||
42fa98a9 XL |
389 | static const struct regmap_config fsl_pwm_regmap_config = { |
390 | .reg_bits = 32, | |
391 | .reg_stride = 4, | |
392 | .val_bits = 32, | |
393 | ||
394 | .max_register = FTM_PWMLOAD, | |
49599cf6 | 395 | .volatile_reg = fsl_pwm_volatile_reg, |
ad06fdee | 396 | .cache_type = REGCACHE_FLAT, |
42fa98a9 XL |
397 | }; |
398 | ||
b505183b XL |
399 | static int fsl_pwm_probe(struct platform_device *pdev) |
400 | { | |
401 | struct fsl_pwm_chip *fpc; | |
402 | struct resource *res; | |
42fa98a9 | 403 | void __iomem *base; |
b505183b XL |
404 | int ret; |
405 | ||
406 | fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL); | |
407 | if (!fpc) | |
408 | return -ENOMEM; | |
409 | ||
410 | mutex_init(&fpc->lock); | |
411 | ||
db6c51ab | 412 | fpc->soc = of_device_get_match_data(&pdev->dev); |
b505183b XL |
413 | fpc->chip.dev = &pdev->dev; |
414 | ||
415 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
42fa98a9 XL |
416 | base = devm_ioremap_resource(&pdev->dev, res); |
417 | if (IS_ERR(base)) | |
418 | return PTR_ERR(base); | |
419 | ||
97d0b42e | 420 | fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base, |
42fa98a9 XL |
421 | &fsl_pwm_regmap_config); |
422 | if (IS_ERR(fpc->regmap)) { | |
423 | dev_err(&pdev->dev, "regmap init failed\n"); | |
424 | return PTR_ERR(fpc->regmap); | |
425 | } | |
b505183b XL |
426 | |
427 | fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys"); | |
428 | if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) { | |
429 | dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n"); | |
430 | return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]); | |
431 | } | |
432 | ||
433 | fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix"); | |
434 | if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX])) | |
435 | return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]); | |
436 | ||
437 | fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext"); | |
438 | if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT])) | |
439 | return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]); | |
440 | ||
441 | fpc->clk[FSL_PWM_CLK_CNTEN] = | |
442 | devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en"); | |
443 | if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN])) | |
444 | return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]); | |
445 | ||
82a9c55a | 446 | /* |
447 | * ipg_clk is the interface clock for the IP. If not provided, use the | |
448 | * ftm_sys clock as the default. | |
449 | */ | |
450 | fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); | |
451 | if (IS_ERR(fpc->ipg_clk)) | |
452 | fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS]; | |
453 | ||
454 | ||
b505183b XL |
455 | fpc->chip.ops = &fsl_pwm_ops; |
456 | fpc->chip.of_xlate = of_pwm_xlate_with_flags; | |
457 | fpc->chip.of_pwm_n_cells = 3; | |
458 | fpc->chip.base = -1; | |
459 | fpc->chip.npwm = 8; | |
460 | ||
461 | ret = pwmchip_add(&fpc->chip); | |
462 | if (ret < 0) { | |
463 | dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); | |
464 | return ret; | |
465 | } | |
466 | ||
467 | platform_set_drvdata(pdev, fpc); | |
468 | ||
469 | return fsl_pwm_init(fpc); | |
470 | } | |
471 | ||
472 | static int fsl_pwm_remove(struct platform_device *pdev) | |
473 | { | |
474 | struct fsl_pwm_chip *fpc = platform_get_drvdata(pdev); | |
475 | ||
476 | return pwmchip_remove(&fpc->chip); | |
477 | } | |
478 | ||
97d0b42e XL |
479 | #ifdef CONFIG_PM_SLEEP |
480 | static int fsl_pwm_suspend(struct device *dev) | |
481 | { | |
482 | struct fsl_pwm_chip *fpc = dev_get_drvdata(dev); | |
816aec23 | 483 | int i; |
97d0b42e XL |
484 | |
485 | regcache_cache_only(fpc->regmap, true); | |
486 | regcache_mark_dirty(fpc->regmap); | |
487 | ||
816aec23 SA |
488 | for (i = 0; i < fpc->chip.npwm; i++) { |
489 | struct pwm_device *pwm = &fpc->chip.pwms[i]; | |
490 | ||
491 | if (!test_bit(PWMF_REQUESTED, &pwm->flags)) | |
492 | continue; | |
493 | ||
82a9c55a | 494 | clk_disable_unprepare(fpc->ipg_clk); |
816aec23 SA |
495 | |
496 | if (!pwm_is_enabled(pwm)) | |
497 | continue; | |
498 | ||
97d0b42e | 499 | clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]); |
3479bbd1 | 500 | clk_disable_unprepare(fpc->clk[fpc->period.clk_select]); |
97d0b42e XL |
501 | } |
502 | ||
503 | return 0; | |
504 | } | |
505 | ||
506 | static int fsl_pwm_resume(struct device *dev) | |
507 | { | |
508 | struct fsl_pwm_chip *fpc = dev_get_drvdata(dev); | |
816aec23 SA |
509 | int i; |
510 | ||
511 | for (i = 0; i < fpc->chip.npwm; i++) { | |
512 | struct pwm_device *pwm = &fpc->chip.pwms[i]; | |
513 | ||
514 | if (!test_bit(PWMF_REQUESTED, &pwm->flags)) | |
515 | continue; | |
97d0b42e | 516 | |
82a9c55a | 517 | clk_prepare_enable(fpc->ipg_clk); |
816aec23 SA |
518 | |
519 | if (!pwm_is_enabled(pwm)) | |
520 | continue; | |
521 | ||
3479bbd1 | 522 | clk_prepare_enable(fpc->clk[fpc->period.clk_select]); |
97d0b42e XL |
523 | clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]); |
524 | } | |
525 | ||
526 | /* restore all registers from cache */ | |
527 | regcache_cache_only(fpc->regmap, false); | |
528 | regcache_sync(fpc->regmap); | |
529 | ||
530 | return 0; | |
531 | } | |
532 | #endif | |
533 | ||
534 | static const struct dev_pm_ops fsl_pwm_pm_ops = { | |
535 | SET_SYSTEM_SLEEP_PM_OPS(fsl_pwm_suspend, fsl_pwm_resume) | |
536 | }; | |
537 | ||
db6c51ab | 538 | static const struct fsl_ftm_soc vf610_ftm_pwm = { |
539 | .has_enable_bits = false, | |
540 | }; | |
541 | ||
2c4f2e32 | 542 | static const struct fsl_ftm_soc imx8qm_ftm_pwm = { |
543 | .has_enable_bits = true, | |
544 | }; | |
545 | ||
b505183b | 546 | static const struct of_device_id fsl_pwm_dt_ids[] = { |
db6c51ab | 547 | { .compatible = "fsl,vf610-ftm-pwm", .data = &vf610_ftm_pwm }, |
2c4f2e32 | 548 | { .compatible = "fsl,imx8qm-ftm-pwm", .data = &imx8qm_ftm_pwm }, |
b505183b XL |
549 | { /* sentinel */ } |
550 | }; | |
551 | MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids); | |
552 | ||
553 | static struct platform_driver fsl_pwm_driver = { | |
554 | .driver = { | |
555 | .name = "fsl-ftm-pwm", | |
556 | .of_match_table = fsl_pwm_dt_ids, | |
97d0b42e | 557 | .pm = &fsl_pwm_pm_ops, |
b505183b XL |
558 | }, |
559 | .probe = fsl_pwm_probe, | |
560 | .remove = fsl_pwm_remove, | |
561 | }; | |
562 | module_platform_driver(fsl_pwm_driver); | |
563 | ||
564 | MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver"); | |
565 | MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>"); | |
566 | MODULE_ALIAS("platform:fsl-ftm-pwm"); | |
567 | MODULE_LICENSE("GPL"); |