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d09f0081 | 1 | /* |
2 | * PWM Controller Driver for HiSilicon BVT SoCs | |
3 | * | |
4 | * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include <linux/bitops.h> | |
21 | #include <linux/clk.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/of_device.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/pwm.h> | |
28 | #include <linux/reset.h> | |
29 | ||
30 | #define PWM_CFG0_ADDR(x) (((x) * 0x20) + 0x0) | |
31 | #define PWM_CFG1_ADDR(x) (((x) * 0x20) + 0x4) | |
32 | #define PWM_CFG2_ADDR(x) (((x) * 0x20) + 0x8) | |
33 | #define PWM_CTRL_ADDR(x) (((x) * 0x20) + 0xC) | |
34 | ||
35 | #define PWM_ENABLE_SHIFT 0 | |
36 | #define PWM_ENABLE_MASK BIT(0) | |
37 | ||
38 | #define PWM_POLARITY_SHIFT 1 | |
39 | #define PWM_POLARITY_MASK BIT(1) | |
40 | ||
41 | #define PWM_KEEP_SHIFT 2 | |
42 | #define PWM_KEEP_MASK BIT(2) | |
43 | ||
44 | #define PWM_PERIOD_MASK GENMASK(31, 0) | |
45 | #define PWM_DUTY_MASK GENMASK(31, 0) | |
46 | ||
47 | struct hibvt_pwm_chip { | |
48 | struct pwm_chip chip; | |
49 | struct clk *clk; | |
50 | void __iomem *base; | |
51 | struct reset_control *rstc; | |
52 | }; | |
53 | ||
54 | struct hibvt_pwm_soc { | |
55 | u32 num_pwms; | |
56 | }; | |
57 | ||
58 | static const struct hibvt_pwm_soc pwm_soc[2] = { | |
59 | { .num_pwms = 4 }, | |
60 | { .num_pwms = 8 }, | |
61 | }; | |
62 | ||
63 | static inline struct hibvt_pwm_chip *to_hibvt_pwm_chip(struct pwm_chip *chip) | |
64 | { | |
65 | return container_of(chip, struct hibvt_pwm_chip, chip); | |
66 | } | |
67 | ||
68 | static void hibvt_pwm_set_bits(void __iomem *base, u32 offset, | |
69 | u32 mask, u32 data) | |
70 | { | |
71 | void __iomem *address = base + offset; | |
72 | u32 value; | |
73 | ||
74 | value = readl(address); | |
75 | value &= ~mask; | |
76 | value |= (data & mask); | |
77 | writel(value, address); | |
78 | } | |
79 | ||
80 | static void hibvt_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) | |
81 | { | |
82 | struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip); | |
83 | ||
84 | hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), | |
85 | PWM_ENABLE_MASK, 0x1); | |
86 | } | |
87 | ||
88 | static void hibvt_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) | |
89 | { | |
90 | struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip); | |
91 | ||
92 | hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), | |
93 | PWM_ENABLE_MASK, 0x0); | |
94 | } | |
95 | ||
96 | static void hibvt_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, | |
97 | int duty_cycle_ns, int period_ns) | |
98 | { | |
99 | struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip); | |
100 | u32 freq, period, duty; | |
101 | ||
102 | freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000); | |
103 | ||
104 | period = div_u64(freq * period_ns, 1000); | |
105 | duty = div_u64(period * duty_cycle_ns, period_ns); | |
106 | ||
107 | hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG0_ADDR(pwm->hwpwm), | |
108 | PWM_PERIOD_MASK, period); | |
109 | ||
110 | hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG1_ADDR(pwm->hwpwm), | |
111 | PWM_DUTY_MASK, duty); | |
112 | } | |
113 | ||
114 | static void hibvt_pwm_set_polarity(struct pwm_chip *chip, | |
115 | struct pwm_device *pwm, | |
116 | enum pwm_polarity polarity) | |
117 | { | |
118 | struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip); | |
119 | ||
120 | if (polarity == PWM_POLARITY_INVERSED) | |
121 | hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), | |
122 | PWM_POLARITY_MASK, (0x1 << PWM_POLARITY_SHIFT)); | |
123 | else | |
124 | hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), | |
125 | PWM_POLARITY_MASK, (0x0 << PWM_POLARITY_SHIFT)); | |
126 | } | |
127 | ||
128 | static void hibvt_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, | |
129 | struct pwm_state *state) | |
130 | { | |
131 | struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip); | |
132 | void __iomem *base; | |
133 | u32 freq, value; | |
134 | ||
135 | freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000); | |
136 | base = hi_pwm_chip->base; | |
137 | ||
138 | value = readl(base + PWM_CFG0_ADDR(pwm->hwpwm)); | |
139 | state->period = div_u64(value * 1000, freq); | |
140 | ||
141 | value = readl(base + PWM_CFG1_ADDR(pwm->hwpwm)); | |
142 | state->duty_cycle = div_u64(value * 1000, freq); | |
143 | ||
144 | value = readl(base + PWM_CTRL_ADDR(pwm->hwpwm)); | |
145 | state->enabled = (PWM_ENABLE_MASK & value); | |
146 | } | |
147 | ||
148 | static int hibvt_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, | |
149 | struct pwm_state *state) | |
150 | { | |
151 | if (state->polarity != pwm->state.polarity) | |
152 | hibvt_pwm_set_polarity(chip, pwm, state->polarity); | |
153 | ||
154 | if (state->period != pwm->state.period || | |
155 | state->duty_cycle != pwm->state.duty_cycle) | |
156 | hibvt_pwm_config(chip, pwm, state->duty_cycle, state->period); | |
157 | ||
158 | if (state->enabled != pwm->state.enabled) { | |
159 | if (state->enabled) | |
160 | hibvt_pwm_enable(chip, pwm); | |
161 | else | |
162 | hibvt_pwm_disable(chip, pwm); | |
163 | } | |
164 | ||
165 | return 0; | |
166 | } | |
167 | ||
168 | static struct pwm_ops hibvt_pwm_ops = { | |
169 | .get_state = hibvt_pwm_get_state, | |
170 | .apply = hibvt_pwm_apply, | |
171 | ||
172 | .owner = THIS_MODULE, | |
173 | }; | |
174 | ||
175 | static int hibvt_pwm_probe(struct platform_device *pdev) | |
176 | { | |
177 | const struct hibvt_pwm_soc *soc = | |
178 | of_device_get_match_data(&pdev->dev); | |
179 | struct hibvt_pwm_chip *pwm_chip; | |
180 | struct resource *res; | |
181 | int ret; | |
182 | int i; | |
183 | ||
184 | pwm_chip = devm_kzalloc(&pdev->dev, sizeof(*pwm_chip), GFP_KERNEL); | |
185 | if (pwm_chip == NULL) | |
186 | return -ENOMEM; | |
187 | ||
188 | pwm_chip->clk = devm_clk_get(&pdev->dev, NULL); | |
189 | if (IS_ERR(pwm_chip->clk)) { | |
190 | dev_err(&pdev->dev, "getting clock failed with %ld\n", | |
191 | PTR_ERR(pwm_chip->clk)); | |
192 | return PTR_ERR(pwm_chip->clk); | |
193 | } | |
194 | ||
195 | pwm_chip->chip.ops = &hibvt_pwm_ops; | |
196 | pwm_chip->chip.dev = &pdev->dev; | |
197 | pwm_chip->chip.base = -1; | |
198 | pwm_chip->chip.npwm = soc->num_pwms; | |
199 | pwm_chip->chip.of_xlate = of_pwm_xlate_with_flags; | |
200 | pwm_chip->chip.of_pwm_n_cells = 3; | |
201 | ||
202 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
203 | pwm_chip->base = devm_ioremap_resource(&pdev->dev, res); | |
204 | if (IS_ERR(pwm_chip->base)) | |
205 | return PTR_ERR(pwm_chip->base); | |
206 | ||
207 | ret = clk_prepare_enable(pwm_chip->clk); | |
208 | if (ret < 0) | |
209 | return ret; | |
210 | ||
211 | pwm_chip->rstc = devm_reset_control_get(&pdev->dev, NULL); | |
212 | if (IS_ERR(pwm_chip->rstc)) { | |
213 | clk_disable_unprepare(pwm_chip->clk); | |
214 | return PTR_ERR(pwm_chip->rstc); | |
215 | } | |
216 | ||
217 | reset_control_assert(pwm_chip->rstc); | |
218 | msleep(30); | |
219 | reset_control_deassert(pwm_chip->rstc); | |
220 | ||
221 | ret = pwmchip_add(&pwm_chip->chip); | |
222 | if (ret < 0) { | |
223 | clk_disable_unprepare(pwm_chip->clk); | |
224 | return ret; | |
225 | } | |
226 | ||
227 | for (i = 0; i < pwm_chip->chip.npwm; i++) { | |
228 | hibvt_pwm_set_bits(pwm_chip->base, PWM_CTRL_ADDR(i), | |
229 | PWM_KEEP_MASK, (0x1 << PWM_KEEP_SHIFT)); | |
230 | } | |
231 | ||
232 | platform_set_drvdata(pdev, pwm_chip); | |
233 | ||
234 | return 0; | |
235 | } | |
236 | ||
237 | static int hibvt_pwm_remove(struct platform_device *pdev) | |
238 | { | |
239 | struct hibvt_pwm_chip *pwm_chip; | |
240 | ||
241 | pwm_chip = platform_get_drvdata(pdev); | |
242 | ||
243 | reset_control_assert(pwm_chip->rstc); | |
244 | msleep(30); | |
245 | reset_control_deassert(pwm_chip->rstc); | |
246 | ||
247 | clk_disable_unprepare(pwm_chip->clk); | |
248 | ||
249 | return pwmchip_remove(&pwm_chip->chip); | |
250 | } | |
251 | ||
252 | static const struct of_device_id hibvt_pwm_of_match[] = { | |
253 | { .compatible = "hisilicon,hi3516cv300-pwm", .data = &pwm_soc[0] }, | |
254 | { .compatible = "hisilicon,hi3519v100-pwm", .data = &pwm_soc[1] }, | |
255 | { } | |
256 | }; | |
257 | MODULE_DEVICE_TABLE(of, hibvt_pwm_of_match); | |
258 | ||
259 | static struct platform_driver hibvt_pwm_driver = { | |
260 | .driver = { | |
261 | .name = "hibvt-pwm", | |
262 | .of_match_table = hibvt_pwm_of_match, | |
263 | }, | |
264 | .probe = hibvt_pwm_probe, | |
265 | .remove = hibvt_pwm_remove, | |
266 | }; | |
267 | module_platform_driver(hibvt_pwm_driver); | |
268 | ||
269 | MODULE_AUTHOR("Jian Yuan"); | |
270 | MODULE_DESCRIPTION("HiSilicon BVT SoCs PWM driver"); | |
271 | MODULE_LICENSE("GPL"); |