[mirror_ubuntu-artful-kernel.git] / drivers / pwm / pwm-imx.c

/*
 * simple driver for PWM (Pulse Width Modulator) controller
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/pwm.h>
#include <linux/of.h>
#include <linux/of_device.h>

/* i.MX1 and i.MX21 share the same PWM function block: */

#define MX1_PWMC			0x00   /* PWM Control Register */
#define MX1_PWMS			0x04   /* PWM Sample Register */
#define MX1_PWMP			0x08   /* PWM Period Register */

#define MX1_PWMC_EN			(1 << 4)

/* i.MX27, i.MX31, i.MX35 share the same PWM function block: */

#define MX3_PWMCR			0x00    /* PWM Control Register */
#define MX3_PWMSR			0x04    /* PWM Status Register */
#define MX3_PWMSAR			0x0C    /* PWM Sample Register */
#define MX3_PWMPR			0x10    /* PWM Period Register */
#define MX3_PWMCR_PRESCALER(x)		((((x) - 1) & 0xFFF) << 4)
#define MX3_PWMCR_DOZEEN		(1 << 24)
#define MX3_PWMCR_WAITEN		(1 << 23)
#define MX3_PWMCR_DBGEN			(1 << 22)
#define MX3_PWMCR_POUTC			(1 << 18)
#define MX3_PWMCR_CLKSRC_IPG_HIGH	(2 << 16)
#define MX3_PWMCR_CLKSRC_IPG		(1 << 16)
#define MX3_PWMCR_SWR			(1 << 3)
#define MX3_PWMCR_EN			(1 << 0)
#define MX3_PWMSR_FIFOAV_4WORDS		0x4
#define MX3_PWMSR_FIFOAV_MASK		0x7

#define MX3_PWM_SWR_LOOP		5

struct imx_chip {
	struct clk	*clk_per;

	void __iomem	*mmio_base;

	struct pwm_chip	chip;
};

#define to_imx_chip(chip)	container_of(chip, struct imx_chip, chip)

static int imx_pwm_config_v1(struct pwm_chip *chip,
		struct pwm_device *pwm, int duty_ns, int period_ns)
{
	struct imx_chip *imx = to_imx_chip(chip);

	/*
	 * The PWM subsystem allows for exact frequencies. However,
	 * I cannot connect a scope on my device to the PWM line and
	 * thus cannot provide the program the PWM controller
	 * exactly. Instead, I'm relying on the fact that the
	 * Bootloader (u-boot or WinCE+haret) has programmed the PWM
	 * function group already. So I'll just modify the PWM sample
	 * register to follow the ratio of duty_ns vs. period_ns
	 * accordingly.
	 *
	 * This is good enough for programming the brightness of
	 * the LCD backlight.
	 *
	 * The real implementation would divide PERCLK[0] first by
	 * both the prescaler (/1 .. /128) and then by CLKSEL
	 * (/2 .. /16).
	 */
	u32 max = readl(imx->mmio_base + MX1_PWMP);
	u32 p = max * duty_ns / period_ns;
	writel(max - p, imx->mmio_base + MX1_PWMS);

	return 0;
}

static int imx_pwm_enable_v1(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct imx_chip *imx = to_imx_chip(chip);
	u32 val;
	int ret;

	ret = clk_prepare_enable(imx->clk_per);
	if (ret < 0)
		return ret;

	val = readl(imx->mmio_base + MX1_PWMC);
	val |= MX1_PWMC_EN;
	writel(val, imx->mmio_base + MX1_PWMC);

	return 0;
}

static void imx_pwm_disable_v1(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct imx_chip *imx = to_imx_chip(chip);
	u32 val;

	val = readl(imx->mmio_base + MX1_PWMC);
	val &= ~MX1_PWMC_EN;
	writel(val, imx->mmio_base + MX1_PWMC);

	clk_disable_unprepare(imx->clk_per);
}

static void imx_pwm_sw_reset(struct pwm_chip *chip)
{
	struct imx_chip *imx = to_imx_chip(chip);
	struct device *dev = chip->dev;
	int wait_count = 0;
	u32 cr;

	writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
	do {
		usleep_range(200, 1000);
		cr = readl(imx->mmio_base + MX3_PWMCR);
	} while ((cr & MX3_PWMCR_SWR) &&
		 (wait_count++ < MX3_PWM_SWR_LOOP));

	if (cr & MX3_PWMCR_SWR)
		dev_warn(dev, "software reset timeout\n");
}

static void imx_pwm_wait_fifo_slot(struct pwm_chip *chip,
				   struct pwm_device *pwm)
{
	struct imx_chip *imx = to_imx_chip(chip);
	struct device *dev = chip->dev;
	unsigned int period_ms;
	int fifoav;
	u32 sr;

	sr = readl(imx->mmio_base + MX3_PWMSR);
	fifoav = sr & MX3_PWMSR_FIFOAV_MASK;
	if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
		period_ms = DIV_ROUND_UP(pwm_get_period(pwm),
					 NSEC_PER_MSEC);
		msleep(period_ms);

		sr = readl(imx->mmio_base + MX3_PWMSR);
		if (fifoav == (sr & MX3_PWMSR_FIFOAV_MASK))
			dev_warn(dev, "there is no free FIFO slot\n");
	}
}

static int imx_pwm_apply_v2(struct pwm_chip *chip, struct pwm_device *pwm,
			    struct pwm_state *state)
{
	unsigned long period_cycles, duty_cycles, prescale;
	struct imx_chip *imx = to_imx_chip(chip);
	struct pwm_state cstate;
	unsigned long long c;
	int ret;
	u32 cr;

	pwm_get_state(pwm, &cstate);

	if (state->enabled) {
		c = clk_get_rate(imx->clk_per);
		c *= state->period;

		do_div(c, 1000000000);
		period_cycles = c;

		prescale = period_cycles / 0x10000 + 1;

		period_cycles /= prescale;
		c = (unsigned long long)period_cycles * state->duty_cycle;
		do_div(c, state->period);
		duty_cycles = c;

		/*
		 * according to imx pwm RM, the real period value should be
		 * PERIOD value in PWMPR plus 2.
		 */
		if (period_cycles > 2)
			period_cycles -= 2;
		else
			period_cycles = 0;

		/*
		 * Wait for a free FIFO slot if the PWM is already enabled, and
		 * flush the FIFO if the PWM was disabled and is about to be
		 * enabled.
		 */
		if (cstate.enabled) {
			imx_pwm_wait_fifo_slot(chip, pwm);
		} else {
			ret = clk_prepare_enable(imx->clk_per);
			if (ret)
				return ret;

			imx_pwm_sw_reset(chip);
		}

		writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
		writel(period_cycles, imx->mmio_base + MX3_PWMPR);

		cr = MX3_PWMCR_PRESCALER(prescale) |
		     MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
		     MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH |
		     MX3_PWMCR_EN;

		if (state->polarity == PWM_POLARITY_INVERSED)
			cr |= MX3_PWMCR_POUTC;

		writel(cr, imx->mmio_base + MX3_PWMCR);
	} else if (cstate.enabled) {
		writel(0, imx->mmio_base + MX3_PWMCR);

		clk_disable_unprepare(imx->clk_per);
	}

	return 0;
}

static const struct pwm_ops imx_pwm_ops_v1 = {
	.enable = imx_pwm_enable_v1,
	.disable = imx_pwm_disable_v1,
	.config = imx_pwm_config_v1,
	.owner = THIS_MODULE,
};

static const struct pwm_ops imx_pwm_ops_v2 = {
	.apply = imx_pwm_apply_v2,
	.owner = THIS_MODULE,
};

struct imx_pwm_data {
	bool polarity_supported;
	const struct pwm_ops *ops;
};

static struct imx_pwm_data imx_pwm_data_v1 = {
	.ops = &imx_pwm_ops_v1,
};

static struct imx_pwm_data imx_pwm_data_v2 = {
	.polarity_supported = true,
	.ops = &imx_pwm_ops_v2,
};

static const struct of_device_id imx_pwm_dt_ids[] = {
	{ .compatible = "fsl,imx1-pwm", .data = &imx_pwm_data_v1, },
	{ .compatible = "fsl,imx27-pwm", .data = &imx_pwm_data_v2, },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx_pwm_dt_ids);

static int imx_pwm_probe(struct platform_device *pdev)
{
	const struct of_device_id *of_id =
			of_match_device(imx_pwm_dt_ids, &pdev->dev);
	const struct imx_pwm_data *data;
	struct imx_chip *imx;
	struct resource *r;
	int ret = 0;

	if (!of_id)
		return -ENODEV;

	data = of_id->data;

	imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
	if (imx == NULL)
		return -ENOMEM;

	imx->clk_per = devm_clk_get(&pdev->dev, "per");
	if (IS_ERR(imx->clk_per)) {
		dev_err(&pdev->dev, "getting per clock failed with %ld\n",
				PTR_ERR(imx->clk_per));
		return PTR_ERR(imx->clk_per);
	}

	imx->chip.ops = data->ops;
	imx->chip.dev = &pdev->dev;
	imx->chip.base = -1;
	imx->chip.npwm = 1;

	if (data->polarity_supported) {
		dev_dbg(&pdev->dev, "PWM supports output inversion\n");
		imx->chip.of_xlate = of_pwm_xlate_with_flags;
		imx->chip.of_pwm_n_cells = 3;
	}

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(imx->mmio_base))
		return PTR_ERR(imx->mmio_base);

	ret = pwmchip_add(&imx->chip);
	if (ret < 0)
		return ret;

	platform_set_drvdata(pdev, imx);
	return 0;
}

static int imx_pwm_remove(struct platform_device *pdev)
{
	struct imx_chip *imx;

	imx = platform_get_drvdata(pdev);
	if (imx == NULL)
		return -ENODEV;

	return pwmchip_remove(&imx->chip);
}

static struct platform_driver imx_pwm_driver = {
	.driver		= {
		.name	= "imx-pwm",
		.of_match_table = imx_pwm_dt_ids,
	},
	.probe		= imx_pwm_probe,
	.remove		= imx_pwm_remove,
};

module_platform_driver(imx_pwm_driver);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
Commit	Line	Data
166091b1 SH	1	/*
	2	* simple driver for PWM (Pulse Width Modulator) controller
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
	9	*/
	10
	11	#include <linux/module.h>
	12	#include <linux/kernel.h>
	13	#include <linux/platform_device.h>
5a0e3ad6	14	#include <linux/slab.h>
166091b1 SH	15	#include <linux/err.h>
166091b1 SH	16	#include <linux/clk.h>
137fd45f	17	#include <linux/delay.h>
166091b1 SH	18	#include <linux/io.h>
166091b1 SH	19	#include <linux/pwm.h>
2a8876cf	20	#include <linux/of.h>
479e2e30	21	#include <linux/of_device.h>
c010dba8	22
c010dba8 HS	23	/* i.MX1 and i.MX21 share the same PWM function block: */
c010dba8 HS	24
40f260c2 LY	25	#define MX1_PWMC 0x00 /* PWM Control Register */
	26	#define MX1_PWMS 0x04 /* PWM Sample Register */
	27	#define MX1_PWMP 0x08 /* PWM Period Register */
c010dba8	28
40f260c2	29	#define MX1_PWMC_EN (1 << 4)
c010dba8 HS	30
	31	/* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
	32
40f260c2	33	#define MX3_PWMCR 0x00 /* PWM Control Register */
137fd45f	34	#define MX3_PWMSR 0x04 /* PWM Status Register */
40f260c2 LY	35	#define MX3_PWMSAR 0x0C /* PWM Sample Register */
	36	#define MX3_PWMPR 0x10 /* PWM Period Register */
	37	#define MX3_PWMCR_PRESCALER(x) ((((x) - 1) & 0xFFF) << 4)
	38	#define MX3_PWMCR_DOZEEN (1 << 24)
	39	#define MX3_PWMCR_WAITEN (1 << 23)
c0d96aed	40	#define MX3_PWMCR_DBGEN (1 << 22)
326ed314	41	#define MX3_PWMCR_POUTC (1 << 18)
40f260c2 LY	42	#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
40f260c2 LY	43	#define MX3_PWMCR_CLKSRC_IPG (1 << 16)
137fd45f	44	#define MX3_PWMCR_SWR (1 << 3)
40f260c2	45	#define MX3_PWMCR_EN (1 << 0)
137fd45f LY	46	#define MX3_PWMSR_FIFOAV_4WORDS 0x4
	47	#define MX3_PWMSR_FIFOAV_MASK 0x7
	48
	49	#define MX3_PWM_SWR_LOOP 5
c010dba8	50
29693248	51	struct imx_chip {
7b27c160	52	struct clk *clk_per;
166091b1	53
166091b1 SH	54	void __iomem *mmio_base;
166091b1 SH	55
29693248	56	struct pwm_chip chip;
166091b1 SH	57	};
166091b1 SH	58
29693248 SH	59	#define to_imx_chip(chip) container_of(chip, struct imx_chip, chip)
29693248 SH	60
19e73333	61	static int imx_pwm_config_v1(struct pwm_chip *chip,
29693248	62	struct pwm_device *pwm, int duty_ns, int period_ns)
166091b1	63	{
29693248	64	struct imx_chip *imx = to_imx_chip(chip);
166091b1	65
19e73333 SH	66	/*
	67	* The PWM subsystem allows for exact frequencies. However,
	68	* I cannot connect a scope on my device to the PWM line and
	69	* thus cannot provide the program the PWM controller
	70	* exactly. Instead, I'm relying on the fact that the
	71	* Bootloader (u-boot or WinCE+haret) has programmed the PWM
	72	* function group already. So I'll just modify the PWM sample
	73	* register to follow the ratio of duty_ns vs. period_ns
	74	* accordingly.
	75	*
	76	* This is good enough for programming the brightness of
	77	* the LCD backlight.
	78	*
	79	* The real implementation would divide PERCLK[0] first by
	80	* both the prescaler (/1 .. /128) and then by CLKSEL
	81	* (/2 .. /16).
	82	*/
	83	u32 max = readl(imx->mmio_base + MX1_PWMP);
	84	u32 p = max * duty_ns / period_ns;
	85	writel(max - p, imx->mmio_base + MX1_PWMS);
	86
	87	return 0;
	88	}
	89
b3c088fe	90	static int imx_pwm_enable_v1(struct pwm_chip chip, struct pwm_device pwm)
66ad6a61 SH	91	{
	92	struct imx_chip *imx = to_imx_chip(chip);
	93	u32 val;
b3c088fe	94	int ret;
66ad6a61	95
b3c088fe LM	96	ret = clk_prepare_enable(imx->clk_per);
	97	if (ret < 0)
	98	return ret;
66ad6a61	99
66ad6a61	100	val = readl(imx->mmio_base + MX1_PWMC);
b3c088fe	101	val \|= MX1_PWMC_EN;
66ad6a61	102	writel(val, imx->mmio_base + MX1_PWMC);
166091b1 SH	103
	104	return 0;
	105	}
166091b1	106
b3c088fe	107	static void imx_pwm_disable_v1(struct pwm_chip chip, struct pwm_device pwm)
66ad6a61 SH	108	{
	109	struct imx_chip *imx = to_imx_chip(chip);
	110	u32 val;
	111
b3c088fe LM	112	val = readl(imx->mmio_base + MX1_PWMC);
b3c088fe LM	113	val &= ~MX1_PWMC_EN;
66ad6a61	114	writel(val, imx->mmio_base + MX1_PWMC);
66ad6a61	115
b3c088fe	116	clk_disable_unprepare(imx->clk_per);
66ad6a61 SH	117	}
66ad6a61 SH	118
970247a4	119	static void imx_pwm_sw_reset(struct pwm_chip *chip)
19e73333 SH	120	{
19e73333 SH	121	struct imx_chip *imx = to_imx_chip(chip);
970247a4 LM	122	struct device *dev = chip->dev;
	123	int wait_count = 0;
	124	u32 cr;
	125
	126	writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
	127	do {
	128	usleep_range(200, 1000);
	129	cr = readl(imx->mmio_base + MX3_PWMCR);
	130	} while ((cr & MX3_PWMCR_SWR) &&
	131	(wait_count++ < MX3_PWM_SWR_LOOP));
	132
	133	if (cr & MX3_PWMCR_SWR)
	134	dev_warn(dev, "software reset timeout\n");
	135	}
19e73333	136
73b1ff1f LM	137	static void imx_pwm_wait_fifo_slot(struct pwm_chip *chip,
	138	struct pwm_device *pwm)
	139	{
	140	struct imx_chip *imx = to_imx_chip(chip);
	141	struct device *dev = chip->dev;
	142	unsigned int period_ms;
	143	int fifoav;
	144	u32 sr;
7b27c160	145
73b1ff1f LM	146	sr = readl(imx->mmio_base + MX3_PWMSR);
	147	fifoav = sr & MX3_PWMSR_FIFOAV_MASK;
	148	if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
	149	period_ms = DIV_ROUND_UP(pwm_get_period(pwm),
	150	NSEC_PER_MSEC);
	151	msleep(period_ms);
7b27c160	152
73b1ff1f LM	153	sr = readl(imx->mmio_base + MX3_PWMSR);
	154	if (fifoav == (sr & MX3_PWMSR_FIFOAV_MASK))
	155	dev_warn(dev, "there is no free FIFO slot\n");
	156	}
19e73333 SH	157	}
19e73333 SH	158
0ca1a11a LM	159	static int imx_pwm_apply_v2(struct pwm_chip chip, struct pwm_device pwm,
0ca1a11a LM	160	struct pwm_state *state)
166091b1	161	{
0ca1a11a	162	unsigned long period_cycles, duty_cycles, prescale;
29693248	163	struct imx_chip *imx = to_imx_chip(chip);
0ca1a11a LM	164	struct pwm_state cstate;
0ca1a11a LM	165	unsigned long long c;
140827c1	166	int ret;
326ed314	167	u32 cr;
0ca1a11a LM	168
	169	pwm_get_state(pwm, &cstate);
	170
	171	if (state->enabled) {
	172	c = clk_get_rate(imx->clk_per);
	173	c *= state->period;
	174
	175	do_div(c, 1000000000);
	176	period_cycles = c;
	177
	178	prescale = period_cycles / 0x10000 + 1;
	179
	180	period_cycles /= prescale;
	181	c = (unsigned long long)period_cycles * state->duty_cycle;
	182	do_div(c, state->period);
	183	duty_cycles = c;
	184
	185	/*
	186	* according to imx pwm RM, the real period value should be
	187	* PERIOD value in PWMPR plus 2.
	188	*/
	189	if (period_cycles > 2)
	190	period_cycles -= 2;
	191	else
	192	period_cycles = 0;
	193
	194	/*
	195	* Wait for a free FIFO slot if the PWM is already enabled, and
	196	* flush the FIFO if the PWM was disabled and is about to be
	197	* enabled.
	198	*/
	199	if (cstate.enabled) {
	200	imx_pwm_wait_fifo_slot(chip, pwm);
	201	} else {
	202	ret = clk_prepare_enable(imx->clk_per);
	203	if (ret)
	204	return ret;
	205
	206	imx_pwm_sw_reset(chip);
	207	}
166091b1	208
0ca1a11a LM	209	writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
0ca1a11a LM	210	writel(period_cycles, imx->mmio_base + MX3_PWMPR);
140827c1	211
326ed314 LM	212	cr = MX3_PWMCR_PRESCALER(prescale) \|
	213	MX3_PWMCR_DOZEEN \| MX3_PWMCR_WAITEN \|
	214	MX3_PWMCR_DBGEN \| MX3_PWMCR_CLKSRC_IPG_HIGH \|
	215	MX3_PWMCR_EN;
66ad6a61	216
326ed314 LM	217	if (state->polarity == PWM_POLARITY_INVERSED)
326ed314 LM	218	cr \|= MX3_PWMCR_POUTC;
166091b1	219
326ed314	220	writel(cr, imx->mmio_base + MX3_PWMCR);
0ca1a11a LM	221	} else if (cstate.enabled) {
0ca1a11a LM	222	writel(0, imx->mmio_base + MX3_PWMCR);
166091b1	223
0ca1a11a LM	224	clk_disable_unprepare(imx->clk_per);
0ca1a11a LM	225	}
166091b1	226
0ca1a11a	227	return 0;
166091b1	228	}
166091b1	229
00389229	230	static const struct pwm_ops imx_pwm_ops_v1 = {
b3c088fe LM	231	.enable = imx_pwm_enable_v1,
	232	.disable = imx_pwm_disable_v1,
	233	.config = imx_pwm_config_v1,
00389229 LM	234	.owner = THIS_MODULE,
	235	};
	236
	237	static const struct pwm_ops imx_pwm_ops_v2 = {
0ca1a11a	238	.apply = imx_pwm_apply_v2,
29693248 SH	239	.owner = THIS_MODULE,
29693248 SH	240	};
166091b1	241
479e2e30	242	struct imx_pwm_data {
326ed314	243	bool polarity_supported;
00389229	244	const struct pwm_ops *ops;
479e2e30 PZ	245	};
	246
	247	static struct imx_pwm_data imx_pwm_data_v1 = {
00389229	248	.ops = &imx_pwm_ops_v1,
479e2e30 PZ	249	};
	250
	251	static struct imx_pwm_data imx_pwm_data_v2 = {
326ed314	252	.polarity_supported = true,
00389229	253	.ops = &imx_pwm_ops_v2,
479e2e30 PZ	254	};
	255
	256	static const struct of_device_id imx_pwm_dt_ids[] = {
	257	{ .compatible = "fsl,imx1-pwm", .data = &imx_pwm_data_v1, },
	258	{ .compatible = "fsl,imx27-pwm", .data = &imx_pwm_data_v2, },
	259	{ /* sentinel */ }
	260	};
	261	MODULE_DEVICE_TABLE(of, imx_pwm_dt_ids);
	262
3e9fe83d	263	static int imx_pwm_probe(struct platform_device *pdev)
166091b1	264	{
479e2e30 PZ	265	const struct of_device_id *of_id =
479e2e30 PZ	266	of_match_device(imx_pwm_dt_ids, &pdev->dev);
983290b0	267	const struct imx_pwm_data *data;
29693248	268	struct imx_chip *imx;
166091b1 SH	269	struct resource *r;
	270	int ret = 0;
	271
479e2e30 PZ	272	if (!of_id)
	273	return -ENODEV;
	274
00389229 LM	275	data = of_id->data;
00389229 LM	276
a9970e3b	277	imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
1cbec749	278	if (imx == NULL)
166091b1	279	return -ENOMEM;
166091b1	280
7b27c160 PZ	281	imx->clk_per = devm_clk_get(&pdev->dev, "per");
	282	if (IS_ERR(imx->clk_per)) {
	283	dev_err(&pdev->dev, "getting per clock failed with %ld\n",
	284	PTR_ERR(imx->clk_per));
	285	return PTR_ERR(imx->clk_per);
	286	}
166091b1	287
00389229	288	imx->chip.ops = data->ops;
29693248 SH	289	imx->chip.dev = &pdev->dev;
	290	imx->chip.base = -1;
	291	imx->chip.npwm = 1;
166091b1	292
326ed314 LM	293	if (data->polarity_supported) {
	294	dev_dbg(&pdev->dev, "PWM supports output inversion\n");
	295	imx->chip.of_xlate = of_pwm_xlate_with_flags;
	296	imx->chip.of_pwm_n_cells = 3;
	297	}
	298
166091b1	299	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6d4294d1 TR	300	imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
	301	if (IS_ERR(imx->mmio_base))
	302	return PTR_ERR(imx->mmio_base);
166091b1	303
29693248 SH	304	ret = pwmchip_add(&imx->chip);
29693248 SH	305	if (ret < 0)
a9970e3b	306	return ret;
166091b1	307
29693248	308	platform_set_drvdata(pdev, imx);
166091b1	309	return 0;
166091b1 SH	310	}
166091b1 SH	311
77f37917	312	static int imx_pwm_remove(struct platform_device *pdev)
166091b1	313	{
29693248	314	struct imx_chip *imx;
166091b1	315
29693248 SH	316	imx = platform_get_drvdata(pdev);
29693248 SH	317	if (imx == NULL)
166091b1 SH	318	return -ENODEV;
166091b1 SH	319
a9970e3b	320	return pwmchip_remove(&imx->chip);
166091b1 SH	321	}
166091b1 SH	322
29693248	323	static struct platform_driver imx_pwm_driver = {
166091b1	324	.driver = {
479e2e30	325	.name = "imx-pwm",
becbca13	326	.of_match_table = imx_pwm_dt_ids,
166091b1	327	},
29693248	328	.probe = imx_pwm_probe,
fd109112	329	.remove = imx_pwm_remove,
166091b1 SH	330	};
166091b1 SH	331
208d038f	332	module_platform_driver(imx_pwm_driver);
166091b1 SH	333
	334	MODULE_LICENSE("GPL v2");
	335	MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");