[mirror_ubuntu-zesty-kernel.git] / drivers / pwm / pwm-imx.c

/*
 * simple driver for PWM (Pulse Width Modulator) controller
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/pwm.h>
#include <linux/of.h>
#include <linux/of_device.h>

/* i.MX1 and i.MX21 share the same PWM function block: */

#define MX1_PWMC			0x00   /* PWM Control Register */
#define MX1_PWMS			0x04   /* PWM Sample Register */
#define MX1_PWMP			0x08   /* PWM Period Register */

#define MX1_PWMC_EN			(1 << 4)

/* i.MX27, i.MX31, i.MX35 share the same PWM function block: */

#define MX3_PWMCR			0x00    /* PWM Control Register */
#define MX3_PWMSR			0x04    /* PWM Status Register */
#define MX3_PWMSAR			0x0C    /* PWM Sample Register */
#define MX3_PWMPR			0x10    /* PWM Period Register */
#define MX3_PWMCR_PRESCALER(x)		((((x) - 1) & 0xFFF) << 4)
#define MX3_PWMCR_DOZEEN		(1 << 24)
#define MX3_PWMCR_WAITEN		(1 << 23)
#define MX3_PWMCR_DBGEN			(1 << 22)
#define MX3_PWMCR_CLKSRC_IPG_HIGH	(2 << 16)
#define MX3_PWMCR_CLKSRC_IPG		(1 << 16)
#define MX3_PWMCR_SWR			(1 << 3)
#define MX3_PWMCR_EN			(1 << 0)
#define MX3_PWMSR_FIFOAV_4WORDS		0x4
#define MX3_PWMSR_FIFOAV_MASK		0x7

#define MX3_PWM_SWR_LOOP		5

struct imx_chip {
	struct clk	*clk_per;
	struct clk	*clk_ipg;

	void __iomem	*mmio_base;

	struct pwm_chip	chip;

	int (*config)(struct pwm_chip *chip,
		struct pwm_device *pwm, int duty_ns, int period_ns);
	void (*set_enable)(struct pwm_chip *chip, bool enable);
};

#define to_imx_chip(chip)	container_of(chip, struct imx_chip, chip)

static int imx_pwm_config_v1(struct pwm_chip *chip,
		struct pwm_device *pwm, int duty_ns, int period_ns)
{
	struct imx_chip *imx = to_imx_chip(chip);

	/*
	 * The PWM subsystem allows for exact frequencies. However,
	 * I cannot connect a scope on my device to the PWM line and
	 * thus cannot provide the program the PWM controller
	 * exactly. Instead, I'm relying on the fact that the
	 * Bootloader (u-boot or WinCE+haret) has programmed the PWM
	 * function group already. So I'll just modify the PWM sample
	 * register to follow the ratio of duty_ns vs. period_ns
	 * accordingly.
	 *
	 * This is good enough for programming the brightness of
	 * the LCD backlight.
	 *
	 * The real implementation would divide PERCLK[0] first by
	 * both the prescaler (/1 .. /128) and then by CLKSEL
	 * (/2 .. /16).
	 */
	u32 max = readl(imx->mmio_base + MX1_PWMP);
	u32 p = max * duty_ns / period_ns;
	writel(max - p, imx->mmio_base + MX1_PWMS);

	return 0;
}

static void imx_pwm_set_enable_v1(struct pwm_chip *chip, bool enable)
{
	struct imx_chip *imx = to_imx_chip(chip);
	u32 val;

	val = readl(imx->mmio_base + MX1_PWMC);

	if (enable)
		val |= MX1_PWMC_EN;
	else
		val &= ~MX1_PWMC_EN;

	writel(val, imx->mmio_base + MX1_PWMC);
}

static int imx_pwm_config_v2(struct pwm_chip *chip,
		struct pwm_device *pwm, int duty_ns, int period_ns)
{
	struct imx_chip *imx = to_imx_chip(chip);
	struct device *dev = chip->dev;
	unsigned long long c;
	unsigned long period_cycles, duty_cycles, prescale;
	unsigned int period_ms;
	bool enable = pwm_is_enabled(pwm);
	int wait_count = 0, fifoav;
	u32 cr, sr;

	/*
	 * i.MX PWMv2 has a 4-word sample FIFO.
	 * In order to avoid FIFO overflow issue, we do software reset
	 * to clear all sample FIFO if the controller is disabled or
	 * wait for a full PWM cycle to get a relinquished FIFO slot
	 * when the controller is enabled and the FIFO is fully loaded.
	 */
	if (enable) {
		sr = readl(imx->mmio_base + MX3_PWMSR);
		fifoav = sr & MX3_PWMSR_FIFOAV_MASK;
		if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
			period_ms = DIV_ROUND_UP(pwm_get_period(pwm),
						 NSEC_PER_MSEC);
			msleep(period_ms);

			sr = readl(imx->mmio_base + MX3_PWMSR);
			if (fifoav == (sr & MX3_PWMSR_FIFOAV_MASK))
				dev_warn(dev, "there is no free FIFO slot\n");
		}
	} else {
		writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
		do {
			usleep_range(200, 1000);
			cr = readl(imx->mmio_base + MX3_PWMCR);
		} while ((cr & MX3_PWMCR_SWR) &&
			 (wait_count++ < MX3_PWM_SWR_LOOP));

		if (cr & MX3_PWMCR_SWR)
			dev_warn(dev, "software reset timeout\n");
	}

	c = clk_get_rate(imx->clk_per);
	c = c * period_ns;
	do_div(c, 1000000000);
	period_cycles = c;

	prescale = period_cycles / 0x10000 + 1;

	period_cycles /= prescale;
	c = (unsigned long long)period_cycles * duty_ns;
	do_div(c, period_ns);
	duty_cycles = c;

	/*
	 * according to imx pwm RM, the real period value should be
	 * PERIOD value in PWMPR plus 2.
	 */
	if (period_cycles > 2)
		period_cycles -= 2;
	else
		period_cycles = 0;

	writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
	writel(period_cycles, imx->mmio_base + MX3_PWMPR);

	cr = MX3_PWMCR_PRESCALER(prescale) |
		MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
		MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH;

	if (enable)
		cr |= MX3_PWMCR_EN;

	writel(cr, imx->mmio_base + MX3_PWMCR);

	return 0;
}

static void imx_pwm_set_enable_v2(struct pwm_chip *chip, bool enable)
{
	struct imx_chip *imx = to_imx_chip(chip);
	u32 val;

	val = readl(imx->mmio_base + MX3_PWMCR);

	if (enable)
		val |= MX3_PWMCR_EN;
	else
		val &= ~MX3_PWMCR_EN;

	writel(val, imx->mmio_base + MX3_PWMCR);
}

static int imx_pwm_config(struct pwm_chip *chip,
		struct pwm_device *pwm, int duty_ns, int period_ns)
{
	struct imx_chip *imx = to_imx_chip(chip);
	int ret;

	ret = clk_prepare_enable(imx->clk_ipg);
	if (ret)
		return ret;

	ret = imx->config(chip, pwm, duty_ns, period_ns);

	clk_disable_unprepare(imx->clk_ipg);

	return ret;
}

static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct imx_chip *imx = to_imx_chip(chip);
	int ret;

	ret = clk_prepare_enable(imx->clk_per);
	if (ret)
		return ret;

	imx->set_enable(chip, true);

	return 0;
}

static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct imx_chip *imx = to_imx_chip(chip);

	imx->set_enable(chip, false);

	clk_disable_unprepare(imx->clk_per);
}

static struct pwm_ops imx_pwm_ops = {
	.enable = imx_pwm_enable,
	.disable = imx_pwm_disable,
	.config = imx_pwm_config,
	.owner = THIS_MODULE,
};

struct imx_pwm_data {
	int (*config)(struct pwm_chip *chip,
		struct pwm_device *pwm, int duty_ns, int period_ns);
	void (*set_enable)(struct pwm_chip *chip, bool enable);
};

static struct imx_pwm_data imx_pwm_data_v1 = {
	.config = imx_pwm_config_v1,
	.set_enable = imx_pwm_set_enable_v1,
};

static struct imx_pwm_data imx_pwm_data_v2 = {
	.config = imx_pwm_config_v2,
	.set_enable = imx_pwm_set_enable_v2,
};

static const struct of_device_id imx_pwm_dt_ids[] = {
	{ .compatible = "fsl,imx1-pwm", .data = &imx_pwm_data_v1, },
	{ .compatible = "fsl,imx27-pwm", .data = &imx_pwm_data_v2, },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx_pwm_dt_ids);

static int imx_pwm_probe(struct platform_device *pdev)
{
	const struct of_device_id *of_id =
			of_match_device(imx_pwm_dt_ids, &pdev->dev);
	const struct imx_pwm_data *data;
	struct imx_chip *imx;
	struct resource *r;
	int ret = 0;

	if (!of_id)
		return -ENODEV;

	imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
	if (imx == NULL)
		return -ENOMEM;

	imx->clk_per = devm_clk_get(&pdev->dev, "per");
	if (IS_ERR(imx->clk_per)) {
		dev_err(&pdev->dev, "getting per clock failed with %ld\n",
				PTR_ERR(imx->clk_per));
		return PTR_ERR(imx->clk_per);
	}

	imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
	if (IS_ERR(imx->clk_ipg)) {
		dev_err(&pdev->dev, "getting ipg clock failed with %ld\n",
				PTR_ERR(imx->clk_ipg));
		return PTR_ERR(imx->clk_ipg);
	}

	imx->chip.ops = &imx_pwm_ops;
	imx->chip.dev = &pdev->dev;
	imx->chip.base = -1;
	imx->chip.npwm = 1;
	imx->chip.can_sleep = true;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(imx->mmio_base))
		return PTR_ERR(imx->mmio_base);

	data = of_id->data;
	imx->config = data->config;
	imx->set_enable = data->set_enable;

	ret = pwmchip_add(&imx->chip);
	if (ret < 0)
		return ret;

	platform_set_drvdata(pdev, imx);
	return 0;
}

static int imx_pwm_remove(struct platform_device *pdev)
{
	struct imx_chip *imx;

	imx = platform_get_drvdata(pdev);
	if (imx == NULL)
		return -ENODEV;

	return pwmchip_remove(&imx->chip);
}

static struct platform_driver imx_pwm_driver = {
	.driver		= {
		.name	= "imx-pwm",
		.of_match_table = imx_pwm_dt_ids,
	},
	.probe		= imx_pwm_probe,
	.remove		= imx_pwm_remove,
};

module_platform_driver(imx_pwm_driver);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
Commit	Line	Data
166091b1 SH	1	/*
	2	* simple driver for PWM (Pulse Width Modulator) controller
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
	9	*/
	10
	11	#include <linux/module.h>
	12	#include <linux/kernel.h>
	13	#include <linux/platform_device.h>
5a0e3ad6	14	#include <linux/slab.h>
166091b1 SH	15	#include <linux/err.h>
166091b1 SH	16	#include <linux/clk.h>
137fd45f	17	#include <linux/delay.h>
166091b1 SH	18	#include <linux/io.h>
166091b1 SH	19	#include <linux/pwm.h>
2a8876cf	20	#include <linux/of.h>
479e2e30	21	#include <linux/of_device.h>
c010dba8	22
c010dba8 HS	23	/* i.MX1 and i.MX21 share the same PWM function block: */
c010dba8 HS	24
40f260c2 LY	25	#define MX1_PWMC 0x00 /* PWM Control Register */
	26	#define MX1_PWMS 0x04 /* PWM Sample Register */
	27	#define MX1_PWMP 0x08 /* PWM Period Register */
c010dba8	28
40f260c2	29	#define MX1_PWMC_EN (1 << 4)
c010dba8 HS	30
	31	/* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
	32
40f260c2	33	#define MX3_PWMCR 0x00 /* PWM Control Register */
137fd45f	34	#define MX3_PWMSR 0x04 /* PWM Status Register */
40f260c2 LY	35	#define MX3_PWMSAR 0x0C /* PWM Sample Register */
	36	#define MX3_PWMPR 0x10 /* PWM Period Register */
	37	#define MX3_PWMCR_PRESCALER(x) ((((x) - 1) & 0xFFF) << 4)
	38	#define MX3_PWMCR_DOZEEN (1 << 24)
	39	#define MX3_PWMCR_WAITEN (1 << 23)
c0d96aed	40	#define MX3_PWMCR_DBGEN (1 << 22)
40f260c2 LY	41	#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
40f260c2 LY	42	#define MX3_PWMCR_CLKSRC_IPG (1 << 16)
137fd45f	43	#define MX3_PWMCR_SWR (1 << 3)
40f260c2	44	#define MX3_PWMCR_EN (1 << 0)
137fd45f LY	45	#define MX3_PWMSR_FIFOAV_4WORDS 0x4
	46	#define MX3_PWMSR_FIFOAV_MASK 0x7
	47
	48	#define MX3_PWM_SWR_LOOP 5
c010dba8	49
29693248	50	struct imx_chip {
7b27c160 PZ	51	struct clk *clk_per;
7b27c160 PZ	52	struct clk *clk_ipg;
166091b1	53
166091b1 SH	54	void __iomem *mmio_base;
166091b1 SH	55
29693248	56	struct pwm_chip chip;
19e73333 SH	57
	58	int (config)(struct pwm_chip chip,
	59	struct pwm_device *pwm, int duty_ns, int period_ns);
66ad6a61	60	void (set_enable)(struct pwm_chip chip, bool enable);
166091b1 SH	61	};
166091b1 SH	62
29693248 SH	63	#define to_imx_chip(chip) container_of(chip, struct imx_chip, chip)
29693248 SH	64
19e73333	65	static int imx_pwm_config_v1(struct pwm_chip *chip,
29693248	66	struct pwm_device *pwm, int duty_ns, int period_ns)
166091b1	67	{
29693248	68	struct imx_chip *imx = to_imx_chip(chip);
166091b1	69
19e73333 SH	70	/*
	71	* The PWM subsystem allows for exact frequencies. However,
	72	* I cannot connect a scope on my device to the PWM line and
	73	* thus cannot provide the program the PWM controller
	74	* exactly. Instead, I'm relying on the fact that the
	75	* Bootloader (u-boot or WinCE+haret) has programmed the PWM
	76	* function group already. So I'll just modify the PWM sample
	77	* register to follow the ratio of duty_ns vs. period_ns
	78	* accordingly.
	79	*
	80	* This is good enough for programming the brightness of
	81	* the LCD backlight.
	82	*
	83	* The real implementation would divide PERCLK[0] first by
	84	* both the prescaler (/1 .. /128) and then by CLKSEL
	85	* (/2 .. /16).
	86	*/
	87	u32 max = readl(imx->mmio_base + MX1_PWMP);
	88	u32 p = max * duty_ns / period_ns;
	89	writel(max - p, imx->mmio_base + MX1_PWMS);
	90
	91	return 0;
	92	}
	93
66ad6a61 SH	94	static void imx_pwm_set_enable_v1(struct pwm_chip *chip, bool enable)
	95	{
	96	struct imx_chip *imx = to_imx_chip(chip);
	97	u32 val;
	98
	99	val = readl(imx->mmio_base + MX1_PWMC);
	100
	101	if (enable)
	102	val \|= MX1_PWMC_EN;
	103	else
	104	val &= ~MX1_PWMC_EN;
	105
	106	writel(val, imx->mmio_base + MX1_PWMC);
	107	}
	108
19e73333 SH	109	static int imx_pwm_config_v2(struct pwm_chip *chip,
	110	struct pwm_device *pwm, int duty_ns, int period_ns)
	111	{
	112	struct imx_chip *imx = to_imx_chip(chip);
137fd45f	113	struct device *dev = chip->dev;
19e73333 SH	114	unsigned long long c;
19e73333 SH	115	unsigned long period_cycles, duty_cycles, prescale;
137fd45f	116	unsigned int period_ms;
5c31252c	117	bool enable = pwm_is_enabled(pwm);
137fd45f LY	118	int wait_count = 0, fifoav;
	119	u32 cr, sr;
	120
	121	/*
	122	* i.MX PWMv2 has a 4-word sample FIFO.
	123	* In order to avoid FIFO overflow issue, we do software reset
	124	* to clear all sample FIFO if the controller is disabled or
	125	* wait for a full PWM cycle to get a relinquished FIFO slot
	126	* when the controller is enabled and the FIFO is fully loaded.
	127	*/
	128	if (enable) {
	129	sr = readl(imx->mmio_base + MX3_PWMSR);
	130	fifoav = sr & MX3_PWMSR_FIFOAV_MASK;
	131	if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
15da7b50 BB	132	period_ms = DIV_ROUND_UP(pwm_get_period(pwm),
15da7b50 BB	133	NSEC_PER_MSEC);
137fd45f LY	134	msleep(period_ms);
	135
	136	sr = readl(imx->mmio_base + MX3_PWMSR);
	137	if (fifoav == (sr & MX3_PWMSR_FIFOAV_MASK))
	138	dev_warn(dev, "there is no free FIFO slot\n");
	139	}
	140	} else {
	141	writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
	142	do {
	143	usleep_range(200, 1000);
	144	cr = readl(imx->mmio_base + MX3_PWMCR);
	145	} while ((cr & MX3_PWMCR_SWR) &&
	146	(wait_count++ < MX3_PWM_SWR_LOOP));
	147
	148	if (cr & MX3_PWMCR_SWR)
	149	dev_warn(dev, "software reset timeout\n");
	150	}
19e73333	151
7b27c160	152	c = clk_get_rate(imx->clk_per);
19e73333 SH	153	c = c * period_ns;
	154	do_div(c, 1000000000);
	155	period_cycles = c;
	156
	157	prescale = period_cycles / 0x10000 + 1;
	158
	159	period_cycles /= prescale;
	160	c = (unsigned long long)period_cycles * duty_ns;
	161	do_div(c, period_ns);
	162	duty_cycles = c;
	163
	164	/*
	165	* according to imx pwm RM, the real period value should be
	166	* PERIOD value in PWMPR plus 2.
	167	*/
	168	if (period_cycles > 2)
	169	period_cycles -= 2;
	170	else
	171	period_cycles = 0;
	172
	173	writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
	174	writel(period_cycles, imx->mmio_base + MX3_PWMPR);
	175
	176	cr = MX3_PWMCR_PRESCALER(prescale) \|
	177	MX3_PWMCR_DOZEEN \| MX3_PWMCR_WAITEN \|
8d1c24bf	178	MX3_PWMCR_DBGEN \| MX3_PWMCR_CLKSRC_IPG_HIGH;
66ad6a61	179
137fd45f	180	if (enable)
66ad6a61	181	cr \|= MX3_PWMCR_EN;
19e73333	182
19e73333	183	writel(cr, imx->mmio_base + MX3_PWMCR);
166091b1 SH	184
	185	return 0;
	186	}
166091b1	187
66ad6a61 SH	188	static void imx_pwm_set_enable_v2(struct pwm_chip *chip, bool enable)
	189	{
	190	struct imx_chip *imx = to_imx_chip(chip);
	191	u32 val;
	192
	193	val = readl(imx->mmio_base + MX3_PWMCR);
	194
	195	if (enable)
	196	val \|= MX3_PWMCR_EN;
	197	else
	198	val &= ~MX3_PWMCR_EN;
	199
	200	writel(val, imx->mmio_base + MX3_PWMCR);
	201	}
	202
19e73333 SH	203	static int imx_pwm_config(struct pwm_chip *chip,
	204	struct pwm_device *pwm, int duty_ns, int period_ns)
	205	{
	206	struct imx_chip *imx = to_imx_chip(chip);
7b27c160 PZ	207	int ret;
	208
	209	ret = clk_prepare_enable(imx->clk_ipg);
	210	if (ret)
	211	return ret;
19e73333	212
7b27c160 PZ	213	ret = imx->config(chip, pwm, duty_ns, period_ns);
	214
	215	clk_disable_unprepare(imx->clk_ipg);
	216
	217	return ret;
19e73333 SH	218	}
19e73333 SH	219
29693248	220	static int imx_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
166091b1	221	{
29693248	222	struct imx_chip *imx = to_imx_chip(chip);
140827c1	223	int ret;
166091b1	224
7b27c160	225	ret = clk_prepare_enable(imx->clk_per);
140827c1 SH	226	if (ret)
	227	return ret;
	228
66ad6a61 SH	229	imx->set_enable(chip, true);
66ad6a61 SH	230
140827c1	231	return 0;
166091b1	232	}
166091b1	233
29693248	234	static void imx_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
166091b1	235	{
29693248	236	struct imx_chip *imx = to_imx_chip(chip);
166091b1	237
66ad6a61	238	imx->set_enable(chip, false);
166091b1	239
7b27c160	240	clk_disable_unprepare(imx->clk_per);
166091b1	241	}
166091b1	242
29693248 SH	243	static struct pwm_ops imx_pwm_ops = {
	244	.enable = imx_pwm_enable,
	245	.disable = imx_pwm_disable,
	246	.config = imx_pwm_config,
	247	.owner = THIS_MODULE,
	248	};
166091b1	249
479e2e30 PZ	250	struct imx_pwm_data {
	251	int (config)(struct pwm_chip chip,
	252	struct pwm_device *pwm, int duty_ns, int period_ns);
	253	void (set_enable)(struct pwm_chip chip, bool enable);
	254	};
	255
	256	static struct imx_pwm_data imx_pwm_data_v1 = {
	257	.config = imx_pwm_config_v1,
	258	.set_enable = imx_pwm_set_enable_v1,
	259	};
	260
	261	static struct imx_pwm_data imx_pwm_data_v2 = {
	262	.config = imx_pwm_config_v2,
	263	.set_enable = imx_pwm_set_enable_v2,
	264	};
	265
	266	static const struct of_device_id imx_pwm_dt_ids[] = {
	267	{ .compatible = "fsl,imx1-pwm", .data = &imx_pwm_data_v1, },
	268	{ .compatible = "fsl,imx27-pwm", .data = &imx_pwm_data_v2, },
	269	{ /* sentinel */ }
	270	};
	271	MODULE_DEVICE_TABLE(of, imx_pwm_dt_ids);
	272
3e9fe83d	273	static int imx_pwm_probe(struct platform_device *pdev)
166091b1	274	{
479e2e30 PZ	275	const struct of_device_id *of_id =
479e2e30 PZ	276	of_match_device(imx_pwm_dt_ids, &pdev->dev);
983290b0	277	const struct imx_pwm_data *data;
29693248	278	struct imx_chip *imx;
166091b1 SH	279	struct resource *r;
	280	int ret = 0;
	281
479e2e30 PZ	282	if (!of_id)
	283	return -ENODEV;
	284
a9970e3b	285	imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
1cbec749	286	if (imx == NULL)
166091b1	287	return -ENOMEM;
166091b1	288
7b27c160 PZ	289	imx->clk_per = devm_clk_get(&pdev->dev, "per");
	290	if (IS_ERR(imx->clk_per)) {
	291	dev_err(&pdev->dev, "getting per clock failed with %ld\n",
	292	PTR_ERR(imx->clk_per));
	293	return PTR_ERR(imx->clk_per);
	294	}
166091b1	295
7b27c160 PZ	296	imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
	297	if (IS_ERR(imx->clk_ipg)) {
	298	dev_err(&pdev->dev, "getting ipg clock failed with %ld\n",
	299	PTR_ERR(imx->clk_ipg));
	300	return PTR_ERR(imx->clk_ipg);
	301	}
166091b1	302
29693248 SH	303	imx->chip.ops = &imx_pwm_ops;
	304	imx->chip.dev = &pdev->dev;
	305	imx->chip.base = -1;
	306	imx->chip.npwm = 1;
31c4fa34	307	imx->chip.can_sleep = true;
166091b1	308
166091b1	309	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6d4294d1 TR	310	imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
	311	if (IS_ERR(imx->mmio_base))
	312	return PTR_ERR(imx->mmio_base);
166091b1	313
479e2e30 PZ	314	data = of_id->data;
	315	imx->config = data->config;
	316	imx->set_enable = data->set_enable;
19e73333	317
29693248 SH	318	ret = pwmchip_add(&imx->chip);
29693248 SH	319	if (ret < 0)
a9970e3b	320	return ret;
166091b1	321
29693248	322	platform_set_drvdata(pdev, imx);
166091b1	323	return 0;
166091b1 SH	324	}
166091b1 SH	325
77f37917	326	static int imx_pwm_remove(struct platform_device *pdev)
166091b1	327	{
29693248	328	struct imx_chip *imx;
166091b1	329
29693248 SH	330	imx = platform_get_drvdata(pdev);
29693248 SH	331	if (imx == NULL)
166091b1 SH	332	return -ENODEV;
166091b1 SH	333
a9970e3b	334	return pwmchip_remove(&imx->chip);
166091b1 SH	335	}
166091b1 SH	336
29693248	337	static struct platform_driver imx_pwm_driver = {
166091b1	338	.driver = {
479e2e30	339	.name = "imx-pwm",
becbca13	340	.of_match_table = imx_pwm_dt_ids,
166091b1	341	},
29693248	342	.probe = imx_pwm_probe,
fd109112	343	.remove = imx_pwm_remove,
166091b1 SH	344	};
166091b1 SH	345
208d038f	346	module_platform_driver(imx_pwm_driver);
166091b1 SH	347
	348	MODULE_LICENSE("GPL v2");
	349	MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");