[mirror_ubuntu-artful-kernel.git] / drivers / pwm / pwm-imx.c

/*
 * simple driver for PWM (Pulse Width Modulator) controller
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/pwm.h>
#include <linux/of.h>
#include <linux/of_device.h>

/* i.MX1 and i.MX21 share the same PWM function block: */

#define MX1_PWMC			0x00   /* PWM Control Register */
#define MX1_PWMS			0x04   /* PWM Sample Register */
#define MX1_PWMP			0x08   /* PWM Period Register */

#define MX1_PWMC_EN			(1 << 4)

/* i.MX27, i.MX31, i.MX35 share the same PWM function block: */

#define MX3_PWMCR			0x00    /* PWM Control Register */
#define MX3_PWMSR			0x04    /* PWM Status Register */
#define MX3_PWMSAR			0x0C    /* PWM Sample Register */
#define MX3_PWMPR			0x10    /* PWM Period Register */
#define MX3_PWMCR_PRESCALER(x)		((((x) - 1) & 0xFFF) << 4)
#define MX3_PWMCR_DOZEEN		(1 << 24)
#define MX3_PWMCR_WAITEN		(1 << 23)
#define MX3_PWMCR_DBGEN			(1 << 22)
#define MX3_PWMCR_CLKSRC_IPG_HIGH	(2 << 16)
#define MX3_PWMCR_CLKSRC_IPG		(1 << 16)
#define MX3_PWMCR_SWR			(1 << 3)
#define MX3_PWMCR_EN			(1 << 0)
#define MX3_PWMSR_FIFOAV_4WORDS		0x4
#define MX3_PWMSR_FIFOAV_MASK		0x7

#define MX3_PWM_SWR_LOOP		5

struct imx_chip {
	struct clk	*clk_per;

	void __iomem	*mmio_base;

	struct pwm_chip	chip;
};

#define to_imx_chip(chip)	container_of(chip, struct imx_chip, chip)

static int imx_pwm_config_v1(struct pwm_chip *chip,
		struct pwm_device *pwm, int duty_ns, int period_ns)
{
	struct imx_chip *imx = to_imx_chip(chip);

	/*
	 * The PWM subsystem allows for exact frequencies. However,
	 * I cannot connect a scope on my device to the PWM line and
	 * thus cannot provide the program the PWM controller
	 * exactly. Instead, I'm relying on the fact that the
	 * Bootloader (u-boot or WinCE+haret) has programmed the PWM
	 * function group already. So I'll just modify the PWM sample
	 * register to follow the ratio of duty_ns vs. period_ns
	 * accordingly.
	 *
	 * This is good enough for programming the brightness of
	 * the LCD backlight.
	 *
	 * The real implementation would divide PERCLK[0] first by
	 * both the prescaler (/1 .. /128) and then by CLKSEL
	 * (/2 .. /16).
	 */
	u32 max = readl(imx->mmio_base + MX1_PWMP);
	u32 p = max * duty_ns / period_ns;
	writel(max - p, imx->mmio_base + MX1_PWMS);

	return 0;
}

static int imx_pwm_enable_v1(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct imx_chip *imx = to_imx_chip(chip);
	u32 val;
	int ret;

	ret = clk_prepare_enable(imx->clk_per);
	if (ret < 0)
		return ret;

	val = readl(imx->mmio_base + MX1_PWMC);
	val |= MX1_PWMC_EN;
	writel(val, imx->mmio_base + MX1_PWMC);

	return 0;
}

static void imx_pwm_disable_v1(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct imx_chip *imx = to_imx_chip(chip);
	u32 val;

	val = readl(imx->mmio_base + MX1_PWMC);
	val &= ~MX1_PWMC_EN;
	writel(val, imx->mmio_base + MX1_PWMC);

	clk_disable_unprepare(imx->clk_per);
}

static void imx_pwm_sw_reset(struct pwm_chip *chip)
{
	struct imx_chip *imx = to_imx_chip(chip);
	struct device *dev = chip->dev;
	int wait_count = 0;
	u32 cr;

	writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
	do {
		usleep_range(200, 1000);
		cr = readl(imx->mmio_base + MX3_PWMCR);
	} while ((cr & MX3_PWMCR_SWR) &&
		 (wait_count++ < MX3_PWM_SWR_LOOP));

	if (cr & MX3_PWMCR_SWR)
		dev_warn(dev, "software reset timeout\n");
}

static void imx_pwm_wait_fifo_slot(struct pwm_chip *chip,
				   struct pwm_device *pwm)
{
	struct imx_chip *imx = to_imx_chip(chip);
	struct device *dev = chip->dev;
	unsigned int period_ms;
	int fifoav;
	u32 sr;

	sr = readl(imx->mmio_base + MX3_PWMSR);
	fifoav = sr & MX3_PWMSR_FIFOAV_MASK;
	if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
		period_ms = DIV_ROUND_UP(pwm_get_period(pwm),
					 NSEC_PER_MSEC);
		msleep(period_ms);

		sr = readl(imx->mmio_base + MX3_PWMSR);
		if (fifoav == (sr & MX3_PWMSR_FIFOAV_MASK))
			dev_warn(dev, "there is no free FIFO slot\n");
	}
}

static int imx_pwm_apply_v2(struct pwm_chip *chip, struct pwm_device *pwm,
			    struct pwm_state *state)
{
	unsigned long period_cycles, duty_cycles, prescale;
	struct imx_chip *imx = to_imx_chip(chip);
	struct pwm_state cstate;
	unsigned long long c;
	int ret;

	pwm_get_state(pwm, &cstate);

	if (state->enabled) {
		c = clk_get_rate(imx->clk_per);
		c *= state->period;

		do_div(c, 1000000000);
		period_cycles = c;

		prescale = period_cycles / 0x10000 + 1;

		period_cycles /= prescale;
		c = (unsigned long long)period_cycles * state->duty_cycle;
		do_div(c, state->period);
		duty_cycles = c;

		/*
		 * according to imx pwm RM, the real period value should be
		 * PERIOD value in PWMPR plus 2.
		 */
		if (period_cycles > 2)
			period_cycles -= 2;
		else
			period_cycles = 0;

		/*
		 * Wait for a free FIFO slot if the PWM is already enabled, and
		 * flush the FIFO if the PWM was disabled and is about to be
		 * enabled.
		 */
		if (cstate.enabled) {
			imx_pwm_wait_fifo_slot(chip, pwm);
		} else {
			ret = clk_prepare_enable(imx->clk_per);
			if (ret)
				return ret;

			imx_pwm_sw_reset(chip);
		}

		writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
		writel(period_cycles, imx->mmio_base + MX3_PWMPR);

		writel(MX3_PWMCR_PRESCALER(prescale) |
		       MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
		       MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH |
		       MX3_PWMCR_EN,
		       imx->mmio_base + MX3_PWMCR);
	} else if (cstate.enabled) {
		writel(0, imx->mmio_base + MX3_PWMCR);

		clk_disable_unprepare(imx->clk_per);
	}

	return 0;
}

static const struct pwm_ops imx_pwm_ops_v1 = {
	.enable = imx_pwm_enable_v1,
	.disable = imx_pwm_disable_v1,
	.config = imx_pwm_config_v1,
	.owner = THIS_MODULE,
};

static const struct pwm_ops imx_pwm_ops_v2 = {
	.apply = imx_pwm_apply_v2,
	.owner = THIS_MODULE,
};

struct imx_pwm_data {
	const struct pwm_ops *ops;
};

static struct imx_pwm_data imx_pwm_data_v1 = {
	.ops = &imx_pwm_ops_v1,
};

static struct imx_pwm_data imx_pwm_data_v2 = {
	.ops = &imx_pwm_ops_v2,
};

static const struct of_device_id imx_pwm_dt_ids[] = {
	{ .compatible = "fsl,imx1-pwm", .data = &imx_pwm_data_v1, },
	{ .compatible = "fsl,imx27-pwm", .data = &imx_pwm_data_v2, },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx_pwm_dt_ids);

static int imx_pwm_probe(struct platform_device *pdev)
{
	const struct of_device_id *of_id =
			of_match_device(imx_pwm_dt_ids, &pdev->dev);
	const struct imx_pwm_data *data;
	struct imx_chip *imx;
	struct resource *r;
	int ret = 0;

	if (!of_id)
		return -ENODEV;

	data = of_id->data;

	imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
	if (imx == NULL)
		return -ENOMEM;

	imx->clk_per = devm_clk_get(&pdev->dev, "per");
	if (IS_ERR(imx->clk_per)) {
		dev_err(&pdev->dev, "getting per clock failed with %ld\n",
				PTR_ERR(imx->clk_per));
		return PTR_ERR(imx->clk_per);
	}

	imx->chip.ops = data->ops;
	imx->chip.dev = &pdev->dev;
	imx->chip.base = -1;
	imx->chip.npwm = 1;
	imx->chip.can_sleep = true;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(imx->mmio_base))
		return PTR_ERR(imx->mmio_base);

	ret = pwmchip_add(&imx->chip);
	if (ret < 0)
		return ret;

	platform_set_drvdata(pdev, imx);
	return 0;
}

static int imx_pwm_remove(struct platform_device *pdev)
{
	struct imx_chip *imx;

	imx = platform_get_drvdata(pdev);
	if (imx == NULL)
		return -ENODEV;

	return pwmchip_remove(&imx->chip);
}

static struct platform_driver imx_pwm_driver = {
	.driver		= {
		.name	= "imx-pwm",
		.of_match_table = imx_pwm_dt_ids,
	},
	.probe		= imx_pwm_probe,
	.remove		= imx_pwm_remove,
};

module_platform_driver(imx_pwm_driver);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
Commit	Line	Data
166091b1 SH	1	/*
	2	* simple driver for PWM (Pulse Width Modulator) controller
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
	9	*/
	10
	11	#include <linux/module.h>
	12	#include <linux/kernel.h>
	13	#include <linux/platform_device.h>
5a0e3ad6	14	#include <linux/slab.h>
166091b1 SH	15	#include <linux/err.h>
166091b1 SH	16	#include <linux/clk.h>
137fd45f	17	#include <linux/delay.h>
166091b1 SH	18	#include <linux/io.h>
166091b1 SH	19	#include <linux/pwm.h>
2a8876cf	20	#include <linux/of.h>
479e2e30	21	#include <linux/of_device.h>
c010dba8	22
c010dba8 HS	23	/* i.MX1 and i.MX21 share the same PWM function block: */
c010dba8 HS	24
40f260c2 LY	25	#define MX1_PWMC 0x00 /* PWM Control Register */
	26	#define MX1_PWMS 0x04 /* PWM Sample Register */
	27	#define MX1_PWMP 0x08 /* PWM Period Register */
c010dba8	28
40f260c2	29	#define MX1_PWMC_EN (1 << 4)
c010dba8 HS	30
	31	/* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
	32
40f260c2	33	#define MX3_PWMCR 0x00 /* PWM Control Register */
137fd45f	34	#define MX3_PWMSR 0x04 /* PWM Status Register */
40f260c2 LY	35	#define MX3_PWMSAR 0x0C /* PWM Sample Register */
	36	#define MX3_PWMPR 0x10 /* PWM Period Register */
	37	#define MX3_PWMCR_PRESCALER(x) ((((x) - 1) & 0xFFF) << 4)
	38	#define MX3_PWMCR_DOZEEN (1 << 24)
	39	#define MX3_PWMCR_WAITEN (1 << 23)
c0d96aed	40	#define MX3_PWMCR_DBGEN (1 << 22)
40f260c2 LY	41	#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
40f260c2 LY	42	#define MX3_PWMCR_CLKSRC_IPG (1 << 16)
137fd45f	43	#define MX3_PWMCR_SWR (1 << 3)
40f260c2	44	#define MX3_PWMCR_EN (1 << 0)
137fd45f LY	45	#define MX3_PWMSR_FIFOAV_4WORDS 0x4
	46	#define MX3_PWMSR_FIFOAV_MASK 0x7
	47
	48	#define MX3_PWM_SWR_LOOP 5
c010dba8	49
29693248	50	struct imx_chip {
7b27c160	51	struct clk *clk_per;
166091b1	52
166091b1 SH	53	void __iomem *mmio_base;
166091b1 SH	54
29693248	55	struct pwm_chip chip;
166091b1 SH	56	};
166091b1 SH	57
29693248 SH	58	#define to_imx_chip(chip) container_of(chip, struct imx_chip, chip)
29693248 SH	59
19e73333	60	static int imx_pwm_config_v1(struct pwm_chip *chip,
29693248	61	struct pwm_device *pwm, int duty_ns, int period_ns)
166091b1	62	{
29693248	63	struct imx_chip *imx = to_imx_chip(chip);
166091b1	64
19e73333 SH	65	/*
	66	* The PWM subsystem allows for exact frequencies. However,
	67	* I cannot connect a scope on my device to the PWM line and
	68	* thus cannot provide the program the PWM controller
	69	* exactly. Instead, I'm relying on the fact that the
	70	* Bootloader (u-boot or WinCE+haret) has programmed the PWM
	71	* function group already. So I'll just modify the PWM sample
	72	* register to follow the ratio of duty_ns vs. period_ns
	73	* accordingly.
	74	*
	75	* This is good enough for programming the brightness of
	76	* the LCD backlight.
	77	*
	78	* The real implementation would divide PERCLK[0] first by
	79	* both the prescaler (/1 .. /128) and then by CLKSEL
	80	* (/2 .. /16).
	81	*/
	82	u32 max = readl(imx->mmio_base + MX1_PWMP);
	83	u32 p = max * duty_ns / period_ns;
	84	writel(max - p, imx->mmio_base + MX1_PWMS);
	85
	86	return 0;
	87	}
	88
b3c088fe	89	static int imx_pwm_enable_v1(struct pwm_chip chip, struct pwm_device pwm)
66ad6a61 SH	90	{
	91	struct imx_chip *imx = to_imx_chip(chip);
	92	u32 val;
b3c088fe LM	93	int ret;
	94
	95	ret = clk_prepare_enable(imx->clk_per);
	96	if (ret < 0)
	97	return ret;
66ad6a61 SH	98
66ad6a61 SH	99	val = readl(imx->mmio_base + MX1_PWMC);
b3c088fe LM	100	val \|= MX1_PWMC_EN;
b3c088fe LM	101	writel(val, imx->mmio_base + MX1_PWMC);
66ad6a61	102
b3c088fe LM	103	return 0;
b3c088fe LM	104	}
66ad6a61	105
b3c088fe LM	106	static void imx_pwm_disable_v1(struct pwm_chip chip, struct pwm_device pwm)
	107	{
	108	struct imx_chip *imx = to_imx_chip(chip);
	109	u32 val;
	110
	111	val = readl(imx->mmio_base + MX1_PWMC);
	112	val &= ~MX1_PWMC_EN;
66ad6a61	113	writel(val, imx->mmio_base + MX1_PWMC);
b3c088fe LM	114
b3c088fe LM	115	clk_disable_unprepare(imx->clk_per);
66ad6a61 SH	116	}
66ad6a61 SH	117
970247a4 LM	118	static void imx_pwm_sw_reset(struct pwm_chip *chip)
	119	{
	120	struct imx_chip *imx = to_imx_chip(chip);
	121	struct device *dev = chip->dev;
	122	int wait_count = 0;
	123	u32 cr;
	124
	125	writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
	126	do {
	127	usleep_range(200, 1000);
	128	cr = readl(imx->mmio_base + MX3_PWMCR);
	129	} while ((cr & MX3_PWMCR_SWR) &&
	130	(wait_count++ < MX3_PWM_SWR_LOOP));
	131
	132	if (cr & MX3_PWMCR_SWR)
	133	dev_warn(dev, "software reset timeout\n");
	134	}
	135
73b1ff1f LM	136	static void imx_pwm_wait_fifo_slot(struct pwm_chip *chip,
	137	struct pwm_device *pwm)
	138	{
	139	struct imx_chip *imx = to_imx_chip(chip);
	140	struct device *dev = chip->dev;
	141	unsigned int period_ms;
	142	int fifoav;
	143	u32 sr;
	144
	145	sr = readl(imx->mmio_base + MX3_PWMSR);
	146	fifoav = sr & MX3_PWMSR_FIFOAV_MASK;
	147	if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
	148	period_ms = DIV_ROUND_UP(pwm_get_period(pwm),
	149	NSEC_PER_MSEC);
	150	msleep(period_ms);
	151
	152	sr = readl(imx->mmio_base + MX3_PWMSR);
	153	if (fifoav == (sr & MX3_PWMSR_FIFOAV_MASK))
	154	dev_warn(dev, "there is no free FIFO slot\n");
	155	}
	156	}
970247a4	157
0ca1a11a LM	158	static int imx_pwm_apply_v2(struct pwm_chip chip, struct pwm_device pwm,
	159	struct pwm_state *state)
	160	{
	161	unsigned long period_cycles, duty_cycles, prescale;
	162	struct imx_chip *imx = to_imx_chip(chip);
	163	struct pwm_state cstate;
	164	unsigned long long c;
	165	int ret;
	166
	167	pwm_get_state(pwm, &cstate);
	168
	169	if (state->enabled) {
	170	c = clk_get_rate(imx->clk_per);
	171	c *= state->period;
	172
	173	do_div(c, 1000000000);
	174	period_cycles = c;
	175
	176	prescale = period_cycles / 0x10000 + 1;
	177
	178	period_cycles /= prescale;
	179	c = (unsigned long long)period_cycles * state->duty_cycle;
	180	do_div(c, state->period);
	181	duty_cycles = c;
	182
	183	/*
	184	* according to imx pwm RM, the real period value should be
	185	* PERIOD value in PWMPR plus 2.
	186	*/
	187	if (period_cycles > 2)
	188	period_cycles -= 2;
	189	else
	190	period_cycles = 0;
	191
	192	/*
	193	* Wait for a free FIFO slot if the PWM is already enabled, and
	194	* flush the FIFO if the PWM was disabled and is about to be
	195	* enabled.
	196	*/
	197	if (cstate.enabled) {
	198	imx_pwm_wait_fifo_slot(chip, pwm);
	199	} else {
	200	ret = clk_prepare_enable(imx->clk_per);
	201	if (ret)
	202	return ret;
	203
	204	imx_pwm_sw_reset(chip);
	205	}
	206
	207	writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
	208	writel(period_cycles, imx->mmio_base + MX3_PWMPR);
	209
	210	writel(MX3_PWMCR_PRESCALER(prescale) \|
	211	MX3_PWMCR_DOZEEN \| MX3_PWMCR_WAITEN \|
	212	MX3_PWMCR_DBGEN \| MX3_PWMCR_CLKSRC_IPG_HIGH \|
	213	MX3_PWMCR_EN,
	214	imx->mmio_base + MX3_PWMCR);
	215	} else if (cstate.enabled) {
	216	writel(0, imx->mmio_base + MX3_PWMCR);
	217
	218	clk_disable_unprepare(imx->clk_per);
	219	}
	220
	221	return 0;
222	}
223
00389229	224	static const struct pwm_ops imx_pwm_ops_v1 = {
b3c088fe LM	225	.enable = imx_pwm_enable_v1,
	226	.disable = imx_pwm_disable_v1,
	227	.config = imx_pwm_config_v1,
00389229 LM	228	.owner = THIS_MODULE,
	229	};
	230
	231	static const struct pwm_ops imx_pwm_ops_v2 = {
0ca1a11a	232	.apply = imx_pwm_apply_v2,
29693248 SH	233	.owner = THIS_MODULE,
29693248 SH	234	};
166091b1	235
479e2e30	236	struct imx_pwm_data {
00389229	237	const struct pwm_ops *ops;
479e2e30 PZ	238	};
	239
	240	static struct imx_pwm_data imx_pwm_data_v1 = {
00389229	241	.ops = &imx_pwm_ops_v1,
479e2e30 PZ	242	};
	243
	244	static struct imx_pwm_data imx_pwm_data_v2 = {
00389229	245	.ops = &imx_pwm_ops_v2,
479e2e30 PZ	246	};
	247
	248	static const struct of_device_id imx_pwm_dt_ids[] = {
	249	{ .compatible = "fsl,imx1-pwm", .data = &imx_pwm_data_v1, },
	250	{ .compatible = "fsl,imx27-pwm", .data = &imx_pwm_data_v2, },
	251	{ /* sentinel */ }
	252	};
	253	MODULE_DEVICE_TABLE(of, imx_pwm_dt_ids);
	254
3e9fe83d	255	static int imx_pwm_probe(struct platform_device *pdev)
166091b1	256	{
479e2e30 PZ	257	const struct of_device_id *of_id =
479e2e30 PZ	258	of_match_device(imx_pwm_dt_ids, &pdev->dev);
983290b0	259	const struct imx_pwm_data *data;
29693248	260	struct imx_chip *imx;
166091b1 SH	261	struct resource *r;
	262	int ret = 0;
	263
479e2e30 PZ	264	if (!of_id)
	265	return -ENODEV;
	266
00389229 LM	267	data = of_id->data;
00389229 LM	268
a9970e3b	269	imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
1cbec749	270	if (imx == NULL)
166091b1	271	return -ENOMEM;
166091b1	272
7b27c160 PZ	273	imx->clk_per = devm_clk_get(&pdev->dev, "per");
	274	if (IS_ERR(imx->clk_per)) {
	275	dev_err(&pdev->dev, "getting per clock failed with %ld\n",
	276	PTR_ERR(imx->clk_per));
	277	return PTR_ERR(imx->clk_per);
	278	}
166091b1	279
00389229	280	imx->chip.ops = data->ops;
29693248 SH	281	imx->chip.dev = &pdev->dev;
	282	imx->chip.base = -1;
	283	imx->chip.npwm = 1;
31c4fa34	284	imx->chip.can_sleep = true;
166091b1	285
166091b1	286	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6d4294d1 TR	287	imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
	288	if (IS_ERR(imx->mmio_base))
	289	return PTR_ERR(imx->mmio_base);
166091b1	290
29693248 SH	291	ret = pwmchip_add(&imx->chip);
29693248 SH	292	if (ret < 0)
a9970e3b	293	return ret;
166091b1	294
29693248	295	platform_set_drvdata(pdev, imx);
166091b1	296	return 0;
166091b1 SH	297	}
166091b1 SH	298
77f37917	299	static int imx_pwm_remove(struct platform_device *pdev)
166091b1	300	{
29693248	301	struct imx_chip *imx;
166091b1	302
29693248 SH	303	imx = platform_get_drvdata(pdev);
29693248 SH	304	if (imx == NULL)
166091b1 SH	305	return -ENODEV;
166091b1 SH	306
a9970e3b	307	return pwmchip_remove(&imx->chip);
166091b1 SH	308	}
166091b1 SH	309
29693248	310	static struct platform_driver imx_pwm_driver = {
166091b1	311	.driver = {
479e2e30	312	.name = "imx-pwm",
becbca13	313	.of_match_table = imx_pwm_dt_ids,
166091b1	314	},
29693248	315	.probe = imx_pwm_probe,
fd109112	316	.remove = imx_pwm_remove,
166091b1 SH	317	};
166091b1 SH	318
208d038f	319	module_platform_driver(imx_pwm_driver);
166091b1 SH	320
	321	MODULE_LICENSE("GPL v2");
	322	MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");