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1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Intel Keem Bay PWM driver | |
4 | * | |
5 | * Copyright (C) 2020 Intel Corporation | |
6 | * Authors: Lai Poey Seng <poey.seng.lai@intel.com> | |
7 | * Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com> | |
8 | * | |
9 | * Limitations: | |
10 | * - Upon disabling a channel, the currently running | |
11 | * period will not be completed. However, upon | |
12 | * reconfiguration of the duty cycle/period, the | |
13 | * currently running period will be completed first. | |
14 | */ | |
15 | ||
16 | #include <linux/bitfield.h> | |
17 | #include <linux/clk.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/mod_devicetable.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/pwm.h> | |
23 | #include <linux/regmap.h> | |
24 | ||
25 | #define KMB_TOTAL_PWM_CHANNELS 6 | |
26 | #define KMB_PWM_COUNT_MAX U16_MAX | |
27 | #define KMB_PWM_EN_BIT BIT(31) | |
28 | ||
29 | /* Mask */ | |
30 | #define KMB_PWM_HIGH_MASK GENMASK(31, 16) | |
31 | #define KMB_PWM_LOW_MASK GENMASK(15, 0) | |
32 | #define KMB_PWM_LEADIN_MASK GENMASK(30, 0) | |
33 | ||
34 | /* PWM Register offset */ | |
35 | #define KMB_PWM_LEADIN_OFFSET(ch) (0x00 + 4 * (ch)) | |
36 | #define KMB_PWM_HIGHLOW_OFFSET(ch) (0x20 + 4 * (ch)) | |
37 | ||
38 | struct keembay_pwm { | |
39 | struct pwm_chip chip; | |
40 | struct device *dev; | |
41 | struct clk *clk; | |
42 | void __iomem *base; | |
43 | }; | |
44 | ||
45 | static inline struct keembay_pwm *to_keembay_pwm_dev(struct pwm_chip *chip) | |
46 | { | |
47 | return container_of(chip, struct keembay_pwm, chip); | |
48 | } | |
49 | ||
50 | static void keembay_clk_unprepare(void *data) | |
51 | { | |
52 | clk_disable_unprepare(data); | |
53 | } | |
54 | ||
55 | static int keembay_clk_enable(struct device *dev, struct clk *clk) | |
56 | { | |
57 | int ret; | |
58 | ||
59 | ret = clk_prepare_enable(clk); | |
60 | if (ret) | |
61 | return ret; | |
62 | ||
63 | return devm_add_action_or_reset(dev, keembay_clk_unprepare, clk); | |
64 | } | |
65 | ||
66 | static inline void keembay_pwm_update_bits(struct keembay_pwm *priv, u32 mask, | |
67 | u32 val, u32 offset) | |
68 | { | |
69 | u32 buff = readl(priv->base + offset); | |
70 | ||
71 | buff = u32_replace_bits(buff, val, mask); | |
72 | writel(buff, priv->base + offset); | |
73 | } | |
74 | ||
75 | static void keembay_pwm_enable(struct keembay_pwm *priv, int ch) | |
76 | { | |
77 | keembay_pwm_update_bits(priv, KMB_PWM_EN_BIT, 1, | |
78 | KMB_PWM_LEADIN_OFFSET(ch)); | |
79 | } | |
80 | ||
81 | static void keembay_pwm_disable(struct keembay_pwm *priv, int ch) | |
82 | { | |
83 | keembay_pwm_update_bits(priv, KMB_PWM_EN_BIT, 0, | |
84 | KMB_PWM_LEADIN_OFFSET(ch)); | |
85 | } | |
86 | ||
87 | static void keembay_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, | |
88 | struct pwm_state *state) | |
89 | { | |
90 | struct keembay_pwm *priv = to_keembay_pwm_dev(chip); | |
91 | unsigned long long high, low; | |
92 | unsigned long clk_rate; | |
93 | u32 highlow; | |
94 | ||
95 | clk_rate = clk_get_rate(priv->clk); | |
96 | ||
97 | /* Read channel enabled status */ | |
98 | highlow = readl(priv->base + KMB_PWM_LEADIN_OFFSET(pwm->hwpwm)); | |
99 | if (highlow & KMB_PWM_EN_BIT) | |
100 | state->enabled = true; | |
101 | else | |
102 | state->enabled = false; | |
103 | ||
104 | /* Read period and duty cycle */ | |
105 | highlow = readl(priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm)); | |
106 | low = FIELD_GET(KMB_PWM_LOW_MASK, highlow) * NSEC_PER_SEC; | |
107 | high = FIELD_GET(KMB_PWM_HIGH_MASK, highlow) * NSEC_PER_SEC; | |
108 | state->duty_cycle = DIV_ROUND_UP_ULL(high, clk_rate); | |
109 | state->period = DIV_ROUND_UP_ULL(high + low, clk_rate); | |
110 | state->polarity = PWM_POLARITY_NORMAL; | |
111 | } | |
112 | ||
113 | static int keembay_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, | |
114 | const struct pwm_state *state) | |
115 | { | |
116 | struct keembay_pwm *priv = to_keembay_pwm_dev(chip); | |
117 | struct pwm_state current_state; | |
118 | unsigned long long div; | |
119 | unsigned long clk_rate; | |
120 | u32 pwm_count = 0; | |
121 | u16 high, low; | |
122 | ||
123 | if (state->polarity != PWM_POLARITY_NORMAL) | |
124 | return -EINVAL; | |
125 | ||
126 | /* | |
127 | * Configure the pwm repeat count as infinite at (15:0) and leadin | |
128 | * low time as 0 at (30:16), which is in terms of clock cycles. | |
129 | */ | |
130 | keembay_pwm_update_bits(priv, KMB_PWM_LEADIN_MASK, 0, | |
131 | KMB_PWM_LEADIN_OFFSET(pwm->hwpwm)); | |
132 | ||
133 | keembay_pwm_get_state(chip, pwm, ¤t_state); | |
134 | ||
135 | if (!state->enabled) { | |
136 | if (current_state.enabled) | |
137 | keembay_pwm_disable(priv, pwm->hwpwm); | |
138 | return 0; | |
139 | } | |
140 | ||
141 | /* | |
142 | * The upper 16 bits and lower 16 bits of the KMB_PWM_HIGHLOW_OFFSET | |
143 | * register contain the high time and low time of waveform accordingly. | |
144 | * All the values are in terms of clock cycles. | |
145 | */ | |
146 | ||
147 | clk_rate = clk_get_rate(priv->clk); | |
148 | div = clk_rate * state->duty_cycle; | |
149 | div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC); | |
150 | if (div > KMB_PWM_COUNT_MAX) | |
151 | return -ERANGE; | |
152 | ||
153 | high = div; | |
154 | div = clk_rate * state->period; | |
155 | div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC); | |
156 | div = div - high; | |
157 | if (div > KMB_PWM_COUNT_MAX) | |
158 | return -ERANGE; | |
159 | ||
160 | low = div; | |
161 | ||
162 | pwm_count = FIELD_PREP(KMB_PWM_HIGH_MASK, high) | | |
163 | FIELD_PREP(KMB_PWM_LOW_MASK, low); | |
164 | ||
165 | writel(pwm_count, priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm)); | |
166 | ||
167 | if (state->enabled && !current_state.enabled) | |
168 | keembay_pwm_enable(priv, pwm->hwpwm); | |
169 | ||
170 | return 0; | |
171 | } | |
172 | ||
173 | static const struct pwm_ops keembay_pwm_ops = { | |
174 | .owner = THIS_MODULE, | |
175 | .apply = keembay_pwm_apply, | |
176 | .get_state = keembay_pwm_get_state, | |
177 | }; | |
178 | ||
179 | static int keembay_pwm_probe(struct platform_device *pdev) | |
180 | { | |
181 | struct device *dev = &pdev->dev; | |
182 | struct keembay_pwm *priv; | |
183 | int ret; | |
184 | ||
185 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); | |
186 | if (!priv) | |
187 | return -ENOMEM; | |
188 | ||
189 | priv->clk = devm_clk_get(dev, NULL); | |
190 | if (IS_ERR(priv->clk)) | |
191 | return dev_err_probe(dev, PTR_ERR(priv->clk), "Failed to get clock\n"); | |
192 | ||
193 | priv->base = devm_platform_ioremap_resource(pdev, 0); | |
194 | if (IS_ERR(priv->base)) | |
195 | return PTR_ERR(priv->base); | |
196 | ||
197 | ret = keembay_clk_enable(dev, priv->clk); | |
198 | if (ret) | |
199 | return ret; | |
200 | ||
201 | priv->chip.base = -1; | |
202 | priv->chip.dev = dev; | |
203 | priv->chip.ops = &keembay_pwm_ops; | |
204 | priv->chip.npwm = KMB_TOTAL_PWM_CHANNELS; | |
205 | ||
206 | ret = pwmchip_add(&priv->chip); | |
207 | if (ret) | |
208 | return dev_err_probe(dev, ret, "Failed to add PWM chip\n"); | |
209 | ||
210 | platform_set_drvdata(pdev, priv); | |
211 | ||
212 | return 0; | |
213 | } | |
214 | ||
215 | static int keembay_pwm_remove(struct platform_device *pdev) | |
216 | { | |
217 | struct keembay_pwm *priv = platform_get_drvdata(pdev); | |
218 | ||
219 | return pwmchip_remove(&priv->chip); | |
220 | } | |
221 | ||
222 | static const struct of_device_id keembay_pwm_of_match[] = { | |
223 | { .compatible = "intel,keembay-pwm" }, | |
224 | { } | |
225 | }; | |
226 | MODULE_DEVICE_TABLE(of, keembay_pwm_of_match); | |
227 | ||
228 | static struct platform_driver keembay_pwm_driver = { | |
229 | .probe = keembay_pwm_probe, | |
230 | .remove = keembay_pwm_remove, | |
231 | .driver = { | |
232 | .name = "pwm-keembay", | |
233 | .of_match_table = keembay_pwm_of_match, | |
234 | }, | |
235 | }; | |
236 | module_platform_driver(keembay_pwm_driver); | |
237 | ||
238 | MODULE_ALIAS("platform:pwm-keembay"); | |
239 | MODULE_DESCRIPTION("Intel Keem Bay PWM driver"); | |
240 | MODULE_LICENSE("GPL v2"); |