[mirror_ubuntu-zesty-kernel.git] / drivers / pwm / pwm-lpc32xx.c

/*
 * Copyright 2012 Alexandre Pereira da Silva <aletes.xgr@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2.
 *
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>

struct lpc32xx_pwm_chip {
	struct pwm_chip chip;
	struct clk *clk;
	void __iomem *base;
};

#define PWM_ENABLE	(1 << 31)
#define PWM_RELOADV(x)	(((x) & 0xFF) << 8)
#define PWM_DUTY(x)	((x) & 0xFF)

#define to_lpc32xx_pwm_chip(_chip) \
	container_of(_chip, struct lpc32xx_pwm_chip, chip)

static int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
			      int duty_ns, int period_ns)
{
	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
	unsigned long long c;
	int period_cycles, duty_cycles;
	u32 val;

	c = clk_get_rate(lpc32xx->clk) / 256;
	c = c * period_ns;
	do_div(c, NSEC_PER_SEC);

	/* Handle high and low extremes */
	if (c == 0)
		c = 1;
	if (c > 255)
		c = 0; /* 0 set division by 256 */
	period_cycles = c;

	/* The duty-cycle value is as follows:
	 *
	 *  DUTY-CYCLE     HIGH LEVEL
	 *      1            99.9%
	 *      25           90.0%
	 *      128          50.0%
	 *      220          10.0%
	 *      255           0.1%
	 *      0             0.0%
	 *
	 * In other words, the register value is duty-cycle % 256 with
	 * duty-cycle in the range 1-256.
	 */
	c = 256 * duty_ns;
	do_div(c, period_ns);
	if (c > 255)
		c = 255;
	duty_cycles = 256 - c;

	val = readl(lpc32xx->base + (pwm->hwpwm << 2));
	val &= ~0xFFFF;
	val |= PWM_RELOADV(period_cycles) | PWM_DUTY(duty_cycles);
	writel(val, lpc32xx->base + (pwm->hwpwm << 2));

	return 0;
}

static int lpc32xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
	u32 val;
	int ret;

	ret = clk_enable(lpc32xx->clk);
	if (ret)
		return ret;

	val = readl(lpc32xx->base + (pwm->hwpwm << 2));
	val |= PWM_ENABLE;
	writel(val, lpc32xx->base + (pwm->hwpwm << 2));

	return 0;
}

static void lpc32xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
	u32 val;

	val = readl(lpc32xx->base + (pwm->hwpwm << 2));
	val &= ~PWM_ENABLE;
	writel(val, lpc32xx->base + (pwm->hwpwm << 2));

	clk_disable(lpc32xx->clk);
}

static const struct pwm_ops lpc32xx_pwm_ops = {
	.config = lpc32xx_pwm_config,
	.enable = lpc32xx_pwm_enable,
	.disable = lpc32xx_pwm_disable,
	.owner = THIS_MODULE,
};

static int lpc32xx_pwm_probe(struct platform_device *pdev)
{
	struct lpc32xx_pwm_chip *lpc32xx;
	struct resource *res;
	int ret;

	lpc32xx = devm_kzalloc(&pdev->dev, sizeof(*lpc32xx), GFP_KERNEL);
	if (!lpc32xx)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	lpc32xx->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(lpc32xx->base))
		return PTR_ERR(lpc32xx->base);

	lpc32xx->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(lpc32xx->clk))
		return PTR_ERR(lpc32xx->clk);

	lpc32xx->chip.dev = &pdev->dev;
	lpc32xx->chip.ops = &lpc32xx_pwm_ops;
	lpc32xx->chip.npwm = 2;
	lpc32xx->chip.base = -1;

	ret = pwmchip_add(&lpc32xx->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to add PWM chip, error %d\n", ret);
		return ret;
	}

	platform_set_drvdata(pdev, lpc32xx);

	return 0;
}

static int lpc32xx_pwm_remove(struct platform_device *pdev)
{
	struct lpc32xx_pwm_chip *lpc32xx = platform_get_drvdata(pdev);
	unsigned int i;

	for (i = 0; i < lpc32xx->chip.npwm; i++)
		pwm_disable(&lpc32xx->chip.pwms[i]);

	return pwmchip_remove(&lpc32xx->chip);
}

static const struct of_device_id lpc32xx_pwm_dt_ids[] = {
	{ .compatible = "nxp,lpc3220-pwm", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, lpc32xx_pwm_dt_ids);

static struct platform_driver lpc32xx_pwm_driver = {
	.driver = {
		.name = "lpc32xx-pwm",
		.of_match_table = lpc32xx_pwm_dt_ids,
	},
	.probe = lpc32xx_pwm_probe,
	.remove = lpc32xx_pwm_remove,
};
module_platform_driver(lpc32xx_pwm_driver);

MODULE_ALIAS("platform:lpc32xx-pwm");
MODULE_AUTHOR("Alexandre Pereira da Silva <aletes.xgr@gmail.com>");
MODULE_DESCRIPTION("LPC32XX PWM Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2132fa8d APS	1	/*
	2	* Copyright 2012 Alexandre Pereira da Silva <aletes.xgr@gmail.com>
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; version 2.
	7	*
	8	*/
	9
	10	#include <linux/clk.h>
	11	#include <linux/err.h>
	12	#include <linux/io.h>
	13	#include <linux/kernel.h>
	14	#include <linux/module.h>
	15	#include <linux/of.h>
	16	#include <linux/of_address.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/pwm.h>
	19	#include <linux/slab.h>
	20
	21	struct lpc32xx_pwm_chip {
	22	struct pwm_chip chip;
	23	struct clk *clk;
	24	void __iomem *base;
	25	};
	26
	27	#define PWM_ENABLE (1 << 31)
	28	#define PWM_RELOADV(x) (((x) & 0xFF) << 8)
	29	#define PWM_DUTY(x) ((x) & 0xFF)
	30
	31	#define to_lpc32xx_pwm_chip(_chip) \
	32	container_of(_chip, struct lpc32xx_pwm_chip, chip)
	33
	34	static int lpc32xx_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
	35	int duty_ns, int period_ns)
	36	{
	37	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
	38	unsigned long long c;
	39	int period_cycles, duty_cycles;
affb923d	40	u32 val;
2132fa8d APS	41
	42	c = clk_get_rate(lpc32xx->clk) / 256;
	43	c = c * period_ns;
	44	do_div(c, NSEC_PER_SEC);
	45
	46	/* Handle high and low extremes */
	47	if (c == 0)
	48	c = 1;
	49	if (c > 255)
	50	c = 0; /* 0 set division by 256 */
	51	period_cycles = c;
	52
a9a18e06 AB	53	/* The duty-cycle value is as follows:
	54	*
	55	* DUTY-CYCLE HIGH LEVEL
	56	* 1 99.9%
	57	* 25 90.0%
	58	* 128 50.0%
	59	* 220 10.0%
	60	* 255 0.1%
	61	* 0 0.0%
	62	*
	63	* In other words, the register value is duty-cycle % 256 with
	64	* duty-cycle in the range 1-256.
	65	*/
2132fa8d APS	66	c = 256 * duty_ns;
2132fa8d APS	67	do_div(c, period_ns);
a9a18e06 AB	68	if (c > 255)
	69	c = 255;
	70	duty_cycles = 256 - c;
2132fa8d	71
affb923d AL	72	val = readl(lpc32xx->base + (pwm->hwpwm << 2));
	73	val &= ~0xFFFF;
	74	val \|= PWM_RELOADV(period_cycles) \| PWM_DUTY(duty_cycles);
	75	writel(val, lpc32xx->base + (pwm->hwpwm << 2));
2132fa8d APS	76
	77	return 0;
	78	}
	79
	80	static int lpc32xx_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
	81	{
	82	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
08ee77b5 AL	83	u32 val;
	84	int ret;
	85
	86	ret = clk_enable(lpc32xx->clk);
	87	if (ret)
	88	return ret;
	89
	90	val = readl(lpc32xx->base + (pwm->hwpwm << 2));
	91	val \|= PWM_ENABLE;
	92	writel(val, lpc32xx->base + (pwm->hwpwm << 2));
2132fa8d	93
08ee77b5	94	return 0;
2132fa8d APS	95	}
	96
	97	static void lpc32xx_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
	98	{
	99	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
08ee77b5 AL	100	u32 val;
	101
	102	val = readl(lpc32xx->base + (pwm->hwpwm << 2));
	103	val &= ~PWM_ENABLE;
	104	writel(val, lpc32xx->base + (pwm->hwpwm << 2));
2132fa8d	105
2132fa8d APS	106	clk_disable(lpc32xx->clk);
	107	}
	108
	109	static const struct pwm_ops lpc32xx_pwm_ops = {
	110	.config = lpc32xx_pwm_config,
	111	.enable = lpc32xx_pwm_enable,
	112	.disable = lpc32xx_pwm_disable,
	113	.owner = THIS_MODULE,
	114	};
	115
	116	static int lpc32xx_pwm_probe(struct platform_device *pdev)
	117	{
	118	struct lpc32xx_pwm_chip *lpc32xx;
	119	struct resource *res;
	120	int ret;
	121
	122	lpc32xx = devm_kzalloc(&pdev->dev, sizeof(*lpc32xx), GFP_KERNEL);
	123	if (!lpc32xx)
	124	return -ENOMEM;
	125
	126	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6d4294d1 TR	127	lpc32xx->base = devm_ioremap_resource(&pdev->dev, res);
	128	if (IS_ERR(lpc32xx->base))
	129	return PTR_ERR(lpc32xx->base);
2132fa8d APS	130
	131	lpc32xx->clk = devm_clk_get(&pdev->dev, NULL);
	132	if (IS_ERR(lpc32xx->clk))
	133	return PTR_ERR(lpc32xx->clk);
	134
	135	lpc32xx->chip.dev = &pdev->dev;
	136	lpc32xx->chip.ops = &lpc32xx_pwm_ops;
	137	lpc32xx->chip.npwm = 2;
8fc6d09d	138	lpc32xx->chip.base = -1;
2132fa8d APS	139
	140	ret = pwmchip_add(&lpc32xx->chip);
	141	if (ret < 0) {
	142	dev_err(&pdev->dev, "failed to add PWM chip, error %d\n", ret);
	143	return ret;
	144	}
	145
	146	platform_set_drvdata(pdev, lpc32xx);
	147
	148	return 0;
	149	}
	150
77f37917	151	static int lpc32xx_pwm_remove(struct platform_device *pdev)
2132fa8d APS	152	{
2132fa8d APS	153	struct lpc32xx_pwm_chip *lpc32xx = platform_get_drvdata(pdev);
54b2a999 AB	154	unsigned int i;
	155
	156	for (i = 0; i < lpc32xx->chip.npwm; i++)
	157	pwm_disable(&lpc32xx->chip.pwms[i]);
2132fa8d	158
2132fa8d APS	159	return pwmchip_remove(&lpc32xx->chip);
	160	}
	161
f1a8870a	162	static const struct of_device_id lpc32xx_pwm_dt_ids[] = {
2132fa8d APS	163	{ .compatible = "nxp,lpc3220-pwm", },
	164	{ /* sentinel */ }
	165	};
	166	MODULE_DEVICE_TABLE(of, lpc32xx_pwm_dt_ids);
	167
	168	static struct platform_driver lpc32xx_pwm_driver = {
	169	.driver = {
	170	.name = "lpc32xx-pwm",
3cb3b2bf	171	.of_match_table = lpc32xx_pwm_dt_ids,
2132fa8d APS	172	},
2132fa8d APS	173	.probe = lpc32xx_pwm_probe,
fd109112	174	.remove = lpc32xx_pwm_remove,
2132fa8d APS	175	};
	176	module_platform_driver(lpc32xx_pwm_driver);
	177
	178	MODULE_ALIAS("platform:lpc32xx-pwm");
	179	MODULE_AUTHOR("Alexandre Pereira da Silva <aletes.xgr@gmail.com>");
	180	MODULE_DESCRIPTION("LPC32XX PWM Driver");
	181	MODULE_LICENSE("GPL v2");