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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
d16a5aa9 MW |
2 | /* |
3 | * Intel Low Power Subsystem PWM controller driver | |
4 | * | |
5 | * Copyright (C) 2014, Intel Corporation | |
6 | * Author: Mika Westerberg <mika.westerberg@linux.intel.com> | |
7 | * Author: Chew Kean Ho <kean.ho.chew@intel.com> | |
8 | * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com> | |
9 | * Author: Chew Chiau Ee <chiau.ee.chew@intel.com> | |
093e00bb | 10 | * Author: Alan Cox <alan@linux.intel.com> |
d16a5aa9 MW |
11 | */ |
12 | ||
37670676 | 13 | #include <linux/delay.h> |
e0c86a3b | 14 | #include <linux/io.h> |
10d56a4c | 15 | #include <linux/iopoll.h> |
d16a5aa9 MW |
16 | #include <linux/kernel.h> |
17 | #include <linux/module.h> | |
f080be27 | 18 | #include <linux/pm_runtime.h> |
883e4d07 | 19 | #include <linux/time.h> |
093e00bb | 20 | |
c558e39e | 21 | #include "pwm-lpss.h" |
d16a5aa9 MW |
22 | |
23 | #define PWM 0x00000000 | |
24 | #define PWM_ENABLE BIT(31) | |
25 | #define PWM_SW_UPDATE BIT(30) | |
26 | #define PWM_BASE_UNIT_SHIFT 8 | |
d16a5aa9 | 27 | #define PWM_ON_TIME_DIV_MASK 0x000000ff |
d16a5aa9 | 28 | |
4e11f5ac MW |
29 | /* Size of each PWM register space if multiple */ |
30 | #define PWM_SIZE 0x400 | |
31 | ||
d16a5aa9 MW |
32 | static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip) |
33 | { | |
34 | return container_of(chip, struct pwm_lpss_chip, chip); | |
35 | } | |
36 | ||
4e11f5ac MW |
37 | static inline u32 pwm_lpss_read(const struct pwm_device *pwm) |
38 | { | |
39 | struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip); | |
40 | ||
41 | return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); | |
42 | } | |
43 | ||
44 | static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value) | |
45 | { | |
46 | struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip); | |
47 | ||
48 | writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); | |
49 | } | |
50 | ||
b997e3ed | 51 | static int pwm_lpss_wait_for_update(struct pwm_device *pwm) |
37670676 | 52 | { |
10d56a4c IK |
53 | struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip); |
54 | const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM; | |
55 | const unsigned int ms = 500 * USEC_PER_MSEC; | |
56 | u32 val; | |
57 | int err; | |
58 | ||
b14e8cef | 59 | /* |
10d56a4c IK |
60 | * PWM Configuration register has SW_UPDATE bit that is set when a new |
61 | * configuration is written to the register. The bit is automatically | |
62 | * cleared at the start of the next output cycle by the IP block. | |
63 | * | |
64 | * If one writes a new configuration to the register while it still has | |
65 | * the bit enabled, PWM may freeze. That is, while one can still write | |
66 | * to the register, it won't have an effect. Thus, we try to sleep long | |
67 | * enough that the bit gets cleared and make sure the bit is not | |
68 | * enabled while we update the configuration. | |
b14e8cef | 69 | */ |
10d56a4c IK |
70 | err = readl_poll_timeout(addr, val, !(val & PWM_SW_UPDATE), 40, ms); |
71 | if (err) | |
72 | dev_err(pwm->chip->dev, "PWM_SW_UPDATE was not cleared\n"); | |
b14e8cef | 73 | |
10d56a4c IK |
74 | return err; |
75 | } | |
76 | ||
77 | static inline int pwm_lpss_is_updating(struct pwm_device *pwm) | |
78 | { | |
79 | return (pwm_lpss_read(pwm) & PWM_SW_UPDATE) ? -EBUSY : 0; | |
37670676 MW |
80 | } |
81 | ||
b14e8cef AS |
82 | static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm, |
83 | int duty_ns, int period_ns) | |
d16a5aa9 | 84 | { |
ab248b60 | 85 | unsigned long long on_time_div; |
d9cd4a73 | 86 | unsigned long c = lpwm->info->clk_rate, base_unit_range; |
883e4d07 | 87 | unsigned long long base_unit, freq = NSEC_PER_SEC; |
2153bbc1 | 88 | u32 orig_ctrl, ctrl; |
d16a5aa9 MW |
89 | |
90 | do_div(freq, period_ns); | |
91 | ||
883e4d07 | 92 | /* |
93 | * The equation is: | |
e5ca4245 | 94 | * base_unit = round(base_unit_range * freq / c) |
883e4d07 | 95 | */ |
684309e5 | 96 | base_unit_range = BIT(lpwm->info->base_unit_bits) - 1; |
e5ca4245 | 97 | freq *= base_unit_range; |
d16a5aa9 | 98 | |
e5ca4245 | 99 | base_unit = DIV_ROUND_CLOSEST_ULL(freq, c); |
d16a5aa9 | 100 | |
ab248b60 MW |
101 | on_time_div = 255ULL * duty_ns; |
102 | do_div(on_time_div, period_ns); | |
103 | on_time_div = 255ULL - on_time_div; | |
d16a5aa9 | 104 | |
2153bbc1 | 105 | orig_ctrl = ctrl = pwm_lpss_read(pwm); |
883e4d07 | 106 | ctrl &= ~PWM_ON_TIME_DIV_MASK; |
684309e5 AS |
107 | ctrl &= ~(base_unit_range << PWM_BASE_UNIT_SHIFT); |
108 | base_unit &= base_unit_range; | |
883e4d07 | 109 | ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT; |
d16a5aa9 | 110 | ctrl |= on_time_div; |
2153bbc1 HG |
111 | |
112 | if (orig_ctrl != ctrl) { | |
113 | pwm_lpss_write(pwm, ctrl); | |
114 | pwm_lpss_write(pwm, ctrl | PWM_SW_UPDATE); | |
115 | } | |
d16a5aa9 MW |
116 | } |
117 | ||
b997e3ed HG |
118 | static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond) |
119 | { | |
120 | if (cond) | |
121 | pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE); | |
122 | } | |
123 | ||
b14e8cef AS |
124 | static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
125 | struct pwm_state *state) | |
d16a5aa9 | 126 | { |
b14e8cef | 127 | struct pwm_lpss_chip *lpwm = to_lpwm(chip); |
10d56a4c | 128 | int ret; |
37670676 | 129 | |
b14e8cef AS |
130 | if (state->enabled) { |
131 | if (!pwm_is_enabled(pwm)) { | |
132 | pm_runtime_get_sync(chip->dev); | |
10d56a4c IK |
133 | ret = pwm_lpss_is_updating(pwm); |
134 | if (ret) { | |
135 | pm_runtime_put(chip->dev); | |
136 | return ret; | |
137 | } | |
b14e8cef | 138 | pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period); |
b997e3ed HG |
139 | pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false); |
140 | ret = pwm_lpss_wait_for_update(pwm); | |
10d56a4c IK |
141 | if (ret) { |
142 | pm_runtime_put(chip->dev); | |
143 | return ret; | |
144 | } | |
b997e3ed | 145 | pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true); |
b14e8cef | 146 | } else { |
10d56a4c IK |
147 | ret = pwm_lpss_is_updating(pwm); |
148 | if (ret) | |
149 | return ret; | |
b14e8cef | 150 | pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period); |
b997e3ed | 151 | return pwm_lpss_wait_for_update(pwm); |
b14e8cef AS |
152 | } |
153 | } else if (pwm_is_enabled(pwm)) { | |
154 | pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE); | |
155 | pm_runtime_put(chip->dev); | |
156 | } | |
d16a5aa9 | 157 | |
b14e8cef | 158 | return 0; |
d16a5aa9 MW |
159 | } |
160 | ||
280fec4c HG |
161 | /* This function gets called once from pwmchip_add to get the initial state */ |
162 | static void pwm_lpss_get_state(struct pwm_chip *chip, struct pwm_device *pwm, | |
163 | struct pwm_state *state) | |
164 | { | |
165 | struct pwm_lpss_chip *lpwm = to_lpwm(chip); | |
166 | unsigned long base_unit_range; | |
167 | unsigned long long base_unit, freq, on_time_div; | |
168 | u32 ctrl; | |
169 | ||
170 | base_unit_range = BIT(lpwm->info->base_unit_bits); | |
171 | ||
172 | ctrl = pwm_lpss_read(pwm); | |
173 | on_time_div = 255 - (ctrl & PWM_ON_TIME_DIV_MASK); | |
174 | base_unit = (ctrl >> PWM_BASE_UNIT_SHIFT) & (base_unit_range - 1); | |
175 | ||
176 | freq = base_unit * lpwm->info->clk_rate; | |
177 | do_div(freq, base_unit_range); | |
178 | if (freq == 0) | |
179 | state->period = NSEC_PER_SEC; | |
180 | else | |
181 | state->period = NSEC_PER_SEC / (unsigned long)freq; | |
182 | ||
183 | on_time_div *= state->period; | |
184 | do_div(on_time_div, 255); | |
185 | state->duty_cycle = on_time_div; | |
186 | ||
187 | state->polarity = PWM_POLARITY_NORMAL; | |
188 | state->enabled = !!(ctrl & PWM_ENABLE); | |
189 | ||
190 | if (state->enabled) | |
191 | pm_runtime_get(chip->dev); | |
192 | } | |
193 | ||
d16a5aa9 | 194 | static const struct pwm_ops pwm_lpss_ops = { |
b14e8cef | 195 | .apply = pwm_lpss_apply, |
280fec4c | 196 | .get_state = pwm_lpss_get_state, |
d16a5aa9 MW |
197 | .owner = THIS_MODULE, |
198 | }; | |
199 | ||
c558e39e AS |
200 | struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r, |
201 | const struct pwm_lpss_boardinfo *info) | |
d16a5aa9 MW |
202 | { |
203 | struct pwm_lpss_chip *lpwm; | |
d9cd4a73 | 204 | unsigned long c; |
d16a5aa9 MW |
205 | int ret; |
206 | ||
1d375b58 HG |
207 | if (WARN_ON(info->npwm > MAX_PWMS)) |
208 | return ERR_PTR(-ENODEV); | |
209 | ||
093e00bb | 210 | lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL); |
d16a5aa9 | 211 | if (!lpwm) |
093e00bb | 212 | return ERR_PTR(-ENOMEM); |
d16a5aa9 | 213 | |
093e00bb | 214 | lpwm->regs = devm_ioremap_resource(dev, r); |
d16a5aa9 | 215 | if (IS_ERR(lpwm->regs)) |
89c0339e | 216 | return ERR_CAST(lpwm->regs); |
093e00bb | 217 | |
883e4d07 | 218 | lpwm->info = info; |
d9cd4a73 AS |
219 | |
220 | c = lpwm->info->clk_rate; | |
221 | if (!c) | |
222 | return ERR_PTR(-EINVAL); | |
223 | ||
093e00bb | 224 | lpwm->chip.dev = dev; |
d16a5aa9 MW |
225 | lpwm->chip.ops = &pwm_lpss_ops; |
226 | lpwm->chip.base = -1; | |
4e11f5ac | 227 | lpwm->chip.npwm = info->npwm; |
d16a5aa9 MW |
228 | |
229 | ret = pwmchip_add(&lpwm->chip); | |
230 | if (ret) { | |
093e00bb AC |
231 | dev_err(dev, "failed to add PWM chip: %d\n", ret); |
232 | return ERR_PTR(ret); | |
d16a5aa9 MW |
233 | } |
234 | ||
093e00bb | 235 | return lpwm; |
d16a5aa9 | 236 | } |
c558e39e | 237 | EXPORT_SYMBOL_GPL(pwm_lpss_probe); |
d16a5aa9 | 238 | |
c558e39e | 239 | int pwm_lpss_remove(struct pwm_lpss_chip *lpwm) |
d16a5aa9 | 240 | { |
42885551 HG |
241 | int i; |
242 | ||
243 | for (i = 0; i < lpwm->info->npwm; i++) { | |
244 | if (pwm_is_enabled(&lpwm->chip.pwms[i])) | |
245 | pm_runtime_put(lpwm->chip.dev); | |
246 | } | |
d16a5aa9 MW |
247 | return pwmchip_remove(&lpwm->chip); |
248 | } | |
c558e39e | 249 | EXPORT_SYMBOL_GPL(pwm_lpss_remove); |
d16a5aa9 | 250 | |
1d375b58 HG |
251 | int pwm_lpss_suspend(struct device *dev) |
252 | { | |
253 | struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev); | |
254 | int i; | |
255 | ||
256 | for (i = 0; i < lpwm->info->npwm; i++) | |
257 | lpwm->saved_ctrl[i] = readl(lpwm->regs + i * PWM_SIZE + PWM); | |
258 | ||
259 | return 0; | |
260 | } | |
261 | EXPORT_SYMBOL_GPL(pwm_lpss_suspend); | |
262 | ||
263 | int pwm_lpss_resume(struct device *dev) | |
264 | { | |
265 | struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev); | |
266 | int i; | |
267 | ||
268 | for (i = 0; i < lpwm->info->npwm; i++) | |
269 | writel(lpwm->saved_ctrl[i], lpwm->regs + i * PWM_SIZE + PWM); | |
270 | ||
271 | return 0; | |
272 | } | |
273 | EXPORT_SYMBOL_GPL(pwm_lpss_resume); | |
274 | ||
d16a5aa9 MW |
275 | MODULE_DESCRIPTION("PWM driver for Intel LPSS"); |
276 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); | |
277 | MODULE_LICENSE("GPL v2"); |