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caf065f8 JC |
1 | /* |
2 | * Mediatek Pulse Width Modulator driver | |
3 | * | |
4 | * Copyright (C) 2015 John Crispin <blogic@openwrt.org> | |
e7c197ec | 5 | * Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com> |
caf065f8 JC |
6 | * |
7 | * This file is licensed under the terms of the GNU General Public | |
8 | * License version 2. This program is licensed "as is" without any | |
9 | * warranty of any kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #include <linux/err.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/clk.h> | |
18 | #include <linux/of.h> | |
424268c7 | 19 | #include <linux/of_device.h> |
caf065f8 JC |
20 | #include <linux/platform_device.h> |
21 | #include <linux/pwm.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/types.h> | |
24 | ||
25 | /* PWM registers and bits definitions */ | |
26 | #define PWMCON 0x00 | |
27 | #define PWMHDUR 0x04 | |
28 | #define PWMLDUR 0x08 | |
29 | #define PWMGDUR 0x0c | |
30 | #define PWMWAVENUM 0x28 | |
31 | #define PWMDWIDTH 0x2c | |
b350333c | 32 | #define PWM45DWIDTH_FIXUP 0x30 |
caf065f8 | 33 | #define PWMTHRES 0x30 |
b350333c | 34 | #define PWM45THRES_FIXUP 0x34 |
caf065f8 | 35 | |
8bdb65dc ZM |
36 | #define PWM_CLK_DIV_MAX 7 |
37 | ||
caf065f8 JC |
38 | enum { |
39 | MTK_CLK_MAIN = 0, | |
40 | MTK_CLK_TOP, | |
41 | MTK_CLK_PWM1, | |
42 | MTK_CLK_PWM2, | |
43 | MTK_CLK_PWM3, | |
44 | MTK_CLK_PWM4, | |
45 | MTK_CLK_PWM5, | |
424268c7 ZM |
46 | MTK_CLK_PWM6, |
47 | MTK_CLK_PWM7, | |
48 | MTK_CLK_PWM8, | |
caf065f8 JC |
49 | MTK_CLK_MAX, |
50 | }; | |
51 | ||
424268c7 ZM |
52 | static const char * const mtk_pwm_clk_name[MTK_CLK_MAX] = { |
53 | "main", "top", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7", | |
54 | "pwm8" | |
55 | }; | |
56 | ||
57 | struct mtk_pwm_platform_data { | |
58 | unsigned int num_pwms; | |
b350333c | 59 | bool pwm45_fixup; |
caf065f8 JC |
60 | }; |
61 | ||
62 | /** | |
63 | * struct mtk_pwm_chip - struct representing PWM chip | |
64 | * @chip: linux PWM chip representation | |
65 | * @regs: base address of PWM chip | |
66 | * @clks: list of clocks | |
67 | */ | |
68 | struct mtk_pwm_chip { | |
69 | struct pwm_chip chip; | |
70 | void __iomem *regs; | |
71 | struct clk *clks[MTK_CLK_MAX]; | |
b350333c | 72 | const struct mtk_pwm_platform_data *soc; |
caf065f8 JC |
73 | }; |
74 | ||
424268c7 ZM |
75 | static const unsigned int mtk_pwm_reg_offset[] = { |
76 | 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 | |
77 | }; | |
78 | ||
caf065f8 JC |
79 | static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip) |
80 | { | |
81 | return container_of(chip, struct mtk_pwm_chip, chip); | |
82 | } | |
83 | ||
e7c197ec ZM |
84 | static int mtk_pwm_clk_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
85 | { | |
86 | struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); | |
87 | int ret; | |
88 | ||
89 | ret = clk_prepare_enable(pc->clks[MTK_CLK_TOP]); | |
90 | if (ret < 0) | |
91 | return ret; | |
92 | ||
93 | ret = clk_prepare_enable(pc->clks[MTK_CLK_MAIN]); | |
94 | if (ret < 0) | |
95 | goto disable_clk_top; | |
96 | ||
97 | ret = clk_prepare_enable(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]); | |
98 | if (ret < 0) | |
99 | goto disable_clk_main; | |
100 | ||
101 | return 0; | |
102 | ||
103 | disable_clk_main: | |
104 | clk_disable_unprepare(pc->clks[MTK_CLK_MAIN]); | |
105 | disable_clk_top: | |
106 | clk_disable_unprepare(pc->clks[MTK_CLK_TOP]); | |
107 | ||
108 | return ret; | |
109 | } | |
110 | ||
111 | static void mtk_pwm_clk_disable(struct pwm_chip *chip, struct pwm_device *pwm) | |
112 | { | |
113 | struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); | |
114 | ||
115 | clk_disable_unprepare(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]); | |
116 | clk_disable_unprepare(pc->clks[MTK_CLK_MAIN]); | |
117 | clk_disable_unprepare(pc->clks[MTK_CLK_TOP]); | |
118 | } | |
119 | ||
caf065f8 JC |
120 | static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num, |
121 | unsigned int offset) | |
122 | { | |
424268c7 | 123 | return readl(chip->regs + mtk_pwm_reg_offset[num] + offset); |
caf065f8 JC |
124 | } |
125 | ||
126 | static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip, | |
127 | unsigned int num, unsigned int offset, | |
128 | u32 value) | |
129 | { | |
424268c7 | 130 | writel(value, chip->regs + mtk_pwm_reg_offset[num] + offset); |
caf065f8 JC |
131 | } |
132 | ||
133 | static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, | |
134 | int duty_ns, int period_ns) | |
135 | { | |
136 | struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); | |
137 | struct clk *clk = pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]; | |
0d72414b | 138 | u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH, |
b350333c | 139 | reg_thres = PWMTHRES; |
0d72414b | 140 | u64 resolution; |
e7c197ec ZM |
141 | int ret; |
142 | ||
143 | ret = mtk_pwm_clk_enable(chip, pwm); | |
144 | if (ret < 0) | |
145 | return ret; | |
caf065f8 | 146 | |
0d72414b SW |
147 | /* Using resolution in picosecond gets accuracy higher */ |
148 | resolution = (u64)NSEC_PER_SEC * 1000; | |
149 | do_div(resolution, clk_get_rate(clk)); | |
caf065f8 | 150 | |
0d72414b SW |
151 | cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution); |
152 | while (cnt_period > 8191) { | |
caf065f8 JC |
153 | resolution *= 2; |
154 | clkdiv++; | |
0d72414b SW |
155 | cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, |
156 | resolution); | |
caf065f8 JC |
157 | } |
158 | ||
8bdb65dc ZM |
159 | if (clkdiv > PWM_CLK_DIV_MAX) { |
160 | mtk_pwm_clk_disable(chip, pwm); | |
161 | dev_err(chip->dev, "period %d not supported\n", period_ns); | |
caf065f8 | 162 | return -EINVAL; |
8bdb65dc | 163 | } |
caf065f8 | 164 | |
b350333c SW |
165 | if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) { |
166 | /* | |
167 | * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES | |
168 | * from the other PWMs on MT7623. | |
169 | */ | |
170 | reg_width = PWM45DWIDTH_FIXUP; | |
171 | reg_thres = PWM45THRES_FIXUP; | |
172 | } | |
173 | ||
0d72414b | 174 | cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution); |
cd30798a | 175 | mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); |
0d72414b SW |
176 | mtk_pwm_writel(pc, pwm->hwpwm, reg_width, cnt_period); |
177 | mtk_pwm_writel(pc, pwm->hwpwm, reg_thres, cnt_duty); | |
caf065f8 | 178 | |
e7c197ec ZM |
179 | mtk_pwm_clk_disable(chip, pwm); |
180 | ||
caf065f8 JC |
181 | return 0; |
182 | } | |
183 | ||
184 | static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) | |
185 | { | |
186 | struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); | |
187 | u32 value; | |
188 | int ret; | |
189 | ||
e7c197ec | 190 | ret = mtk_pwm_clk_enable(chip, pwm); |
caf065f8 JC |
191 | if (ret < 0) |
192 | return ret; | |
193 | ||
194 | value = readl(pc->regs); | |
195 | value |= BIT(pwm->hwpwm); | |
196 | writel(value, pc->regs); | |
197 | ||
198 | return 0; | |
199 | } | |
200 | ||
201 | static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) | |
202 | { | |
203 | struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); | |
204 | u32 value; | |
205 | ||
206 | value = readl(pc->regs); | |
207 | value &= ~BIT(pwm->hwpwm); | |
208 | writel(value, pc->regs); | |
209 | ||
e7c197ec | 210 | mtk_pwm_clk_disable(chip, pwm); |
caf065f8 JC |
211 | } |
212 | ||
213 | static const struct pwm_ops mtk_pwm_ops = { | |
214 | .config = mtk_pwm_config, | |
215 | .enable = mtk_pwm_enable, | |
216 | .disable = mtk_pwm_disable, | |
217 | .owner = THIS_MODULE, | |
218 | }; | |
219 | ||
220 | static int mtk_pwm_probe(struct platform_device *pdev) | |
221 | { | |
424268c7 | 222 | const struct mtk_pwm_platform_data *data; |
caf065f8 JC |
223 | struct mtk_pwm_chip *pc; |
224 | struct resource *res; | |
225 | unsigned int i; | |
226 | int ret; | |
227 | ||
228 | pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); | |
229 | if (!pc) | |
230 | return -ENOMEM; | |
231 | ||
424268c7 ZM |
232 | data = of_device_get_match_data(&pdev->dev); |
233 | if (data == NULL) | |
234 | return -EINVAL; | |
b350333c | 235 | pc->soc = data; |
424268c7 | 236 | |
caf065f8 JC |
237 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
238 | pc->regs = devm_ioremap_resource(&pdev->dev, res); | |
239 | if (IS_ERR(pc->regs)) | |
240 | return PTR_ERR(pc->regs); | |
241 | ||
424268c7 | 242 | for (i = 0; i < data->num_pwms + 2; i++) { |
caf065f8 | 243 | pc->clks[i] = devm_clk_get(&pdev->dev, mtk_pwm_clk_name[i]); |
424268c7 ZM |
244 | if (IS_ERR(pc->clks[i])) { |
245 | dev_err(&pdev->dev, "clock: %s fail: %ld\n", | |
246 | mtk_pwm_clk_name[i], PTR_ERR(pc->clks[i])); | |
caf065f8 | 247 | return PTR_ERR(pc->clks[i]); |
424268c7 | 248 | } |
caf065f8 JC |
249 | } |
250 | ||
caf065f8 JC |
251 | platform_set_drvdata(pdev, pc); |
252 | ||
253 | pc->chip.dev = &pdev->dev; | |
254 | pc->chip.ops = &mtk_pwm_ops; | |
255 | pc->chip.base = -1; | |
424268c7 | 256 | pc->chip.npwm = data->num_pwms; |
caf065f8 JC |
257 | |
258 | ret = pwmchip_add(&pc->chip); | |
259 | if (ret < 0) { | |
260 | dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); | |
e7c197ec | 261 | return ret; |
caf065f8 JC |
262 | } |
263 | ||
264 | return 0; | |
caf065f8 JC |
265 | } |
266 | ||
267 | static int mtk_pwm_remove(struct platform_device *pdev) | |
268 | { | |
269 | struct mtk_pwm_chip *pc = platform_get_drvdata(pdev); | |
caf065f8 JC |
270 | |
271 | return pwmchip_remove(&pc->chip); | |
272 | } | |
273 | ||
424268c7 ZM |
274 | static const struct mtk_pwm_platform_data mt2712_pwm_data = { |
275 | .num_pwms = 8, | |
b350333c | 276 | .pwm45_fixup = false, |
424268c7 ZM |
277 | }; |
278 | ||
279 | static const struct mtk_pwm_platform_data mt7622_pwm_data = { | |
280 | .num_pwms = 6, | |
b350333c | 281 | .pwm45_fixup = false, |
424268c7 ZM |
282 | }; |
283 | ||
284 | static const struct mtk_pwm_platform_data mt7623_pwm_data = { | |
285 | .num_pwms = 5, | |
b350333c | 286 | .pwm45_fixup = true, |
424268c7 ZM |
287 | }; |
288 | ||
caf065f8 | 289 | static const struct of_device_id mtk_pwm_of_match[] = { |
424268c7 ZM |
290 | { .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data }, |
291 | { .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data }, | |
292 | { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, | |
293 | { }, | |
caf065f8 JC |
294 | }; |
295 | MODULE_DEVICE_TABLE(of, mtk_pwm_of_match); | |
296 | ||
297 | static struct platform_driver mtk_pwm_driver = { | |
298 | .driver = { | |
299 | .name = "mtk-pwm", | |
caf065f8 JC |
300 | .of_match_table = mtk_pwm_of_match, |
301 | }, | |
302 | .probe = mtk_pwm_probe, | |
303 | .remove = mtk_pwm_remove, | |
304 | }; | |
305 | module_platform_driver(mtk_pwm_driver); | |
306 | ||
307 | MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); | |
308 | MODULE_ALIAS("platform:mtk-pwm"); | |
309 | MODULE_LICENSE("GPL"); |