[mirror_ubuntu-artful-kernel.git] / drivers / pwm / pwm-mxs.c

/*
 * Copyright 2012 Freescale Semiconductor, Inc.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>
#include <linux/stmp_device.h>

#define SET	0x4
#define CLR	0x8
#define TOG	0xc

#define PWM_CTRL		0x0
#define PWM_ACTIVE0		0x10
#define PWM_PERIOD0		0x20
#define  PERIOD_PERIOD(p)	((p) & 0xffff)
#define  PERIOD_PERIOD_MAX	0x10000
#define  PERIOD_ACTIVE_HIGH	(3 << 16)
#define  PERIOD_INACTIVE_LOW	(2 << 18)
#define  PERIOD_CDIV(div)	(((div) & 0x7) << 20)
#define  PERIOD_CDIV_MAX	8

struct mxs_pwm_chip {
	struct pwm_chip chip;
	struct device *dev;
	struct clk *clk;
	void __iomem *base;
};

#define to_mxs_pwm_chip(_chip) container_of(_chip, struct mxs_pwm_chip, chip)

static int mxs_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
			  int duty_ns, int period_ns)
{
	struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
	int ret, div = 0;
	unsigned int period_cycles, duty_cycles;
	unsigned long rate;
	unsigned long long c;

	rate = clk_get_rate(mxs->clk);
	while (1) {
		c = rate / (1 << div);
		c = c * period_ns;
		do_div(c, 1000000000);
		if (c < PERIOD_PERIOD_MAX)
			break;
		div++;
		if (div > PERIOD_CDIV_MAX)
			return -EINVAL;
	}

	period_cycles = c;
	c *= duty_ns;
	do_div(c, period_ns);
	duty_cycles = c;

	/*
	 * If the PWM channel is disabled, make sure to turn on the clock
	 * before writing the register. Otherwise, keep it enabled.
	 */
	if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
		ret = clk_prepare_enable(mxs->clk);
		if (ret)
			return ret;
	}

	writel(duty_cycles << 16,
			mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20);
	writel(PERIOD_PERIOD(period_cycles) | PERIOD_ACTIVE_HIGH |
	       PERIOD_INACTIVE_LOW | PERIOD_CDIV(div),
			mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20);

	/*
	 * If the PWM is not enabled, turn the clock off again to save power.
	 */
	if (!test_bit(PWMF_ENABLED, &pwm->flags))
		clk_disable_unprepare(mxs->clk);

	return 0;
}

static int mxs_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
	int ret;

	ret = clk_prepare_enable(mxs->clk);
	if (ret)
		return ret;

	writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET);

	return 0;
}

static void mxs_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);

	writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR);

	clk_disable_unprepare(mxs->clk);
}

static const struct pwm_ops mxs_pwm_ops = {
	.config = mxs_pwm_config,
	.enable = mxs_pwm_enable,
	.disable = mxs_pwm_disable,
	.owner = THIS_MODULE,
};

static int mxs_pwm_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct mxs_pwm_chip *mxs;
	struct resource *res;
	struct pinctrl *pinctrl;
	int ret;

	mxs = devm_kzalloc(&pdev->dev, sizeof(*mxs), GFP_KERNEL);
	if (!mxs)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	mxs->base = devm_request_and_ioremap(&pdev->dev, res);
	if (!mxs->base)
		return -EADDRNOTAVAIL;

	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
	if (IS_ERR(pinctrl))
		return PTR_ERR(pinctrl);

	mxs->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(mxs->clk))
		return PTR_ERR(mxs->clk);

	mxs->chip.dev = &pdev->dev;
	mxs->chip.ops = &mxs_pwm_ops;
	mxs->chip.base = -1;
	ret = of_property_read_u32(np, "fsl,pwm-number", &mxs->chip.npwm);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to get pwm number: %d\n", ret);
		return ret;
	}

	ret = pwmchip_add(&mxs->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to add pwm chip %d\n", ret);
		return ret;
	}

	mxs->dev = &pdev->dev;
	platform_set_drvdata(pdev, mxs);

	stmp_reset_block(mxs->base);

	return 0;
}

static int mxs_pwm_remove(struct platform_device *pdev)
{
	struct mxs_pwm_chip *mxs = platform_get_drvdata(pdev);

	return pwmchip_remove(&mxs->chip);
}

static struct of_device_id mxs_pwm_dt_ids[] = {
	{ .compatible = "fsl,imx23-pwm", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxs_pwm_dt_ids);

static struct platform_driver mxs_pwm_driver = {
	.driver = {
		.name = "mxs-pwm",
		.of_match_table = of_match_ptr(mxs_pwm_dt_ids),
	},
	.probe = mxs_pwm_probe,
	.remove = mxs_pwm_remove,
};
module_platform_driver(mxs_pwm_driver);

MODULE_ALIAS("platform:mxs-pwm");
MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
MODULE_DESCRIPTION("Freescale MXS PWM Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
4dce82c1 SG	1	/*
	2	* Copyright 2012 Freescale Semiconductor, Inc.
	3	*
	4	* The code contained herein is licensed under the GNU General Public
	5	* License. You may obtain a copy of the GNU General Public License
	6	* Version 2 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/gpl-license.html
	9	* http://www.gnu.org/copyleft/gpl.html
	10	*/
	11
	12	#include <linux/clk.h>
	13	#include <linux/err.h>
	14	#include <linux/io.h>
	15	#include <linux/kernel.h>
	16	#include <linux/module.h>
	17	#include <linux/of.h>
	18	#include <linux/of_address.h>
1112fe88	19	#include <linux/pinctrl/consumer.h>
4dce82c1 SG	20	#include <linux/platform_device.h>
	21	#include <linux/pwm.h>
	22	#include <linux/slab.h>
01bf32e9	23	#include <linux/stmp_device.h>
4dce82c1 SG	24
	25	#define SET 0x4
	26	#define CLR 0x8
	27	#define TOG 0xc
	28
	29	#define PWM_CTRL 0x0
	30	#define PWM_ACTIVE0 0x10
	31	#define PWM_PERIOD0 0x20
	32	#define PERIOD_PERIOD(p) ((p) & 0xffff)
	33	#define PERIOD_PERIOD_MAX 0x10000
	34	#define PERIOD_ACTIVE_HIGH (3 << 16)
	35	#define PERIOD_INACTIVE_LOW (2 << 18)
	36	#define PERIOD_CDIV(div) (((div) & 0x7) << 20)
	37	#define PERIOD_CDIV_MAX 8
	38
	39	struct mxs_pwm_chip {
	40	struct pwm_chip chip;
	41	struct device *dev;
	42	struct clk *clk;
	43	void __iomem *base;
	44	};
	45
	46	#define to_mxs_pwm_chip(_chip) container_of(_chip, struct mxs_pwm_chip, chip)
	47
	48	static int mxs_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
	49	int duty_ns, int period_ns)
	50	{
	51	struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
	52	int ret, div = 0;
	53	unsigned int period_cycles, duty_cycles;
	54	unsigned long rate;
	55	unsigned long long c;
	56
	57	rate = clk_get_rate(mxs->clk);
	58	while (1) {
	59	c = rate / (1 << div);
	60	c = c * period_ns;
	61	do_div(c, 1000000000);
	62	if (c < PERIOD_PERIOD_MAX)
	63	break;
	64	div++;
	65	if (div > PERIOD_CDIV_MAX)
	66	return -EINVAL;
	67	}
	68
	69	period_cycles = c;
	70	c *= duty_ns;
	71	do_div(c, period_ns);
	72	duty_cycles = c;
	73
	74	/*
	75	* If the PWM channel is disabled, make sure to turn on the clock
	76	* before writing the register. Otherwise, keep it enabled.
	77	*/
	78	if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
	79	ret = clk_prepare_enable(mxs->clk);
	80	if (ret)
	81	return ret;
	82	}
	83
	84	writel(duty_cycles << 16,
	85	mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20);
	86	writel(PERIOD_PERIOD(period_cycles) \| PERIOD_ACTIVE_HIGH \|
	87	PERIOD_INACTIVE_LOW \| PERIOD_CDIV(div),
88	mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20);
89
90	/*
91	* If the PWM is not enabled, turn the clock off again to save power.
92	*/
93	if (!test_bit(PWMF_ENABLED, &pwm->flags))
94	clk_disable_unprepare(mxs->clk);
95
96	return 0;
97	}
98
99	static int mxs_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
100	{
101	struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
102	int ret;
103
104	ret = clk_prepare_enable(mxs->clk);
105	if (ret)
106	return ret;
107
108	writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET);
109
110	return 0;
111	}
112
113	static void mxs_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
114	{
115	struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
116
117	writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR);
118
119	clk_disable_unprepare(mxs->clk);
120	}
121
122	static const struct pwm_ops mxs_pwm_ops = {
123	.config = mxs_pwm_config,
124	.enable = mxs_pwm_enable,
125	.disable = mxs_pwm_disable,
126	.owner = THIS_MODULE,
127	};
128
129	static int mxs_pwm_probe(struct platform_device *pdev)
130	{
131	struct device_node *np = pdev->dev.of_node;
132	struct mxs_pwm_chip *mxs;
22d260bd	133	struct resource *res;
1112fe88	134	struct pinctrl *pinctrl;
4dce82c1 SG	135	int ret;
	136
	137	mxs = devm_kzalloc(&pdev->dev, sizeof(*mxs), GFP_KERNEL);
	138	if (!mxs)
	139	return -ENOMEM;
	140
22d260bd SG	141	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
22d260bd SG	142	mxs->base = devm_request_and_ioremap(&pdev->dev, res);
4dce82c1 SG	143	if (!mxs->base)
	144	return -EADDRNOTAVAIL;
	145
1112fe88 SG	146	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
	147	if (IS_ERR(pinctrl))
	148	return PTR_ERR(pinctrl);
	149
22d260bd SG	150	mxs->clk = devm_clk_get(&pdev->dev, NULL);
	151	if (IS_ERR(mxs->clk))
	152	return PTR_ERR(mxs->clk);
4dce82c1 SG	153
	154	mxs->chip.dev = &pdev->dev;
	155	mxs->chip.ops = &mxs_pwm_ops;
	156	mxs->chip.base = -1;
	157	ret = of_property_read_u32(np, "fsl,pwm-number", &mxs->chip.npwm);
	158	if (ret < 0) {
	159	dev_err(&pdev->dev, "failed to get pwm number: %d\n", ret);
22d260bd	160	return ret;
4dce82c1 SG	161	}
	162
	163	ret = pwmchip_add(&mxs->chip);
	164	if (ret < 0) {
	165	dev_err(&pdev->dev, "failed to add pwm chip %d\n", ret);
22d260bd	166	return ret;
4dce82c1 SG	167	}
	168
	169	mxs->dev = &pdev->dev;
	170	platform_set_drvdata(pdev, mxs);
	171
01bf32e9	172	stmp_reset_block(mxs->base);
4dce82c1 SG	173
4dce82c1 SG	174	return 0;
4dce82c1 SG	175	}
4dce82c1 SG	176
77f37917	177	static int mxs_pwm_remove(struct platform_device *pdev)
4dce82c1 SG	178	{
	179	struct mxs_pwm_chip *mxs = platform_get_drvdata(pdev);
	180
457fd768	181	return pwmchip_remove(&mxs->chip);
4dce82c1 SG	182	}
	183
	184	static struct of_device_id mxs_pwm_dt_ids[] = {
071407ee	185	{ .compatible = "fsl,imx23-pwm", },
4dce82c1 SG	186	{ /* sentinel */ }
	187	};
	188	MODULE_DEVICE_TABLE(of, mxs_pwm_dt_ids);
	189
	190	static struct platform_driver mxs_pwm_driver = {
	191	.driver = {
	192	.name = "mxs-pwm",
	193	.of_match_table = of_match_ptr(mxs_pwm_dt_ids),
	194	},
	195	.probe = mxs_pwm_probe,
fd109112	196	.remove = mxs_pwm_remove,
4dce82c1 SG	197	};
	198	module_platform_driver(mxs_pwm_driver);
	199
	200	MODULE_ALIAS("platform:mxs-pwm");
	201	MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
	202	MODULE_DESCRIPTION("Freescale MXS PWM Driver");
	203	MODULE_LICENSE("GPL v2");