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Commit | Line | Data |
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75540c1a | 1 | /* |
45b301d2 | 2 | * drivers/pwm/pwm-pxa.c |
75540c1a | 3 | * |
4 | * simple driver for PWM (Pulse Width Modulator) controller | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * 2008-02-13 initial version | |
11 | * eric miao <eric.miao@marvell.com> | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/platform_device.h> | |
5a0e3ad6 | 17 | #include <linux/slab.h> |
75540c1a | 18 | #include <linux/err.h> |
19 | #include <linux/clk.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/pwm.h> | |
22 | ||
23 | #include <asm/div64.h> | |
75540c1a | 24 | |
3d2a98cd | 25 | #define HAS_SECONDARY_PWM 0x10 |
a757ad8b | 26 | #define PWM_ID_BASE(d) ((d) & 0xf) |
3d2a98cd EM |
27 | |
28 | static const struct platform_device_id pwm_id_table[] = { | |
29 | /* PWM has_secondary_pwm? */ | |
30 | { "pxa25x-pwm", 0 }, | |
a757ad8b | 31 | { "pxa27x-pwm", 0 | HAS_SECONDARY_PWM }, |
a27ba768 EM |
32 | { "pxa168-pwm", 1 }, |
33 | { "pxa910-pwm", 1 }, | |
3d2a98cd EM |
34 | { }, |
35 | }; | |
36 | MODULE_DEVICE_TABLE(platform, pwm_id_table); | |
37 | ||
75540c1a | 38 | /* PWM registers and bits definitions */ |
39 | #define PWMCR (0x00) | |
40 | #define PWMDCR (0x04) | |
41 | #define PWMPCR (0x08) | |
42 | ||
43 | #define PWMCR_SD (1 << 6) | |
44 | #define PWMDCR_FD (1 << 10) | |
45 | ||
17b2b478 TR |
46 | struct pxa_pwm_chip { |
47 | struct pwm_chip chip; | |
48 | struct device *dev; | |
75540c1a | 49 | |
75540c1a | 50 | struct clk *clk; |
c860d701 | 51 | int clk_enabled; |
75540c1a | 52 | void __iomem *mmio_base; |
75540c1a | 53 | }; |
54 | ||
17b2b478 TR |
55 | static inline struct pxa_pwm_chip *to_pxa_pwm_chip(struct pwm_chip *chip) |
56 | { | |
57 | return container_of(chip, struct pxa_pwm_chip, chip); | |
58 | } | |
59 | ||
75540c1a | 60 | /* |
61 | * period_ns = 10^9 * (PRESCALE + 1) * (PV + 1) / PWM_CLK_RATE | |
62 | * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE | |
63 | */ | |
17b2b478 TR |
64 | static int pxa_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, |
65 | int duty_ns, int period_ns) | |
75540c1a | 66 | { |
17b2b478 | 67 | struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip); |
75540c1a | 68 | unsigned long long c; |
69 | unsigned long period_cycles, prescale, pv, dc; | |
17b2b478 TR |
70 | unsigned long offset; |
71 | int rc; | |
75540c1a | 72 | |
17b2b478 TR |
73 | offset = pwm->hwpwm ? 0x10 : 0; |
74 | ||
75 | c = clk_get_rate(pc->clk); | |
75540c1a | 76 | c = c * period_ns; |
77 | do_div(c, 1000000000); | |
78 | period_cycles = c; | |
79 | ||
71a35d75 | 80 | if (period_cycles < 1) |
75540c1a | 81 | period_cycles = 1; |
82 | prescale = (period_cycles - 1) / 1024; | |
83 | pv = period_cycles / (prescale + 1) - 1; | |
84 | ||
85 | if (prescale > 63) | |
86 | return -EINVAL; | |
87 | ||
88 | if (duty_ns == period_ns) | |
89 | dc = PWMDCR_FD; | |
90 | else | |
91 | dc = (pv + 1) * duty_ns / period_ns; | |
92 | ||
93 | /* NOTE: the clock to PWM has to be enabled first | |
94 | * before writing to the registers | |
95 | */ | |
17b2b478 TR |
96 | rc = clk_prepare_enable(pc->clk); |
97 | if (rc < 0) | |
98 | return rc; | |
99 | ||
100 | writel(prescale, pc->mmio_base + offset + PWMCR); | |
101 | writel(dc, pc->mmio_base + offset + PWMDCR); | |
102 | writel(pv, pc->mmio_base + offset + PWMPCR); | |
75540c1a | 103 | |
17b2b478 | 104 | clk_disable_unprepare(pc->clk); |
75540c1a | 105 | return 0; |
106 | } | |
75540c1a | 107 | |
17b2b478 | 108 | static int pxa_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
75540c1a | 109 | { |
17b2b478 | 110 | struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip); |
c860d701 RJ |
111 | int rc = 0; |
112 | ||
17b2b478 TR |
113 | if (!pc->clk_enabled) { |
114 | rc = clk_prepare_enable(pc->clk); | |
c860d701 | 115 | if (!rc) |
17b2b478 | 116 | pc->clk_enabled++; |
c860d701 RJ |
117 | } |
118 | return rc; | |
75540c1a | 119 | } |
75540c1a | 120 | |
17b2b478 | 121 | static void pxa_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) |
75540c1a | 122 | { |
17b2b478 | 123 | struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip); |
75540c1a | 124 | |
17b2b478 TR |
125 | if (pc->clk_enabled) { |
126 | clk_disable_unprepare(pc->clk); | |
127 | pc->clk_enabled--; | |
75540c1a | 128 | } |
75540c1a | 129 | } |
75540c1a | 130 | |
17b2b478 TR |
131 | static struct pwm_ops pxa_pwm_ops = { |
132 | .config = pxa_pwm_config, | |
133 | .enable = pxa_pwm_enable, | |
134 | .disable = pxa_pwm_disable, | |
135 | .owner = THIS_MODULE, | |
136 | }; | |
75540c1a | 137 | |
3e9fe83d | 138 | static int pwm_probe(struct platform_device *pdev) |
75540c1a | 139 | { |
b3282ab1 | 140 | const struct platform_device_id *id = platform_get_device_id(pdev); |
17b2b478 | 141 | struct pxa_pwm_chip *pwm; |
75540c1a | 142 | struct resource *r; |
143 | int ret = 0; | |
144 | ||
45b301d2 | 145 | pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL); |
75540c1a | 146 | if (pwm == NULL) { |
147 | dev_err(&pdev->dev, "failed to allocate memory\n"); | |
3d2a98cd | 148 | return -ENOMEM; |
75540c1a | 149 | } |
150 | ||
45b301d2 AL |
151 | pwm->clk = devm_clk_get(&pdev->dev, NULL); |
152 | if (IS_ERR(pwm->clk)) | |
153 | return PTR_ERR(pwm->clk); | |
154 | ||
c860d701 | 155 | pwm->clk_enabled = 0; |
75540c1a | 156 | |
17b2b478 TR |
157 | pwm->chip.dev = &pdev->dev; |
158 | pwm->chip.ops = &pxa_pwm_ops; | |
159 | pwm->chip.base = -1; | |
160 | pwm->chip.npwm = (id->driver_data & HAS_SECONDARY_PWM) ? 2 : 1; | |
75540c1a | 161 | |
75540c1a | 162 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
163 | if (r == NULL) { | |
164 | dev_err(&pdev->dev, "no memory resource defined\n"); | |
45b301d2 | 165 | return -ENODEV; |
75540c1a | 166 | } |
167 | ||
6d4294d1 TR |
168 | pwm->mmio_base = devm_ioremap_resource(&pdev->dev, r); |
169 | if (IS_ERR(pwm->mmio_base)) | |
170 | return PTR_ERR(pwm->mmio_base); | |
75540c1a | 171 | |
17b2b478 TR |
172 | ret = pwmchip_add(&pwm->chip); |
173 | if (ret < 0) { | |
174 | dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); | |
175 | return ret; | |
3d2a98cd EM |
176 | } |
177 | ||
75540c1a | 178 | platform_set_drvdata(pdev, pwm); |
3d2a98cd | 179 | return 0; |
75540c1a | 180 | } |
181 | ||
77f37917 | 182 | static int pwm_remove(struct platform_device *pdev) |
75540c1a | 183 | { |
17b2b478 | 184 | struct pxa_pwm_chip *chip; |
75540c1a | 185 | |
17b2b478 TR |
186 | chip = platform_get_drvdata(pdev); |
187 | if (chip == NULL) | |
75540c1a | 188 | return -ENODEV; |
189 | ||
abeaf755 | 190 | return pwmchip_remove(&chip->chip); |
75540c1a | 191 | } |
192 | ||
3d2a98cd | 193 | static struct platform_driver pwm_driver = { |
75540c1a | 194 | .driver = { |
195 | .name = "pxa25x-pwm", | |
3d2a98cd | 196 | .owner = THIS_MODULE, |
75540c1a | 197 | }, |
3d2a98cd | 198 | .probe = pwm_probe, |
fd109112 | 199 | .remove = pwm_remove, |
3d2a98cd | 200 | .id_table = pwm_id_table, |
75540c1a | 201 | }; |
202 | ||
203 | static int __init pwm_init(void) | |
204 | { | |
3d2a98cd | 205 | return platform_driver_register(&pwm_driver); |
75540c1a | 206 | } |
207 | arch_initcall(pwm_init); | |
208 | ||
209 | static void __exit pwm_exit(void) | |
210 | { | |
3d2a98cd | 211 | platform_driver_unregister(&pwm_driver); |
75540c1a | 212 | } |
213 | module_exit(pwm_exit); | |
b5f0228a GL |
214 | |
215 | MODULE_LICENSE("GPL v2"); |