[mirror_ubuntu-bionic-kernel.git] / drivers / pwm / pwm-rockchip.c

/*
 * PWM driver for Rockchip SoCs
 *
 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
 * Copyright (C) 2014 ROCKCHIP, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/time.h>

#define PWM_CTRL_TIMER_EN	(1 << 0)
#define PWM_CTRL_OUTPUT_EN	(1 << 3)

#define PWM_ENABLE		(1 << 0)
#define PWM_CONTINUOUS		(1 << 1)
#define PWM_DUTY_POSITIVE	(1 << 3)
#define PWM_DUTY_NEGATIVE	(0 << 3)
#define PWM_INACTIVE_NEGATIVE	(0 << 4)
#define PWM_INACTIVE_POSITIVE	(1 << 4)
#define PWM_OUTPUT_LEFT		(0 << 5)
#define PWM_LP_DISABLE		(0 << 8)

struct rockchip_pwm_chip {
	struct pwm_chip chip;
	struct clk *clk;
	const struct rockchip_pwm_data *data;
	void __iomem *base;
};

struct rockchip_pwm_regs {
	unsigned long duty;
	unsigned long period;
	unsigned long cntr;
	unsigned long ctrl;
};

struct rockchip_pwm_data {
	struct rockchip_pwm_regs regs;
	unsigned int prescaler;
	const struct pwm_ops *ops;

	void (*set_enable)(struct pwm_chip *chip,
			   struct pwm_device *pwm, bool enable);
};

static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c)
{
	return container_of(c, struct rockchip_pwm_chip, chip);
}

static void rockchip_pwm_set_enable_v1(struct pwm_chip *chip,
				       struct pwm_device *pwm, bool enable)
{
	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
	u32 enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN;
	u32 val;

	val = readl_relaxed(pc->base + pc->data->regs.ctrl);

	if (enable)
		val |= enable_conf;
	else
		val &= ~enable_conf;

	writel_relaxed(val, pc->base + pc->data->regs.ctrl);
}

static void rockchip_pwm_set_enable_v2(struct pwm_chip *chip,
				       struct pwm_device *pwm, bool enable)
{
	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
	u32 enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
			  PWM_CONTINUOUS;
	u32 val;

	if (pwm_get_polarity(pwm) == PWM_POLARITY_INVERSED)
		enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE;
	else
		enable_conf |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE;

	val = readl_relaxed(pc->base + pc->data->regs.ctrl);

	if (enable)
		val |= enable_conf;
	else
		val &= ~enable_conf;

	writel_relaxed(val, pc->base + pc->data->regs.ctrl);
}

static int rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
			       int duty_ns, int period_ns)
{
	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
	unsigned long period, duty;
	u64 clk_rate, div;
	int ret;

	clk_rate = clk_get_rate(pc->clk);

	/*
	 * Since period and duty cycle registers have a width of 32
	 * bits, every possible input period can be obtained using the
	 * default prescaler value for all practical clock rate values.
	 */
	div = clk_rate * period_ns;
	period = DIV_ROUND_CLOSEST_ULL(div,
				       pc->data->prescaler * NSEC_PER_SEC);

	div = clk_rate * duty_ns;
	duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);

	ret = clk_enable(pc->clk);
	if (ret)
		return ret;

	writel(period, pc->base + pc->data->regs.period);
	writel(duty, pc->base + pc->data->regs.duty);
	writel(0, pc->base + pc->data->regs.cntr);

	clk_disable(pc->clk);

	return 0;
}

static int rockchip_pwm_set_polarity(struct pwm_chip *chip,
				     struct pwm_device *pwm,
				     enum pwm_polarity polarity)
{
	/*
	 * No action needed here because pwm->polarity will be set by the core
	 * and the core will only change polarity when the PWM is not enabled.
	 * We'll handle things in set_enable().
	 */

	return 0;
}

static int rockchip_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
	int ret;

	ret = clk_enable(pc->clk);
	if (ret)
		return ret;

	pc->data->set_enable(chip, pwm, true);

	return 0;
}

static void rockchip_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);

	pc->data->set_enable(chip, pwm, false);

	clk_disable(pc->clk);
}

static const struct pwm_ops rockchip_pwm_ops_v1 = {
	.config = rockchip_pwm_config,
	.enable = rockchip_pwm_enable,
	.disable = rockchip_pwm_disable,
	.owner = THIS_MODULE,
};

static const struct pwm_ops rockchip_pwm_ops_v2 = {
	.config = rockchip_pwm_config,
	.set_polarity = rockchip_pwm_set_polarity,
	.enable = rockchip_pwm_enable,
	.disable = rockchip_pwm_disable,
	.owner = THIS_MODULE,
};

static const struct rockchip_pwm_data pwm_data_v1 = {
	.regs = {
		.duty = 0x04,
		.period = 0x08,
		.cntr = 0x00,
		.ctrl = 0x0c,
	},
	.prescaler = 2,
	.ops = &rockchip_pwm_ops_v1,
	.set_enable = rockchip_pwm_set_enable_v1,
};

static const struct rockchip_pwm_data pwm_data_v2 = {
	.regs = {
		.duty = 0x08,
		.period = 0x04,
		.cntr = 0x00,
		.ctrl = 0x0c,
	},
	.prescaler = 1,
	.ops = &rockchip_pwm_ops_v2,
	.set_enable = rockchip_pwm_set_enable_v2,
};

static const struct rockchip_pwm_data pwm_data_vop = {
	.regs = {
		.duty = 0x08,
		.period = 0x04,
		.cntr = 0x0c,
		.ctrl = 0x00,
	},
	.prescaler = 1,
	.ops = &rockchip_pwm_ops_v2,
	.set_enable = rockchip_pwm_set_enable_v2,
};

static const struct of_device_id rockchip_pwm_dt_ids[] = {
	{ .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
	{ .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
	{ .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);

static int rockchip_pwm_probe(struct platform_device *pdev)
{
	const struct of_device_id *id;
	struct rockchip_pwm_chip *pc;
	struct resource *r;
	int ret;

	id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
	if (!id)
		return -EINVAL;

	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
	if (!pc)
		return -ENOMEM;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	pc->base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(pc->base))
		return PTR_ERR(pc->base);

	pc->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(pc->clk))
		return PTR_ERR(pc->clk);

	ret = clk_prepare(pc->clk);
	if (ret)
		return ret;

	platform_set_drvdata(pdev, pc);

	pc->data = id->data;
	pc->chip.dev = &pdev->dev;
	pc->chip.ops = pc->data->ops;
	pc->chip.base = -1;
	pc->chip.npwm = 1;

	if (pc->data->ops->set_polarity) {
		pc->chip.of_xlate = of_pwm_xlate_with_flags;
		pc->chip.of_pwm_n_cells = 3;
	}

	ret = pwmchip_add(&pc->chip);
	if (ret < 0) {
		clk_unprepare(pc->clk);
		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
	}

	return ret;
}

static int rockchip_pwm_remove(struct platform_device *pdev)
{
	struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);

	clk_unprepare(pc->clk);

	return pwmchip_remove(&pc->chip);
}

static struct platform_driver rockchip_pwm_driver = {
	.driver = {
		.name = "rockchip-pwm",
		.of_match_table = rockchip_pwm_dt_ids,
	},
	.probe = rockchip_pwm_probe,
	.remove = rockchip_pwm_remove,
};
module_platform_driver(rockchip_pwm_driver);

MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
MODULE_DESCRIPTION("Rockchip SoC PWM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
101353c8 BG	1	/*
	2	* PWM driver for Rockchip SoCs
	3	*
	4	* Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
f6306299	5	* Copyright (C) 2014 ROCKCHIP, Inc.
101353c8 BG	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* version 2 as published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/clk.h>
	13	#include <linux/io.h>
	14	#include <linux/module.h>
	15	#include <linux/of.h>
f6306299	16	#include <linux/of_device.h>
101353c8 BG	17	#include <linux/platform_device.h>
	18	#include <linux/pwm.h>
	19	#include <linux/time.h>
	20
101353c8 BG	21	#define PWM_CTRL_TIMER_EN (1 << 0)
	22	#define PWM_CTRL_OUTPUT_EN (1 << 3)
	23
f6306299 CW	24	#define PWM_ENABLE (1 << 0)
	25	#define PWM_CONTINUOUS (1 << 1)
	26	#define PWM_DUTY_POSITIVE (1 << 3)
7264354c	27	#define PWM_DUTY_NEGATIVE (0 << 3)
f6306299	28	#define PWM_INACTIVE_NEGATIVE (0 << 4)
7264354c	29	#define PWM_INACTIVE_POSITIVE (1 << 4)
f6306299 CW	30	#define PWM_OUTPUT_LEFT (0 << 5)
f6306299 CW	31	#define PWM_LP_DISABLE (0 << 8)
101353c8 BG	32
	33	struct rockchip_pwm_chip {
	34	struct pwm_chip chip;
	35	struct clk *clk;
f6306299	36	const struct rockchip_pwm_data *data;
101353c8 BG	37	void __iomem *base;
	38	};
	39
f6306299 CW	40	struct rockchip_pwm_regs {
	41	unsigned long duty;
	42	unsigned long period;
	43	unsigned long cntr;
	44	unsigned long ctrl;
	45	};
	46
	47	struct rockchip_pwm_data {
	48	struct rockchip_pwm_regs regs;
	49	unsigned int prescaler;
7264354c	50	const struct pwm_ops *ops;
f6306299	51
7264354c DA	52	void (set_enable)(struct pwm_chip chip,
7264354c DA	53	struct pwm_device *pwm, bool enable);
f6306299 CW	54	};
f6306299 CW	55
101353c8 BG	56	static inline struct rockchip_pwm_chip to_rockchip_pwm_chip(struct pwm_chip c)
	57	{
	58	return container_of(c, struct rockchip_pwm_chip, chip);
	59	}
	60
7264354c DA	61	static void rockchip_pwm_set_enable_v1(struct pwm_chip *chip,
7264354c DA	62	struct pwm_device *pwm, bool enable)
f6306299 CW	63	{
	64	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
	65	u32 enable_conf = PWM_CTRL_OUTPUT_EN \| PWM_CTRL_TIMER_EN;
	66	u32 val;
	67
	68	val = readl_relaxed(pc->base + pc->data->regs.ctrl);
	69
	70	if (enable)
	71	val \|= enable_conf;
	72	else
	73	val &= ~enable_conf;
	74
	75	writel_relaxed(val, pc->base + pc->data->regs.ctrl);
	76	}
	77
7264354c DA	78	static void rockchip_pwm_set_enable_v2(struct pwm_chip *chip,
7264354c DA	79	struct pwm_device *pwm, bool enable)
f6306299 CW	80	{
	81	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
	82	u32 enable_conf = PWM_OUTPUT_LEFT \| PWM_LP_DISABLE \| PWM_ENABLE \|
7264354c	83	PWM_CONTINUOUS;
f6306299 CW	84	u32 val;
f6306299 CW	85
15da7b50	86	if (pwm_get_polarity(pwm) == PWM_POLARITY_INVERSED)
7264354c DA	87	enable_conf \|= PWM_DUTY_NEGATIVE \| PWM_INACTIVE_POSITIVE;
	88	else
	89	enable_conf \|= PWM_DUTY_POSITIVE \| PWM_INACTIVE_NEGATIVE;
	90
f6306299 CW	91	val = readl_relaxed(pc->base + pc->data->regs.ctrl);
	92
	93	if (enable)
	94	val \|= enable_conf;
	95	else
	96	val &= ~enable_conf;
	97
	98	writel_relaxed(val, pc->base + pc->data->regs.ctrl);
	99	}
	100
101353c8 BG	101	static int rockchip_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
	102	int duty_ns, int period_ns)
	103	{
	104	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
	105	unsigned long period, duty;
	106	u64 clk_rate, div;
	107	int ret;
	108
	109	clk_rate = clk_get_rate(pc->clk);
	110
	111	/*
	112	* Since period and duty cycle registers have a width of 32
	113	* bits, every possible input period can be obtained using the
	114	* default prescaler value for all practical clock rate values.
	115	*/
	116	div = clk_rate * period_ns;
12f9ce4a BB	117	period = DIV_ROUND_CLOSEST_ULL(div,
12f9ce4a BB	118	pc->data->prescaler * NSEC_PER_SEC);
101353c8 BG	119
101353c8 BG	120	div = clk_rate * duty_ns;
12f9ce4a	121	duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);
101353c8 BG	122
	123	ret = clk_enable(pc->clk);
	124	if (ret)
	125	return ret;
	126
f6306299 CW	127	writel(period, pc->base + pc->data->regs.period);
	128	writel(duty, pc->base + pc->data->regs.duty);
	129	writel(0, pc->base + pc->data->regs.cntr);
101353c8 BG	130
	131	clk_disable(pc->clk);
	132
	133	return 0;
	134	}
	135
7264354c DA	136	static int rockchip_pwm_set_polarity(struct pwm_chip *chip,
	137	struct pwm_device *pwm,
	138	enum pwm_polarity polarity)
	139	{
	140	/*
	141	* No action needed here because pwm->polarity will be set by the core
	142	* and the core will only change polarity when the PWM is not enabled.
	143	* We'll handle things in set_enable().
	144	*/
	145
	146	return 0;
	147	}
	148
101353c8 BG	149	static int rockchip_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
	150	{
	151	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
	152	int ret;
101353c8 BG	153
	154	ret = clk_enable(pc->clk);
	155	if (ret)
	156	return ret;
	157
7264354c	158	pc->data->set_enable(chip, pwm, true);
101353c8 BG	159
	160	return 0;
	161	}
	162
	163	static void rockchip_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
	164	{
	165	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
101353c8	166
7264354c	167	pc->data->set_enable(chip, pwm, false);
101353c8 BG	168
	169	clk_disable(pc->clk);
	170	}
	171
7264354c	172	static const struct pwm_ops rockchip_pwm_ops_v1 = {
101353c8 BG	173	.config = rockchip_pwm_config,
	174	.enable = rockchip_pwm_enable,
	175	.disable = rockchip_pwm_disable,
	176	.owner = THIS_MODULE,
	177	};
	178
7264354c DA	179	static const struct pwm_ops rockchip_pwm_ops_v2 = {
	180	.config = rockchip_pwm_config,
	181	.set_polarity = rockchip_pwm_set_polarity,
	182	.enable = rockchip_pwm_enable,
	183	.disable = rockchip_pwm_disable,
	184	.owner = THIS_MODULE,
	185	};
	186
f6306299 CW	187	static const struct rockchip_pwm_data pwm_data_v1 = {
	188	.regs = {
	189	.duty = 0x04,
	190	.period = 0x08,
	191	.cntr = 0x00,
	192	.ctrl = 0x0c,
	193	},
	194	.prescaler = 2,
7264354c	195	.ops = &rockchip_pwm_ops_v1,
f6306299 CW	196	.set_enable = rockchip_pwm_set_enable_v1,
	197	};
	198
	199	static const struct rockchip_pwm_data pwm_data_v2 = {
	200	.regs = {
	201	.duty = 0x08,
	202	.period = 0x04,
	203	.cntr = 0x00,
	204	.ctrl = 0x0c,
	205	},
	206	.prescaler = 1,
7264354c	207	.ops = &rockchip_pwm_ops_v2,
f6306299 CW	208	.set_enable = rockchip_pwm_set_enable_v2,
	209	};
	210
	211	static const struct rockchip_pwm_data pwm_data_vop = {
	212	.regs = {
	213	.duty = 0x08,
	214	.period = 0x04,
	215	.cntr = 0x0c,
	216	.ctrl = 0x00,
	217	},
	218	.prescaler = 1,
7264354c	219	.ops = &rockchip_pwm_ops_v2,
f6306299 CW	220	.set_enable = rockchip_pwm_set_enable_v2,
	221	};
	222
	223	static const struct of_device_id rockchip_pwm_dt_ids[] = {
	224	{ .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
	225	{ .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
	226	{ .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
	227	{ /* sentinel */ }
	228	};
	229	MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
	230
101353c8 BG	231	static int rockchip_pwm_probe(struct platform_device *pdev)
101353c8 BG	232	{
f6306299	233	const struct of_device_id *id;
101353c8 BG	234	struct rockchip_pwm_chip *pc;
	235	struct resource *r;
	236	int ret;
	237
f6306299 CW	238	id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
	239	if (!id)
	240	return -EINVAL;
	241
101353c8 BG	242	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
	243	if (!pc)
	244	return -ENOMEM;
	245
	246	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	247	pc->base = devm_ioremap_resource(&pdev->dev, r);
	248	if (IS_ERR(pc->base))
	249	return PTR_ERR(pc->base);
	250
	251	pc->clk = devm_clk_get(&pdev->dev, NULL);
	252	if (IS_ERR(pc->clk))
	253	return PTR_ERR(pc->clk);
	254
	255	ret = clk_prepare(pc->clk);
	256	if (ret)
	257	return ret;
	258
	259	platform_set_drvdata(pdev, pc);
	260
f6306299	261	pc->data = id->data;
101353c8	262	pc->chip.dev = &pdev->dev;
7264354c	263	pc->chip.ops = pc->data->ops;
101353c8 BG	264	pc->chip.base = -1;
	265	pc->chip.npwm = 1;
	266
7264354c DA	267	if (pc->data->ops->set_polarity) {
	268	pc->chip.of_xlate = of_pwm_xlate_with_flags;
	269	pc->chip.of_pwm_n_cells = 3;
	270	}
	271
101353c8 BG	272	ret = pwmchip_add(&pc->chip);
	273	if (ret < 0) {
	274	clk_unprepare(pc->clk);
	275	dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
	276	}
	277
	278	return ret;
	279	}
	280
	281	static int rockchip_pwm_remove(struct platform_device *pdev)
	282	{
	283	struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);
	284
	285	clk_unprepare(pc->clk);
	286
	287	return pwmchip_remove(&pc->chip);
	288	}
	289
101353c8 BG	290	static struct platform_driver rockchip_pwm_driver = {
	291	.driver = {
	292	.name = "rockchip-pwm",
	293	.of_match_table = rockchip_pwm_dt_ids,
	294	},
	295	.probe = rockchip_pwm_probe,
	296	.remove = rockchip_pwm_remove,
	297	};
	298	module_platform_driver(rockchip_pwm_driver);
	299
	300	MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
	301	MODULE_DESCRIPTION("Rockchip SoC PWM driver");
	302	MODULE_LICENSE("GPL v2");