[mirror_ubuntu-hirsute-kernel.git] / drivers / pwm / pwm-sti.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * PWM device driver for ST SoCs
 *
 * Copyright (C) 2013-2016 STMicroelectronics (R&D) Limited
 *
 * Author: Ajit Pal Singh <ajitpal.singh@st.com>
 *         Lee Jones <lee.jones@linaro.org>
 */

#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/math64.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/regmap.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/time.h>
#include <linux/wait.h>

#define PWM_OUT_VAL(x)	(0x00 + (4 * (x))) /* Device's Duty Cycle register */
#define PWM_CPT_VAL(x)	(0x10 + (4 * (x))) /* Capture value */
#define PWM_CPT_EDGE(x) (0x30 + (4 * (x))) /* Edge to capture on */

#define STI_PWM_CTRL		0x50	/* Control/Config register */
#define STI_INT_EN		0x54	/* Interrupt Enable/Disable register */
#define STI_INT_STA		0x58	/* Interrupt Status register */
#define PWM_INT_ACK		0x5c
#define PWM_PRESCALE_LOW_MASK	0x0f
#define PWM_PRESCALE_HIGH_MASK	0xf0
#define PWM_CPT_EDGE_MASK	0x03
#define PWM_INT_ACK_MASK	0x1ff

#define STI_MAX_CPT_DEVS	4
#define CPT_DC_MAX		0xff

/* Regfield IDs */
enum {
	/* Bits in PWM_CTRL*/
	PWMCLK_PRESCALE_LOW,
	PWMCLK_PRESCALE_HIGH,
	CPTCLK_PRESCALE,

	PWM_OUT_EN,
	PWM_CPT_EN,

	PWM_CPT_INT_EN,
	PWM_CPT_INT_STAT,

	/* Keep last */
	MAX_REGFIELDS
};

/*
 * Each capture input can be programmed to detect rising-edge, falling-edge,
 * either edge or neither egde.
 */
enum sti_cpt_edge {
	CPT_EDGE_DISABLED,
	CPT_EDGE_RISING,
	CPT_EDGE_FALLING,
	CPT_EDGE_BOTH,
};

struct sti_cpt_ddata {
	u32 snapshot[3];
	unsigned int index;
	struct mutex lock;
	wait_queue_head_t wait;
};

struct sti_pwm_compat_data {
	const struct reg_field *reg_fields;
	unsigned int pwm_num_devs;
	unsigned int cpt_num_devs;
	unsigned int max_pwm_cnt;
	unsigned int max_prescale;
};

struct sti_pwm_chip {
	struct device *dev;
	struct clk *pwm_clk;
	struct clk *cpt_clk;
	struct regmap *regmap;
	struct sti_pwm_compat_data *cdata;
	struct regmap_field *prescale_low;
	struct regmap_field *prescale_high;
	struct regmap_field *pwm_out_en;
	struct regmap_field *pwm_cpt_en;
	struct regmap_field *pwm_cpt_int_en;
	struct regmap_field *pwm_cpt_int_stat;
	struct pwm_chip chip;
	struct pwm_device *cur;
	unsigned long configured;
	unsigned int en_count;
	struct mutex sti_pwm_lock; /* To sync between enable/disable calls */
	void __iomem *mmio;
};

static const struct reg_field sti_pwm_regfields[MAX_REGFIELDS] = {
	[PWMCLK_PRESCALE_LOW] = REG_FIELD(STI_PWM_CTRL, 0, 3),
	[PWMCLK_PRESCALE_HIGH] = REG_FIELD(STI_PWM_CTRL, 11, 14),
	[CPTCLK_PRESCALE] = REG_FIELD(STI_PWM_CTRL, 4, 8),
	[PWM_OUT_EN] = REG_FIELD(STI_PWM_CTRL, 9, 9),
	[PWM_CPT_EN] = REG_FIELD(STI_PWM_CTRL, 10, 10),
	[PWM_CPT_INT_EN] = REG_FIELD(STI_INT_EN, 1, 4),
	[PWM_CPT_INT_STAT] = REG_FIELD(STI_INT_STA, 1, 4),
};

static inline struct sti_pwm_chip *to_sti_pwmchip(struct pwm_chip *chip)
{
	return container_of(chip, struct sti_pwm_chip, chip);
}

/*
 * Calculate the prescaler value corresponding to the period.
 */
static int sti_pwm_get_prescale(struct sti_pwm_chip *pc, unsigned long period,
				unsigned int *prescale)
{
	struct sti_pwm_compat_data *cdata = pc->cdata;
	unsigned long clk_rate;
	unsigned long value;
	unsigned int ps;

	clk_rate = clk_get_rate(pc->pwm_clk);
	if (!clk_rate) {
		dev_err(pc->dev, "failed to get clock rate\n");
		return -EINVAL;
	}

	/*
	 * prescale = ((period_ns * clk_rate) / (10^9 * (max_pwm_cnt + 1)) - 1
	 */
	value = NSEC_PER_SEC / clk_rate;
	value *= cdata->max_pwm_cnt + 1;

	if (period % value)
		return -EINVAL;

	ps  = period / value - 1;
	if (ps > cdata->max_prescale)
		return -EINVAL;

	*prescale = ps;

	return 0;
}

/*
 * For STiH4xx PWM IP, the PWM period is fixed to 256 local clock cycles. The
 * only way to change the period (apart from changing the PWM input clock) is
 * to change the PWM clock prescaler.
 *
 * The prescaler is of 8 bits, so 256 prescaler values and hence 256 possible
 * period values are supported (for a particular clock rate). The requested
 * period will be applied only if it matches one of these 256 values.
 */
static int sti_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
			  int duty_ns, int period_ns)
{
	struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
	struct sti_pwm_compat_data *cdata = pc->cdata;
	unsigned int ncfg, value, prescale = 0;
	struct pwm_device *cur = pc->cur;
	struct device *dev = pc->dev;
	bool period_same = false;
	int ret;

	ncfg = hweight_long(pc->configured);
	if (ncfg)
		period_same = (period_ns == pwm_get_period(cur));

	/*
	 * Allow configuration changes if one of the following conditions
	 * satisfy.
	 * 1. No devices have been configured.
	 * 2. Only one device has been configured and the new request is for
	 *    the same device.
	 * 3. Only one device has been configured and the new request is for
	 *    a new device and period of the new device is same as the current
	 *    configured period.
	 * 4. More than one devices are configured and period of the new
	 *    requestis the same as the current period.
	 */
	if (!ncfg ||
	    ((ncfg == 1) && (pwm->hwpwm == cur->hwpwm)) ||
	    ((ncfg == 1) && (pwm->hwpwm != cur->hwpwm) && period_same) ||
	    ((ncfg > 1) && period_same)) {
		/* Enable clock before writing to PWM registers. */
		ret = clk_enable(pc->pwm_clk);
		if (ret)
			return ret;

		ret = clk_enable(pc->cpt_clk);
		if (ret)
			return ret;

		if (!period_same) {
			ret = sti_pwm_get_prescale(pc, period_ns, &prescale);
			if (ret)
				goto clk_dis;

			value = prescale & PWM_PRESCALE_LOW_MASK;

			ret = regmap_field_write(pc->prescale_low, value);
			if (ret)
				goto clk_dis;

			value = (prescale & PWM_PRESCALE_HIGH_MASK) >> 4;

			ret = regmap_field_write(pc->prescale_high, value);
			if (ret)
				goto clk_dis;
		}

		/*
		 * When PWMVal == 0, PWM pulse = 1 local clock cycle.
		 * When PWMVal == max_pwm_count,
		 * PWM pulse = (max_pwm_count + 1) local cycles,
		 * that is continuous pulse: signal never goes low.
		 */
		value = cdata->max_pwm_cnt * duty_ns / period_ns;

		ret = regmap_write(pc->regmap, PWM_OUT_VAL(pwm->hwpwm), value);
		if (ret)
			goto clk_dis;

		ret = regmap_field_write(pc->pwm_cpt_int_en, 0);

		set_bit(pwm->hwpwm, &pc->configured);
		pc->cur = pwm;

		dev_dbg(dev, "prescale:%u, period:%i, duty:%i, value:%u\n",
			prescale, period_ns, duty_ns, value);
	} else {
		return -EINVAL;
	}

clk_dis:
	clk_disable(pc->pwm_clk);
	clk_disable(pc->cpt_clk);
	return ret;
}

static int sti_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
	struct device *dev = pc->dev;
	int ret = 0;

	/*
	 * Since we have a common enable for all PWM devices, do not enable if
	 * already enabled.
	 */
	mutex_lock(&pc->sti_pwm_lock);

	if (!pc->en_count) {
		ret = clk_enable(pc->pwm_clk);
		if (ret)
			goto out;

		ret = clk_enable(pc->cpt_clk);
		if (ret)
			goto out;

		ret = regmap_field_write(pc->pwm_out_en, 1);
		if (ret) {
			dev_err(dev, "failed to enable PWM device %u: %d\n",
				pwm->hwpwm, ret);
			goto out;
		}
	}

	pc->en_count++;

out:
	mutex_unlock(&pc->sti_pwm_lock);
	return ret;
}

static void sti_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct sti_pwm_chip *pc = to_sti_pwmchip(chip);

	mutex_lock(&pc->sti_pwm_lock);

	if (--pc->en_count) {
		mutex_unlock(&pc->sti_pwm_lock);
		return;
	}

	regmap_field_write(pc->pwm_out_en, 0);

	clk_disable(pc->pwm_clk);
	clk_disable(pc->cpt_clk);

	mutex_unlock(&pc->sti_pwm_lock);
}

static void sti_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct sti_pwm_chip *pc = to_sti_pwmchip(chip);

	clear_bit(pwm->hwpwm, &pc->configured);
}

static int sti_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm,
			   struct pwm_capture *result, unsigned long timeout)
{
	struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
	struct sti_pwm_compat_data *cdata = pc->cdata;
	struct sti_cpt_ddata *ddata = pwm_get_chip_data(pwm);
	struct device *dev = pc->dev;
	unsigned int effective_ticks;
	unsigned long long high, low;
	int ret;

	if (pwm->hwpwm >= cdata->cpt_num_devs) {
		dev_err(dev, "device %u is not valid\n", pwm->hwpwm);
		return -EINVAL;
	}

	mutex_lock(&ddata->lock);
	ddata->index = 0;

	/* Prepare capture measurement */
	regmap_write(pc->regmap, PWM_CPT_EDGE(pwm->hwpwm), CPT_EDGE_RISING);
	regmap_field_write(pc->pwm_cpt_int_en, BIT(pwm->hwpwm));

	/* Enable capture */
	ret = regmap_field_write(pc->pwm_cpt_en, 1);
	if (ret) {
		dev_err(dev, "failed to enable PWM capture %u: %d\n",
			pwm->hwpwm, ret);
		goto out;
	}

	ret = wait_event_interruptible_timeout(ddata->wait, ddata->index > 1,
					       msecs_to_jiffies(timeout));

	regmap_write(pc->regmap, PWM_CPT_EDGE(pwm->hwpwm), CPT_EDGE_DISABLED);

	if (ret == -ERESTARTSYS)
		goto out;

	switch (ddata->index) {
	case 0:
	case 1:
		/*
		 * Getting here could mean:
		 *  - input signal is constant of less than 1 Hz
		 *  - there is no input signal at all
		 *
		 * In such case the frequency is rounded down to 0
		 */
		result->period = 0;
		result->duty_cycle = 0;

		break;

	case 2:
		/* We have everying we need */
		high = ddata->snapshot[1] - ddata->snapshot[0];
		low = ddata->snapshot[2] - ddata->snapshot[1];

		effective_ticks = clk_get_rate(pc->cpt_clk);

		result->period = (high + low) * NSEC_PER_SEC;
		result->period /= effective_ticks;

		result->duty_cycle = high * NSEC_PER_SEC;
		result->duty_cycle /= effective_ticks;

		break;

	default:
		dev_err(dev, "internal error\n");
		break;
	}

out:
	/* Disable capture */
	regmap_field_write(pc->pwm_cpt_en, 0);

	mutex_unlock(&ddata->lock);
	return ret;
}

static const struct pwm_ops sti_pwm_ops = {
	.capture = sti_pwm_capture,
	.config = sti_pwm_config,
	.enable = sti_pwm_enable,
	.disable = sti_pwm_disable,
	.free = sti_pwm_free,
	.owner = THIS_MODULE,
};

static irqreturn_t sti_pwm_interrupt(int irq, void *data)
{
	struct sti_pwm_chip *pc = data;
	struct device *dev = pc->dev;
	struct sti_cpt_ddata *ddata;
	int devicenum;
	unsigned int cpt_int_stat;
	unsigned int reg;
	int ret = IRQ_NONE;

	ret = regmap_field_read(pc->pwm_cpt_int_stat, &cpt_int_stat);
	if (ret)
		return ret;

	while (cpt_int_stat) {
		devicenum = ffs(cpt_int_stat) - 1;

		ddata = pwm_get_chip_data(&pc->chip.pwms[devicenum]);

		/*
		 * Capture input:
		 *    _______                   _______
		 *   |       |                 |       |
		 * __|       |_________________|       |________
		 *   ^0      ^1                ^2
		 *
		 * Capture start by the first available rising edge. When a
		 * capture event occurs, capture value (CPT_VALx) is stored,
		 * index incremented, capture edge changed.
		 *
		 * After the capture, if the index > 1, we have collected the
		 * necessary data so we signal the thread waiting for it and
		 * disable the capture by setting capture edge to none
		 */

		regmap_read(pc->regmap,
			    PWM_CPT_VAL(devicenum),
			    &ddata->snapshot[ddata->index]);

		switch (ddata->index) {
		case 0:
		case 1:
			regmap_read(pc->regmap, PWM_CPT_EDGE(devicenum), &reg);
			reg ^= PWM_CPT_EDGE_MASK;
			regmap_write(pc->regmap, PWM_CPT_EDGE(devicenum), reg);

			ddata->index++;
			break;

		case 2:
			regmap_write(pc->regmap,
				     PWM_CPT_EDGE(devicenum),
				     CPT_EDGE_DISABLED);
			wake_up(&ddata->wait);
			break;

		default:
			dev_err(dev, "Internal error\n");
		}

		cpt_int_stat &= ~BIT_MASK(devicenum);

		ret = IRQ_HANDLED;
	}

	/* Just ACK everything */
	regmap_write(pc->regmap, PWM_INT_ACK, PWM_INT_ACK_MASK);

	return ret;
}

static int sti_pwm_probe_dt(struct sti_pwm_chip *pc)
{
	struct device *dev = pc->dev;
	const struct reg_field *reg_fields;
	struct device_node *np = dev->of_node;
	struct sti_pwm_compat_data *cdata = pc->cdata;
	u32 num_devs;
	int ret;

	ret = of_property_read_u32(np, "st,pwm-num-chan", &num_devs);
	if (!ret)
		cdata->pwm_num_devs = num_devs;

	ret = of_property_read_u32(np, "st,capture-num-chan", &num_devs);
	if (!ret)
		cdata->cpt_num_devs = num_devs;

	if (!cdata->pwm_num_devs && !cdata->cpt_num_devs) {
		dev_err(dev, "No channels configured\n");
		return -EINVAL;
	}

	reg_fields = cdata->reg_fields;

	pc->prescale_low = devm_regmap_field_alloc(dev, pc->regmap,
					reg_fields[PWMCLK_PRESCALE_LOW]);
	if (IS_ERR(pc->prescale_low))
		return PTR_ERR(pc->prescale_low);

	pc->prescale_high = devm_regmap_field_alloc(dev, pc->regmap,
					reg_fields[PWMCLK_PRESCALE_HIGH]);
	if (IS_ERR(pc->prescale_high))
		return PTR_ERR(pc->prescale_high);


	pc->pwm_out_en = devm_regmap_field_alloc(dev, pc->regmap,
						 reg_fields[PWM_OUT_EN]);
	if (IS_ERR(pc->pwm_out_en))
		return PTR_ERR(pc->pwm_out_en);

	pc->pwm_cpt_en = devm_regmap_field_alloc(dev, pc->regmap,
						 reg_fields[PWM_CPT_EN]);
	if (IS_ERR(pc->pwm_cpt_en))
		return PTR_ERR(pc->pwm_cpt_en);

	pc->pwm_cpt_int_en = devm_regmap_field_alloc(dev, pc->regmap,
						reg_fields[PWM_CPT_INT_EN]);
	if (IS_ERR(pc->pwm_cpt_int_en))
		return PTR_ERR(pc->pwm_cpt_int_en);

	pc->pwm_cpt_int_stat = devm_regmap_field_alloc(dev, pc->regmap,
						reg_fields[PWM_CPT_INT_STAT]);
	if (PTR_ERR_OR_ZERO(pc->pwm_cpt_int_stat))
		return PTR_ERR(pc->pwm_cpt_int_stat);

	return 0;
}

static const struct regmap_config sti_pwm_regmap_config = {
	.reg_bits = 32,
	.val_bits = 32,
	.reg_stride = 4,
};

static int sti_pwm_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct sti_pwm_compat_data *cdata;
	struct sti_pwm_chip *pc;
	struct resource *res;
	unsigned int i;
	int irq, ret;

	pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
	if (!pc)
		return -ENOMEM;

	cdata = devm_kzalloc(dev, sizeof(*cdata), GFP_KERNEL);
	if (!cdata)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	pc->mmio = devm_ioremap_resource(dev, res);
	if (IS_ERR(pc->mmio))
		return PTR_ERR(pc->mmio);

	pc->regmap = devm_regmap_init_mmio(dev, pc->mmio,
					   &sti_pwm_regmap_config);
	if (IS_ERR(pc->regmap))
		return PTR_ERR(pc->regmap);

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	ret = devm_request_irq(&pdev->dev, irq, sti_pwm_interrupt, 0,
			       pdev->name, pc);
	if (ret < 0) {
		dev_err(&pdev->dev, "Failed to request IRQ\n");
		return ret;
	}

	/*
	 * Setup PWM data with default values: some values could be replaced
	 * with specific ones provided from Device Tree.
	 */
	cdata->reg_fields = sti_pwm_regfields;
	cdata->max_prescale = 0xff;
	cdata->max_pwm_cnt = 255;
	cdata->pwm_num_devs = 0;
	cdata->cpt_num_devs = 0;

	pc->cdata = cdata;
	pc->dev = dev;
	pc->en_count = 0;
	mutex_init(&pc->sti_pwm_lock);

	ret = sti_pwm_probe_dt(pc);
	if (ret)
		return ret;

	if (!cdata->pwm_num_devs)
		goto skip_pwm;

	pc->pwm_clk = of_clk_get_by_name(dev->of_node, "pwm");
	if (IS_ERR(pc->pwm_clk)) {
		dev_err(dev, "failed to get PWM clock\n");
		return PTR_ERR(pc->pwm_clk);
	}

	ret = clk_prepare(pc->pwm_clk);
	if (ret) {
		dev_err(dev, "failed to prepare clock\n");
		return ret;
	}

skip_pwm:
	if (!cdata->cpt_num_devs)
		goto skip_cpt;

	pc->cpt_clk = of_clk_get_by_name(dev->of_node, "capture");
	if (IS_ERR(pc->cpt_clk)) {
		dev_err(dev, "failed to get PWM capture clock\n");
		return PTR_ERR(pc->cpt_clk);
	}

	ret = clk_prepare(pc->cpt_clk);
	if (ret) {
		dev_err(dev, "failed to prepare clock\n");
		return ret;
	}

skip_cpt:
	pc->chip.dev = dev;
	pc->chip.ops = &sti_pwm_ops;
	pc->chip.base = -1;
	pc->chip.npwm = pc->cdata->pwm_num_devs;

	ret = pwmchip_add(&pc->chip);
	if (ret < 0) {
		clk_unprepare(pc->pwm_clk);
		clk_unprepare(pc->cpt_clk);
		return ret;
	}

	for (i = 0; i < cdata->cpt_num_devs; i++) {
		struct sti_cpt_ddata *ddata;

		ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
		if (!ddata)
			return -ENOMEM;

		init_waitqueue_head(&ddata->wait);
		mutex_init(&ddata->lock);

		pwm_set_chip_data(&pc->chip.pwms[i], ddata);
	}

	platform_set_drvdata(pdev, pc);

	return 0;
}

static int sti_pwm_remove(struct platform_device *pdev)
{
	struct sti_pwm_chip *pc = platform_get_drvdata(pdev);
	unsigned int i;

	for (i = 0; i < pc->cdata->pwm_num_devs; i++)
		pwm_disable(&pc->chip.pwms[i]);

	clk_unprepare(pc->pwm_clk);
	clk_unprepare(pc->cpt_clk);

	return pwmchip_remove(&pc->chip);
}

static const struct of_device_id sti_pwm_of_match[] = {
	{ .compatible = "st,sti-pwm", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sti_pwm_of_match);

static struct platform_driver sti_pwm_driver = {
	.driver = {
		.name = "sti-pwm",
		.of_match_table = sti_pwm_of_match,
	},
	.probe = sti_pwm_probe,
	.remove = sti_pwm_remove,
};
module_platform_driver(sti_pwm_driver);

MODULE_AUTHOR("Ajit Pal Singh <ajitpal.singh@st.com>");
MODULE_DESCRIPTION("STMicroelectronics ST PWM driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
378fe115	2	/*
7d8a600c LJ	3	* PWM device driver for ST SoCs
	4	*
	5	* Copyright (C) 2013-2016 STMicroelectronics (R&D) Limited
378fe115	6	*
7d8a600c LJ	7	* Author: Ajit Pal Singh <ajitpal.singh@st.com>
7d8a600c LJ	8	* Lee Jones <lee.jones@linaro.org>
378fe115 LJ	9	*/
378fe115 LJ	10
378fe115	11	#include <linux/clk.h>
3f0925b5	12	#include <linux/interrupt.h>
378fe115 LJ	13	#include <linux/math64.h>
	14	#include <linux/mfd/syscon.h>
	15	#include <linux/module.h>
	16	#include <linux/of.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/pwm.h>
	19	#include <linux/regmap.h>
3f0925b5	20	#include <linux/sched.h>
378fe115 LJ	21	#include <linux/slab.h>
378fe115 LJ	22	#include <linux/time.h>
3f0925b5	23	#include <linux/wait.h>
378fe115	24
c5f94ae6	25	#define PWM_OUT_VAL(x) (0x00 + (4 * (x))) /* Device's Duty Cycle register */
f66d78fa LJ	26	#define PWM_CPT_VAL(x) (0x10 + (4 * (x))) /* Capture value */
f66d78fa LJ	27	#define PWM_CPT_EDGE(x) (0x30 + (4 * (x))) /* Edge to capture on */
c5f94ae6 LJ	28
	29	#define STI_PWM_CTRL 0x50 /* Control/Config register */
	30	#define STI_INT_EN 0x54 /* Interrupt Enable/Disable register */
f66d78fa	31	#define STI_INT_STA 0x58 /* Interrupt Status register */
7d8a600c LJ	32	#define PWM_INT_ACK 0x5c
	33	#define PWM_PRESCALE_LOW_MASK 0x0f
	34	#define PWM_PRESCALE_HIGH_MASK 0xf0
	35	#define PWM_CPT_EDGE_MASK 0x03
	36	#define PWM_INT_ACK_MASK 0x1ff
f66d78fa	37
7d8a600c LJ	38	#define STI_MAX_CPT_DEVS 4
7d8a600c LJ	39	#define CPT_DC_MAX 0xff
378fe115 LJ	40
	41	/* Regfield IDs */
	42	enum {
c5f94ae6	43	/* Bits in PWM_CTRL*/
bf9cc80b APS	44	PWMCLK_PRESCALE_LOW,
bf9cc80b APS	45	PWMCLK_PRESCALE_HIGH,
f66d78fa	46	CPTCLK_PRESCALE,
c5f94ae6 LJ	47
c5f94ae6 LJ	48	PWM_OUT_EN,
f66d78fa	49	PWM_CPT_EN,
c5f94ae6 LJ	50
c5f94ae6 LJ	51	PWM_CPT_INT_EN,
f66d78fa	52	PWM_CPT_INT_STAT,
378fe115 LJ	53
	54	/* Keep last */
	55	MAX_REGFIELDS
	56	};
	57
7d8a600c LJ	58	/*
	59	* Each capture input can be programmed to detect rising-edge, falling-edge,
	60	* either edge or neither egde.
f66d78fa LJ	61	*/
	62	enum sti_cpt_edge {
	63	CPT_EDGE_DISABLED,
	64	CPT_EDGE_RISING,
	65	CPT_EDGE_FALLING,
	66	CPT_EDGE_BOTH,
	67	};
	68
3f0925b5 LJ	69	struct sti_cpt_ddata {
	70	u32 snapshot[3];
	71	unsigned int index;
	72	struct mutex lock;
	73	wait_queue_head_t wait;
	74	};
	75
378fe115 LJ	76	struct sti_pwm_compat_data {
378fe115 LJ	77	const struct reg_field *reg_fields;
3f0925b5 LJ	78	unsigned int pwm_num_devs;
3f0925b5 LJ	79	unsigned int cpt_num_devs;
378fe115 LJ	80	unsigned int max_pwm_cnt;
	81	unsigned int max_prescale;
	82	};
	83
	84	struct sti_pwm_chip {
	85	struct device *dev;
c5f94ae6	86	struct clk *pwm_clk;
d66a928d	87	struct clk *cpt_clk;
378fe115 LJ	88	struct regmap *regmap;
378fe115 LJ	89	struct sti_pwm_compat_data *cdata;
bf9cc80b APS	90	struct regmap_field *prescale_low;
bf9cc80b APS	91	struct regmap_field *prescale_high;
c5f94ae6	92	struct regmap_field *pwm_out_en;
25eb5380	93	struct regmap_field *pwm_cpt_en;
c5f94ae6	94	struct regmap_field *pwm_cpt_int_en;
25eb5380	95	struct regmap_field *pwm_cpt_int_stat;
378fe115	96	struct pwm_chip chip;
5165166e	97	struct pwm_device *cur;
cd264b6a	98	unsigned long configured;
6ad6b838 APS	99	unsigned int en_count;
6ad6b838 APS	100	struct mutex sti_pwm_lock; /* To sync between enable/disable calls */
378fe115 LJ	101	void __iomem *mmio;
	102	};
	103
	104	static const struct reg_field sti_pwm_regfields[MAX_REGFIELDS] = {
7d8a600c LJ	105	[PWMCLK_PRESCALE_LOW] = REG_FIELD(STI_PWM_CTRL, 0, 3),
	106	[PWMCLK_PRESCALE_HIGH] = REG_FIELD(STI_PWM_CTRL, 11, 14),
	107	[CPTCLK_PRESCALE] = REG_FIELD(STI_PWM_CTRL, 4, 8),
	108	[PWM_OUT_EN] = REG_FIELD(STI_PWM_CTRL, 9, 9),
	109	[PWM_CPT_EN] = REG_FIELD(STI_PWM_CTRL, 10, 10),
	110	[PWM_CPT_INT_EN] = REG_FIELD(STI_INT_EN, 1, 4),
	111	[PWM_CPT_INT_STAT] = REG_FIELD(STI_INT_STA, 1, 4),
378fe115 LJ	112	};
	113
	114	static inline struct sti_pwm_chip to_sti_pwmchip(struct pwm_chip chip)
	115	{
	116	return container_of(chip, struct sti_pwm_chip, chip);
	117	}
	118
	119	/*
3aacd3e1	120	* Calculate the prescaler value corresponding to the period.
378fe115	121	*/
3aacd3e1 APS	122	static int sti_pwm_get_prescale(struct sti_pwm_chip *pc, unsigned long period,
3aacd3e1 APS	123	unsigned int *prescale)
378fe115 LJ	124	{
378fe115 LJ	125	struct sti_pwm_compat_data *cdata = pc->cdata;
d81738b7	126	unsigned long clk_rate;
7d8a600c	127	unsigned long value;
3aacd3e1	128	unsigned int ps;
378fe115	129
d81738b7 LJ	130	clk_rate = clk_get_rate(pc->pwm_clk);
	131	if (!clk_rate) {
	132	dev_err(pc->dev, "failed to get clock rate\n");
	133	return -EINVAL;
	134	}
	135
378fe115	136	/*
7d8a600c	137	* prescale = ((period_ns * clk_rate) / (10^9 * (max_pwm_cnt + 1)) - 1
378fe115	138	*/
7d8a600c LJ	139	value = NSEC_PER_SEC / clk_rate;
7d8a600c LJ	140	value *= cdata->max_pwm_cnt + 1;
378fe115	141
7d8a600c	142	if (period % value)
3aacd3e1	143	return -EINVAL;
7d8a600c LJ	144
	145	ps = period / value - 1;
	146	if (ps > cdata->max_prescale)
	147	return -EINVAL;
	148
3aacd3e1 APS	149	*prescale = ps;
	150
	151	return 0;
378fe115 LJ	152	}
378fe115 LJ	153
378fe115	154	/*
7d8a600c LJ	155	* For STiH4xx PWM IP, the PWM period is fixed to 256 local clock cycles. The
	156	* only way to change the period (apart from changing the PWM input clock) is
	157	* to change the PWM clock prescaler.
	158	*
	159	* The prescaler is of 8 bits, so 256 prescaler values and hence 256 possible
	160	* period values are supported (for a particular clock rate). The requested
	161	* period will be applied only if it matches one of these 256 values.
378fe115 LJ	162	*/
378fe115 LJ	163	static int sti_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
7d8a600c	164	int duty_ns, int period_ns)
378fe115 LJ	165	{
	166	struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
	167	struct sti_pwm_compat_data *cdata = pc->cdata;
7d8a600c	168	unsigned int ncfg, value, prescale = 0;
5165166e	169	struct pwm_device *cur = pc->cur;
378fe115	170	struct device *dev = pc->dev;
5165166e	171	bool period_same = false;
7d8a600c	172	int ret;
5165166e	173
cd264b6a	174	ncfg = hweight_long(pc->configured);
5165166e APS	175	if (ncfg)
	176	period_same = (period_ns == pwm_get_period(cur));
	177
7d8a600c LJ	178	/*
	179	* Allow configuration changes if one of the following conditions
	180	* satisfy.
09022e61	181	* 1. No devices have been configured.
7d8a600c LJ	182	* 2. Only one device has been configured and the new request is for
	183	* the same device.
	184	* 3. Only one device has been configured and the new request is for
	185	* a new device and period of the new device is same as the current
	186	* configured period.
09022e61	187	* 4. More than one devices are configured and period of the new
5165166e	188	* requestis the same as the current period.
378fe115	189	*/
5165166e APS	190	if (!ncfg \|\|
	191	((ncfg == 1) && (pwm->hwpwm == cur->hwpwm)) \|\|
	192	((ncfg == 1) && (pwm->hwpwm != cur->hwpwm) && period_same) \|\|
	193	((ncfg > 1) && period_same)) {
	194	/* Enable clock before writing to PWM registers. */
c5f94ae6	195	ret = clk_enable(pc->pwm_clk);
5165166e APS	196	if (ret)
	197	return ret;
	198
d66a928d LJ	199	ret = clk_enable(pc->cpt_clk);
	200	if (ret)
	201	return ret;
	202
5165166e	203	if (!period_same) {
3aacd3e1 APS	204	ret = sti_pwm_get_prescale(pc, period_ns, &prescale);
3aacd3e1 APS	205	if (ret)
5165166e	206	goto clk_dis;
5165166e	207
7d8a600c LJ	208	value = prescale & PWM_PRESCALE_LOW_MASK;
	209
	210	ret = regmap_field_write(pc->prescale_low, value);
5165166e APS	211	if (ret)
	212	goto clk_dis;
	213
7d8a600c LJ	214	value = (prescale & PWM_PRESCALE_HIGH_MASK) >> 4;
	215
	216	ret = regmap_field_write(pc->prescale_high, value);
5165166e APS	217	if (ret)
	218	goto clk_dis;
	219	}
	220
	221	/*
	222	* When PWMVal == 0, PWM pulse = 1 local clock cycle.
	223	* When PWMVal == max_pwm_count,
	224	* PWM pulse = (max_pwm_count + 1) local cycles,
	225	* that is continuous pulse: signal never goes low.
	226	*/
7d8a600c	227	value = cdata->max_pwm_cnt * duty_ns / period_ns;
5165166e	228
7d8a600c	229	ret = regmap_write(pc->regmap, PWM_OUT_VAL(pwm->hwpwm), value);
5165166e APS	230	if (ret)
	231	goto clk_dis;
	232
c5f94ae6	233	ret = regmap_field_write(pc->pwm_cpt_int_en, 0);
5165166e	234
cd264b6a	235	set_bit(pwm->hwpwm, &pc->configured);
5165166e APS	236	pc->cur = pwm;
5165166e APS	237
7d8a600c LJ	238	dev_dbg(dev, "prescale:%u, period:%i, duty:%i, value:%u\n",
7d8a600c LJ	239	prescale, period_ns, duty_ns, value);
5165166e	240	} else {
378fe115 LJ	241	return -EINVAL;
	242	}
	243
378fe115	244	clk_dis:
c5f94ae6	245	clk_disable(pc->pwm_clk);
d66a928d	246	clk_disable(pc->cpt_clk);
378fe115 LJ	247	return ret;
	248	}
	249
	250	static int sti_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
	251	{
	252	struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
	253	struct device *dev = pc->dev;
6ad6b838	254	int ret = 0;
378fe115	255
6ad6b838	256	/*
7d8a600c LJ	257	* Since we have a common enable for all PWM devices, do not enable if
7d8a600c LJ	258	* already enabled.
6ad6b838 APS	259	*/
6ad6b838 APS	260	mutex_lock(&pc->sti_pwm_lock);
7d8a600c	261
6ad6b838	262	if (!pc->en_count) {
c5f94ae6	263	ret = clk_enable(pc->pwm_clk);
6ad6b838 APS	264	if (ret)
6ad6b838 APS	265	goto out;
378fe115	266
d66a928d LJ	267	ret = clk_enable(pc->cpt_clk);
	268	if (ret)
	269	goto out;
	270
c5f94ae6	271	ret = regmap_field_write(pc->pwm_out_en, 1);
6ad6b838	272	if (ret) {
7d8a600c LJ	273	dev_err(dev, "failed to enable PWM device %u: %d\n",
7d8a600c LJ	274	pwm->hwpwm, ret);
6ad6b838 APS	275	goto out;
	276	}
	277	}
7d8a600c	278
6ad6b838	279	pc->en_count++;
7d8a600c	280
6ad6b838 APS	281	out:
6ad6b838 APS	282	mutex_unlock(&pc->sti_pwm_lock);
378fe115 LJ	283	return ret;
	284	}
	285
	286	static void sti_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
	287	{
	288	struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
378fe115	289
6ad6b838	290	mutex_lock(&pc->sti_pwm_lock);
7d8a600c	291
6ad6b838 APS	292	if (--pc->en_count) {
	293	mutex_unlock(&pc->sti_pwm_lock);
	294	return;
	295	}
7d8a600c	296
c5f94ae6	297	regmap_field_write(pc->pwm_out_en, 0);
378fe115	298
c5f94ae6	299	clk_disable(pc->pwm_clk);
d66a928d	300	clk_disable(pc->cpt_clk);
7d8a600c	301
6ad6b838	302	mutex_unlock(&pc->sti_pwm_lock);
378fe115 LJ	303	}
378fe115 LJ	304
cd264b6a APS	305	static void sti_pwm_free(struct pwm_chip chip, struct pwm_device pwm)
	306	{
	307	struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
	308
	309	clear_bit(pwm->hwpwm, &pc->configured);
	310	}
	311
c97267ae LJ	312	static int sti_pwm_capture(struct pwm_chip chip, struct pwm_device pwm,
	313	struct pwm_capture *result, unsigned long timeout)
	314	{
	315	struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
	316	struct sti_pwm_compat_data *cdata = pc->cdata;
	317	struct sti_cpt_ddata *ddata = pwm_get_chip_data(pwm);
	318	struct device *dev = pc->dev;
	319	unsigned int effective_ticks;
	320	unsigned long long high, low;
	321	int ret;
	322
	323	if (pwm->hwpwm >= cdata->cpt_num_devs) {
	324	dev_err(dev, "device %u is not valid\n", pwm->hwpwm);
	325	return -EINVAL;
	326	}
	327
	328	mutex_lock(&ddata->lock);
	329	ddata->index = 0;
	330
	331	/* Prepare capture measurement */
	332	regmap_write(pc->regmap, PWM_CPT_EDGE(pwm->hwpwm), CPT_EDGE_RISING);
	333	regmap_field_write(pc->pwm_cpt_int_en, BIT(pwm->hwpwm));
	334
	335	/* Enable capture */
	336	ret = regmap_field_write(pc->pwm_cpt_en, 1);
	337	if (ret) {
	338	dev_err(dev, "failed to enable PWM capture %u: %d\n",
	339	pwm->hwpwm, ret);
	340	goto out;
	341	}
	342
	343	ret = wait_event_interruptible_timeout(ddata->wait, ddata->index > 1,
	344	msecs_to_jiffies(timeout));
	345
	346	regmap_write(pc->regmap, PWM_CPT_EDGE(pwm->hwpwm), CPT_EDGE_DISABLED);
	347
	348	if (ret == -ERESTARTSYS)
	349	goto out;
	350
	351	switch (ddata->index) {
	352	case 0:
	353	case 1:
	354	/*
	355	* Getting here could mean:
	356	* - input signal is constant of less than 1 Hz
	357	* - there is no input signal at all
	358	*
	359	* In such case the frequency is rounded down to 0
	360	*/
	361	result->period = 0;
	362	result->duty_cycle = 0;
	363
	364	break;
	365
	366	case 2:
	367	/* We have everying we need */
	368	high = ddata->snapshot[1] - ddata->snapshot[0];
	369	low = ddata->snapshot[2] - ddata->snapshot[1];
	370
	371	effective_ticks = clk_get_rate(pc->cpt_clk);
	372
	373	result->period = (high + low) * NSEC_PER_SEC;
	374	result->period /= effective_ticks;
	375
376	result->duty_cycle = high * NSEC_PER_SEC;
377	result->duty_cycle /= effective_ticks;
378
379	break;
380
381	default:
382	dev_err(dev, "internal error\n");
383	break;
384	}
385
386	out:
387	/* Disable capture */
388	regmap_field_write(pc->pwm_cpt_en, 0);
389
390	mutex_unlock(&ddata->lock);
391	return ret;
392	}
393
378fe115	394	static const struct pwm_ops sti_pwm_ops = {
c97267ae	395	.capture = sti_pwm_capture,
378fe115 LJ	396	.config = sti_pwm_config,
	397	.enable = sti_pwm_enable,
	398	.disable = sti_pwm_disable,
cd264b6a	399	.free = sti_pwm_free,
378fe115 LJ	400	.owner = THIS_MODULE,
	401	};
	402
25eb5380 LJ	403	static irqreturn_t sti_pwm_interrupt(int irq, void *data)
	404	{
	405	struct sti_pwm_chip *pc = data;
	406	struct device *dev = pc->dev;
	407	struct sti_cpt_ddata *ddata;
	408	int devicenum;
	409	unsigned int cpt_int_stat;
	410	unsigned int reg;
	411	int ret = IRQ_NONE;
	412
	413	ret = regmap_field_read(pc->pwm_cpt_int_stat, &cpt_int_stat);
	414	if (ret)
	415	return ret;
	416
	417	while (cpt_int_stat) {
	418	devicenum = ffs(cpt_int_stat) - 1;
	419
	420	ddata = pwm_get_chip_data(&pc->chip.pwms[devicenum]);
	421
	422	/*
	423	* Capture input:
	424	* _______ _______
	425	* \| \| \| \|
	426	* __\| \|_________________\| \|________
	427	* ^0 ^1 ^2
	428	*
7d8a600c LJ	429	* Capture start by the first available rising edge. When a
	430	* capture event occurs, capture value (CPT_VALx) is stored,
	431	* index incremented, capture edge changed.
25eb5380	432	*
7d8a600c LJ	433	* After the capture, if the index > 1, we have collected the
	434	* necessary data so we signal the thread waiting for it and
	435	* disable the capture by setting capture edge to none
25eb5380 LJ	436	*/
	437
	438	regmap_read(pc->regmap,
	439	PWM_CPT_VAL(devicenum),
	440	&ddata->snapshot[ddata->index]);
	441
	442	switch (ddata->index) {
	443	case 0:
	444	case 1:
	445	regmap_read(pc->regmap, PWM_CPT_EDGE(devicenum), &reg);
	446	reg ^= PWM_CPT_EDGE_MASK;
	447	regmap_write(pc->regmap, PWM_CPT_EDGE(devicenum), reg);
	448
	449	ddata->index++;
	450	break;
7d8a600c	451
25eb5380 LJ	452	case 2:
	453	regmap_write(pc->regmap,
	454	PWM_CPT_EDGE(devicenum),
	455	CPT_EDGE_DISABLED);
	456	wake_up(&ddata->wait);
	457	break;
7d8a600c	458
25eb5380 LJ	459	default:
	460	dev_err(dev, "Internal error\n");
	461	}
	462
	463	cpt_int_stat &= ~BIT_MASK(devicenum);
	464
	465	ret = IRQ_HANDLED;
	466	}
	467
	468	/* Just ACK everything */
	469	regmap_write(pc->regmap, PWM_INT_ACK, PWM_INT_ACK_MASK);
	470
	471	return ret;
	472	}
	473
378fe115 LJ	474	static int sti_pwm_probe_dt(struct sti_pwm_chip *pc)
	475	{
	476	struct device *dev = pc->dev;
	477	const struct reg_field *reg_fields;
	478	struct device_node *np = dev->of_node;
	479	struct sti_pwm_compat_data *cdata = pc->cdata;
09022e61	480	u32 num_devs;
3f0925b5	481	int ret;
378fe115	482
3f0925b5 LJ	483	ret = of_property_read_u32(np, "st,pwm-num-chan", &num_devs);
	484	if (!ret)
	485	cdata->pwm_num_devs = num_devs;
	486
	487	ret = of_property_read_u32(np, "st,capture-num-chan", &num_devs);
	488	if (!ret)
	489	cdata->cpt_num_devs = num_devs;
378fe115	490
85a834c4 LJ	491	if (!cdata->pwm_num_devs && !cdata->cpt_num_devs) {
	492	dev_err(dev, "No channels configured\n");
	493	return -EINVAL;
	494	}
	495
378fe115 LJ	496	reg_fields = cdata->reg_fields;
378fe115 LJ	497
bf9cc80b APS	498	pc->prescale_low = devm_regmap_field_alloc(dev, pc->regmap,
	499	reg_fields[PWMCLK_PRESCALE_LOW]);
	500	if (IS_ERR(pc->prescale_low))
	501	return PTR_ERR(pc->prescale_low);
	502
	503	pc->prescale_high = devm_regmap_field_alloc(dev, pc->regmap,
	504	reg_fields[PWMCLK_PRESCALE_HIGH]);
	505	if (IS_ERR(pc->prescale_high))
	506	return PTR_ERR(pc->prescale_high);
378fe115	507
378fe115	508
c5f94ae6 LJ	509	pc->pwm_out_en = devm_regmap_field_alloc(dev, pc->regmap,
	510	reg_fields[PWM_OUT_EN]);
	511	if (IS_ERR(pc->pwm_out_en))
	512	return PTR_ERR(pc->pwm_out_en);
	513
c97267ae LJ	514	pc->pwm_cpt_en = devm_regmap_field_alloc(dev, pc->regmap,
	515	reg_fields[PWM_CPT_EN]);
	516	if (IS_ERR(pc->pwm_cpt_en))
	517	return PTR_ERR(pc->pwm_cpt_en);
	518
c5f94ae6	519	pc->pwm_cpt_int_en = devm_regmap_field_alloc(dev, pc->regmap,
7d8a600c	520	reg_fields[PWM_CPT_INT_EN]);
c5f94ae6 LJ	521	if (IS_ERR(pc->pwm_cpt_int_en))
c5f94ae6 LJ	522	return PTR_ERR(pc->pwm_cpt_int_en);
378fe115	523
25eb5380 LJ	524	pc->pwm_cpt_int_stat = devm_regmap_field_alloc(dev, pc->regmap,
	525	reg_fields[PWM_CPT_INT_STAT]);
	526	if (PTR_ERR_OR_ZERO(pc->pwm_cpt_int_stat))
	527	return PTR_ERR(pc->pwm_cpt_int_stat);
	528
378fe115 LJ	529	return 0;
	530	}
	531
	532	static const struct regmap_config sti_pwm_regmap_config = {
	533	.reg_bits = 32,
	534	.val_bits = 32,
	535	.reg_stride = 4,
	536	};
	537
	538	static int sti_pwm_probe(struct platform_device *pdev)
	539	{
	540	struct device *dev = &pdev->dev;
	541	struct sti_pwm_compat_data *cdata;
	542	struct sti_pwm_chip *pc;
	543	struct resource *res;
3f0925b5	544	unsigned int i;
25eb5380	545	int irq, ret;
378fe115 LJ	546
	547	pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
	548	if (!pc)
	549	return -ENOMEM;
	550
	551	cdata = devm_kzalloc(dev, sizeof(*cdata), GFP_KERNEL);
	552	if (!cdata)
	553	return -ENOMEM;
	554
	555	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	556
	557	pc->mmio = devm_ioremap_resource(dev, res);
	558	if (IS_ERR(pc->mmio))
	559	return PTR_ERR(pc->mmio);
	560
	561	pc->regmap = devm_regmap_init_mmio(dev, pc->mmio,
	562	&sti_pwm_regmap_config);
	563	if (IS_ERR(pc->regmap))
	564	return PTR_ERR(pc->regmap);
	565
25eb5380	566	irq = platform_get_irq(pdev, 0);
fb5a35db	567	if (irq < 0)
25eb5380	568	return irq;
25eb5380 LJ	569
	570	ret = devm_request_irq(&pdev->dev, irq, sti_pwm_interrupt, 0,
	571	pdev->name, pc);
	572	if (ret < 0) {
	573	dev_err(&pdev->dev, "Failed to request IRQ\n");
	574	return ret;
	575	}
	576
378fe115 LJ	577	/*
	578	* Setup PWM data with default values: some values could be replaced
	579	* with specific ones provided from Device Tree.
	580	*/
7d8a600c	581	cdata->reg_fields = sti_pwm_regfields;
378fe115	582	cdata->max_prescale = 0xff;
7d8a600c	583	cdata->max_pwm_cnt = 255;
85a834c4	584	cdata->pwm_num_devs = 0;
3f0925b5	585	cdata->cpt_num_devs = 0;
378fe115 LJ	586
	587	pc->cdata = cdata;
	588	pc->dev = dev;
6ad6b838 APS	589	pc->en_count = 0;
6ad6b838 APS	590	mutex_init(&pc->sti_pwm_lock);
378fe115 LJ	591
	592	ret = sti_pwm_probe_dt(pc);
	593	if (ret)
	594	return ret;
	595
85a834c4 LJ	596	if (!cdata->pwm_num_devs)
	597	goto skip_pwm;
	598
c5f94ae6 LJ	599	pc->pwm_clk = of_clk_get_by_name(dev->of_node, "pwm");
c5f94ae6 LJ	600	if (IS_ERR(pc->pwm_clk)) {
378fe115	601	dev_err(dev, "failed to get PWM clock\n");
c5f94ae6	602	return PTR_ERR(pc->pwm_clk);
378fe115 LJ	603	}
378fe115 LJ	604
c5f94ae6	605	ret = clk_prepare(pc->pwm_clk);
378fe115 LJ	606	if (ret) {
	607	dev_err(dev, "failed to prepare clock\n");
	608	return ret;
	609	}
	610
85a834c4 LJ	611	skip_pwm:
	612	if (!cdata->cpt_num_devs)
	613	goto skip_cpt;
	614
d66a928d LJ	615	pc->cpt_clk = of_clk_get_by_name(dev->of_node, "capture");
	616	if (IS_ERR(pc->cpt_clk)) {
	617	dev_err(dev, "failed to get PWM capture clock\n");
	618	return PTR_ERR(pc->cpt_clk);
	619	}
	620
	621	ret = clk_prepare(pc->cpt_clk);
	622	if (ret) {
	623	dev_err(dev, "failed to prepare clock\n");
	624	return ret;
	625	}
	626
85a834c4	627	skip_cpt:
378fe115 LJ	628	pc->chip.dev = dev;
	629	pc->chip.ops = &sti_pwm_ops;
	630	pc->chip.base = -1;
3f0925b5	631	pc->chip.npwm = pc->cdata->pwm_num_devs;
378fe115 LJ	632
	633	ret = pwmchip_add(&pc->chip);
	634	if (ret < 0) {
c5f94ae6	635	clk_unprepare(pc->pwm_clk);
d66a928d	636	clk_unprepare(pc->cpt_clk);
378fe115 LJ	637	return ret;
	638	}
	639
3f0925b5 LJ	640	for (i = 0; i < cdata->cpt_num_devs; i++) {
	641	struct sti_cpt_ddata *ddata;
	642
	643	ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
	644	if (!ddata)
	645	return -ENOMEM;
	646
	647	init_waitqueue_head(&ddata->wait);
	648	mutex_init(&ddata->lock);
	649
	650	pwm_set_chip_data(&pc->chip.pwms[i], ddata);
	651	}
	652
378fe115 LJ	653	platform_set_drvdata(pdev, pc);
	654
	655	return 0;
	656	}
	657
	658	static int sti_pwm_remove(struct platform_device *pdev)
	659	{
	660	struct sti_pwm_chip *pc = platform_get_drvdata(pdev);
	661	unsigned int i;
	662
3f0925b5	663	for (i = 0; i < pc->cdata->pwm_num_devs; i++)
378fe115 LJ	664	pwm_disable(&pc->chip.pwms[i]);
378fe115 LJ	665
c5f94ae6	666	clk_unprepare(pc->pwm_clk);
d66a928d	667	clk_unprepare(pc->cpt_clk);
378fe115 LJ	668
	669	return pwmchip_remove(&pc->chip);
	670	}
	671
	672	static const struct of_device_id sti_pwm_of_match[] = {
	673	{ .compatible = "st,sti-pwm", },
	674	{ /* sentinel */ }
	675	};
	676	MODULE_DEVICE_TABLE(of, sti_pwm_of_match);
	677
	678	static struct platform_driver sti_pwm_driver = {
	679	.driver = {
	680	.name = "sti-pwm",
	681	.of_match_table = sti_pwm_of_match,
	682	},
	683	.probe = sti_pwm_probe,
	684	.remove = sti_pwm_remove,
	685	};
	686	module_platform_driver(sti_pwm_driver);
	687
	688	MODULE_AUTHOR("Ajit Pal Singh <ajitpal.singh@st.com>");
	689	MODULE_DESCRIPTION("STMicroelectronics ST PWM driver");
	690	MODULE_LICENSE("GPL");