[mirror_ubuntu-jammy-kernel.git] / drivers / pwm / pwm-stm32.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) STMicroelectronics 2016
 *
 * Author: Gerald Baeza <gerald.baeza@st.com>
 *
 * Inspired by timer-stm32.c from Maxime Coquelin
 *             pwm-atmel.c from Bo Shen
 */

#include <linux/bitfield.h>
#include <linux/mfd/stm32-timers.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>

#define CCMR_CHANNEL_SHIFT 8
#define CCMR_CHANNEL_MASK  0xFF
#define MAX_BREAKINPUT 2

struct stm32_breakinput {
	u32 index;
	u32 level;
	u32 filter;
};

struct stm32_pwm {
	struct pwm_chip chip;
	struct mutex lock; /* protect pwm config/enable */
	struct clk *clk;
	struct regmap *regmap;
	u32 max_arr;
	bool have_complementary_output;
	struct stm32_breakinput breakinputs[MAX_BREAKINPUT];
	unsigned int num_breakinputs;
	u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */
};

static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip)
{
	return container_of(chip, struct stm32_pwm, chip);
}

static u32 active_channels(struct stm32_pwm *dev)
{
	u32 ccer;

	regmap_read(dev->regmap, TIM_CCER, &ccer);

	return ccer & TIM_CCER_CCXE;
}

static int write_ccrx(struct stm32_pwm *dev, int ch, u32 value)
{
	switch (ch) {
	case 0:
		return regmap_write(dev->regmap, TIM_CCR1, value);
	case 1:
		return regmap_write(dev->regmap, TIM_CCR2, value);
	case 2:
		return regmap_write(dev->regmap, TIM_CCR3, value);
	case 3:
		return regmap_write(dev->regmap, TIM_CCR4, value);
	}
	return -EINVAL;
}

#define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P)
#define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E)
#define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P)
#define TIM_CCER_CC34E (TIM_CCER_CC3E | TIM_CCER_CC4E)

/*
 * Capture using PWM input mode:
 *                              ___          ___
 * TI[1, 2, 3 or 4]: ........._|   |________|
 *                             ^0  ^1       ^2
 *                              .   .        .
 *                              .   .        XXXXX
 *                              .   .   XXXXX     |
 *                              .  XXXXX     .    |
 *                            XXXXX .        .    |
 * COUNTER:        ______XXXXX  .   .        .    |_XXX
 *                 start^       .   .        .        ^stop
 *                      .       .   .        .
 *                      v       v   .        v
 *                                  v
 * CCR1/CCR3:       tx..........t0...........t2
 * CCR2/CCR4:       tx..............t1.........
 *
 * DMA burst transfer:          |            |
 *                              v            v
 * DMA buffer:                  { t0, tx }   { t2, t1 }
 * DMA done:                                 ^
 *
 * 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
 *    + DMA transfer CCR[1/3] & CCR[2/4] values (t0, tx: doesn't care)
 * 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4
 * 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
 *    + DMA transfer CCR[1/3] & CCR[2/4] values (t2, t1)
 *
 * DMA done, compute:
 * - Period     = t2 - t0
 * - Duty cycle = t1 - t0
 */
static int stm32_pwm_raw_capture(struct stm32_pwm *priv, struct pwm_device *pwm,
				 unsigned long tmo_ms, u32 *raw_prd,
				 u32 *raw_dty)
{
	struct device *parent = priv->chip.dev->parent;
	enum stm32_timers_dmas dma_id;
	u32 ccen, ccr;
	int ret;

	/* Ensure registers have been updated, enable counter and capture */
	regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);

	/* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */
	dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3;
	ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E;
	ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3;
	regmap_update_bits(priv->regmap, TIM_CCER, ccen, ccen);

	/*
	 * Timer DMA burst mode. Request 2 registers, 2 bursts, to get both
	 * CCR1 & CCR2 (or CCR3 & CCR4) on each capture event.
	 * We'll get two capture snapchots: { CCR1, CCR2 }, { CCR1, CCR2 }
	 * or { CCR3, CCR4 }, { CCR3, CCR4 }
	 */
	ret = stm32_timers_dma_burst_read(parent, priv->capture, dma_id, ccr, 2,
					  2, tmo_ms);
	if (ret)
		goto stop;

	/* Period: t2 - t0 (take care of counter overflow) */
	if (priv->capture[0] <= priv->capture[2])
		*raw_prd = priv->capture[2] - priv->capture[0];
	else
		*raw_prd = priv->max_arr - priv->capture[0] + priv->capture[2];

	/* Duty cycle capture requires at least two capture units */
	if (pwm->chip->npwm < 2)
		*raw_dty = 0;
	else if (priv->capture[0] <= priv->capture[3])
		*raw_dty = priv->capture[3] - priv->capture[0];
	else
		*raw_dty = priv->max_arr - priv->capture[0] + priv->capture[3];

	if (*raw_dty > *raw_prd) {
		/*
		 * Race beetween PWM input and DMA: it may happen
		 * falling edge triggers new capture on TI2/4 before DMA
		 * had a chance to read CCR2/4. It means capture[1]
		 * contains period + duty_cycle. So, subtract period.
		 */
		*raw_dty -= *raw_prd;
	}

stop:
	regmap_update_bits(priv->regmap, TIM_CCER, ccen, 0);
	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);

	return ret;
}

static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm,
			     struct pwm_capture *result, unsigned long tmo_ms)
{
	struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
	unsigned long long prd, div, dty;
	unsigned long rate;
	unsigned int psc = 0, icpsc, scale;
	u32 raw_prd = 0, raw_dty = 0;
	int ret = 0;

	mutex_lock(&priv->lock);

	if (active_channels(priv)) {
		ret = -EBUSY;
		goto unlock;
	}

	ret = clk_enable(priv->clk);
	if (ret) {
		dev_err(priv->chip.dev, "failed to enable counter clock\n");
		goto unlock;
	}

	rate = clk_get_rate(priv->clk);
	if (!rate) {
		ret = -EINVAL;
		goto clk_dis;
	}

	/* prescaler: fit timeout window provided by upper layer */
	div = (unsigned long long)rate * (unsigned long long)tmo_ms;
	do_div(div, MSEC_PER_SEC);
	prd = div;
	while ((div > priv->max_arr) && (psc < MAX_TIM_PSC)) {
		psc++;
		div = prd;
		do_div(div, psc + 1);
	}
	regmap_write(priv->regmap, TIM_ARR, priv->max_arr);
	regmap_write(priv->regmap, TIM_PSC, psc);

	/* Map TI1 or TI2 PWM input to IC1 & IC2 (or TI3/4 to IC3 & IC4) */
	regmap_update_bits(priv->regmap,
			   pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
			   TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ?
			   TIM_CCMR_CC1S_TI2 | TIM_CCMR_CC2S_TI2 :
			   TIM_CCMR_CC1S_TI1 | TIM_CCMR_CC2S_TI1);

	/* Capture period on IC1/3 rising edge, duty cycle on IC2/4 falling. */
	regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ?
			   TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ?
			   TIM_CCER_CC2P : TIM_CCER_CC4P);

	ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty);
	if (ret)
		goto stop;

	/*
	 * Got a capture. Try to improve accuracy at high rates:
	 * - decrease counter clock prescaler, scale up to max rate.
	 * - use input prescaler, capture once every /2 /4 or /8 edges.
	 */
	if (raw_prd) {
		u32 max_arr = priv->max_arr - 0x1000; /* arbitrary margin */

		scale = max_arr / min(max_arr, raw_prd);
	} else {
		scale = priv->max_arr; /* bellow resolution, use max scale */
	}

	if (psc && scale > 1) {
		/* 2nd measure with new scale */
		psc /= scale;
		regmap_write(priv->regmap, TIM_PSC, psc);
		ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd,
					    &raw_dty);
		if (ret)
			goto stop;
	}

	/* Compute intermediate period not to exceed timeout at low rates */
	prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
	do_div(prd, rate);

	for (icpsc = 0; icpsc < MAX_TIM_ICPSC ; icpsc++) {
		/* input prescaler: also keep arbitrary margin */
		if (raw_prd >= (priv->max_arr - 0x1000) >> (icpsc + 1))
			break;
		if (prd >= (tmo_ms * NSEC_PER_MSEC) >> (icpsc + 2))
			break;
	}

	if (!icpsc)
		goto done;

	/* Last chance to improve period accuracy, using input prescaler */
	regmap_update_bits(priv->regmap,
			   pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
			   TIM_CCMR_IC1PSC | TIM_CCMR_IC2PSC,
			   FIELD_PREP(TIM_CCMR_IC1PSC, icpsc) |
			   FIELD_PREP(TIM_CCMR_IC2PSC, icpsc));

	ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty);
	if (ret)
		goto stop;

	if (raw_dty >= (raw_prd >> icpsc)) {
		/*
		 * We may fall here using input prescaler, when input
		 * capture starts on high side (before falling edge).
		 * Example with icpsc to capture on each 4 events:
		 *
		 *       start   1st capture                     2nd capture
		 *         v     v                               v
		 *         ___   _____   _____   _____   _____   ____
		 * TI1..4     |__|    |__|    |__|    |__|    |__|
		 *            v  v    .  .    .  .    .       v  v
		 * icpsc1/3:  .  0    .  1    .  2    .  3    .  0
		 * icpsc2/4:  0       1       2       3       0
		 *            v  v                            v  v
		 * CCR1/3  ......t0..............................t2
		 * CCR2/4  ..t1..............................t1'...
		 *               .                            .  .
		 * Capture0:     .<----------------------------->.
		 * Capture1:     .<-------------------------->.  .
		 *               .                            .  .
		 * Period:       .<------>                    .  .
		 * Low side:                                  .<>.
		 *
		 * Result:
		 * - Period = Capture0 / icpsc
		 * - Duty = Period - Low side = Period - (Capture0 - Capture1)
		 */
		raw_dty = (raw_prd >> icpsc) - (raw_prd - raw_dty);
	}

done:
	prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
	result->period = DIV_ROUND_UP_ULL(prd, rate << icpsc);
	dty = (unsigned long long)raw_dty * (psc + 1) * NSEC_PER_SEC;
	result->duty_cycle = DIV_ROUND_UP_ULL(dty, rate);
stop:
	regmap_write(priv->regmap, TIM_CCER, 0);
	regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0);
	regmap_write(priv->regmap, TIM_PSC, 0);
clk_dis:
	clk_disable(priv->clk);
unlock:
	mutex_unlock(&priv->lock);

	return ret;
}

static int stm32_pwm_config(struct stm32_pwm *priv, int ch,
			    int duty_ns, int period_ns)
{
	unsigned long long prd, div, dty;
	unsigned int prescaler = 0;
	u32 ccmr, mask, shift;

	/* Period and prescaler values depends on clock rate */
	div = (unsigned long long)clk_get_rate(priv->clk) * period_ns;

	do_div(div, NSEC_PER_SEC);
	prd = div;

	while (div > priv->max_arr) {
		prescaler++;
		div = prd;
		do_div(div, prescaler + 1);
	}

	prd = div;

	if (prescaler > MAX_TIM_PSC)
		return -EINVAL;

	/*
	 * All channels share the same prescaler and counter so when two
	 * channels are active at the same time we can't change them
	 */
	if (active_channels(priv) & ~(1 << ch * 4)) {
		u32 psc, arr;

		regmap_read(priv->regmap, TIM_PSC, &psc);
		regmap_read(priv->regmap, TIM_ARR, &arr);

		if ((psc != prescaler) || (arr != prd - 1))
			return -EBUSY;
	}

	regmap_write(priv->regmap, TIM_PSC, prescaler);
	regmap_write(priv->regmap, TIM_ARR, prd - 1);
	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);

	/* Calculate the duty cycles */
	dty = prd * duty_ns;
	do_div(dty, period_ns);

	write_ccrx(priv, ch, dty);

	/* Configure output mode */
	shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;
	ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
	mask = CCMR_CHANNEL_MASK << shift;

	if (ch < 2)
		regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);
	else
		regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);

	regmap_update_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE, TIM_BDTR_MOE);

	return 0;
}

static int stm32_pwm_set_polarity(struct stm32_pwm *priv, int ch,
				  enum pwm_polarity polarity)
{
	u32 mask;

	mask = TIM_CCER_CC1P << (ch * 4);
	if (priv->have_complementary_output)
		mask |= TIM_CCER_CC1NP << (ch * 4);

	regmap_update_bits(priv->regmap, TIM_CCER, mask,
			   polarity == PWM_POLARITY_NORMAL ? 0 : mask);

	return 0;
}

static int stm32_pwm_enable(struct stm32_pwm *priv, int ch)
{
	u32 mask;
	int ret;

	ret = clk_enable(priv->clk);
	if (ret)
		return ret;

	/* Enable channel */
	mask = TIM_CCER_CC1E << (ch * 4);
	if (priv->have_complementary_output)
		mask |= TIM_CCER_CC1NE << (ch * 4);

	regmap_update_bits(priv->regmap, TIM_CCER, mask, mask);

	/* Make sure that registers are updated */
	regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);

	/* Enable controller */
	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);

	return 0;
}

static void stm32_pwm_disable(struct stm32_pwm *priv, int ch)
{
	u32 mask;

	/* Disable channel */
	mask = TIM_CCER_CC1E << (ch * 4);
	if (priv->have_complementary_output)
		mask |= TIM_CCER_CC1NE << (ch * 4);

	regmap_update_bits(priv->regmap, TIM_CCER, mask, 0);

	/* When all channels are disabled, we can disable the controller */
	if (!active_channels(priv))
		regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);

	clk_disable(priv->clk);
}

static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			   const struct pwm_state *state)
{
	bool enabled;
	struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
	int ret;

	enabled = pwm->state.enabled;

	if (enabled && !state->enabled) {
		stm32_pwm_disable(priv, pwm->hwpwm);
		return 0;
	}

	if (state->polarity != pwm->state.polarity)
		stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity);

	ret = stm32_pwm_config(priv, pwm->hwpwm,
			       state->duty_cycle, state->period);
	if (ret)
		return ret;

	if (!enabled && state->enabled)
		ret = stm32_pwm_enable(priv, pwm->hwpwm);

	return ret;
}

static int stm32_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm,
				  const struct pwm_state *state)
{
	struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
	int ret;

	/* protect common prescaler for all active channels */
	mutex_lock(&priv->lock);
	ret = stm32_pwm_apply(chip, pwm, state);
	mutex_unlock(&priv->lock);

	return ret;
}

static const struct pwm_ops stm32pwm_ops = {
	.owner = THIS_MODULE,
	.apply = stm32_pwm_apply_locked,
	.capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL,
};

static int stm32_pwm_set_breakinput(struct stm32_pwm *priv,
				    const struct stm32_breakinput *bi)
{
	u32 shift = TIM_BDTR_BKF_SHIFT(bi->index);
	u32 bke = TIM_BDTR_BKE(bi->index);
	u32 bkp = TIM_BDTR_BKP(bi->index);
	u32 bkf = TIM_BDTR_BKF(bi->index);
	u32 mask = bkf | bkp | bke;
	u32 bdtr;

	bdtr = (bi->filter & TIM_BDTR_BKF_MASK) << shift | bke;

	if (bi->level)
		bdtr |= bkp;

	regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr);

	regmap_read(priv->regmap, TIM_BDTR, &bdtr);

	return (bdtr & bke) ? 0 : -EINVAL;
}

static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv)
{
	unsigned int i;
	int ret;

	for (i = 0; i < priv->num_breakinputs; i++) {
		ret = stm32_pwm_set_breakinput(priv, &priv->breakinputs[i]);
		if (ret < 0)
			return ret;
	}

	return 0;
}

static int stm32_pwm_probe_breakinputs(struct stm32_pwm *priv,
				       struct device_node *np)
{
	int nb, ret, array_size;
	unsigned int i;

	nb = of_property_count_elems_of_size(np, "st,breakinput",
					     sizeof(struct stm32_breakinput));

	/*
	 * Because "st,breakinput" parameter is optional do not make probe
	 * failed if it doesn't exist.
	 */
	if (nb <= 0)
		return 0;

	if (nb > MAX_BREAKINPUT)
		return -EINVAL;

	priv->num_breakinputs = nb;
	array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32);
	ret = of_property_read_u32_array(np, "st,breakinput",
					 (u32 *)priv->breakinputs, array_size);
	if (ret)
		return ret;

	for (i = 0; i < priv->num_breakinputs; i++) {
		if (priv->breakinputs[i].index > 1 ||
		    priv->breakinputs[i].level > 1 ||
		    priv->breakinputs[i].filter > 15)
			return -EINVAL;
	}

	return stm32_pwm_apply_breakinputs(priv);
}

static void stm32_pwm_detect_complementary(struct stm32_pwm *priv)
{
	u32 ccer;

	/*
	 * If complementary bit doesn't exist writing 1 will have no
	 * effect so we can detect it.
	 */
	regmap_update_bits(priv->regmap,
			   TIM_CCER, TIM_CCER_CC1NE, TIM_CCER_CC1NE);
	regmap_read(priv->regmap, TIM_CCER, &ccer);
	regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE, 0);

	priv->have_complementary_output = (ccer != 0);
}

static int stm32_pwm_detect_channels(struct stm32_pwm *priv)
{
	u32 ccer;
	int npwm = 0;

	/*
	 * If channels enable bits don't exist writing 1 will have no
	 * effect so we can detect and count them.
	 */
	regmap_update_bits(priv->regmap,
			   TIM_CCER, TIM_CCER_CCXE, TIM_CCER_CCXE);
	regmap_read(priv->regmap, TIM_CCER, &ccer);
	regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE, 0);

	if (ccer & TIM_CCER_CC1E)
		npwm++;

	if (ccer & TIM_CCER_CC2E)
		npwm++;

	if (ccer & TIM_CCER_CC3E)
		npwm++;

	if (ccer & TIM_CCER_CC4E)
		npwm++;

	return npwm;
}

static int stm32_pwm_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
	struct stm32_pwm *priv;
	int ret;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	mutex_init(&priv->lock);
	priv->regmap = ddata->regmap;
	priv->clk = ddata->clk;
	priv->max_arr = ddata->max_arr;

	if (!priv->regmap || !priv->clk)
		return -EINVAL;

	ret = stm32_pwm_probe_breakinputs(priv, np);
	if (ret)
		return ret;

	stm32_pwm_detect_complementary(priv);

	priv->chip.dev = dev;
	priv->chip.ops = &stm32pwm_ops;
	priv->chip.npwm = stm32_pwm_detect_channels(priv);

	ret = pwmchip_add(&priv->chip);
	if (ret < 0)
		return ret;

	platform_set_drvdata(pdev, priv);

	return 0;
}

static int stm32_pwm_remove(struct platform_device *pdev)
{
	struct stm32_pwm *priv = platform_get_drvdata(pdev);
	unsigned int i;

	for (i = 0; i < priv->chip.npwm; i++)
		pwm_disable(&priv->chip.pwms[i]);

	pwmchip_remove(&priv->chip);

	return 0;
}

static int __maybe_unused stm32_pwm_suspend(struct device *dev)
{
	struct stm32_pwm *priv = dev_get_drvdata(dev);
	unsigned int i;
	u32 ccer, mask;

	/* Look for active channels */
	ccer = active_channels(priv);

	for (i = 0; i < priv->chip.npwm; i++) {
		mask = TIM_CCER_CC1E << (i * 4);
		if (ccer & mask) {
			dev_err(dev, "PWM %u still in use by consumer %s\n",
				i, priv->chip.pwms[i].label);
			return -EBUSY;
		}
	}

	return pinctrl_pm_select_sleep_state(dev);
}

static int __maybe_unused stm32_pwm_resume(struct device *dev)
{
	struct stm32_pwm *priv = dev_get_drvdata(dev);
	int ret;

	ret = pinctrl_pm_select_default_state(dev);
	if (ret)
		return ret;

	/* restore breakinput registers that may have been lost in low power */
	return stm32_pwm_apply_breakinputs(priv);
}

static SIMPLE_DEV_PM_OPS(stm32_pwm_pm_ops, stm32_pwm_suspend, stm32_pwm_resume);

static const struct of_device_id stm32_pwm_of_match[] = {
	{ .compatible = "st,stm32-pwm",	},
	{ /* end node */ },
};
MODULE_DEVICE_TABLE(of, stm32_pwm_of_match);

static struct platform_driver stm32_pwm_driver = {
	.probe	= stm32_pwm_probe,
	.remove	= stm32_pwm_remove,
	.driver	= {
		.name = "stm32-pwm",
		.of_match_table = stm32_pwm_of_match,
		.pm = &stm32_pwm_pm_ops,
	},
};
module_platform_driver(stm32_pwm_driver);

MODULE_ALIAS("platform:stm32-pwm");
MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
d7a131d3	1	// SPDX-License-Identifier: GPL-2.0
7edf7369 BG	2	/*
	3	* Copyright (C) STMicroelectronics 2016
	4	*
	5	* Author: Gerald Baeza <gerald.baeza@st.com>
	6	*
7edf7369 BG	7	* Inspired by timer-stm32.c from Maxime Coquelin
	8	* pwm-atmel.c from Bo Shen
	9	*/
	10
ab3a8978	11	#include <linux/bitfield.h>
7edf7369 BG	12	#include <linux/mfd/stm32-timers.h>
	13	#include <linux/module.h>
	14	#include <linux/of.h>
2d3aa06b	15	#include <linux/pinctrl/consumer.h>
7edf7369 BG	16	#include <linux/platform_device.h>
	17	#include <linux/pwm.h>
	18
	19	#define CCMR_CHANNEL_SHIFT 8
	20	#define CCMR_CHANNEL_MASK 0xFF
	21	#define MAX_BREAKINPUT 2
	22
0f9d2ecb FG	23	struct stm32_breakinput {
	24	u32 index;
	25	u32 level;
	26	u32 filter;
	27	};
	28
7edf7369 BG	29	struct stm32_pwm {
7edf7369 BG	30	struct pwm_chip chip;
4eb67a20	31	struct mutex lock; /* protect pwm config/enable */
7edf7369 BG	32	struct clk *clk;
	33	struct regmap *regmap;
	34	u32 max_arr;
	35	bool have_complementary_output;
0f9d2ecb FG	36	struct stm32_breakinput breakinputs[MAX_BREAKINPUT];
0f9d2ecb FG	37	unsigned int num_breakinputs;
53e38fe7	38	u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */
7edf7369 BG	39	};
7edf7369 BG	40
7edf7369 BG	41	static inline struct stm32_pwm to_stm32_pwm_dev(struct pwm_chip chip)
	42	{
	43	return container_of(chip, struct stm32_pwm, chip);
	44	}
	45
	46	static u32 active_channels(struct stm32_pwm *dev)
	47	{
	48	u32 ccer;
	49
	50	regmap_read(dev->regmap, TIM_CCER, &ccer);
	51
	52	return ccer & TIM_CCER_CCXE;
	53	}
	54
	55	static int write_ccrx(struct stm32_pwm *dev, int ch, u32 value)
	56	{
	57	switch (ch) {
	58	case 0:
	59	return regmap_write(dev->regmap, TIM_CCR1, value);
	60	case 1:
	61	return regmap_write(dev->regmap, TIM_CCR2, value);
	62	case 2:
	63	return regmap_write(dev->regmap, TIM_CCR3, value);
	64	case 3:
	65	return regmap_write(dev->regmap, TIM_CCR4, value);
	66	}
	67	return -EINVAL;
	68	}
	69
53e38fe7 FG	70	#define TIM_CCER_CC12P (TIM_CCER_CC1P \| TIM_CCER_CC2P)
	71	#define TIM_CCER_CC12E (TIM_CCER_CC1E \| TIM_CCER_CC2E)
	72	#define TIM_CCER_CC34P (TIM_CCER_CC3P \| TIM_CCER_CC4P)
	73	#define TIM_CCER_CC34E (TIM_CCER_CC3E \| TIM_CCER_CC4E)
	74
	75	/*
	76	* Capture using PWM input mode:
	77	* ___ ___
	78	* TI[1, 2, 3 or 4]: ........._\| \|________\|
	79	* ^0 ^1 ^2
	80	* . . .
	81	* . . XXXXX
	82	* . . XXXXX \|
	83	* . XXXXX . \|
	84	* XXXXX . . \|
	85	* COUNTER: ______XXXXX . . . \|_XXX
	86	* start^ . . . ^stop
	87	* . . . .
	88	* v v . v
	89	* v
	90	* CCR1/CCR3: tx..........t0...........t2
	91	* CCR2/CCR4: tx..............t1.........
	92	*
	93	* DMA burst transfer: \| \|
	94	* v v
	95	* DMA buffer: { t0, tx } { t2, t1 }
	96	* DMA done: ^
	97	*
	98	* 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
	99	* + DMA transfer CCR[1/3] & CCR[2/4] values (t0, tx: doesn't care)
	100	* 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4
	101	* 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
	102	* + DMA transfer CCR[1/3] & CCR[2/4] values (t2, t1)
	103	*
	104	* DMA done, compute:
	105	* - Period = t2 - t0
	106	* - Duty cycle = t1 - t0
	107	*/
	108	static int stm32_pwm_raw_capture(struct stm32_pwm priv, struct pwm_device pwm,
	109	unsigned long tmo_ms, u32 *raw_prd,
	110	u32 *raw_dty)
	111	{
	112	struct device *parent = priv->chip.dev->parent;
	113	enum stm32_timers_dmas dma_id;
	114	u32 ccen, ccr;
	115	int ret;
	116
	117	/* Ensure registers have been updated, enable counter and capture */
	118	regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
	119	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
	120
	121	/* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */
	122	dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3;
	123	ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E;
	124	ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3;
	125	regmap_update_bits(priv->regmap, TIM_CCER, ccen, ccen);
	126
	127	/*
	128	* Timer DMA burst mode. Request 2 registers, 2 bursts, to get both
	129	* CCR1 & CCR2 (or CCR3 & CCR4) on each capture event.
	130	* We'll get two capture snapchots: { CCR1, CCR2 }, { CCR1, CCR2 }
	131	* or { CCR3, CCR4 }, { CCR3, CCR4 }
	132	*/
	133	ret = stm32_timers_dma_burst_read(parent, priv->capture, dma_id, ccr, 2,
134	2, tmo_ms);
135	if (ret)
136	goto stop;
137
138	/* Period: t2 - t0 (take care of counter overflow) */
139	if (priv->capture[0] <= priv->capture[2])
140	*raw_prd = priv->capture[2] - priv->capture[0];
141	else
142	*raw_prd = priv->max_arr - priv->capture[0] + priv->capture[2];
143
144	/* Duty cycle capture requires at least two capture units */
145	if (pwm->chip->npwm < 2)
146	*raw_dty = 0;
147	else if (priv->capture[0] <= priv->capture[3])
148	*raw_dty = priv->capture[3] - priv->capture[0];
149	else
150	*raw_dty = priv->max_arr - priv->capture[0] + priv->capture[3];
151
152	if (raw_dty > raw_prd) {
153	/*
154	* Race beetween PWM input and DMA: it may happen
155	* falling edge triggers new capture on TI2/4 before DMA
156	* had a chance to read CCR2/4. It means capture[1]
157	* contains period + duty_cycle. So, subtract period.
158	*/
159	raw_dty -= raw_prd;
160	}
161
162	stop:
163	regmap_update_bits(priv->regmap, TIM_CCER, ccen, 0);
164	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
165
166	return ret;
167	}
168
169	static int stm32_pwm_capture(struct pwm_chip chip, struct pwm_device pwm,
170	struct pwm_capture *result, unsigned long tmo_ms)
171	{
172	struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
173	unsigned long long prd, div, dty;
174	unsigned long rate;
ab3a8978	175	unsigned int psc = 0, icpsc, scale;
a3b51be3	176	u32 raw_prd = 0, raw_dty = 0;
53e38fe7 FG	177	int ret = 0;
	178
	179	mutex_lock(&priv->lock);
	180
	181	if (active_channels(priv)) {
	182	ret = -EBUSY;
	183	goto unlock;
	184	}
	185
	186	ret = clk_enable(priv->clk);
	187	if (ret) {
	188	dev_err(priv->chip.dev, "failed to enable counter clock\n");
	189	goto unlock;
	190	}
	191
	192	rate = clk_get_rate(priv->clk);
	193	if (!rate) {
	194	ret = -EINVAL;
	195	goto clk_dis;
	196	}
	197
	198	/* prescaler: fit timeout window provided by upper layer */
	199	div = (unsigned long long)rate * (unsigned long long)tmo_ms;
	200	do_div(div, MSEC_PER_SEC);
	201	prd = div;
	202	while ((div > priv->max_arr) && (psc < MAX_TIM_PSC)) {
	203	psc++;
	204	div = prd;
	205	do_div(div, psc + 1);
	206	}
	207	regmap_write(priv->regmap, TIM_ARR, priv->max_arr);
	208	regmap_write(priv->regmap, TIM_PSC, psc);
	209
	210	/* Map TI1 or TI2 PWM input to IC1 & IC2 (or TI3/4 to IC3 & IC4) */
	211	regmap_update_bits(priv->regmap,
	212	pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
	213	TIM_CCMR_CC1S \| TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ?
	214	TIM_CCMR_CC1S_TI2 \| TIM_CCMR_CC2S_TI2 :
	215	TIM_CCMR_CC1S_TI1 \| TIM_CCMR_CC2S_TI1);
	216
	217	/* Capture period on IC1/3 rising edge, duty cycle on IC2/4 falling. */
	218	regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ?
	219	TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ?
	220	TIM_CCER_CC2P : TIM_CCER_CC4P);
	221
	222	ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty);
	223	if (ret)
	224	goto stop;
	225
d66ffb91 FG	226	/*
	227	* Got a capture. Try to improve accuracy at high rates:
	228	* - decrease counter clock prescaler, scale up to max rate.
ab3a8978	229	* - use input prescaler, capture once every /2 /4 or /8 edges.
d66ffb91 FG	230	*/
	231	if (raw_prd) {
	232	u32 max_arr = priv->max_arr - 0x1000; /* arbitrary margin */
	233
	234	scale = max_arr / min(max_arr, raw_prd);
	235	} else {
	236	scale = priv->max_arr; /* bellow resolution, use max scale */
	237	}
	238
	239	if (psc && scale > 1) {
	240	/* 2nd measure with new scale */
	241	psc /= scale;
	242	regmap_write(priv->regmap, TIM_PSC, psc);
	243	ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd,
	244	&raw_dty);
	245	if (ret)
	246	goto stop;
	247	}
	248
ab3a8978	249	/* Compute intermediate period not to exceed timeout at low rates */
53e38fe7	250	prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
ab3a8978 FG	251	do_div(prd, rate);
	252
	253	for (icpsc = 0; icpsc < MAX_TIM_ICPSC ; icpsc++) {
	254	/* input prescaler: also keep arbitrary margin */
	255	if (raw_prd >= (priv->max_arr - 0x1000) >> (icpsc + 1))
	256	break;
	257	if (prd >= (tmo_ms * NSEC_PER_MSEC) >> (icpsc + 2))
	258	break;
	259	}
	260
	261	if (!icpsc)
	262	goto done;
	263
	264	/* Last chance to improve period accuracy, using input prescaler */
	265	regmap_update_bits(priv->regmap,
	266	pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
	267	TIM_CCMR_IC1PSC \| TIM_CCMR_IC2PSC,
	268	FIELD_PREP(TIM_CCMR_IC1PSC, icpsc) \|
	269	FIELD_PREP(TIM_CCMR_IC2PSC, icpsc));
	270
	271	ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty);
	272	if (ret)
	273	goto stop;
	274
	275	if (raw_dty >= (raw_prd >> icpsc)) {
	276	/*
	277	* We may fall here using input prescaler, when input
	278	* capture starts on high side (before falling edge).
	279	* Example with icpsc to capture on each 4 events:
	280	*
	281	* start 1st capture 2nd capture
	282	* v v v
	283	* ___ _____ _____ _____ _____ ____
	284	* TI1..4 \|__\| \|__\| \|__\| \|__\| \|__\|
	285	* v v . . . . . v v
	286	* icpsc1/3: . 0 . 1 . 2 . 3 . 0
	287	* icpsc2/4: 0 1 2 3 0
	288	* v v v v
	289	* CCR1/3 ......t0..............................t2
	290	* CCR2/4 ..t1..............................t1'...
	291	* . . .
	292	* Capture0: .<----------------------------->.
	293	* Capture1: .<-------------------------->. .
	294	* . . .
	295	* Period: .<------> . .
	296	* Low side: .<>.
	297	*
	298	* Result:
	299	* - Period = Capture0 / icpsc
	300	* - Duty = Period - Low side = Period - (Capture0 - Capture1)
	301	*/
	302	raw_dty = (raw_prd >> icpsc) - (raw_prd - raw_dty);
	303	}
	304
	305	done:
	306	prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
	307	result->period = DIV_ROUND_UP_ULL(prd, rate << icpsc);
53e38fe7 FG	308	dty = (unsigned long long)raw_dty * (psc + 1) * NSEC_PER_SEC;
	309	result->duty_cycle = DIV_ROUND_UP_ULL(dty, rate);
	310	stop:
	311	regmap_write(priv->regmap, TIM_CCER, 0);
	312	regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0);
	313	regmap_write(priv->regmap, TIM_PSC, 0);
	314	clk_dis:
	315	clk_disable(priv->clk);
	316	unlock:
	317	mutex_unlock(&priv->lock);
	318
	319	return ret;
	320	}
	321
7edf7369 BG	322	static int stm32_pwm_config(struct stm32_pwm *priv, int ch,
	323	int duty_ns, int period_ns)
	324	{
	325	unsigned long long prd, div, dty;
	326	unsigned int prescaler = 0;
	327	u32 ccmr, mask, shift;
	328
	329	/* Period and prescaler values depends on clock rate */
	330	div = (unsigned long long)clk_get_rate(priv->clk) * period_ns;
	331
	332	do_div(div, NSEC_PER_SEC);
	333	prd = div;
	334
	335	while (div > priv->max_arr) {
	336	prescaler++;
	337	div = prd;
	338	do_div(div, prescaler + 1);
	339	}
	340
	341	prd = div;
	342
	343	if (prescaler > MAX_TIM_PSC)
	344	return -EINVAL;
	345
	346	/*
	347	* All channels share the same prescaler and counter so when two
	348	* channels are active at the same time we can't change them
	349	*/
	350	if (active_channels(priv) & ~(1 << ch * 4)) {
	351	u32 psc, arr;
	352
	353	regmap_read(priv->regmap, TIM_PSC, &psc);
	354	regmap_read(priv->regmap, TIM_ARR, &arr);
	355
	356	if ((psc != prescaler) \|\| (arr != prd - 1))
	357	return -EBUSY;
	358	}
	359
	360	regmap_write(priv->regmap, TIM_PSC, prescaler);
	361	regmap_write(priv->regmap, TIM_ARR, prd - 1);
	362	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
	363
	364	/* Calculate the duty cycles */
	365	dty = prd * duty_ns;
	366	do_div(dty, period_ns);
	367
	368	write_ccrx(priv, ch, dty);
	369
	370	/* Configure output mode */
	371	shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;
	372	ccmr = (TIM_CCMR_PE \| TIM_CCMR_M1) << shift;
	373	mask = CCMR_CHANNEL_MASK << shift;
	374
	375	if (ch < 2)
	376	regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);
	377	else
	378	regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);
	379
0c73201c	380	regmap_update_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE, TIM_BDTR_MOE);
7edf7369 BG	381
	382	return 0;
	383	}
	384
	385	static int stm32_pwm_set_polarity(struct stm32_pwm *priv, int ch,
	386	enum pwm_polarity polarity)
	387	{
	388	u32 mask;
	389
	390	mask = TIM_CCER_CC1P << (ch * 4);
	391	if (priv->have_complementary_output)
	392	mask \|= TIM_CCER_CC1NP << (ch * 4);
	393
	394	regmap_update_bits(priv->regmap, TIM_CCER, mask,
	395	polarity == PWM_POLARITY_NORMAL ? 0 : mask);
	396
	397	return 0;
	398	}
	399
	400	static int stm32_pwm_enable(struct stm32_pwm *priv, int ch)
	401	{
	402	u32 mask;
	403	int ret;
	404
	405	ret = clk_enable(priv->clk);
	406	if (ret)
	407	return ret;
	408
	409	/* Enable channel */
	410	mask = TIM_CCER_CC1E << (ch * 4);
	411	if (priv->have_complementary_output)
	412	mask \|= TIM_CCER_CC1NE << (ch * 4);
	413
	414	regmap_update_bits(priv->regmap, TIM_CCER, mask, mask);
	415
	416	/* Make sure that registers are updated */
	417	regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
	418
	419	/* Enable controller */
	420	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
	421
	422	return 0;
	423	}
	424
	425	static void stm32_pwm_disable(struct stm32_pwm *priv, int ch)
	426	{
	427	u32 mask;
	428
	429	/* Disable channel */
	430	mask = TIM_CCER_CC1E << (ch * 4);
	431	if (priv->have_complementary_output)
	432	mask \|= TIM_CCER_CC1NE << (ch * 4);
	433
	434	regmap_update_bits(priv->regmap, TIM_CCER, mask, 0);
	435
	436	/* When all channels are disabled, we can disable the controller */
	437	if (!active_channels(priv))
	438	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
	439
	440	clk_disable(priv->clk);
	441	}
	442
	443	static int stm32_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
71523d18	444	const struct pwm_state *state)
7edf7369 BG	445	{
	446	bool enabled;
	447	struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
	448	int ret;
	449
	450	enabled = pwm->state.enabled;
	451
	452	if (enabled && !state->enabled) {
	453	stm32_pwm_disable(priv, pwm->hwpwm);
	454	return 0;
	455	}
	456
	457	if (state->polarity != pwm->state.polarity)
	458	stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity);
	459
	460	ret = stm32_pwm_config(priv, pwm->hwpwm,
	461	state->duty_cycle, state->period);
	462	if (ret)
	463	return ret;
	464
	465	if (!enabled && state->enabled)
	466	ret = stm32_pwm_enable(priv, pwm->hwpwm);
	467
	468	return ret;
	469	}
	470
4eb67a20	471	static int stm32_pwm_apply_locked(struct pwm_chip chip, struct pwm_device pwm,
71523d18	472	const struct pwm_state *state)
4eb67a20 FG	473	{
	474	struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
	475	int ret;
	476
	477	/* protect common prescaler for all active channels */
	478	mutex_lock(&priv->lock);
	479	ret = stm32_pwm_apply(chip, pwm, state);
	480	mutex_unlock(&priv->lock);
	481
	482	return ret;
	483	}
	484
7edf7369 BG	485	static const struct pwm_ops stm32pwm_ops = {
7edf7369 BG	486	.owner = THIS_MODULE,
4eb67a20	487	.apply = stm32_pwm_apply_locked,
414c52b7	488	.capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL,
7edf7369 BG	489	};
	490
	491	static int stm32_pwm_set_breakinput(struct stm32_pwm *priv,
9e1b4999	492	const struct stm32_breakinput *bi)
7edf7369	493	{
9e1b4999 TR	494	u32 shift = TIM_BDTR_BKF_SHIFT(bi->index);
	495	u32 bke = TIM_BDTR_BKE(bi->index);
	496	u32 bkp = TIM_BDTR_BKP(bi->index);
	497	u32 bkf = TIM_BDTR_BKF(bi->index);
8e536225 TR	498	u32 mask = bkf \| bkp \| bke;
8e536225 TR	499	u32 bdtr;
7edf7369	500
9e1b4999	501	bdtr = (bi->filter & TIM_BDTR_BKF_MASK) << shift \| bke;
7edf7369	502
9e1b4999	503	if (bi->level)
8e536225	504	bdtr \|= bkp;
7edf7369 BG	505
	506	regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr);
	507
	508	regmap_read(priv->regmap, TIM_BDTR, &bdtr);
	509
	510	return (bdtr & bke) ? 0 : -EINVAL;
	511	}
	512
0f9d2ecb FG	513	static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv)
	514	{
	515	unsigned int i;
	516	int ret;
	517
	518	for (i = 0; i < priv->num_breakinputs; i++) {
9e1b4999	519	ret = stm32_pwm_set_breakinput(priv, &priv->breakinputs[i]);
0f9d2ecb FG	520	if (ret < 0)
	521	return ret;
	522	}
	523
	524	return 0;
	525	}
	526
	527	static int stm32_pwm_probe_breakinputs(struct stm32_pwm *priv,
7edf7369 BG	528	struct device_node *np)
7edf7369 BG	529	{
0f9d2ecb	530	int nb, ret, array_size;
8dfa620e	531	unsigned int i;
7edf7369 BG	532
	533	nb = of_property_count_elems_of_size(np, "st,breakinput",
	534	sizeof(struct stm32_breakinput));
	535
	536	/*
	537	* Because "st,breakinput" parameter is optional do not make probe
	538	* failed if it doesn't exist.
	539	*/
	540	if (nb <= 0)
	541	return 0;
	542
	543	if (nb > MAX_BREAKINPUT)
	544	return -EINVAL;
	545
0f9d2ecb	546	priv->num_breakinputs = nb;
7edf7369 BG	547	array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32);
7edf7369 BG	548	ret = of_property_read_u32_array(np, "st,breakinput",
0f9d2ecb	549	(u32 *)priv->breakinputs, array_size);
7edf7369 BG	550	if (ret)
	551	return ret;
	552
8dfa620e TR	553	for (i = 0; i < priv->num_breakinputs; i++) {
	554	if (priv->breakinputs[i].index > 1 \|\|
	555	priv->breakinputs[i].level > 1 \|\|
	556	priv->breakinputs[i].filter > 15)
	557	return -EINVAL;
	558	}
	559
0f9d2ecb	560	return stm32_pwm_apply_breakinputs(priv);
7edf7369 BG	561	}
	562
	563	static void stm32_pwm_detect_complementary(struct stm32_pwm *priv)
	564	{
	565	u32 ccer;
	566
	567	/*
	568	* If complementary bit doesn't exist writing 1 will have no
	569	* effect so we can detect it.
	570	*/
	571	regmap_update_bits(priv->regmap,
	572	TIM_CCER, TIM_CCER_CC1NE, TIM_CCER_CC1NE);
	573	regmap_read(priv->regmap, TIM_CCER, &ccer);
	574	regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE, 0);
	575
	576	priv->have_complementary_output = (ccer != 0);
	577	}
	578
	579	static int stm32_pwm_detect_channels(struct stm32_pwm *priv)
	580	{
	581	u32 ccer;
	582	int npwm = 0;
	583
	584	/*
	585	* If channels enable bits don't exist writing 1 will have no
	586	* effect so we can detect and count them.
	587	*/
	588	regmap_update_bits(priv->regmap,
	589	TIM_CCER, TIM_CCER_CCXE, TIM_CCER_CCXE);
	590	regmap_read(priv->regmap, TIM_CCER, &ccer);
	591	regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE, 0);
	592
	593	if (ccer & TIM_CCER_CC1E)
	594	npwm++;
	595
	596	if (ccer & TIM_CCER_CC2E)
	597	npwm++;
	598
	599	if (ccer & TIM_CCER_CC3E)
	600	npwm++;
	601
	602	if (ccer & TIM_CCER_CC4E)
	603	npwm++;
	604
	605	return npwm;
	606	}
	607
	608	static int stm32_pwm_probe(struct platform_device *pdev)
	609	{
	610	struct device *dev = &pdev->dev;
	611	struct device_node *np = dev->of_node;
	612	struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
	613	struct stm32_pwm *priv;
	614	int ret;
	615
	616	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	617	if (!priv)
	618	return -ENOMEM;
	619
4eb67a20	620	mutex_init(&priv->lock);
7edf7369 BG	621	priv->regmap = ddata->regmap;
	622	priv->clk = ddata->clk;
	623	priv->max_arr = ddata->max_arr;
	624
	625	if (!priv->regmap \|\| !priv->clk)
	626	return -EINVAL;
	627
0f9d2ecb	628	ret = stm32_pwm_probe_breakinputs(priv, np);
7edf7369 BG	629	if (ret)
	630	return ret;
	631
	632	stm32_pwm_detect_complementary(priv);
	633
7edf7369 BG	634	priv->chip.dev = dev;
	635	priv->chip.ops = &stm32pwm_ops;
	636	priv->chip.npwm = stm32_pwm_detect_channels(priv);
	637
	638	ret = pwmchip_add(&priv->chip);
	639	if (ret < 0)
	640	return ret;
	641
	642	platform_set_drvdata(pdev, priv);
	643
	644	return 0;
	645	}
	646
	647	static int stm32_pwm_remove(struct platform_device *pdev)
	648	{
	649	struct stm32_pwm *priv = platform_get_drvdata(pdev);
	650	unsigned int i;
	651
	652	for (i = 0; i < priv->chip.npwm; i++)
	653	pwm_disable(&priv->chip.pwms[i]);
	654
	655	pwmchip_remove(&priv->chip);
	656
	657	return 0;
	658	}
	659
2d3aa06b FG	660	static int __maybe_unused stm32_pwm_suspend(struct device *dev)
	661	{
	662	struct stm32_pwm *priv = dev_get_drvdata(dev);
	663	unsigned int i;
	664	u32 ccer, mask;
	665
	666	/* Look for active channels */
	667	ccer = active_channels(priv);
	668
	669	for (i = 0; i < priv->chip.npwm; i++) {
	670	mask = TIM_CCER_CC1E << (i * 4);
	671	if (ccer & mask) {
	672	dev_err(dev, "PWM %u still in use by consumer %s\n",
	673	i, priv->chip.pwms[i].label);
	674	return -EBUSY;
	675	}
	676	}
	677
	678	return pinctrl_pm_select_sleep_state(dev);
	679	}
	680
	681	static int __maybe_unused stm32_pwm_resume(struct device *dev)
	682	{
	683	struct stm32_pwm *priv = dev_get_drvdata(dev);
	684	int ret;
	685
	686	ret = pinctrl_pm_select_default_state(dev);
	687	if (ret)
	688	return ret;
	689
	690	/* restore breakinput registers that may have been lost in low power */
	691	return stm32_pwm_apply_breakinputs(priv);
	692	}
	693
	694	static SIMPLE_DEV_PM_OPS(stm32_pwm_pm_ops, stm32_pwm_suspend, stm32_pwm_resume);
	695
7edf7369 BG	696	static const struct of_device_id stm32_pwm_of_match[] = {
	697	{ .compatible = "st,stm32-pwm", },
	698	{ /* end node */ },
	699	};
	700	MODULE_DEVICE_TABLE(of, stm32_pwm_of_match);
	701
	702	static struct platform_driver stm32_pwm_driver = {
	703	.probe = stm32_pwm_probe,
	704	.remove = stm32_pwm_remove,
	705	.driver = {
	706	.name = "stm32-pwm",
	707	.of_match_table = stm32_pwm_of_match,
2d3aa06b	708	.pm = &stm32_pwm_pm_ops,
7edf7369 BG	709	},
	710	};
	711	module_platform_driver(stm32_pwm_driver);
	712
	713	MODULE_ALIAS("platform:stm32-pwm");
	714	MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver");
	715	MODULE_LICENSE("GPL v2");