[mirror_ubuntu-artful-kernel.git] / drivers / pwm / pwm-tegra.c

/*
 * drivers/pwm/pwm-tegra.c
 *
 * Tegra pulse-width-modulation controller driver
 *
 * Copyright (c) 2010, NVIDIA Corporation.
 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pwm.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/reset.h>

#define PWM_ENABLE	(1 << 31)
#define PWM_DUTY_WIDTH	8
#define PWM_DUTY_SHIFT	16
#define PWM_SCALE_WIDTH	13
#define PWM_SCALE_SHIFT	0

struct tegra_pwm_soc {
	unsigned int num_channels;
};

struct tegra_pwm_chip {
	struct pwm_chip chip;
	struct device *dev;

	struct clk *clk;
	struct reset_control*rst;

	void __iomem *regs;

	const struct tegra_pwm_soc *soc;
};

static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct tegra_pwm_chip, chip);
}

static inline u32 pwm_readl(struct tegra_pwm_chip *chip, unsigned int num)
{
	return readl(chip->regs + (num << 4));
}

static inline void pwm_writel(struct tegra_pwm_chip *chip, unsigned int num,
			     unsigned long val)
{
	writel(val, chip->regs + (num << 4));
}

static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
			    int duty_ns, int period_ns)
{
	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	unsigned long long c = duty_ns;
	unsigned long rate, hz;
	u32 val = 0;
	int err;

	/*
	 * Convert from duty_ns / period_ns to a fixed number of duty ticks
	 * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
	 * nearest integer during division.
	 */
	c *= (1 << PWM_DUTY_WIDTH);
	c += period_ns / 2;
	do_div(c, period_ns);

	val = (u32)c << PWM_DUTY_SHIFT;

	/*
	 * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
	 * cycles at the PWM clock rate will take period_ns nanoseconds.
	 */
	rate = clk_get_rate(pc->clk) >> PWM_DUTY_WIDTH;
	hz = NSEC_PER_SEC / period_ns;

	rate = (rate + (hz / 2)) / hz;

	/*
	 * Since the actual PWM divider is the register's frequency divider
	 * field minus 1, we need to decrement to get the correct value to
	 * write to the register.
	 */
	if (rate > 0)
		rate--;

	/*
	 * Make sure that the rate will fit in the register's frequency
	 * divider field.
	 */
	if (rate >> PWM_SCALE_WIDTH)
		return -EINVAL;

	val |= rate << PWM_SCALE_SHIFT;

	/*
	 * If the PWM channel is disabled, make sure to turn on the clock
	 * before writing the register. Otherwise, keep it enabled.
	 */
	if (!pwm_is_enabled(pwm)) {
		err = clk_prepare_enable(pc->clk);
		if (err < 0)
			return err;
	} else
		val |= PWM_ENABLE;

	pwm_writel(pc, pwm->hwpwm, val);

	/*
	 * If the PWM is not enabled, turn the clock off again to save power.
	 */
	if (!pwm_is_enabled(pwm))
		clk_disable_unprepare(pc->clk);

	return 0;
}

static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	int rc = 0;
	u32 val;

	rc = clk_prepare_enable(pc->clk);
	if (rc < 0)
		return rc;

	val = pwm_readl(pc, pwm->hwpwm);
	val |= PWM_ENABLE;
	pwm_writel(pc, pwm->hwpwm, val);

	return 0;
}

static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	u32 val;

	val = pwm_readl(pc, pwm->hwpwm);
	val &= ~PWM_ENABLE;
	pwm_writel(pc, pwm->hwpwm, val);

	clk_disable_unprepare(pc->clk);
}

static const struct pwm_ops tegra_pwm_ops = {
	.config = tegra_pwm_config,
	.enable = tegra_pwm_enable,
	.disable = tegra_pwm_disable,
	.owner = THIS_MODULE,
};

static int tegra_pwm_probe(struct platform_device *pdev)
{
	struct tegra_pwm_chip *pwm;
	struct resource *r;
	int ret;

	pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
	if (!pwm)
		return -ENOMEM;

	pwm->soc = of_device_get_match_data(&pdev->dev);
	pwm->dev = &pdev->dev;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	pwm->regs = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(pwm->regs))
		return PTR_ERR(pwm->regs);

	platform_set_drvdata(pdev, pwm);

	pwm->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(pwm->clk))
		return PTR_ERR(pwm->clk);

	pwm->rst = devm_reset_control_get(&pdev->dev, "pwm");
	if (IS_ERR(pwm->rst)) {
		ret = PTR_ERR(pwm->rst);
		dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);
		return ret;
	}

	reset_control_deassert(pwm->rst);

	pwm->chip.dev = &pdev->dev;
	pwm->chip.ops = &tegra_pwm_ops;
	pwm->chip.base = -1;
	pwm->chip.npwm = pwm->soc->num_channels;

	ret = pwmchip_add(&pwm->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
		reset_control_assert(pwm->rst);
		return ret;
	}

	return 0;
}

static int tegra_pwm_remove(struct platform_device *pdev)
{
	struct tegra_pwm_chip *pc = platform_get_drvdata(pdev);
	unsigned int i;
	int err;

	if (WARN_ON(!pc))
		return -ENODEV;

	err = clk_prepare_enable(pc->clk);
	if (err < 0)
		return err;

	for (i = 0; i < pc->chip.npwm; i++) {
		struct pwm_device *pwm = &pc->chip.pwms[i];

		if (!pwm_is_enabled(pwm))
			if (clk_prepare_enable(pc->clk) < 0)
				continue;

		pwm_writel(pc, i, 0);

		clk_disable_unprepare(pc->clk);
	}

	reset_control_assert(pc->rst);
	clk_disable_unprepare(pc->clk);

	return pwmchip_remove(&pc->chip);
}

static const struct tegra_pwm_soc tegra20_pwm_soc = {
	.num_channels = 4,
};

static const struct tegra_pwm_soc tegra186_pwm_soc = {
	.num_channels = 1,
};

static const struct of_device_id tegra_pwm_of_match[] = {
	{ .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
	{ .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
	{ }
};

MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);

static struct platform_driver tegra_pwm_driver = {
	.driver = {
		.name = "tegra-pwm",
		.of_match_table = tegra_pwm_of_match,
	},
	.probe = tegra_pwm_probe,
	.remove = tegra_pwm_remove,
};

module_platform_driver(tegra_pwm_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("NVIDIA Corporation");
MODULE_ALIAS("platform:tegra-pwm");
Commit	Line	Data
0134b932 TR	1	/*
	2	* drivers/pwm/pwm-tegra.c
	3	*
	4	* Tegra pulse-width-modulation controller driver
	5	*
	6	* Copyright (c) 2010, NVIDIA Corporation.
	7	* Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful, but WITHOUT
	15	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	16	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	17	* more details.
	18	*
	19	* You should have received a copy of the GNU General Public License along
	20	* with this program; if not, write to the Free Software Foundation, Inc.,
	21	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
	22	*/
	23
	24	#include <linux/clk.h>
	25	#include <linux/err.h>
	26	#include <linux/io.h>
	27	#include <linux/module.h>
	28	#include <linux/of.h>
e9be88a2	29	#include <linux/of_device.h>
0134b932 TR	30	#include <linux/pwm.h>
	31	#include <linux/platform_device.h>
	32	#include <linux/slab.h>
5dfbd2bd	33	#include <linux/reset.h>
0134b932 TR	34
	35	#define PWM_ENABLE (1 << 31)
	36	#define PWM_DUTY_WIDTH 8
	37	#define PWM_DUTY_SHIFT 16
	38	#define PWM_SCALE_WIDTH 13
	39	#define PWM_SCALE_SHIFT 0
	40
e9be88a2 LD	41	struct tegra_pwm_soc {
	42	unsigned int num_channels;
	43	};
	44
0134b932	45	struct tegra_pwm_chip {
e17c0b22 TR	46	struct pwm_chip chip;
e17c0b22 TR	47	struct device *dev;
0134b932	48
e17c0b22	49	struct clk *clk;
5dfbd2bd	50	struct reset_control*rst;
0134b932	51
4f57f5a0	52	void __iomem *regs;
e9be88a2 LD	53
e9be88a2 LD	54	const struct tegra_pwm_soc *soc;
0134b932 TR	55	};
	56
	57	static inline struct tegra_pwm_chip to_tegra_pwm_chip(struct pwm_chip chip)
	58	{
	59	return container_of(chip, struct tegra_pwm_chip, chip);
	60	}
	61
	62	static inline u32 pwm_readl(struct tegra_pwm_chip *chip, unsigned int num)
	63	{
4f57f5a0	64	return readl(chip->regs + (num << 4));
0134b932 TR	65	}
	66
	67	static inline void pwm_writel(struct tegra_pwm_chip *chip, unsigned int num,
	68	unsigned long val)
	69	{
4f57f5a0	70	writel(val, chip->regs + (num << 4));
0134b932 TR	71	}
	72
	73	static int tegra_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
	74	int duty_ns, int period_ns)
	75	{
	76	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
b979ed53	77	unsigned long long c = duty_ns;
0134b932 TR	78	unsigned long rate, hz;
	79	u32 val = 0;
	80	int err;
	81
	82	/*
	83	* Convert from duty_ns / period_ns to a fixed number of duty ticks
	84	* per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
	85	* nearest integer during division.
	86	*/
b979ed53 HBK	87	c *= (1 << PWM_DUTY_WIDTH);
b979ed53 HBK	88	c += period_ns / 2;
0134b932 TR	89	do_div(c, period_ns);
	90
	91	val = (u32)c << PWM_DUTY_SHIFT;
	92
	93	/*
	94	* Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
	95	* cycles at the PWM clock rate will take period_ns nanoseconds.
	96	*/
	97	rate = clk_get_rate(pc->clk) >> PWM_DUTY_WIDTH;
b65af27a	98	hz = NSEC_PER_SEC / period_ns;
0134b932 TR	99
	100	rate = (rate + (hz / 2)) / hz;
	101
	102	/*
	103	* Since the actual PWM divider is the register's frequency divider
	104	* field minus 1, we need to decrement to get the correct value to
	105	* write to the register.
	106	*/
	107	if (rate > 0)
	108	rate--;
	109
	110	/*
	111	* Make sure that the rate will fit in the register's frequency
	112	* divider field.
	113	*/
	114	if (rate >> PWM_SCALE_WIDTH)
	115	return -EINVAL;
	116
	117	val \|= rate << PWM_SCALE_SHIFT;
	118
	119	/*
	120	* If the PWM channel is disabled, make sure to turn on the clock
	121	* before writing the register. Otherwise, keep it enabled.
	122	*/
5c31252c	123	if (!pwm_is_enabled(pwm)) {
0134b932 TR	124	err = clk_prepare_enable(pc->clk);
	125	if (err < 0)
	126	return err;
	127	} else
	128	val \|= PWM_ENABLE;
	129
	130	pwm_writel(pc, pwm->hwpwm, val);
	131
	132	/*
	133	* If the PWM is not enabled, turn the clock off again to save power.
	134	*/
5c31252c	135	if (!pwm_is_enabled(pwm))
0134b932 TR	136	clk_disable_unprepare(pc->clk);
	137
	138	return 0;
	139	}
	140
	141	static int tegra_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
	142	{
	143	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	144	int rc = 0;
	145	u32 val;
	146
	147	rc = clk_prepare_enable(pc->clk);
	148	if (rc < 0)
	149	return rc;
	150
	151	val = pwm_readl(pc, pwm->hwpwm);
	152	val \|= PWM_ENABLE;
	153	pwm_writel(pc, pwm->hwpwm, val);
	154
	155	return 0;
	156	}
	157
	158	static void tegra_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
	159	{
	160	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	161	u32 val;
	162
	163	val = pwm_readl(pc, pwm->hwpwm);
	164	val &= ~PWM_ENABLE;
	165	pwm_writel(pc, pwm->hwpwm, val);
	166
	167	clk_disable_unprepare(pc->clk);
	168	}
	169
	170	static const struct pwm_ops tegra_pwm_ops = {
	171	.config = tegra_pwm_config,
	172	.enable = tegra_pwm_enable,
	173	.disable = tegra_pwm_disable,
	174	.owner = THIS_MODULE,
	175	};
	176
	177	static int tegra_pwm_probe(struct platform_device *pdev)
	178	{
	179	struct tegra_pwm_chip *pwm;
	180	struct resource *r;
	181	int ret;
	182
	183	pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
474b6902	184	if (!pwm)
0134b932	185	return -ENOMEM;
0134b932	186
e9be88a2	187	pwm->soc = of_device_get_match_data(&pdev->dev);
0134b932 TR	188	pwm->dev = &pdev->dev;
	189
	190	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4f57f5a0 TR	191	pwm->regs = devm_ioremap_resource(&pdev->dev, r);
	192	if (IS_ERR(pwm->regs))
	193	return PTR_ERR(pwm->regs);
0134b932 TR	194
	195	platform_set_drvdata(pdev, pwm);
	196
0c8f527d	197	pwm->clk = devm_clk_get(&pdev->dev, NULL);
0134b932 TR	198	if (IS_ERR(pwm->clk))
	199	return PTR_ERR(pwm->clk);
	200
5dfbd2bd RS	201	pwm->rst = devm_reset_control_get(&pdev->dev, "pwm");
	202	if (IS_ERR(pwm->rst)) {
	203	ret = PTR_ERR(pwm->rst);
	204	dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);
	205	return ret;
	206	}
	207
	208	reset_control_deassert(pwm->rst);
	209
0134b932 TR	210	pwm->chip.dev = &pdev->dev;
	211	pwm->chip.ops = &tegra_pwm_ops;
	212	pwm->chip.base = -1;
e9be88a2	213	pwm->chip.npwm = pwm->soc->num_channels;
0134b932 TR	214
	215	ret = pwmchip_add(&pwm->chip);
	216	if (ret < 0) {
	217	dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
5dfbd2bd	218	reset_control_assert(pwm->rst);
0134b932 TR	219	return ret;
	220	}
	221
	222	return 0;
	223	}
	224
77f37917	225	static int tegra_pwm_remove(struct platform_device *pdev)
0134b932 TR	226	{
0134b932 TR	227	struct tegra_pwm_chip *pc = platform_get_drvdata(pdev);
c009c564	228	unsigned int i;
5dfbd2bd	229	int err;
0134b932 TR	230
	231	if (WARN_ON(!pc))
	232	return -ENODEV;
	233
5dfbd2bd RS	234	err = clk_prepare_enable(pc->clk);
	235	if (err < 0)
	236	return err;
	237
c009c564	238	for (i = 0; i < pc->chip.npwm; i++) {
0134b932 TR	239	struct pwm_device *pwm = &pc->chip.pwms[i];
0134b932 TR	240
5c31252c	241	if (!pwm_is_enabled(pwm))
0134b932 TR	242	if (clk_prepare_enable(pc->clk) < 0)
	243	continue;
	244
	245	pwm_writel(pc, i, 0);
	246
	247	clk_disable_unprepare(pc->clk);
	248	}
	249
5dfbd2bd RS	250	reset_control_assert(pc->rst);
	251	clk_disable_unprepare(pc->clk);
	252
0c8f527d	253	return pwmchip_remove(&pc->chip);
0134b932 TR	254	}
0134b932 TR	255
e9be88a2 LD	256	static const struct tegra_pwm_soc tegra20_pwm_soc = {
	257	.num_channels = 4,
	258	};
	259
	260	static const struct tegra_pwm_soc tegra186_pwm_soc = {
	261	.num_channels = 1,
	262	};
	263
f1a8870a	264	static const struct of_device_id tegra_pwm_of_match[] = {
e9be88a2 LD	265	{ .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
e9be88a2 LD	266	{ .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
140fd977 TR	267	{ }
	268	};
	269
	270	MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);
140fd977	271
0134b932 TR	272	static struct platform_driver tegra_pwm_driver = {
	273	.driver = {
	274	.name = "tegra-pwm",
838bf09d	275	.of_match_table = tegra_pwm_of_match,
0134b932 TR	276	},
0134b932 TR	277	.probe = tegra_pwm_probe,
fd109112	278	.remove = tegra_pwm_remove,
0134b932 TR	279	};
	280
	281	module_platform_driver(tegra_pwm_driver);
	282
	283	MODULE_LICENSE("GPL");
	284	MODULE_AUTHOR("NVIDIA Corporation");
	285	MODULE_ALIAS("platform:tegra-pwm");