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Commit | Line | Data |
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21f47fbc | 1 | /* |
261995dd | 2 | * drivers/pwm/pwm-vt8500.c |
21f47fbc | 3 | * |
63e1ed23 TP |
4 | * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> |
5 | * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> | |
21f47fbc AC |
6 | * |
7 | * This software is licensed under the terms of the GNU General Public | |
8 | * License version 2, as published by the Free Software Foundation, and | |
9 | * may be copied, distributed, and modified under those terms. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/module.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/err.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/pwm.h> | |
24 | #include <linux/delay.h> | |
63e1ed23 | 25 | #include <linux/clk.h> |
21f47fbc AC |
26 | |
27 | #include <asm/div64.h> | |
28 | ||
63e1ed23 TP |
29 | #include <linux/of.h> |
30 | #include <linux/of_device.h> | |
31 | #include <linux/of_address.h> | |
32 | ||
33 | /* | |
34 | * SoC architecture allocates register space for 4 PWMs but only | |
35 | * 2 are currently implemented. | |
36 | */ | |
37 | #define VT8500_NR_PWMS 2 | |
21f47fbc | 38 | |
a245cceb SH |
39 | struct vt8500_chip { |
40 | struct pwm_chip chip; | |
41 | void __iomem *base; | |
63e1ed23 | 42 | struct clk *clk; |
21f47fbc AC |
43 | }; |
44 | ||
a245cceb SH |
45 | #define to_vt8500_chip(chip) container_of(chip, struct vt8500_chip, chip) |
46 | ||
21f47fbc AC |
47 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) |
48 | static inline void pwm_busy_wait(void __iomem *reg, u8 bitmask) | |
49 | { | |
50 | int loops = msecs_to_loops(10); | |
51 | while ((readb(reg) & bitmask) && --loops) | |
52 | cpu_relax(); | |
53 | ||
54 | if (unlikely(!loops)) | |
eba7cbe5 | 55 | pr_warn("Waiting for status bits 0x%x to clear timed out\n", |
21f47fbc AC |
56 | bitmask); |
57 | } | |
58 | ||
a245cceb SH |
59 | static int vt8500_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, |
60 | int duty_ns, int period_ns) | |
21f47fbc | 61 | { |
a245cceb | 62 | struct vt8500_chip *vt8500 = to_vt8500_chip(chip); |
21f47fbc AC |
63 | unsigned long long c; |
64 | unsigned long period_cycles, prescale, pv, dc; | |
65 | ||
63e1ed23 | 66 | c = clk_get_rate(vt8500->clk); |
21f47fbc AC |
67 | c = c * period_ns; |
68 | do_div(c, 1000000000); | |
69 | period_cycles = c; | |
70 | ||
71 | if (period_cycles < 1) | |
72 | period_cycles = 1; | |
73 | prescale = (period_cycles - 1) / 4096; | |
74 | pv = period_cycles / (prescale + 1) - 1; | |
75 | if (pv > 4095) | |
76 | pv = 4095; | |
77 | ||
78 | if (prescale > 1023) | |
79 | return -EINVAL; | |
80 | ||
81 | c = (unsigned long long)pv * duty_ns; | |
82 | do_div(c, period_ns); | |
83 | dc = c; | |
84 | ||
a245cceb SH |
85 | pwm_busy_wait(vt8500->base + 0x40 + pwm->hwpwm, (1 << 1)); |
86 | writel(prescale, vt8500->base + 0x4 + (pwm->hwpwm << 4)); | |
21f47fbc | 87 | |
a245cceb SH |
88 | pwm_busy_wait(vt8500->base + 0x40 + pwm->hwpwm, (1 << 2)); |
89 | writel(pv, vt8500->base + 0x8 + (pwm->hwpwm << 4)); | |
21f47fbc | 90 | |
a245cceb SH |
91 | pwm_busy_wait(vt8500->base + 0x40 + pwm->hwpwm, (1 << 3)); |
92 | writel(dc, vt8500->base + 0xc + (pwm->hwpwm << 4)); | |
21f47fbc AC |
93 | |
94 | return 0; | |
95 | } | |
21f47fbc | 96 | |
a245cceb | 97 | static int vt8500_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
21f47fbc | 98 | { |
63e1ed23 | 99 | int err; |
a245cceb | 100 | struct vt8500_chip *vt8500 = to_vt8500_chip(chip); |
21f47fbc | 101 | |
63e1ed23 | 102 | err = clk_enable(vt8500->clk); |
2f9569f7 | 103 | if (err < 0) { |
63e1ed23 TP |
104 | dev_err(chip->dev, "failed to enable clock\n"); |
105 | return err; | |
106 | }; | |
107 | ||
a245cceb SH |
108 | pwm_busy_wait(vt8500->base + 0x40 + pwm->hwpwm, (1 << 0)); |
109 | writel(5, vt8500->base + (pwm->hwpwm << 4)); | |
110 | return 0; | |
21f47fbc | 111 | } |
21f47fbc | 112 | |
a245cceb | 113 | static void vt8500_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) |
21f47fbc | 114 | { |
a245cceb | 115 | struct vt8500_chip *vt8500 = to_vt8500_chip(chip); |
21f47fbc | 116 | |
a245cceb SH |
117 | pwm_busy_wait(vt8500->base + 0x40 + pwm->hwpwm, (1 << 0)); |
118 | writel(0, vt8500->base + (pwm->hwpwm << 4)); | |
63e1ed23 TP |
119 | |
120 | clk_disable(vt8500->clk); | |
21f47fbc | 121 | } |
21f47fbc | 122 | |
a245cceb SH |
123 | static struct pwm_ops vt8500_pwm_ops = { |
124 | .enable = vt8500_pwm_enable, | |
125 | .disable = vt8500_pwm_disable, | |
126 | .config = vt8500_pwm_config, | |
127 | .owner = THIS_MODULE, | |
128 | }; | |
21f47fbc | 129 | |
63e1ed23 TP |
130 | static const struct of_device_id vt8500_pwm_dt_ids[] = { |
131 | { .compatible = "via,vt8500-pwm", }, | |
132 | { /* Sentinel */ } | |
133 | }; | |
134 | MODULE_DEVICE_TABLE(of, vt8500_pwm_dt_ids); | |
135 | ||
136 | static int vt8500_pwm_probe(struct platform_device *pdev) | |
21f47fbc | 137 | { |
a245cceb | 138 | struct vt8500_chip *chip; |
21f47fbc | 139 | struct resource *r; |
63e1ed23 | 140 | struct device_node *np = pdev->dev.of_node; |
a245cceb | 141 | int ret; |
21f47fbc | 142 | |
63e1ed23 TP |
143 | if (!np) { |
144 | dev_err(&pdev->dev, "invalid devicetree node\n"); | |
145 | return -EINVAL; | |
146 | } | |
147 | ||
261995dd | 148 | chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); |
a245cceb | 149 | if (chip == NULL) { |
21f47fbc AC |
150 | dev_err(&pdev->dev, "failed to allocate memory\n"); |
151 | return -ENOMEM; | |
152 | } | |
153 | ||
a245cceb SH |
154 | chip->chip.dev = &pdev->dev; |
155 | chip->chip.ops = &vt8500_pwm_ops; | |
156 | chip->chip.base = -1; | |
157 | chip->chip.npwm = VT8500_NR_PWMS; | |
21f47fbc | 158 | |
63e1ed23 TP |
159 | chip->clk = devm_clk_get(&pdev->dev, NULL); |
160 | if (IS_ERR(chip->clk)) { | |
161 | dev_err(&pdev->dev, "clock source not specified\n"); | |
162 | return PTR_ERR(chip->clk); | |
163 | } | |
164 | ||
21f47fbc AC |
165 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
166 | if (r == NULL) { | |
167 | dev_err(&pdev->dev, "no memory resource defined\n"); | |
261995dd | 168 | return -ENODEV; |
21f47fbc AC |
169 | } |
170 | ||
261995dd | 171 | chip->base = devm_request_and_ioremap(&pdev->dev, r); |
63e1ed23 | 172 | if (!chip->base) |
261995dd | 173 | return -EADDRNOTAVAIL; |
21f47fbc | 174 | |
63e1ed23 TP |
175 | ret = clk_prepare(chip->clk); |
176 | if (ret < 0) { | |
177 | dev_err(&pdev->dev, "failed to prepare clock\n"); | |
178 | return ret; | |
179 | } | |
180 | ||
a245cceb | 181 | ret = pwmchip_add(&chip->chip); |
63e1ed23 TP |
182 | if (ret < 0) { |
183 | dev_err(&pdev->dev, "failed to add PWM chip\n"); | |
261995dd | 184 | return ret; |
63e1ed23 | 185 | } |
21f47fbc | 186 | |
a245cceb SH |
187 | platform_set_drvdata(pdev, chip); |
188 | return ret; | |
21f47fbc AC |
189 | } |
190 | ||
63e1ed23 | 191 | static int vt8500_pwm_remove(struct platform_device *pdev) |
21f47fbc | 192 | { |
a245cceb | 193 | struct vt8500_chip *chip; |
21f47fbc | 194 | |
a245cceb SH |
195 | chip = platform_get_drvdata(pdev); |
196 | if (chip == NULL) | |
21f47fbc AC |
197 | return -ENODEV; |
198 | ||
63e1ed23 TP |
199 | clk_unprepare(chip->clk); |
200 | ||
261995dd | 201 | return pwmchip_remove(&chip->chip); |
21f47fbc AC |
202 | } |
203 | ||
63e1ed23 TP |
204 | static struct platform_driver vt8500_pwm_driver = { |
205 | .probe = vt8500_pwm_probe, | |
206 | .remove = vt8500_pwm_remove, | |
21f47fbc AC |
207 | .driver = { |
208 | .name = "vt8500-pwm", | |
209 | .owner = THIS_MODULE, | |
63e1ed23 | 210 | .of_match_table = vt8500_pwm_dt_ids, |
21f47fbc | 211 | }, |
21f47fbc | 212 | }; |
63e1ed23 | 213 | module_platform_driver(vt8500_pwm_driver); |
21f47fbc | 214 | |
63e1ed23 TP |
215 | MODULE_DESCRIPTION("VT8500 PWM Driver"); |
216 | MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>"); | |
217 | MODULE_LICENSE("GPL v2"); |