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Commit | Line | Data |
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21f47fbc | 1 | /* |
261995dd | 2 | * drivers/pwm/pwm-vt8500.c |
21f47fbc | 3 | * |
63e1ed23 TP |
4 | * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> |
5 | * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> | |
21f47fbc AC |
6 | * |
7 | * This software is licensed under the terms of the GNU General Public | |
8 | * License version 2, as published by the Free Software Foundation, and | |
9 | * may be copied, distributed, and modified under those terms. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/module.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/err.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/pwm.h> | |
24 | #include <linux/delay.h> | |
63e1ed23 | 25 | #include <linux/clk.h> |
21f47fbc AC |
26 | |
27 | #include <asm/div64.h> | |
28 | ||
63e1ed23 TP |
29 | #include <linux/of.h> |
30 | #include <linux/of_device.h> | |
31 | #include <linux/of_address.h> | |
32 | ||
33 | /* | |
34 | * SoC architecture allocates register space for 4 PWMs but only | |
35 | * 2 are currently implemented. | |
36 | */ | |
37 | #define VT8500_NR_PWMS 2 | |
21f47fbc | 38 | |
8ab432ca TP |
39 | #define REG_CTRL(pwm) (((pwm) << 4) + 0x00) |
40 | #define REG_SCALAR(pwm) (((pwm) << 4) + 0x04) | |
41 | #define REG_PERIOD(pwm) (((pwm) << 4) + 0x08) | |
42 | #define REG_DUTY(pwm) (((pwm) << 4) + 0x0C) | |
43 | #define REG_STATUS 0x40 | |
44 | ||
45 | #define CTRL_ENABLE BIT(0) | |
46 | #define CTRL_INVERT BIT(1) | |
47 | #define CTRL_AUTOLOAD BIT(2) | |
48 | #define CTRL_STOP_IMM BIT(3) | |
49 | #define CTRL_LOAD_PRESCALE BIT(4) | |
50 | #define CTRL_LOAD_PERIOD BIT(5) | |
51 | ||
52 | #define STATUS_CTRL_UPDATE BIT(0) | |
53 | #define STATUS_SCALAR_UPDATE BIT(1) | |
54 | #define STATUS_PERIOD_UPDATE BIT(2) | |
55 | #define STATUS_DUTY_UPDATE BIT(3) | |
56 | #define STATUS_ALL_UPDATE 0x0F | |
57 | ||
a245cceb SH |
58 | struct vt8500_chip { |
59 | struct pwm_chip chip; | |
60 | void __iomem *base; | |
63e1ed23 | 61 | struct clk *clk; |
21f47fbc AC |
62 | }; |
63 | ||
a245cceb SH |
64 | #define to_vt8500_chip(chip) container_of(chip, struct vt8500_chip, chip) |
65 | ||
21f47fbc | 66 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) |
8ab432ca | 67 | static inline void pwm_busy_wait(struct vt8500_chip *vt8500, int nr, u8 bitmask) |
21f47fbc AC |
68 | { |
69 | int loops = msecs_to_loops(10); | |
8ab432ca TP |
70 | u32 mask = bitmask << (nr << 8); |
71 | ||
72 | while ((readl(vt8500->base + REG_STATUS) & mask) && --loops) | |
21f47fbc AC |
73 | cpu_relax(); |
74 | ||
75 | if (unlikely(!loops)) | |
8ab432ca TP |
76 | dev_warn(vt8500->chip.dev, "Waiting for status bits 0x%x to clear timed out\n", |
77 | mask); | |
21f47fbc AC |
78 | } |
79 | ||
a245cceb SH |
80 | static int vt8500_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, |
81 | int duty_ns, int period_ns) | |
21f47fbc | 82 | { |
a245cceb | 83 | struct vt8500_chip *vt8500 = to_vt8500_chip(chip); |
21f47fbc AC |
84 | unsigned long long c; |
85 | unsigned long period_cycles, prescale, pv, dc; | |
422470a8 | 86 | int err; |
8ab432ca | 87 | u32 val; |
422470a8 TP |
88 | |
89 | err = clk_enable(vt8500->clk); | |
90 | if (err < 0) { | |
91 | dev_err(chip->dev, "failed to enable clock\n"); | |
92 | return err; | |
93 | } | |
21f47fbc | 94 | |
63e1ed23 | 95 | c = clk_get_rate(vt8500->clk); |
21f47fbc AC |
96 | c = c * period_ns; |
97 | do_div(c, 1000000000); | |
98 | period_cycles = c; | |
99 | ||
100 | if (period_cycles < 1) | |
101 | period_cycles = 1; | |
102 | prescale = (period_cycles - 1) / 4096; | |
103 | pv = period_cycles / (prescale + 1) - 1; | |
104 | if (pv > 4095) | |
105 | pv = 4095; | |
106 | ||
422470a8 TP |
107 | if (prescale > 1023) { |
108 | clk_disable(vt8500->clk); | |
21f47fbc | 109 | return -EINVAL; |
422470a8 | 110 | } |
21f47fbc AC |
111 | |
112 | c = (unsigned long long)pv * duty_ns; | |
113 | do_div(c, period_ns); | |
114 | dc = c; | |
115 | ||
8ab432ca TP |
116 | writel(prescale, vt8500->base + REG_SCALAR(pwm->hwpwm)); |
117 | pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_SCALAR_UPDATE); | |
118 | ||
119 | writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm)); | |
120 | pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_PERIOD_UPDATE); | |
21f47fbc | 121 | |
8ab432ca TP |
122 | writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm)); |
123 | pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_DUTY_UPDATE); | |
21f47fbc | 124 | |
8ab432ca TP |
125 | val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); |
126 | val |= CTRL_AUTOLOAD; | |
127 | writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); | |
128 | pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE); | |
21f47fbc | 129 | |
422470a8 | 130 | clk_disable(vt8500->clk); |
21f47fbc AC |
131 | return 0; |
132 | } | |
21f47fbc | 133 | |
a245cceb | 134 | static int vt8500_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
21f47fbc | 135 | { |
a245cceb | 136 | struct vt8500_chip *vt8500 = to_vt8500_chip(chip); |
8ab432ca TP |
137 | int err; |
138 | u32 val; | |
21f47fbc | 139 | |
63e1ed23 | 140 | err = clk_enable(vt8500->clk); |
2f9569f7 | 141 | if (err < 0) { |
63e1ed23 TP |
142 | dev_err(chip->dev, "failed to enable clock\n"); |
143 | return err; | |
422470a8 | 144 | } |
63e1ed23 | 145 | |
8ab432ca TP |
146 | val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); |
147 | val |= CTRL_ENABLE; | |
148 | writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); | |
149 | pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE); | |
150 | ||
a245cceb | 151 | return 0; |
21f47fbc | 152 | } |
21f47fbc | 153 | |
a245cceb | 154 | static void vt8500_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) |
21f47fbc | 155 | { |
a245cceb | 156 | struct vt8500_chip *vt8500 = to_vt8500_chip(chip); |
8ab432ca | 157 | u32 val; |
21f47fbc | 158 | |
8ab432ca TP |
159 | val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); |
160 | val &= ~CTRL_ENABLE; | |
161 | writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); | |
162 | pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE); | |
63e1ed23 TP |
163 | |
164 | clk_disable(vt8500->clk); | |
21f47fbc | 165 | } |
21f47fbc | 166 | |
a245cceb SH |
167 | static struct pwm_ops vt8500_pwm_ops = { |
168 | .enable = vt8500_pwm_enable, | |
169 | .disable = vt8500_pwm_disable, | |
170 | .config = vt8500_pwm_config, | |
171 | .owner = THIS_MODULE, | |
172 | }; | |
21f47fbc | 173 | |
63e1ed23 TP |
174 | static const struct of_device_id vt8500_pwm_dt_ids[] = { |
175 | { .compatible = "via,vt8500-pwm", }, | |
176 | { /* Sentinel */ } | |
177 | }; | |
178 | MODULE_DEVICE_TABLE(of, vt8500_pwm_dt_ids); | |
179 | ||
180 | static int vt8500_pwm_probe(struct platform_device *pdev) | |
21f47fbc | 181 | { |
a245cceb | 182 | struct vt8500_chip *chip; |
21f47fbc | 183 | struct resource *r; |
63e1ed23 | 184 | struct device_node *np = pdev->dev.of_node; |
a245cceb | 185 | int ret; |
21f47fbc | 186 | |
63e1ed23 TP |
187 | if (!np) { |
188 | dev_err(&pdev->dev, "invalid devicetree node\n"); | |
189 | return -EINVAL; | |
190 | } | |
191 | ||
261995dd | 192 | chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); |
a245cceb | 193 | if (chip == NULL) { |
21f47fbc AC |
194 | dev_err(&pdev->dev, "failed to allocate memory\n"); |
195 | return -ENOMEM; | |
196 | } | |
197 | ||
a245cceb SH |
198 | chip->chip.dev = &pdev->dev; |
199 | chip->chip.ops = &vt8500_pwm_ops; | |
200 | chip->chip.base = -1; | |
201 | chip->chip.npwm = VT8500_NR_PWMS; | |
21f47fbc | 202 | |
63e1ed23 TP |
203 | chip->clk = devm_clk_get(&pdev->dev, NULL); |
204 | if (IS_ERR(chip->clk)) { | |
205 | dev_err(&pdev->dev, "clock source not specified\n"); | |
206 | return PTR_ERR(chip->clk); | |
207 | } | |
208 | ||
21f47fbc AC |
209 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
210 | if (r == NULL) { | |
211 | dev_err(&pdev->dev, "no memory resource defined\n"); | |
261995dd | 212 | return -ENODEV; |
21f47fbc AC |
213 | } |
214 | ||
261995dd | 215 | chip->base = devm_request_and_ioremap(&pdev->dev, r); |
63e1ed23 | 216 | if (!chip->base) |
261995dd | 217 | return -EADDRNOTAVAIL; |
21f47fbc | 218 | |
63e1ed23 TP |
219 | ret = clk_prepare(chip->clk); |
220 | if (ret < 0) { | |
221 | dev_err(&pdev->dev, "failed to prepare clock\n"); | |
222 | return ret; | |
223 | } | |
224 | ||
a245cceb | 225 | ret = pwmchip_add(&chip->chip); |
63e1ed23 TP |
226 | if (ret < 0) { |
227 | dev_err(&pdev->dev, "failed to add PWM chip\n"); | |
261995dd | 228 | return ret; |
63e1ed23 | 229 | } |
21f47fbc | 230 | |
a245cceb SH |
231 | platform_set_drvdata(pdev, chip); |
232 | return ret; | |
21f47fbc AC |
233 | } |
234 | ||
63e1ed23 | 235 | static int vt8500_pwm_remove(struct platform_device *pdev) |
21f47fbc | 236 | { |
a245cceb | 237 | struct vt8500_chip *chip; |
21f47fbc | 238 | |
a245cceb SH |
239 | chip = platform_get_drvdata(pdev); |
240 | if (chip == NULL) | |
21f47fbc AC |
241 | return -ENODEV; |
242 | ||
63e1ed23 TP |
243 | clk_unprepare(chip->clk); |
244 | ||
261995dd | 245 | return pwmchip_remove(&chip->chip); |
21f47fbc AC |
246 | } |
247 | ||
63e1ed23 TP |
248 | static struct platform_driver vt8500_pwm_driver = { |
249 | .probe = vt8500_pwm_probe, | |
250 | .remove = vt8500_pwm_remove, | |
21f47fbc AC |
251 | .driver = { |
252 | .name = "vt8500-pwm", | |
253 | .owner = THIS_MODULE, | |
63e1ed23 | 254 | .of_match_table = vt8500_pwm_dt_ids, |
21f47fbc | 255 | }, |
21f47fbc | 256 | }; |
63e1ed23 | 257 | module_platform_driver(vt8500_pwm_driver); |
21f47fbc | 258 | |
63e1ed23 TP |
259 | MODULE_DESCRIPTION("VT8500 PWM Driver"); |
260 | MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>"); | |
261 | MODULE_LICENSE("GPL v2"); |