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regulator: ab8500: Don't update info->update_val if write to register fails
[mirror_ubuntu-hirsute-kernel.git] / drivers / regulator / ab8500.c
CommitLineData
c789ca20
SI		 1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 *
e1159e6d
BJ		 6 * Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson
7 * Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson
547f384f 8 * Daniel Willerud <daniel.willerud@stericsson.com> for ST-Ericsson
c789ca20
SI		 9 *
10 * AB8500 peripheral regulators
11 *
e1159e6d 12 * AB8500 supports the following regulators:
ea05ef31 13 * VAUX1/2/3, VINTCORE, VTVOUT, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
547f384f
LJ		 14 *
15 * AB8505 supports the following regulators:
16 * VAUX1/2/3/4/5/6, VINTCORE, VADC, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
c789ca20
SI		 17 */
18#include <linux/init.h>
19#include <linux/kernel.h>
65602c32 20#include <linux/module.h>
c789ca20
SI		 21#include <linux/err.h>
22#include <linux/platform_device.h>
47c16975 23#include <linux/mfd/abx500.h>
ee66e653 24#include <linux/mfd/abx500/ab8500.h>
3a8334b9
LJ		 25#include <linux/of.h>
26#include <linux/regulator/of_regulator.h>
c789ca20
SI		 27#include <linux/regulator/driver.h>
28#include <linux/regulator/machine.h>
29#include <linux/regulator/ab8500.h>
3a8334b9 30#include <linux/slab.h>
c789ca20 31
3fe52289
LJ		 32/**
33 * struct ab8500_shared_mode - is used when mode is shared between
34 * two regulators.
35 * @shared_regulator: pointer to the other sharing regulator
36 * @lp_mode_req: low power mode requested by this regulator
37 */
38struct ab8500_shared_mode {
39 struct ab8500_regulator_info *shared_regulator;
40 bool lp_mode_req;
41};
42
c789ca20
SI		 43/**
44 * struct ab8500_regulator_info - ab8500 regulator information
e1159e6d 45 * @dev: device pointer
c789ca20 46 * @desc: regulator description
c789ca20 47 * @regulator_dev: regulator device
3fe52289 48 * @shared_mode: used when mode is shared between two regulators
7ce4669c 49 * @load_lp_uA: maximum load in idle (low power) mode
47c16975 50 * @update_bank: bank to control on/off
c789ca20 51 * @update_reg: register to control on/off
bd28a157
EV		 52 * @update_mask: mask to enable/disable and set mode of regulator
53 * @update_val: bits holding the regulator current mode
54 * @update_val_idle: bits to enable the regulator in idle (low power) mode
55 * @update_val_normal: bits to enable the regulator in normal (high power) mode
3fe52289
LJ		 56 * @mode_bank: bank with location of mode register
57 * @mode_reg: mode register
58 * @mode_mask: mask for setting mode
59 * @mode_val_idle: mode setting for low power
60 * @mode_val_normal: mode setting for normal power
47c16975 61 * @voltage_bank: bank to control regulator voltage
c789ca20
SI		 62 * @voltage_reg: register to control regulator voltage
63 * @voltage_mask: mask to control regulator voltage
a0a7014c 64 * @voltage_shift: shift to control regulator voltage
c789ca20
SI		 65 */
66struct ab8500_regulator_info {
67 struct device *dev;
68 struct regulator_desc desc;
c789ca20 69 struct regulator_dev *regulator;
3fe52289 70 struct ab8500_shared_mode *shared_mode;
7ce4669c 71 int load_lp_uA;
47c16975
MW		 72 u8 update_bank;
73 u8 update_reg;
e1159e6d 74 u8 update_mask;
bd28a157
EV		 75 u8 update_val;
76 u8 update_val_idle;
77 u8 update_val_normal;
3fe52289
LJ		 78 u8 mode_bank;
79 u8 mode_reg;
80 u8 mode_mask;
81 u8 mode_val_idle;
82 u8 mode_val_normal;
47c16975
MW		 83 u8 voltage_bank;
84 u8 voltage_reg;
85 u8 voltage_mask;
a0a7014c 86 u8 voltage_shift;
d7607baf
LJ		 87 struct {
88 u8 voltage_limit;
89 u8 voltage_bank;
90 u8 voltage_reg;
91 u8 voltage_mask;
92 u8 voltage_shift;
93 } expand_register;
c789ca20
SI		 94};
95
96/* voltage tables for the vauxn/vintcore supplies */
ec1cc4d9 97static const unsigned int ldo_vauxn_voltages[] = {
c789ca20
SI		 98 1100000,
99 1200000,
100 1300000,
101 1400000,
102 1500000,
103 1800000,
104 1850000,
105 1900000,
106 2500000,
107 2650000,
108 2700000,
109 2750000,
110 2800000,
111 2900000,
112 3000000,
113 3300000,
114};
115
ec1cc4d9 116static const unsigned int ldo_vaux3_voltages[] = {
2b75151a
BJ		 117 1200000,
118 1500000,
119 1800000,
120 2100000,
121 2500000,
122 2750000,
123 2790000,
124 2910000,
125};
126
62ab4111 127static const unsigned int ldo_vaux56_voltages[] = {
547f384f
LJ		 128 1800000,
129 1050000,
130 1100000,
131 1200000,
132 1500000,
133 2200000,
134 2500000,
135 2790000,
136};
137
62ab4111 138static const unsigned int ldo_vaux3_ab8540_voltages[] = {
ae0a9a3e
LJ		 139 1200000,
140 1500000,
141 1800000,
142 2100000,
143 2500000,
144 2750000,
145 2790000,
146 2910000,
147 3050000,
148};
149
684d5ce4
ZH		 150static const unsigned int ldo_vaux56_ab8540_voltages[] = {
151 750000, 760000, 770000, 780000, 790000, 800000,
152 810000, 820000, 830000, 840000, 850000, 860000,
153 870000, 880000, 890000, 900000, 910000, 920000,
154 930000, 940000, 950000, 960000, 970000, 980000,
155 990000, 1000000, 1010000, 1020000, 1030000,
156 1040000, 1050000, 1060000, 1070000, 1080000,
157 1090000, 1100000, 1110000, 1120000, 1130000,
158 1140000, 1150000, 1160000, 1170000, 1180000,
159 1190000, 1200000, 1210000, 1220000, 1230000,
160 1240000, 1250000, 1260000, 1270000, 1280000,
161 1290000, 1300000, 1310000, 1320000, 1330000,
162 1340000, 1350000, 1360000, 1800000, 2790000,
163};
164
ec1cc4d9 165static const unsigned int ldo_vintcore_voltages[] = {
c789ca20
SI		 166 1200000,
167 1225000,
168 1250000,
169 1275000,
170 1300000,
171 1325000,
172 1350000,
173};
174
62ab4111 175static const unsigned int ldo_sdio_voltages[] = {
ae0a9a3e
LJ		 176 1160000,
177 1050000,
178 1100000,
179 1500000,
180 1800000,
181 2200000,
182 2910000,
183 3050000,
184};
185
b080c78a
LJ		 186static const unsigned int fixed_1200000_voltage[] = {
187 1200000,
188};
189
190static const unsigned int fixed_1800000_voltage[] = {
191 1800000,
192};
193
194static const unsigned int fixed_2000000_voltage[] = {
195 2000000,
196};
197
198static const unsigned int fixed_2050000_voltage[] = {
199 2050000,
200};
201
202static const unsigned int fixed_3300000_voltage[] = {
203 3300000,
204};
205
8a3b1b87
LJ		 206static const unsigned int ldo_vana_voltages[] = {
207 1050000,
208 1075000,
209 1100000,
210 1125000,
211 1150000,
212 1175000,
213 1200000,
214 1225000,
215};
216
217static const unsigned int ldo_vaudio_voltages[] = {
218 2000000,
219 2100000,
220 2200000,
221 2300000,
222 2400000,
223 2500000,
224 2600000,
225 2600000, /* Duplicated in Vaudio and IsoUicc Control register. */
226};
227
4c84b4dd
LJ		 228static const unsigned int ldo_vdmic_voltages[] = {
229 1800000,
230 1900000,
231 2000000,
232 2850000,
233};
234
3fe52289
LJ		 235static DEFINE_MUTEX(shared_mode_mutex);
236static struct ab8500_shared_mode ldo_anamic1_shared;
237static struct ab8500_shared_mode ldo_anamic2_shared;
4c84b4dd
LJ		 238static struct ab8500_shared_mode ab8540_ldo_anamic1_shared;
239static struct ab8500_shared_mode ab8540_ldo_anamic2_shared;
3fe52289 240
c789ca20
SI		 241static int ab8500_regulator_enable(struct regulator_dev *rdev)
242{
fc24b426 243 int ret;
c789ca20
SI		 244 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
245
fc24b426
BJ		 246 if (info == NULL) {
247 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 248 return -EINVAL;
fc24b426 249 }
c789ca20 250
47c16975 251 ret = abx500_mask_and_set_register_interruptible(info->dev,
e1159e6d 252 info->update_bank, info->update_reg,
bd28a157 253 info->update_mask, info->update_val);
f71bf528 254 if (ret < 0) {
c789ca20
SI		 255 dev_err(rdev_get_dev(rdev),
256 "couldn't set enable bits for regulator\n");
f71bf528
AL		 257 return ret;
258 }
09aefa12
BJ		 259
260 dev_vdbg(rdev_get_dev(rdev),
261 "%s-enable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
262 info->desc.name, info->update_bank, info->update_reg,
bd28a157 263 info->update_mask, info->update_val);
09aefa12 264
c789ca20
SI		 265 return ret;
266}
267
268static int ab8500_regulator_disable(struct regulator_dev *rdev)
269{
fc24b426 270 int ret;
c789ca20
SI		 271 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
272
fc24b426
BJ		 273 if (info == NULL) {
274 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 275 return -EINVAL;
fc24b426 276 }
c789ca20 277
47c16975 278 ret = abx500_mask_and_set_register_interruptible(info->dev,
e1159e6d
BJ		 279 info->update_bank, info->update_reg,
280 info->update_mask, 0x0);
f71bf528 281 if (ret < 0) {
c789ca20
SI		 282 dev_err(rdev_get_dev(rdev),
283 "couldn't set disable bits for regulator\n");
f71bf528
AL		 284 return ret;
285 }
09aefa12
BJ		 286
287 dev_vdbg(rdev_get_dev(rdev),
288 "%s-disable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
289 info->desc.name, info->update_bank, info->update_reg,
290 info->update_mask, 0x0);
291
c789ca20
SI		 292 return ret;
293}
294
438e695b
AL		 295static int ab8500_regulator_is_enabled(struct regulator_dev *rdev)
296{
297 int ret;
298 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
299 u8 regval;
300
301 if (info == NULL) {
302 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
303 return -EINVAL;
304 }
305
306 ret = abx500_get_register_interruptible(info->dev,
307 info->update_bank, info->update_reg, &regval);
308 if (ret < 0) {
309 dev_err(rdev_get_dev(rdev),
310 "couldn't read 0x%x register\n", info->update_reg);
311 return ret;
312 }
313
314 dev_vdbg(rdev_get_dev(rdev),
315 "%s-is_enabled (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
316 " 0x%x\n",
317 info->desc.name, info->update_bank, info->update_reg,
318 info->update_mask, regval);
319
320 if (regval & info->update_mask)
321 return 1;
322 else
323 return 0;
324}
325
7ce4669c
BJ		 326static unsigned int ab8500_regulator_get_optimum_mode(
327 struct regulator_dev *rdev, int input_uV,
328 int output_uV, int load_uA)
329{
330 unsigned int mode;
331
332 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
333
334 if (info == NULL) {
335 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
336 return -EINVAL;
337 }
338
339 if (load_uA <= info->load_lp_uA)
340 mode = REGULATOR_MODE_IDLE;
341 else
342 mode = REGULATOR_MODE_NORMAL;
343
344 return mode;
345}
346
bd28a157
EV		 347static int ab8500_regulator_set_mode(struct regulator_dev *rdev,
348 unsigned int mode)
349{
3fe52289
LJ		 350 int ret = 0;
351 u8 bank;
352 u8 reg;
353 u8 mask;
354 u8 val;
355 bool dmr = false; /* Dedicated mode register */
bd28a157
EV		 356 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
357
358 if (info == NULL) {
359 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
360 return -EINVAL;
361 }
362
3fe52289
LJ		 363 if (info->shared_mode) {
364 /*
365 * Special case where mode is shared between two regulators.
366 */
367 struct ab8500_shared_mode *sm = info->shared_mode;
368 mutex_lock(&shared_mode_mutex);
369
370 if (mode == REGULATOR_MODE_IDLE) {
371 sm->lp_mode_req = true; /* Low power mode requested */
372 if (!((sm->shared_regulator)->
373 shared_mode->lp_mode_req)) {
374 mutex_unlock(&shared_mode_mutex);
375 return 0; /* Other regulator prevent LP mode */
376 }
377 } else {
378 sm->lp_mode_req = false;
379 }
380 }
381
382 if (info->mode_mask) {
383 /* Dedicated register for handling mode */
384
385 dmr = true;
386
387 switch (mode) {
388 case REGULATOR_MODE_NORMAL:
389 val = info->mode_val_normal;
390 break;
391 case REGULATOR_MODE_IDLE:
392 val = info->mode_val_idle;
393 break;
394 default:
f04adc5a
AL		 395 ret = -EINVAL;
396 goto out_unlock;
3fe52289
LJ		 397 }
398
399 bank = info->mode_bank;
400 reg = info->mode_reg;
401 mask = info->mode_mask;
402 } else {
403 /* Mode register same as enable register */
404
405 switch (mode) {
406 case REGULATOR_MODE_NORMAL:
3fe52289
LJ		 407 val = info->update_val_normal;
408 break;
409 case REGULATOR_MODE_IDLE:
3fe52289
LJ		 410 val = info->update_val_idle;
411 break;
412 default:
f04adc5a
AL		 413 ret = -EINVAL;
414 goto out_unlock;
3fe52289
LJ		 415 }
416
417 bank = info->update_bank;
418 reg = info->update_reg;
419 mask = info->update_mask;
bd28a157
EV		 420 }
421
438e695b 422 if (dmr || ab8500_regulator_is_enabled(rdev)) {
bd28a157 423 ret = abx500_mask_and_set_register_interruptible(info->dev,
3fe52289 424 bank, reg, mask, val);
f04adc5a 425 if (ret < 0) {
bd28a157
EV		 426 dev_err(rdev_get_dev(rdev),
427 "couldn't set regulator mode\n");
f04adc5a
AL		 428 goto out_unlock;
429 }
7ce4669c
BJ		 430
431 dev_vdbg(rdev_get_dev(rdev),
432 "%s-set_mode (bank, reg, mask, value): "
433 "0x%x, 0x%x, 0x%x, 0x%x\n",
3fe52289
LJ		 434 info->desc.name, bank, reg,
435 mask, val);
bd28a157
EV		 436 }
437
f04adc5a
AL		 438 if (!dmr)
439 info->update_val = val;
440
441out_unlock:
3fe52289
LJ		 442 if (info->shared_mode)
443 mutex_unlock(&shared_mode_mutex);
742a7325 444
3fe52289 445 return ret;
bd28a157
EV		 446}
447
448static unsigned int ab8500_regulator_get_mode(struct regulator_dev *rdev)
449{
450 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
451 int ret;
3fe52289
LJ		 452 u8 val;
453 u8 val_normal;
454 u8 val_idle;
bd28a157
EV		 455
456 if (info == NULL) {
457 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
458 return -EINVAL;
459 }
460
3fe52289
LJ		 461 /* Need special handling for shared mode */
462 if (info->shared_mode) {
463 if (info->shared_mode->lp_mode_req)
464 return REGULATOR_MODE_IDLE;
465 else
466 return REGULATOR_MODE_NORMAL;
467 }
468
469 if (info->mode_mask) {
470 /* Dedicated register for handling mode */
471 ret = abx500_get_register_interruptible(info->dev,
472 info->mode_bank, info->mode_reg, &val);
473 val = val & info->mode_mask;
474
475 val_normal = info->mode_val_normal;
476 val_idle = info->mode_val_idle;
477 } else {
478 /* Mode register same as enable register */
479 val = info->update_val;
480 val_normal = info->update_val_normal;
481 val_idle = info->update_val_idle;
482 }
483
484 if (val == val_normal)
bd28a157 485 ret = REGULATOR_MODE_NORMAL;
3fe52289 486 else if (val == val_idle)
bd28a157
EV		 487 ret = REGULATOR_MODE_IDLE;
488 else
489 ret = -EINVAL;
490
491 return ret;
492}
493
3bf6e90e 494static int ab8500_regulator_get_voltage_sel(struct regulator_dev *rdev)
c789ca20 495{
09aefa12 496 int ret, val;
c789ca20 497 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
09aefa12 498 u8 regval;
c789ca20 499
fc24b426
BJ		 500 if (info == NULL) {
501 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 502 return -EINVAL;
fc24b426 503 }
c789ca20 504
09aefa12
BJ		 505 ret = abx500_get_register_interruptible(info->dev,
506 info->voltage_bank, info->voltage_reg, &regval);
c789ca20
SI		 507 if (ret < 0) {
508 dev_err(rdev_get_dev(rdev),
509 "couldn't read voltage reg for regulator\n");
510 return ret;
511 }
512
09aefa12 513 dev_vdbg(rdev_get_dev(rdev),
a0a7014c
LW		 514 "%s-get_voltage (bank, reg, mask, shift, value): "
515 "0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
516 info->desc.name, info->voltage_bank,
517 info->voltage_reg, info->voltage_mask,
518 info->voltage_shift, regval);
09aefa12 519
09aefa12 520 val = regval & info->voltage_mask;
a0a7014c 521 return val >> info->voltage_shift;
c789ca20
SI		 522}
523
d7607baf
LJ		 524static int ab8540_aux3_regulator_get_voltage_sel(struct regulator_dev *rdev)
525{
241896ce 526 int ret;
d7607baf
LJ		 527 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
528 u8 regval, regval_expand;
529
530 if (info == NULL) {
531 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
532 return -EINVAL;
533 }
534
535 ret = abx500_get_register_interruptible(info->dev,
241896ce
AL		 536 info->expand_register.voltage_bank,
537 info->expand_register.voltage_reg, &regval_expand);
d7607baf
LJ		 538 if (ret < 0) {
539 dev_err(rdev_get_dev(rdev),
241896ce 540 "couldn't read voltage expand reg for regulator\n");
d7607baf
LJ		 541 return ret;
542 }
543
241896ce
AL		 544 dev_vdbg(rdev_get_dev(rdev),
545 "%s-get_voltage expand (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
546 info->desc.name, info->expand_register.voltage_bank,
547 info->expand_register.voltage_reg,
548 info->expand_register.voltage_mask, regval_expand);
d7607baf 549
241896ce
AL		 550 if (regval_expand & info->expand_register.voltage_mask)
551 return info->expand_register.voltage_limit;
552
553 ret = abx500_get_register_interruptible(info->dev,
554 info->voltage_bank, info->voltage_reg, &regval);
d7607baf
LJ		 555 if (ret < 0) {
556 dev_err(rdev_get_dev(rdev),
557 "couldn't read voltage reg for regulator\n");
558 return ret;
559 }
560
561 dev_vdbg(rdev_get_dev(rdev),
241896ce
AL		 562 "%s-get_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
563 info->desc.name, info->voltage_bank, info->voltage_reg,
564 info->voltage_mask, regval);
d7607baf 565
241896ce 566 return (regval & info->voltage_mask) >> info->voltage_shift;
d7607baf
LJ		 567}
568
ae713d39
AL		 569static int ab8500_regulator_set_voltage_sel(struct regulator_dev *rdev,
570 unsigned selector)
c789ca20 571{
fc24b426 572 int ret;
c789ca20 573 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
09aefa12 574 u8 regval;
c789ca20 575
fc24b426
BJ		 576 if (info == NULL) {
577 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 578 return -EINVAL;
fc24b426 579 }
c789ca20 580
c789ca20 581 /* set the registers for the request */
a0a7014c 582 regval = (u8)selector << info->voltage_shift;
47c16975 583 ret = abx500_mask_and_set_register_interruptible(info->dev,
09aefa12
BJ		 584 info->voltage_bank, info->voltage_reg,
585 info->voltage_mask, regval);
c789ca20
SI		 586 if (ret < 0)
587 dev_err(rdev_get_dev(rdev),
588 "couldn't set voltage reg for regulator\n");
589
09aefa12
BJ		 590 dev_vdbg(rdev_get_dev(rdev),
591 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
592 " 0x%x\n",
593 info->desc.name, info->voltage_bank, info->voltage_reg,
594 info->voltage_mask, regval);
595
c789ca20
SI		 596 return ret;
597}
598
d7607baf
LJ		 599static int ab8540_aux3_regulator_set_voltage_sel(struct regulator_dev *rdev,
600 unsigned selector)
601{
602 int ret;
603 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
604 u8 regval;
605
606 if (info == NULL) {
607 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
608 return -EINVAL;
609 }
610
611 if (selector >= info->expand_register.voltage_limit) {
612 /* Vaux3 bit4 has different layout */
613 regval = (u8)selector << info->expand_register.voltage_shift;
614 ret = abx500_mask_and_set_register_interruptible(info->dev,
615 info->expand_register.voltage_bank,
616 info->expand_register.voltage_reg,
617 info->expand_register.voltage_mask,
618 regval);
619 } else {
620 /* set the registers for the request */
621 regval = (u8)selector << info->voltage_shift;
622 ret = abx500_mask_and_set_register_interruptible(info->dev,
623 info->voltage_bank, info->voltage_reg,
624 info->voltage_mask, regval);
625 }
626 if (ret < 0)
627 dev_err(rdev_get_dev(rdev),
628 "couldn't set voltage reg for regulator\n");
629
630 dev_vdbg(rdev_get_dev(rdev),
631 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
632 " 0x%x\n",
633 info->desc.name, info->voltage_bank, info->voltage_reg,
634 info->voltage_mask, regval);
635
636 return ret;
637}
638
7ce4669c
BJ		 639static struct regulator_ops ab8500_regulator_volt_mode_ops = {
640 .enable = ab8500_regulator_enable,
641 .disable = ab8500_regulator_disable,
642 .is_enabled = ab8500_regulator_is_enabled,
643 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
644 .set_mode = ab8500_regulator_set_mode,
645 .get_mode = ab8500_regulator_get_mode,
646 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
647 .set_voltage_sel = ab8500_regulator_set_voltage_sel,
648 .list_voltage = regulator_list_voltage_table,
c789ca20
SI		 649};
650
d7607baf
LJ		 651static struct regulator_ops ab8540_aux3_regulator_volt_mode_ops = {
652 .enable = ab8500_regulator_enable,
653 .disable = ab8500_regulator_disable,
654 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
655 .set_mode = ab8500_regulator_set_mode,
656 .get_mode = ab8500_regulator_get_mode,
657 .is_enabled = ab8500_regulator_is_enabled,
658 .get_voltage_sel = ab8540_aux3_regulator_get_voltage_sel,
659 .set_voltage_sel = ab8540_aux3_regulator_set_voltage_sel,
660 .list_voltage = regulator_list_voltage_table,
d7607baf
LJ		 661};
662
8a3b1b87
LJ		 663static struct regulator_ops ab8500_regulator_volt_ops = {
664 .enable = ab8500_regulator_enable,
665 .disable = ab8500_regulator_disable,
666 .is_enabled = ab8500_regulator_is_enabled,
667 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
668 .set_voltage_sel = ab8500_regulator_set_voltage_sel,
669 .list_voltage = regulator_list_voltage_table,
8a3b1b87
LJ		 670};
671
7ce4669c
BJ		 672static struct regulator_ops ab8500_regulator_mode_ops = {
673 .enable = ab8500_regulator_enable,
674 .disable = ab8500_regulator_disable,
675 .is_enabled = ab8500_regulator_is_enabled,
676 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
677 .set_mode = ab8500_regulator_set_mode,
678 .get_mode = ab8500_regulator_get_mode,
d7816ab0 679 .list_voltage = regulator_list_voltage_table,
7ce4669c
BJ		 680};
681
682static struct regulator_ops ab8500_regulator_ops = {
683 .enable = ab8500_regulator_enable,
684 .disable = ab8500_regulator_disable,
685 .is_enabled = ab8500_regulator_is_enabled,
d7816ab0 686 .list_voltage = regulator_list_voltage_table,
c789ca20
SI		 687};
688
3fe52289
LJ		 689static struct regulator_ops ab8500_regulator_anamic_mode_ops = {
690 .enable = ab8500_regulator_enable,
691 .disable = ab8500_regulator_disable,
692 .is_enabled = ab8500_regulator_is_enabled,
693 .set_mode = ab8500_regulator_set_mode,
694 .get_mode = ab8500_regulator_get_mode,
695 .list_voltage = regulator_list_voltage_table,
696};
697
8e6a8d7d 698/* AB8500 regulator information */
6909b452
BJ		 699static struct ab8500_regulator_info
700 ab8500_regulator_info[AB8500_NUM_REGULATORS] = {
c789ca20 701 /*
e1159e6d
BJ		 702 * Variable Voltage Regulators
703 * name, min mV, max mV,
704 * update bank, reg, mask, enable val
ec1cc4d9 705 * volt bank, reg, mask
c789ca20 706 */
6909b452
BJ		 707 [AB8500_LDO_AUX1] = {
708 .desc = {
709 .name = "LDO-AUX1",
7ce4669c 710 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 711 .type = REGULATOR_VOLTAGE,
712 .id = AB8500_LDO_AUX1,
713 .owner = THIS_MODULE,
714 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
ec1cc4d9 715 .volt_table = ldo_vauxn_voltages,
530158b6 716 .enable_time = 200,
6909b452 717 },
7ce4669c 718 .load_lp_uA = 5000,
6909b452
BJ		 719 .update_bank = 0x04,
720 .update_reg = 0x09,
721 .update_mask = 0x03,
bd28a157
EV		 722 .update_val = 0x01,
723 .update_val_idle = 0x03,
724 .update_val_normal = 0x01,
6909b452
BJ		 725 .voltage_bank = 0x04,
726 .voltage_reg = 0x1f,
727 .voltage_mask = 0x0f,
6909b452
BJ		 728 },
729 [AB8500_LDO_AUX2] = {
730 .desc = {
731 .name = "LDO-AUX2",
7ce4669c 732 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 733 .type = REGULATOR_VOLTAGE,
734 .id = AB8500_LDO_AUX2,
735 .owner = THIS_MODULE,
736 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
ec1cc4d9 737 .volt_table = ldo_vauxn_voltages,
530158b6 738 .enable_time = 200,
6909b452 739 },
7ce4669c 740 .load_lp_uA = 5000,
6909b452
BJ		 741 .update_bank = 0x04,
742 .update_reg = 0x09,
743 .update_mask = 0x0c,
bd28a157
EV		 744 .update_val = 0x04,
745 .update_val_idle = 0x0c,
746 .update_val_normal = 0x04,
6909b452
BJ		 747 .voltage_bank = 0x04,
748 .voltage_reg = 0x20,
749 .voltage_mask = 0x0f,
6909b452
BJ		 750 },
751 [AB8500_LDO_AUX3] = {
752 .desc = {
753 .name = "LDO-AUX3",
7ce4669c 754 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 755 .type = REGULATOR_VOLTAGE,
756 .id = AB8500_LDO_AUX3,
757 .owner = THIS_MODULE,
758 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
ec1cc4d9 759 .volt_table = ldo_vaux3_voltages,
530158b6 760 .enable_time = 450,
6909b452 761 },
7ce4669c 762 .load_lp_uA = 5000,
6909b452
BJ		 763 .update_bank = 0x04,
764 .update_reg = 0x0a,
765 .update_mask = 0x03,
bd28a157
EV		 766 .update_val = 0x01,
767 .update_val_idle = 0x03,
768 .update_val_normal = 0x01,
6909b452
BJ		 769 .voltage_bank = 0x04,
770 .voltage_reg = 0x21,
771 .voltage_mask = 0x07,
6909b452
BJ		 772 },
773 [AB8500_LDO_INTCORE] = {
774 .desc = {
775 .name = "LDO-INTCORE",
7ce4669c 776 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 777 .type = REGULATOR_VOLTAGE,
778 .id = AB8500_LDO_INTCORE,
779 .owner = THIS_MODULE,
780 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
ec1cc4d9 781 .volt_table = ldo_vintcore_voltages,
530158b6 782 .enable_time = 750,
6909b452 783 },
7ce4669c 784 .load_lp_uA = 5000,
6909b452
BJ		 785 .update_bank = 0x03,
786 .update_reg = 0x80,
787 .update_mask = 0x44,
cc40dc29 788 .update_val = 0x44,
bd28a157
EV		 789 .update_val_idle = 0x44,
790 .update_val_normal = 0x04,
6909b452
BJ		 791 .voltage_bank = 0x03,
792 .voltage_reg = 0x80,
793 .voltage_mask = 0x38,
a0a7014c 794 .voltage_shift = 3,
6909b452 795 },
c789ca20
SI		 796
797 /*
e1159e6d
BJ		 798 * Fixed Voltage Regulators
799 * name, fixed mV,
800 * update bank, reg, mask, enable val
c789ca20 801 */
6909b452
BJ		 802 [AB8500_LDO_TVOUT] = {
803 .desc = {
804 .name = "LDO-TVOUT",
7ce4669c 805 .ops = &ab8500_regulator_mode_ops,
6909b452
BJ		 806 .type = REGULATOR_VOLTAGE,
807 .id = AB8500_LDO_TVOUT,
808 .owner = THIS_MODULE,
809 .n_voltages = 1,
b080c78a 810 .volt_table = fixed_2000000_voltage,
ed3c138e 811 .enable_time = 500,
6909b452 812 },
7ce4669c 813 .load_lp_uA = 1000,
6909b452
BJ		 814 .update_bank = 0x03,
815 .update_reg = 0x80,
816 .update_mask = 0x82,
bd28a157 817 .update_val = 0x02,
7ce4669c
BJ		 818 .update_val_idle = 0x82,
819 .update_val_normal = 0x02,
6909b452
BJ		 820 },
821 [AB8500_LDO_AUDIO] = {
822 .desc = {
823 .name = "LDO-AUDIO",
7ce4669c 824 .ops = &ab8500_regulator_ops,
6909b452
BJ		 825 .type = REGULATOR_VOLTAGE,
826 .id = AB8500_LDO_AUDIO,
827 .owner = THIS_MODULE,
828 .n_voltages = 1,
530158b6 829 .enable_time = 140,
b080c78a 830 .volt_table = fixed_2000000_voltage,
6909b452 831 },
6909b452
BJ		 832 .update_bank = 0x03,
833 .update_reg = 0x83,
834 .update_mask = 0x02,
bd28a157 835 .update_val = 0x02,
6909b452
BJ		 836 },
837 [AB8500_LDO_ANAMIC1] = {
838 .desc = {
839 .name = "LDO-ANAMIC1",
7ce4669c 840 .ops = &ab8500_regulator_ops,
6909b452
BJ		 841 .type = REGULATOR_VOLTAGE,
842 .id = AB8500_LDO_ANAMIC1,
843 .owner = THIS_MODULE,
844 .n_voltages = 1,
530158b6 845 .enable_time = 500,
b080c78a 846 .volt_table = fixed_2050000_voltage,
6909b452 847 },
6909b452
BJ		 848 .update_bank = 0x03,
849 .update_reg = 0x83,
850 .update_mask = 0x08,
bd28a157 851 .update_val = 0x08,
6909b452
BJ		 852 },
853 [AB8500_LDO_ANAMIC2] = {
854 .desc = {
855 .name = "LDO-ANAMIC2",
7ce4669c 856 .ops = &ab8500_regulator_ops,
6909b452
BJ		 857 .type = REGULATOR_VOLTAGE,
858 .id = AB8500_LDO_ANAMIC2,
859 .owner = THIS_MODULE,
860 .n_voltages = 1,
530158b6 861 .enable_time = 500,
b080c78a 862 .volt_table = fixed_2050000_voltage,
6909b452 863 },
6909b452
BJ		 864 .update_bank = 0x03,
865 .update_reg = 0x83,
866 .update_mask = 0x10,
bd28a157 867 .update_val = 0x10,
6909b452
BJ		 868 },
869 [AB8500_LDO_DMIC] = {
870 .desc = {
871 .name = "LDO-DMIC",
7ce4669c 872 .ops = &ab8500_regulator_ops,
6909b452
BJ		 873 .type = REGULATOR_VOLTAGE,
874 .id = AB8500_LDO_DMIC,
875 .owner = THIS_MODULE,
876 .n_voltages = 1,
530158b6 877 .enable_time = 420,
b080c78a 878 .volt_table = fixed_1800000_voltage,
6909b452 879 },
6909b452
BJ		 880 .update_bank = 0x03,
881 .update_reg = 0x83,
882 .update_mask = 0x04,
bd28a157 883 .update_val = 0x04,
6909b452 884 },
7ce4669c
BJ		 885
886 /*
887 * Regulators with fixed voltage and normal/idle modes
888 */
6909b452
BJ		 889 [AB8500_LDO_ANA] = {
890 .desc = {
891 .name = "LDO-ANA",
7ce4669c 892 .ops = &ab8500_regulator_mode_ops,
6909b452
BJ		 893 .type = REGULATOR_VOLTAGE,
894 .id = AB8500_LDO_ANA,
895 .owner = THIS_MODULE,
896 .n_voltages = 1,
530158b6 897 .enable_time = 140,
b080c78a 898 .volt_table = fixed_1200000_voltage,
6909b452 899 },
7ce4669c 900 .load_lp_uA = 1000,
6909b452
BJ		 901 .update_bank = 0x04,
902 .update_reg = 0x06,
903 .update_mask = 0x0c,
bd28a157 904 .update_val = 0x04,
7ce4669c
BJ		 905 .update_val_idle = 0x0c,
906 .update_val_normal = 0x04,
6909b452 907 },
8e6a8d7d 908};
6909b452 909
547f384f
LJ		 910/* AB8505 regulator information */
911static struct ab8500_regulator_info
912 ab8505_regulator_info[AB8505_NUM_REGULATORS] = {
913 /*
914 * Variable Voltage Regulators
915 * name, min mV, max mV,
916 * update bank, reg, mask, enable val
d3193103 917 * volt bank, reg, mask
547f384f
LJ		 918 */
919 [AB8505_LDO_AUX1] = {
920 .desc = {
921 .name = "LDO-AUX1",
922 .ops = &ab8500_regulator_volt_mode_ops,
923 .type = REGULATOR_VOLTAGE,
0b946411 924 .id = AB8505_LDO_AUX1,
547f384f
LJ		 925 .owner = THIS_MODULE,
926 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 927 .volt_table = ldo_vauxn_voltages,
547f384f 928 },
547f384f
LJ		 929 .load_lp_uA = 5000,
930 .update_bank = 0x04,
931 .update_reg = 0x09,
932 .update_mask = 0x03,
933 .update_val = 0x01,
934 .update_val_idle = 0x03,
935 .update_val_normal = 0x01,
936 .voltage_bank = 0x04,
937 .voltage_reg = 0x1f,
938 .voltage_mask = 0x0f,
547f384f
LJ		 939 },
940 [AB8505_LDO_AUX2] = {
941 .desc = {
942 .name = "LDO-AUX2",
943 .ops = &ab8500_regulator_volt_mode_ops,
944 .type = REGULATOR_VOLTAGE,
0b946411 945 .id = AB8505_LDO_AUX2,
547f384f
LJ		 946 .owner = THIS_MODULE,
947 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 948 .volt_table = ldo_vauxn_voltages,
547f384f 949 },
547f384f
LJ		 950 .load_lp_uA = 5000,
951 .update_bank = 0x04,
952 .update_reg = 0x09,
953 .update_mask = 0x0c,
954 .update_val = 0x04,
955 .update_val_idle = 0x0c,
956 .update_val_normal = 0x04,
957 .voltage_bank = 0x04,
958 .voltage_reg = 0x20,
959 .voltage_mask = 0x0f,
547f384f
LJ		 960 },
961 [AB8505_LDO_AUX3] = {
962 .desc = {
963 .name = "LDO-AUX3",
964 .ops = &ab8500_regulator_volt_mode_ops,
965 .type = REGULATOR_VOLTAGE,
0b946411 966 .id = AB8505_LDO_AUX3,
547f384f
LJ		 967 .owner = THIS_MODULE,
968 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
62ab4111 969 .volt_table = ldo_vaux3_voltages,
547f384f 970 },
547f384f
LJ		 971 .load_lp_uA = 5000,
972 .update_bank = 0x04,
973 .update_reg = 0x0a,
974 .update_mask = 0x03,
975 .update_val = 0x01,
976 .update_val_idle = 0x03,
977 .update_val_normal = 0x01,
978 .voltage_bank = 0x04,
979 .voltage_reg = 0x21,
980 .voltage_mask = 0x07,
547f384f
LJ		 981 },
982 [AB8505_LDO_AUX4] = {
983 .desc = {
984 .name = "LDO-AUX4",
985 .ops = &ab8500_regulator_volt_mode_ops,
986 .type = REGULATOR_VOLTAGE,
0b946411 987 .id = AB8505_LDO_AUX4,
547f384f
LJ		 988 .owner = THIS_MODULE,
989 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 990 .volt_table = ldo_vauxn_voltages,
547f384f 991 },
547f384f
LJ		 992 .load_lp_uA = 5000,
993 /* values for Vaux4Regu register */
994 .update_bank = 0x04,
995 .update_reg = 0x2e,
996 .update_mask = 0x03,
997 .update_val = 0x01,
998 .update_val_idle = 0x03,
999 .update_val_normal = 0x01,
1000 /* values for Vaux4SEL register */
1001 .voltage_bank = 0x04,
1002 .voltage_reg = 0x2f,
1003 .voltage_mask = 0x0f,
547f384f
LJ		 1004 },
1005 [AB8505_LDO_AUX5] = {
1006 .desc = {
1007 .name = "LDO-AUX5",
1008 .ops = &ab8500_regulator_volt_mode_ops,
1009 .type = REGULATOR_VOLTAGE,
1010 .id = AB8505_LDO_AUX5,
1011 .owner = THIS_MODULE,
1012 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
62ab4111 1013 .volt_table = ldo_vaux56_voltages,
547f384f 1014 },
547f384f
LJ		 1015 .load_lp_uA = 2000,
1016 /* values for CtrlVaux5 register */
1017 .update_bank = 0x01,
1018 .update_reg = 0x55,
ae0a9a3e
LJ		 1019 .update_mask = 0x18,
1020 .update_val = 0x10,
1021 .update_val_idle = 0x18,
1022 .update_val_normal = 0x10,
547f384f
LJ		 1023 .voltage_bank = 0x01,
1024 .voltage_reg = 0x55,
1025 .voltage_mask = 0x07,
547f384f
LJ		 1026 },
1027 [AB8505_LDO_AUX6] = {
1028 .desc = {
1029 .name = "LDO-AUX6",
1030 .ops = &ab8500_regulator_volt_mode_ops,
1031 .type = REGULATOR_VOLTAGE,
1032 .id = AB8505_LDO_AUX6,
1033 .owner = THIS_MODULE,
1034 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
62ab4111 1035 .volt_table = ldo_vaux56_voltages,
547f384f 1036 },
547f384f
LJ		 1037 .load_lp_uA = 2000,
1038 /* values for CtrlVaux6 register */
1039 .update_bank = 0x01,
1040 .update_reg = 0x56,
ae0a9a3e
LJ		 1041 .update_mask = 0x18,
1042 .update_val = 0x10,
1043 .update_val_idle = 0x18,
1044 .update_val_normal = 0x10,
547f384f
LJ		 1045 .voltage_bank = 0x01,
1046 .voltage_reg = 0x56,
1047 .voltage_mask = 0x07,
547f384f
LJ		 1048 },
1049 [AB8505_LDO_INTCORE] = {
1050 .desc = {
1051 .name = "LDO-INTCORE",
1052 .ops = &ab8500_regulator_volt_mode_ops,
1053 .type = REGULATOR_VOLTAGE,
0b946411 1054 .id = AB8505_LDO_INTCORE,
547f384f
LJ		 1055 .owner = THIS_MODULE,
1056 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
62ab4111 1057 .volt_table = ldo_vintcore_voltages,
547f384f 1058 },
547f384f
LJ		 1059 .load_lp_uA = 5000,
1060 .update_bank = 0x03,
1061 .update_reg = 0x80,
1062 .update_mask = 0x44,
1063 .update_val = 0x04,
1064 .update_val_idle = 0x44,
1065 .update_val_normal = 0x04,
1066 .voltage_bank = 0x03,
1067 .voltage_reg = 0x80,
1068 .voltage_mask = 0x38,
547f384f
LJ		 1069 .voltage_shift = 3,
1070 },
1071
1072 /*
1073 * Fixed Voltage Regulators
1074 * name, fixed mV,
1075 * update bank, reg, mask, enable val
1076 */
1077 [AB8505_LDO_ADC] = {
1078 .desc = {
1079 .name = "LDO-ADC",
1080 .ops = &ab8500_regulator_mode_ops,
1081 .type = REGULATOR_VOLTAGE,
1082 .id = AB8505_LDO_ADC,
1083 .owner = THIS_MODULE,
1084 .n_voltages = 1,
b080c78a 1085 .volt_table = fixed_2000000_voltage,
a4d68468 1086 .enable_time = 10000,
547f384f 1087 },
547f384f
LJ		 1088 .load_lp_uA = 1000,
1089 .update_bank = 0x03,
1090 .update_reg = 0x80,
1091 .update_mask = 0x82,
1092 .update_val = 0x02,
1093 .update_val_idle = 0x82,
1094 .update_val_normal = 0x02,
1095 },
1096 [AB8505_LDO_USB] = {
1097 .desc = {
1098 .name = "LDO-USB",
1099 .ops = &ab8500_regulator_mode_ops,
1100 .type = REGULATOR_VOLTAGE,
0b946411 1101 .id = AB8505_LDO_USB,
547f384f
LJ		 1102 .owner = THIS_MODULE,
1103 .n_voltages = 1,
b080c78a 1104 .volt_table = fixed_3300000_voltage,
547f384f 1105 },
547f384f
LJ		 1106 .update_bank = 0x03,
1107 .update_reg = 0x82,
1108 .update_mask = 0x03,
1109 .update_val = 0x01,
1110 .update_val_idle = 0x03,
1111 .update_val_normal = 0x01,
1112 },
1113 [AB8505_LDO_AUDIO] = {
1114 .desc = {
1115 .name = "LDO-AUDIO",
8a3b1b87 1116 .ops = &ab8500_regulator_volt_ops,
547f384f 1117 .type = REGULATOR_VOLTAGE,
0b946411 1118 .id = AB8505_LDO_AUDIO,
547f384f 1119 .owner = THIS_MODULE,
8a3b1b87
LJ		 1120 .n_voltages = ARRAY_SIZE(ldo_vaudio_voltages),
1121 .volt_table = ldo_vaudio_voltages,
547f384f 1122 },
547f384f
LJ		 1123 .update_bank = 0x03,
1124 .update_reg = 0x83,
1125 .update_mask = 0x02,
1126 .update_val = 0x02,
8a3b1b87
LJ		 1127 .voltage_bank = 0x01,
1128 .voltage_reg = 0x57,
e4fc9d6d 1129 .voltage_mask = 0x70,
8a3b1b87 1130 .voltage_shift = 4,
547f384f
LJ		 1131 },
1132 [AB8505_LDO_ANAMIC1] = {
1133 .desc = {
1134 .name = "LDO-ANAMIC1",
3fe52289 1135 .ops = &ab8500_regulator_anamic_mode_ops,
547f384f 1136 .type = REGULATOR_VOLTAGE,
0b946411 1137 .id = AB8505_LDO_ANAMIC1,
547f384f
LJ		 1138 .owner = THIS_MODULE,
1139 .n_voltages = 1,
b080c78a 1140 .volt_table = fixed_2050000_voltage,
547f384f 1141 },
4c84b4dd 1142 .shared_mode = &ldo_anamic1_shared,
547f384f
LJ		 1143 .update_bank = 0x03,
1144 .update_reg = 0x83,
1145 .update_mask = 0x08,
1146 .update_val = 0x08,
3fe52289
LJ		 1147 .mode_bank = 0x01,
1148 .mode_reg = 0x54,
1149 .mode_mask = 0x04,
1150 .mode_val_idle = 0x04,
1151 .mode_val_normal = 0x00,
547f384f
LJ		 1152 },
1153 [AB8505_LDO_ANAMIC2] = {
1154 .desc = {
1155 .name = "LDO-ANAMIC2",
3fe52289 1156 .ops = &ab8500_regulator_anamic_mode_ops,
547f384f 1157 .type = REGULATOR_VOLTAGE,
0b946411 1158 .id = AB8505_LDO_ANAMIC2,
547f384f
LJ		 1159 .owner = THIS_MODULE,
1160 .n_voltages = 1,
b080c78a 1161 .volt_table = fixed_2050000_voltage,
547f384f 1162 },
3fe52289 1163 .shared_mode = &ldo_anamic2_shared,
547f384f
LJ		 1164 .update_bank = 0x03,
1165 .update_reg = 0x83,
1166 .update_mask = 0x10,
1167 .update_val = 0x10,
3fe52289
LJ		 1168 .mode_bank = 0x01,
1169 .mode_reg = 0x54,
1170 .mode_mask = 0x04,
1171 .mode_val_idle = 0x04,
1172 .mode_val_normal = 0x00,
547f384f
LJ		 1173 },
1174 [AB8505_LDO_AUX8] = {
1175 .desc = {
1176 .name = "LDO-AUX8",
1177 .ops = &ab8500_regulator_ops,
1178 .type = REGULATOR_VOLTAGE,
1179 .id = AB8505_LDO_AUX8,
1180 .owner = THIS_MODULE,
1181 .n_voltages = 1,
b080c78a 1182 .volt_table = fixed_1800000_voltage,
547f384f 1183 },
547f384f
LJ		 1184 .update_bank = 0x03,
1185 .update_reg = 0x83,
1186 .update_mask = 0x04,
1187 .update_val = 0x04,
1188 },
1189 /*
1190 * Regulators with fixed voltage and normal/idle modes
1191 */
1192 [AB8505_LDO_ANA] = {
1193 .desc = {
1194 .name = "LDO-ANA",
8a3b1b87 1195 .ops = &ab8500_regulator_volt_mode_ops,
547f384f 1196 .type = REGULATOR_VOLTAGE,
0b946411 1197 .id = AB8505_LDO_ANA,
547f384f 1198 .owner = THIS_MODULE,
8a3b1b87
LJ		 1199 .n_voltages = ARRAY_SIZE(ldo_vana_voltages),
1200 .volt_table = ldo_vana_voltages,
547f384f 1201 },
547f384f
LJ		 1202 .load_lp_uA = 1000,
1203 .update_bank = 0x04,
1204 .update_reg = 0x06,
1205 .update_mask = 0x0c,
1206 .update_val = 0x04,
1207 .update_val_idle = 0x0c,
1208 .update_val_normal = 0x04,
8a3b1b87
LJ		 1209 .voltage_bank = 0x04,
1210 .voltage_reg = 0x29,
1211 .voltage_mask = 0x7,
547f384f
LJ		 1212 },
1213};
1214
8e6a8d7d
LJ		 1215/* AB9540 regulator information */
1216static struct ab8500_regulator_info
1217 ab9540_regulator_info[AB9540_NUM_REGULATORS] = {
1218 /*
1219 * Variable Voltage Regulators
1220 * name, min mV, max mV,
1221 * update bank, reg, mask, enable val
d3193103 1222 * volt bank, reg, mask
8e6a8d7d
LJ		 1223 */
1224 [AB9540_LDO_AUX1] = {
1225 .desc = {
1226 .name = "LDO-AUX1",
1227 .ops = &ab8500_regulator_volt_mode_ops,
1228 .type = REGULATOR_VOLTAGE,
0b946411 1229 .id = AB9540_LDO_AUX1,
8e6a8d7d
LJ		 1230 .owner = THIS_MODULE,
1231 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1232 .volt_table = ldo_vauxn_voltages,
8e6a8d7d 1233 },
8e6a8d7d
LJ		 1234 .load_lp_uA = 5000,
1235 .update_bank = 0x04,
1236 .update_reg = 0x09,
1237 .update_mask = 0x03,
1238 .update_val = 0x01,
1239 .update_val_idle = 0x03,
1240 .update_val_normal = 0x01,
1241 .voltage_bank = 0x04,
1242 .voltage_reg = 0x1f,
1243 .voltage_mask = 0x0f,
8e6a8d7d
LJ		 1244 },
1245 [AB9540_LDO_AUX2] = {
1246 .desc = {
1247 .name = "LDO-AUX2",
1248 .ops = &ab8500_regulator_volt_mode_ops,
1249 .type = REGULATOR_VOLTAGE,
0b946411 1250 .id = AB9540_LDO_AUX2,
8e6a8d7d
LJ		 1251 .owner = THIS_MODULE,
1252 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1253 .volt_table = ldo_vauxn_voltages,
8e6a8d7d 1254 },
8e6a8d7d
LJ		 1255 .load_lp_uA = 5000,
1256 .update_bank = 0x04,
1257 .update_reg = 0x09,
1258 .update_mask = 0x0c,
1259 .update_val = 0x04,
1260 .update_val_idle = 0x0c,
1261 .update_val_normal = 0x04,
1262 .voltage_bank = 0x04,
1263 .voltage_reg = 0x20,
1264 .voltage_mask = 0x0f,
8e6a8d7d
LJ		 1265 },
1266 [AB9540_LDO_AUX3] = {
1267 .desc = {
1268 .name = "LDO-AUX3",
1269 .ops = &ab8500_regulator_volt_mode_ops,
1270 .type = REGULATOR_VOLTAGE,
0b946411 1271 .id = AB9540_LDO_AUX3,
8e6a8d7d
LJ		 1272 .owner = THIS_MODULE,
1273 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
62ab4111 1274 .volt_table = ldo_vaux3_voltages,
8e6a8d7d 1275 },
8e6a8d7d
LJ		 1276 .load_lp_uA = 5000,
1277 .update_bank = 0x04,
1278 .update_reg = 0x0a,
1279 .update_mask = 0x03,
1280 .update_val = 0x01,
1281 .update_val_idle = 0x03,
1282 .update_val_normal = 0x01,
1283 .voltage_bank = 0x04,
1284 .voltage_reg = 0x21,
1285 .voltage_mask = 0x07,
8e6a8d7d
LJ		 1286 },
1287 [AB9540_LDO_AUX4] = {
1288 .desc = {
1289 .name = "LDO-AUX4",
1290 .ops = &ab8500_regulator_volt_mode_ops,
1291 .type = REGULATOR_VOLTAGE,
1292 .id = AB9540_LDO_AUX4,
1293 .owner = THIS_MODULE,
1294 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1295 .volt_table = ldo_vauxn_voltages,
8e6a8d7d 1296 },
8e6a8d7d
LJ		 1297 .load_lp_uA = 5000,
1298 /* values for Vaux4Regu register */
1299 .update_bank = 0x04,
1300 .update_reg = 0x2e,
1301 .update_mask = 0x03,
1302 .update_val = 0x01,
1303 .update_val_idle = 0x03,
1304 .update_val_normal = 0x01,
1305 /* values for Vaux4SEL register */
1306 .voltage_bank = 0x04,
1307 .voltage_reg = 0x2f,
1308 .voltage_mask = 0x0f,
8e6a8d7d
LJ		 1309 },
1310 [AB9540_LDO_INTCORE] = {
1311 .desc = {
1312 .name = "LDO-INTCORE",
1313 .ops = &ab8500_regulator_volt_mode_ops,
1314 .type = REGULATOR_VOLTAGE,
0b946411 1315 .id = AB9540_LDO_INTCORE,
8e6a8d7d
LJ		 1316 .owner = THIS_MODULE,
1317 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
62ab4111 1318 .volt_table = ldo_vintcore_voltages,
8e6a8d7d 1319 },
8e6a8d7d
LJ		 1320 .load_lp_uA = 5000,
1321 .update_bank = 0x03,
1322 .update_reg = 0x80,
1323 .update_mask = 0x44,
1324 .update_val = 0x44,
1325 .update_val_idle = 0x44,
1326 .update_val_normal = 0x04,
1327 .voltage_bank = 0x03,
1328 .voltage_reg = 0x80,
1329 .voltage_mask = 0x38,
8e6a8d7d
LJ		 1330 .voltage_shift = 3,
1331 },
6909b452 1332
8e6a8d7d
LJ		 1333 /*
1334 * Fixed Voltage Regulators
1335 * name, fixed mV,
1336 * update bank, reg, mask, enable val
1337 */
1338 [AB9540_LDO_TVOUT] = {
1339 .desc = {
1340 .name = "LDO-TVOUT",
1341 .ops = &ab8500_regulator_mode_ops,
1342 .type = REGULATOR_VOLTAGE,
0b946411 1343 .id = AB9540_LDO_TVOUT,
8e6a8d7d
LJ		 1344 .owner = THIS_MODULE,
1345 .n_voltages = 1,
b080c78a 1346 .volt_table = fixed_2000000_voltage,
a4d68468 1347 .enable_time = 10000,
8e6a8d7d 1348 },
8e6a8d7d
LJ		 1349 .load_lp_uA = 1000,
1350 .update_bank = 0x03,
1351 .update_reg = 0x80,
1352 .update_mask = 0x82,
1353 .update_val = 0x02,
1354 .update_val_idle = 0x82,
1355 .update_val_normal = 0x02,
1356 },
1357 [AB9540_LDO_USB] = {
1358 .desc = {
1359 .name = "LDO-USB",
1360 .ops = &ab8500_regulator_ops,
1361 .type = REGULATOR_VOLTAGE,
1362 .id = AB9540_LDO_USB,
1363 .owner = THIS_MODULE,
1364 .n_voltages = 1,
b080c78a 1365 .volt_table = fixed_3300000_voltage,
8e6a8d7d 1366 },
8e6a8d7d
LJ		 1367 .update_bank = 0x03,
1368 .update_reg = 0x82,
1369 .update_mask = 0x03,
1370 .update_val = 0x01,
1371 .update_val_idle = 0x03,
1372 .update_val_normal = 0x01,
1373 },
1374 [AB9540_LDO_AUDIO] = {
1375 .desc = {
1376 .name = "LDO-AUDIO",
1377 .ops = &ab8500_regulator_ops,
1378 .type = REGULATOR_VOLTAGE,
0b946411 1379 .id = AB9540_LDO_AUDIO,
8e6a8d7d
LJ		 1380 .owner = THIS_MODULE,
1381 .n_voltages = 1,
b080c78a 1382 .volt_table = fixed_2000000_voltage,
8e6a8d7d 1383 },
8e6a8d7d
LJ		 1384 .update_bank = 0x03,
1385 .update_reg = 0x83,
1386 .update_mask = 0x02,
1387 .update_val = 0x02,
1388 },
1389 [AB9540_LDO_ANAMIC1] = {
1390 .desc = {
1391 .name = "LDO-ANAMIC1",
1392 .ops = &ab8500_regulator_ops,
1393 .type = REGULATOR_VOLTAGE,
0b946411 1394 .id = AB9540_LDO_ANAMIC1,
8e6a8d7d
LJ		 1395 .owner = THIS_MODULE,
1396 .n_voltages = 1,
b080c78a 1397 .volt_table = fixed_2050000_voltage,
8e6a8d7d 1398 },
8e6a8d7d
LJ		 1399 .update_bank = 0x03,
1400 .update_reg = 0x83,
1401 .update_mask = 0x08,
1402 .update_val = 0x08,
1403 },
1404 [AB9540_LDO_ANAMIC2] = {
1405 .desc = {
1406 .name = "LDO-ANAMIC2",
1407 .ops = &ab8500_regulator_ops,
1408 .type = REGULATOR_VOLTAGE,
0b946411 1409 .id = AB9540_LDO_ANAMIC2,
8e6a8d7d
LJ		 1410 .owner = THIS_MODULE,
1411 .n_voltages = 1,
b080c78a 1412 .volt_table = fixed_2050000_voltage,
8e6a8d7d 1413 },
8e6a8d7d
LJ		 1414 .update_bank = 0x03,
1415 .update_reg = 0x83,
1416 .update_mask = 0x10,
1417 .update_val = 0x10,
1418 },
1419 [AB9540_LDO_DMIC] = {
1420 .desc = {
1421 .name = "LDO-DMIC",
1422 .ops = &ab8500_regulator_ops,
1423 .type = REGULATOR_VOLTAGE,
0b946411 1424 .id = AB9540_LDO_DMIC,
8e6a8d7d
LJ		 1425 .owner = THIS_MODULE,
1426 .n_voltages = 1,
b080c78a 1427 .volt_table = fixed_1800000_voltage,
8e6a8d7d 1428 },
8e6a8d7d
LJ		 1429 .update_bank = 0x03,
1430 .update_reg = 0x83,
1431 .update_mask = 0x04,
1432 .update_val = 0x04,
1433 },
1434
1435 /*
1436 * Regulators with fixed voltage and normal/idle modes
1437 */
1438 [AB9540_LDO_ANA] = {
1439 .desc = {
1440 .name = "LDO-ANA",
1441 .ops = &ab8500_regulator_mode_ops,
1442 .type = REGULATOR_VOLTAGE,
0b946411 1443 .id = AB9540_LDO_ANA,
8e6a8d7d
LJ		 1444 .owner = THIS_MODULE,
1445 .n_voltages = 1,
b080c78a 1446 .volt_table = fixed_1200000_voltage,
8e6a8d7d 1447 },
8e6a8d7d
LJ		 1448 .load_lp_uA = 1000,
1449 .update_bank = 0x04,
1450 .update_reg = 0x06,
1451 .update_mask = 0x0c,
1452 .update_val = 0x08,
1453 .update_val_idle = 0x0c,
1454 .update_val_normal = 0x08,
1455 },
c789ca20
SI		 1456};
1457
ae0a9a3e
LJ		 1458/* AB8540 regulator information */
1459static struct ab8500_regulator_info
1460 ab8540_regulator_info[AB8540_NUM_REGULATORS] = {
1461 /*
1462 * Variable Voltage Regulators
1463 * name, min mV, max mV,
1464 * update bank, reg, mask, enable val
d3193103 1465 * volt bank, reg, mask
ae0a9a3e
LJ		 1466 */
1467 [AB8540_LDO_AUX1] = {
1468 .desc = {
1469 .name = "LDO-AUX1",
1470 .ops = &ab8500_regulator_volt_mode_ops,
1471 .type = REGULATOR_VOLTAGE,
0b946411 1472 .id = AB8540_LDO_AUX1,
ae0a9a3e
LJ		 1473 .owner = THIS_MODULE,
1474 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1475 .volt_table = ldo_vauxn_voltages,
ae0a9a3e
LJ		 1476 },
1477 .load_lp_uA = 5000,
1478 .update_bank = 0x04,
1479 .update_reg = 0x09,
1480 .update_mask = 0x03,
1481 .update_val = 0x01,
1482 .update_val_idle = 0x03,
1483 .update_val_normal = 0x01,
1484 .voltage_bank = 0x04,
1485 .voltage_reg = 0x1f,
1486 .voltage_mask = 0x0f,
ae0a9a3e
LJ		 1487 },
1488 [AB8540_LDO_AUX2] = {
1489 .desc = {
1490 .name = "LDO-AUX2",
1491 .ops = &ab8500_regulator_volt_mode_ops,
1492 .type = REGULATOR_VOLTAGE,
0b946411 1493 .id = AB8540_LDO_AUX2,
ae0a9a3e
LJ		 1494 .owner = THIS_MODULE,
1495 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1496 .volt_table = ldo_vauxn_voltages,
ae0a9a3e
LJ		 1497 },
1498 .load_lp_uA = 5000,
1499 .update_bank = 0x04,
1500 .update_reg = 0x09,
1501 .update_mask = 0x0c,
1502 .update_val = 0x04,
1503 .update_val_idle = 0x0c,
1504 .update_val_normal = 0x04,
1505 .voltage_bank = 0x04,
1506 .voltage_reg = 0x20,
1507 .voltage_mask = 0x0f,
ae0a9a3e
LJ		 1508 },
1509 [AB8540_LDO_AUX3] = {
1510 .desc = {
1511 .name = "LDO-AUX3",
d7607baf 1512 .ops = &ab8540_aux3_regulator_volt_mode_ops,
ae0a9a3e 1513 .type = REGULATOR_VOLTAGE,
0b946411 1514 .id = AB8540_LDO_AUX3,
ae0a9a3e
LJ		 1515 .owner = THIS_MODULE,
1516 .n_voltages = ARRAY_SIZE(ldo_vaux3_ab8540_voltages),
62ab4111 1517 .volt_table = ldo_vaux3_ab8540_voltages,
ae0a9a3e
LJ		 1518 },
1519 .load_lp_uA = 5000,
1520 .update_bank = 0x04,
1521 .update_reg = 0x0a,
1522 .update_mask = 0x03,
1523 .update_val = 0x01,
1524 .update_val_idle = 0x03,
1525 .update_val_normal = 0x01,
1526 .voltage_bank = 0x04,
1527 .voltage_reg = 0x21,
1528 .voltage_mask = 0x07,
d7607baf
LJ		 1529 .expand_register = {
1530 .voltage_limit = 8,
1531 .voltage_bank = 0x04,
1532 .voltage_reg = 0x01,
1533 .voltage_mask = 0x10,
1534 .voltage_shift = 1,
1535 }
ae0a9a3e
LJ		 1536 },
1537 [AB8540_LDO_AUX4] = {
1538 .desc = {
1539 .name = "LDO-AUX4",
1540 .ops = &ab8500_regulator_volt_mode_ops,
1541 .type = REGULATOR_VOLTAGE,
0b946411 1542 .id = AB8540_LDO_AUX4,
ae0a9a3e
LJ		 1543 .owner = THIS_MODULE,
1544 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1545 .volt_table = ldo_vauxn_voltages,
ae0a9a3e
LJ		 1546 },
1547 .load_lp_uA = 5000,
1548 /* values for Vaux4Regu register */
1549 .update_bank = 0x04,
1550 .update_reg = 0x2e,
1551 .update_mask = 0x03,
1552 .update_val = 0x01,
1553 .update_val_idle = 0x03,
1554 .update_val_normal = 0x01,
1555 /* values for Vaux4SEL register */
1556 .voltage_bank = 0x04,
1557 .voltage_reg = 0x2f,
1558 .voltage_mask = 0x0f,
ae0a9a3e 1559 },
684d5ce4
ZH		 1560 [AB8540_LDO_AUX5] = {
1561 .desc = {
1562 .name = "LDO-AUX5",
1563 .ops = &ab8500_regulator_volt_mode_ops,
1564 .type = REGULATOR_VOLTAGE,
1565 .id = AB8540_LDO_AUX5,
1566 .owner = THIS_MODULE,
1567 .n_voltages = ARRAY_SIZE(ldo_vaux56_ab8540_voltages),
d3193103 1568 .volt_table = ldo_vaux56_ab8540_voltages,
684d5ce4
ZH		 1569 },
1570 .load_lp_uA = 20000,
1571 /* values for Vaux5Regu register */
1572 .update_bank = 0x04,
1573 .update_reg = 0x32,
1574 .update_mask = 0x03,
1575 .update_val = 0x01,
1576 .update_val_idle = 0x03,
1577 .update_val_normal = 0x01,
1578 /* values for Vaux5SEL register */
1579 .voltage_bank = 0x04,
1580 .voltage_reg = 0x33,
1581 .voltage_mask = 0x3f,
684d5ce4
ZH		 1582 },
1583 [AB8540_LDO_AUX6] = {
1584 .desc = {
1585 .name = "LDO-AUX6",
1586 .ops = &ab8500_regulator_volt_mode_ops,
1587 .type = REGULATOR_VOLTAGE,
1588 .id = AB8540_LDO_AUX6,
1589 .owner = THIS_MODULE,
1590 .n_voltages = ARRAY_SIZE(ldo_vaux56_ab8540_voltages),
d3193103 1591 .volt_table = ldo_vaux56_ab8540_voltages,
684d5ce4
ZH		 1592 },
1593 .load_lp_uA = 20000,
1594 /* values for Vaux6Regu register */
1595 .update_bank = 0x04,
1596 .update_reg = 0x35,
1597 .update_mask = 0x03,
1598 .update_val = 0x01,
1599 .update_val_idle = 0x03,
1600 .update_val_normal = 0x01,
1601 /* values for Vaux6SEL register */
1602 .voltage_bank = 0x04,
1603 .voltage_reg = 0x36,
1604 .voltage_mask = 0x3f,
684d5ce4 1605 },
ae0a9a3e
LJ		 1606 [AB8540_LDO_INTCORE] = {
1607 .desc = {
1608 .name = "LDO-INTCORE",
1609 .ops = &ab8500_regulator_volt_mode_ops,
1610 .type = REGULATOR_VOLTAGE,
0b946411 1611 .id = AB8540_LDO_INTCORE,
ae0a9a3e
LJ		 1612 .owner = THIS_MODULE,
1613 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
62ab4111 1614 .volt_table = ldo_vintcore_voltages,
ae0a9a3e
LJ		 1615 },
1616 .load_lp_uA = 5000,
1617 .update_bank = 0x03,
1618 .update_reg = 0x80,
1619 .update_mask = 0x44,
1620 .update_val = 0x44,
1621 .update_val_idle = 0x44,
1622 .update_val_normal = 0x04,
1623 .voltage_bank = 0x03,
1624 .voltage_reg = 0x80,
1625 .voltage_mask = 0x38,
ae0a9a3e
LJ		 1626 .voltage_shift = 3,
1627 },
1628
1629 /*
1630 * Fixed Voltage Regulators
1631 * name, fixed mV,
1632 * update bank, reg, mask, enable val
1633 */
1634 [AB8540_LDO_TVOUT] = {
1635 .desc = {
1636 .name = "LDO-TVOUT",
1637 .ops = &ab8500_regulator_mode_ops,
1638 .type = REGULATOR_VOLTAGE,
0b946411 1639 .id = AB8540_LDO_TVOUT,
ae0a9a3e
LJ		 1640 .owner = THIS_MODULE,
1641 .n_voltages = 1,
aca45e9e 1642 .volt_table = fixed_2000000_voltage,
a4d68468 1643 .enable_time = 10000,
ae0a9a3e 1644 },
ae0a9a3e
LJ		 1645 .load_lp_uA = 1000,
1646 .update_bank = 0x03,
1647 .update_reg = 0x80,
1648 .update_mask = 0x82,
1649 .update_val = 0x02,
1650 .update_val_idle = 0x82,
1651 .update_val_normal = 0x02,
1652 },
1653 [AB8540_LDO_AUDIO] = {
1654 .desc = {
1655 .name = "LDO-AUDIO",
1656 .ops = &ab8500_regulator_ops,
1657 .type = REGULATOR_VOLTAGE,
0b946411 1658 .id = AB8540_LDO_AUDIO,
ae0a9a3e
LJ		 1659 .owner = THIS_MODULE,
1660 .n_voltages = 1,
b080c78a 1661 .volt_table = fixed_2000000_voltage,
ae0a9a3e
LJ		 1662 },
1663 .update_bank = 0x03,
1664 .update_reg = 0x83,
1665 .update_mask = 0x02,
1666 .update_val = 0x02,
1667 },
1668 [AB8540_LDO_ANAMIC1] = {
1669 .desc = {
1670 .name = "LDO-ANAMIC1",
4c84b4dd 1671 .ops = &ab8500_regulator_anamic_mode_ops,
ae0a9a3e 1672 .type = REGULATOR_VOLTAGE,
0b946411 1673 .id = AB8540_LDO_ANAMIC1,
ae0a9a3e
LJ		 1674 .owner = THIS_MODULE,
1675 .n_voltages = 1,
b080c78a 1676 .volt_table = fixed_2050000_voltage,
ae0a9a3e 1677 },
4c84b4dd 1678 .shared_mode = &ab8540_ldo_anamic1_shared,
ae0a9a3e
LJ		 1679 .update_bank = 0x03,
1680 .update_reg = 0x83,
1681 .update_mask = 0x08,
1682 .update_val = 0x08,
4c84b4dd
LJ		 1683 .mode_bank = 0x03,
1684 .mode_reg = 0x83,
1685 .mode_mask = 0x20,
1686 .mode_val_idle = 0x20,
1687 .mode_val_normal = 0x00,
ae0a9a3e
LJ		 1688 },
1689 [AB8540_LDO_ANAMIC2] = {
1690 .desc = {
1691 .name = "LDO-ANAMIC2",
4c84b4dd 1692 .ops = &ab8500_regulator_anamic_mode_ops,
ae0a9a3e 1693 .type = REGULATOR_VOLTAGE,
0b946411 1694 .id = AB8540_LDO_ANAMIC2,
ae0a9a3e
LJ		 1695 .owner = THIS_MODULE,
1696 .n_voltages = 1,
b080c78a 1697 .volt_table = fixed_2050000_voltage,
ae0a9a3e 1698 },
4c84b4dd 1699 .shared_mode = &ab8540_ldo_anamic2_shared,
ae0a9a3e
LJ		 1700 .update_bank = 0x03,
1701 .update_reg = 0x83,
1702 .update_mask = 0x10,
1703 .update_val = 0x10,
4c84b4dd
LJ		 1704 .mode_bank = 0x03,
1705 .mode_reg = 0x83,
1706 .mode_mask = 0x20,
1707 .mode_val_idle = 0x20,
1708 .mode_val_normal = 0x00,
ae0a9a3e
LJ		 1709 },
1710 [AB8540_LDO_DMIC] = {
1711 .desc = {
1712 .name = "LDO-DMIC",
4c84b4dd 1713 .ops = &ab8500_regulator_volt_mode_ops,
ae0a9a3e 1714 .type = REGULATOR_VOLTAGE,
0b946411 1715 .id = AB8540_LDO_DMIC,
ae0a9a3e 1716 .owner = THIS_MODULE,
4c84b4dd 1717 .n_voltages = ARRAY_SIZE(ldo_vdmic_voltages),
d3193103 1718 .volt_table = ldo_vdmic_voltages,
ae0a9a3e 1719 },
4c84b4dd 1720 .load_lp_uA = 1000,
ae0a9a3e
LJ		 1721 .update_bank = 0x03,
1722 .update_reg = 0x83,
1723 .update_mask = 0x04,
1724 .update_val = 0x04,
4c84b4dd
LJ		 1725 .voltage_bank = 0x03,
1726 .voltage_reg = 0x83,
1727 .voltage_mask = 0xc0,
375dc9c1 1728 .voltage_shift = 6,
ae0a9a3e
LJ		 1729 },
1730
1731 /*
1732 * Regulators with fixed voltage and normal/idle modes
1733 */
1734 [AB8540_LDO_ANA] = {
1735 .desc = {
1736 .name = "LDO-ANA",
1737 .ops = &ab8500_regulator_mode_ops,
1738 .type = REGULATOR_VOLTAGE,
0b946411 1739 .id = AB8540_LDO_ANA,
ae0a9a3e
LJ		 1740 .owner = THIS_MODULE,
1741 .n_voltages = 1,
b080c78a 1742 .volt_table = fixed_1200000_voltage,
ae0a9a3e
LJ		 1743 },
1744 .load_lp_uA = 1000,
1745 .update_bank = 0x04,
1746 .update_reg = 0x06,
1747 .update_mask = 0x0c,
1748 .update_val = 0x04,
1749 .update_val_idle = 0x0c,
1750 .update_val_normal = 0x04,
1751 },
1752 [AB8540_LDO_SDIO] = {
1753 .desc = {
1754 .name = "LDO-SDIO",
1755 .ops = &ab8500_regulator_volt_mode_ops,
1756 .type = REGULATOR_VOLTAGE,
1757 .id = AB8540_LDO_SDIO,
1758 .owner = THIS_MODULE,
62ab4111
LJ		 1759 .n_voltages = ARRAY_SIZE(ldo_sdio_voltages),
1760 .volt_table = ldo_sdio_voltages,
ae0a9a3e 1761 },
ae0a9a3e
LJ		 1762 .load_lp_uA = 5000,
1763 .update_bank = 0x03,
1764 .update_reg = 0x88,
1765 .update_mask = 0x30,
1766 .update_val = 0x10,
1767 .update_val_idle = 0x30,
1768 .update_val_normal = 0x10,
1769 .voltage_bank = 0x03,
1770 .voltage_reg = 0x88,
1771 .voltage_mask = 0x07,
ae0a9a3e
LJ		 1772 },
1773};
1774
3fe52289
LJ		 1775static struct ab8500_shared_mode ldo_anamic1_shared = {
1776 .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC2],
1777};
1778
1779static struct ab8500_shared_mode ldo_anamic2_shared = {
1780 .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC1],
1781};
1782
4c84b4dd
LJ		 1783static struct ab8500_shared_mode ab8540_ldo_anamic1_shared = {
1784 .shared_regulator = &ab8540_regulator_info[AB8540_LDO_ANAMIC2],
1785};
1786
1787static struct ab8500_shared_mode ab8540_ldo_anamic2_shared = {
1788 .shared_regulator = &ab8540_regulator_info[AB8540_LDO_ANAMIC1],
1789};
1790
79568b94
BJ		 1791struct ab8500_reg_init {
1792 u8 bank;
1793 u8 addr;
1794 u8 mask;
1795};
1796
1797#define REG_INIT(_id, _bank, _addr, _mask) \
1798 [_id] = { \
1799 .bank = _bank, \
1800 .addr = _addr, \
1801 .mask = _mask, \
1802 }
1803
8e6a8d7d 1804/* AB8500 register init */
79568b94
BJ		 1805static struct ab8500_reg_init ab8500_reg_init[] = {
1806 /*
33bc8f46 1807 * 0x30, VanaRequestCtrl
79568b94
BJ		 1808 * 0xc0, VextSupply1RequestCtrl
1809 */
43a5911b 1810 REG_INIT(AB8500_REGUREQUESTCTRL2, 0x03, 0x04, 0xf0),
79568b94
BJ		 1811 /*
1812 * 0x03, VextSupply2RequestCtrl
1813 * 0x0c, VextSupply3RequestCtrl
1814 * 0x30, Vaux1RequestCtrl
1815 * 0xc0, Vaux2RequestCtrl
1816 */
1817 REG_INIT(AB8500_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
1818 /*
1819 * 0x03, Vaux3RequestCtrl
1820 * 0x04, SwHPReq
1821 */
1822 REG_INIT(AB8500_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
1823 /*
1824 * 0x08, VanaSysClkReq1HPValid
1825 * 0x20, Vaux1SysClkReq1HPValid
1826 * 0x40, Vaux2SysClkReq1HPValid
1827 * 0x80, Vaux3SysClkReq1HPValid
1828 */
43a5911b 1829 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xe8),
79568b94
BJ		 1830 /*
1831 * 0x10, VextSupply1SysClkReq1HPValid
1832 * 0x20, VextSupply2SysClkReq1HPValid
1833 * 0x40, VextSupply3SysClkReq1HPValid
1834 */
43a5911b 1835 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x70),
79568b94
BJ		 1836 /*
1837 * 0x08, VanaHwHPReq1Valid
1838 * 0x20, Vaux1HwHPReq1Valid
1839 * 0x40, Vaux2HwHPReq1Valid
1840 * 0x80, Vaux3HwHPReq1Valid
1841 */
43a5911b 1842 REG_INIT(AB8500_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xe8),
79568b94
BJ		 1843 /*
1844 * 0x01, VextSupply1HwHPReq1Valid
1845 * 0x02, VextSupply2HwHPReq1Valid
1846 * 0x04, VextSupply3HwHPReq1Valid
1847 */
43a5911b 1848 REG_INIT(AB8500_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
79568b94
BJ		 1849 /*
1850 * 0x08, VanaHwHPReq2Valid
1851 * 0x20, Vaux1HwHPReq2Valid
1852 * 0x40, Vaux2HwHPReq2Valid
1853 * 0x80, Vaux3HwHPReq2Valid
1854 */
43a5911b 1855 REG_INIT(AB8500_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xe8),
79568b94
BJ		 1856 /*
1857 * 0x01, VextSupply1HwHPReq2Valid
1858 * 0x02, VextSupply2HwHPReq2Valid
1859 * 0x04, VextSupply3HwHPReq2Valid
1860 */
43a5911b 1861 REG_INIT(AB8500_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
79568b94
BJ		 1862 /*
1863 * 0x20, VanaSwHPReqValid
1864 * 0x80, Vaux1SwHPReqValid
1865 */
43a5911b 1866 REG_INIT(AB8500_REGUSWHPREQVALID1, 0x03, 0x0d, 0xa0),
79568b94
BJ		 1867 /*
1868 * 0x01, Vaux2SwHPReqValid
1869 * 0x02, Vaux3SwHPReqValid
1870 * 0x04, VextSupply1SwHPReqValid
1871 * 0x08, VextSupply2SwHPReqValid
1872 * 0x10, VextSupply3SwHPReqValid
1873 */
43a5911b 1874 REG_INIT(AB8500_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
79568b94
BJ		 1875 /*
1876 * 0x02, SysClkReq2Valid1
43a5911b
LJ		 1877 * 0x04, SysClkReq3Valid1
1878 * 0x08, SysClkReq4Valid1
1879 * 0x10, SysClkReq5Valid1
1880 * 0x20, SysClkReq6Valid1
1881 * 0x40, SysClkReq7Valid1
79568b94
BJ		 1882 * 0x80, SysClkReq8Valid1
1883 */
1884 REG_INIT(AB8500_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
1885 /*
1886 * 0x02, SysClkReq2Valid2
43a5911b
LJ		 1887 * 0x04, SysClkReq3Valid2
1888 * 0x08, SysClkReq4Valid2
1889 * 0x10, SysClkReq5Valid2
1890 * 0x20, SysClkReq6Valid2
1891 * 0x40, SysClkReq7Valid2
79568b94
BJ		 1892 * 0x80, SysClkReq8Valid2
1893 */
1894 REG_INIT(AB8500_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
1895 /*
1896 * 0x02, VTVoutEna
1897 * 0x04, Vintcore12Ena
1898 * 0x38, Vintcore12Sel
1899 * 0x40, Vintcore12LP
1900 * 0x80, VTVoutLP
1901 */
1902 REG_INIT(AB8500_REGUMISC1, 0x03, 0x80, 0xfe),
1903 /*
1904 * 0x02, VaudioEna
1905 * 0x04, VdmicEna
1906 * 0x08, Vamic1Ena
1907 * 0x10, Vamic2Ena
1908 */
1909 REG_INIT(AB8500_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
1910 /*
1911 * 0x01, Vamic1_dzout
1912 * 0x02, Vamic2_dzout
1913 */
1914 REG_INIT(AB8500_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
d79df329 1915 /*
43a5911b 1916 * 0x03, VpllRegu (NOTE! PRCMU register bits)
33bc8f46 1917 * 0x0c, VanaRegu
79568b94
BJ		 1918 */
1919 REG_INIT(AB8500_VPLLVANAREGU, 0x04, 0x06, 0x0f),
1920 /*
1921 * 0x01, VrefDDREna
1922 * 0x02, VrefDDRSleepMode
1923 */
1924 REG_INIT(AB8500_VREFDDR, 0x04, 0x07, 0x03),
1925 /*
1926 * 0x03, VextSupply1Regu
1927 * 0x0c, VextSupply2Regu
1928 * 0x30, VextSupply3Regu
1929 * 0x40, ExtSupply2Bypass
1930 * 0x80, ExtSupply3Bypass
1931 */
1932 REG_INIT(AB8500_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
1933 /*
1934 * 0x03, Vaux1Regu
1935 * 0x0c, Vaux2Regu
1936 */
1937 REG_INIT(AB8500_VAUX12REGU, 0x04, 0x09, 0x0f),
1938 /*
1939 * 0x03, Vaux3Regu
1940 */
43a5911b 1941 REG_INIT(AB8500_VRF1VAUX3REGU, 0x04, 0x0a, 0x03),
79568b94
BJ		 1942 /*
1943 * 0x0f, Vaux1Sel
1944 */
1945 REG_INIT(AB8500_VAUX1SEL, 0x04, 0x1f, 0x0f),
1946 /*
1947 * 0x0f, Vaux2Sel
1948 */
1949 REG_INIT(AB8500_VAUX2SEL, 0x04, 0x20, 0x0f),
1950 /*
1951 * 0x07, Vaux3Sel
1952 */
43a5911b 1953 REG_INIT(AB8500_VRF1VAUX3SEL, 0x04, 0x21, 0x07),
79568b94
BJ		 1954 /*
1955 * 0x01, VextSupply12LP
1956 */
1957 REG_INIT(AB8500_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
1958 /*
1959 * 0x04, Vaux1Disch
1960 * 0x08, Vaux2Disch
1961 * 0x10, Vaux3Disch
1962 * 0x20, Vintcore12Disch
1963 * 0x40, VTVoutDisch
1964 * 0x80, VaudioDisch
1965 */
43a5911b 1966 REG_INIT(AB8500_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
79568b94
BJ		 1967 /*
1968 * 0x02, VanaDisch
1969 * 0x04, VdmicPullDownEna
1970 * 0x10, VdmicDisch
1971 */
43a5911b 1972 REG_INIT(AB8500_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
79568b94
BJ		 1973};
1974
547f384f
LJ		 1975/* AB8505 register init */
1976static struct ab8500_reg_init ab8505_reg_init[] = {
1977 /*
1978 * 0x03, VarmRequestCtrl
1979 * 0x0c, VsmpsCRequestCtrl
1980 * 0x30, VsmpsARequestCtrl
1981 * 0xc0, VsmpsBRequestCtrl
1982 */
1983 REG_INIT(AB8505_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
1984 /*
1985 * 0x03, VsafeRequestCtrl
1986 * 0x0c, VpllRequestCtrl
1987 * 0x30, VanaRequestCtrl
1988 */
1989 REG_INIT(AB8505_REGUREQUESTCTRL2, 0x03, 0x04, 0x3f),
1990 /*
1991 * 0x30, Vaux1RequestCtrl
1992 * 0xc0, Vaux2RequestCtrl
1993 */
1994 REG_INIT(AB8505_REGUREQUESTCTRL3, 0x03, 0x05, 0xf0),
1995 /*
1996 * 0x03, Vaux3RequestCtrl
1997 * 0x04, SwHPReq
1998 */
1999 REG_INIT(AB8505_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
2000 /*
2001 * 0x01, VsmpsASysClkReq1HPValid
2002 * 0x02, VsmpsBSysClkReq1HPValid
2003 * 0x04, VsafeSysClkReq1HPValid
2004 * 0x08, VanaSysClkReq1HPValid
2005 * 0x10, VpllSysClkReq1HPValid
2006 * 0x20, Vaux1SysClkReq1HPValid
2007 * 0x40, Vaux2SysClkReq1HPValid
2008 * 0x80, Vaux3SysClkReq1HPValid
2009 */
2010 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2011 /*
2012 * 0x01, VsmpsCSysClkReq1HPValid
2013 * 0x02, VarmSysClkReq1HPValid
2014 * 0x04, VbbSysClkReq1HPValid
2015 * 0x08, VsmpsMSysClkReq1HPValid
2016 */
2017 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x0f),
2018 /*
2019 * 0x01, VsmpsAHwHPReq1Valid
2020 * 0x02, VsmpsBHwHPReq1Valid
2021 * 0x04, VsafeHwHPReq1Valid
2022 * 0x08, VanaHwHPReq1Valid
2023 * 0x10, VpllHwHPReq1Valid
2024 * 0x20, Vaux1HwHPReq1Valid
2025 * 0x40, Vaux2HwHPReq1Valid
2026 * 0x80, Vaux3HwHPReq1Valid
2027 */
2028 REG_INIT(AB8505_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2029 /*
2030 * 0x08, VsmpsMHwHPReq1Valid
2031 */
2032 REG_INIT(AB8505_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x08),
2033 /*
2034 * 0x01, VsmpsAHwHPReq2Valid
2035 * 0x02, VsmpsBHwHPReq2Valid
2036 * 0x04, VsafeHwHPReq2Valid
2037 * 0x08, VanaHwHPReq2Valid
2038 * 0x10, VpllHwHPReq2Valid
2039 * 0x20, Vaux1HwHPReq2Valid
2040 * 0x40, Vaux2HwHPReq2Valid
2041 * 0x80, Vaux3HwHPReq2Valid
2042 */
2043 REG_INIT(AB8505_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2044 /*
2045 * 0x08, VsmpsMHwHPReq2Valid
2046 */
2047 REG_INIT(AB8505_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x08),
2048 /*
2049 * 0x01, VsmpsCSwHPReqValid
2050 * 0x02, VarmSwHPReqValid
2051 * 0x04, VsmpsASwHPReqValid
2052 * 0x08, VsmpsBSwHPReqValid
2053 * 0x10, VsafeSwHPReqValid
2054 * 0x20, VanaSwHPReqValid
2055 * 0x40, VpllSwHPReqValid
2056 * 0x80, Vaux1SwHPReqValid
2057 */
2058 REG_INIT(AB8505_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2059 /*
2060 * 0x01, Vaux2SwHPReqValid
2061 * 0x02, Vaux3SwHPReqValid
2062 * 0x20, VsmpsMSwHPReqValid
2063 */
2064 REG_INIT(AB8505_REGUSWHPREQVALID2, 0x03, 0x0e, 0x23),
2065 /*
2066 * 0x02, SysClkReq2Valid1
2067 * 0x04, SysClkReq3Valid1
2068 * 0x08, SysClkReq4Valid1
2069 */
2070 REG_INIT(AB8505_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0x0e),
2071 /*
2072 * 0x02, SysClkReq2Valid2
2073 * 0x04, SysClkReq3Valid2
2074 * 0x08, SysClkReq4Valid2
2075 */
2076 REG_INIT(AB8505_REGUSYSCLKREQVALID2, 0x03, 0x10, 0x0e),
2077 /*
2078 * 0x01, Vaux4SwHPReqValid
2079 * 0x02, Vaux4HwHPReq2Valid
2080 * 0x04, Vaux4HwHPReq1Valid
2081 * 0x08, Vaux4SysClkReq1HPValid
2082 */
2083 REG_INIT(AB8505_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2084 /*
2085 * 0x02, VadcEna
2086 * 0x04, VintCore12Ena
2087 * 0x38, VintCore12Sel
2088 * 0x40, VintCore12LP
2089 * 0x80, VadcLP
2090 */
2091 REG_INIT(AB8505_REGUMISC1, 0x03, 0x80, 0xfe),
2092 /*
2093 * 0x02, VaudioEna
2094 * 0x04, VdmicEna
2095 * 0x08, Vamic1Ena
2096 * 0x10, Vamic2Ena
2097 */
2098 REG_INIT(AB8505_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
2099 /*
2100 * 0x01, Vamic1_dzout
2101 * 0x02, Vamic2_dzout
2102 */
2103 REG_INIT(AB8505_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2104 /*
2105 * 0x03, VsmpsARegu
2106 * 0x0c, VsmpsASelCtrl
2107 * 0x10, VsmpsAAutoMode
2108 * 0x20, VsmpsAPWMMode
2109 */
2110 REG_INIT(AB8505_VSMPSAREGU, 0x04, 0x03, 0x3f),
2111 /*
2112 * 0x03, VsmpsBRegu
2113 * 0x0c, VsmpsBSelCtrl
2114 * 0x10, VsmpsBAutoMode
2115 * 0x20, VsmpsBPWMMode
2116 */
2117 REG_INIT(AB8505_VSMPSBREGU, 0x04, 0x04, 0x3f),
2118 /*
2119 * 0x03, VsafeRegu
2120 * 0x0c, VsafeSelCtrl
2121 * 0x10, VsafeAutoMode
2122 * 0x20, VsafePWMMode
2123 */
2124 REG_INIT(AB8505_VSAFEREGU, 0x04, 0x05, 0x3f),
2125 /*
2126 * 0x03, VpllRegu (NOTE! PRCMU register bits)
2127 * 0x0c, VanaRegu
2128 */
2129 REG_INIT(AB8505_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2130 /*
2131 * 0x03, VextSupply1Regu
2132 * 0x0c, VextSupply2Regu
2133 * 0x30, VextSupply3Regu
2134 * 0x40, ExtSupply2Bypass
2135 * 0x80, ExtSupply3Bypass
2136 */
2137 REG_INIT(AB8505_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2138 /*
2139 * 0x03, Vaux1Regu
2140 * 0x0c, Vaux2Regu
2141 */
2142 REG_INIT(AB8505_VAUX12REGU, 0x04, 0x09, 0x0f),
2143 /*
2144 * 0x0f, Vaux3Regu
2145 */
2146 REG_INIT(AB8505_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2147 /*
2148 * 0x3f, VsmpsASel1
2149 */
2150 REG_INIT(AB8505_VSMPSASEL1, 0x04, 0x13, 0x3f),
2151 /*
2152 * 0x3f, VsmpsASel2
2153 */
2154 REG_INIT(AB8505_VSMPSASEL2, 0x04, 0x14, 0x3f),
2155 /*
2156 * 0x3f, VsmpsASel3
2157 */
2158 REG_INIT(AB8505_VSMPSASEL3, 0x04, 0x15, 0x3f),
2159 /*
2160 * 0x3f, VsmpsBSel1
2161 */
2162 REG_INIT(AB8505_VSMPSBSEL1, 0x04, 0x17, 0x3f),
2163 /*
2164 * 0x3f, VsmpsBSel2
2165 */
2166 REG_INIT(AB8505_VSMPSBSEL2, 0x04, 0x18, 0x3f),
2167 /*
2168 * 0x3f, VsmpsBSel3
2169 */
2170 REG_INIT(AB8505_VSMPSBSEL3, 0x04, 0x19, 0x3f),
2171 /*
2172 * 0x7f, VsafeSel1
2173 */
2174 REG_INIT(AB8505_VSAFESEL1, 0x04, 0x1b, 0x7f),
2175 /*
2176 * 0x3f, VsafeSel2
2177 */
2178 REG_INIT(AB8505_VSAFESEL2, 0x04, 0x1c, 0x7f),
2179 /*
2180 * 0x3f, VsafeSel3
2181 */
2182 REG_INIT(AB8505_VSAFESEL3, 0x04, 0x1d, 0x7f),
2183 /*
2184 * 0x0f, Vaux1Sel
2185 */
2186 REG_INIT(AB8505_VAUX1SEL, 0x04, 0x1f, 0x0f),
2187 /*
2188 * 0x0f, Vaux2Sel
2189 */
2190 REG_INIT(AB8505_VAUX2SEL, 0x04, 0x20, 0x0f),
2191 /*
2192 * 0x07, Vaux3Sel
2193 * 0x30, VRF1Sel
2194 */
2195 REG_INIT(AB8505_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
2196 /*
2197 * 0x03, Vaux4RequestCtrl
2198 */
2199 REG_INIT(AB8505_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2200 /*
2201 * 0x03, Vaux4Regu
2202 */
2203 REG_INIT(AB8505_VAUX4REGU, 0x04, 0x2e, 0x03),
2204 /*
2205 * 0x0f, Vaux4Sel
2206 */
2207 REG_INIT(AB8505_VAUX4SEL, 0x04, 0x2f, 0x0f),
2208 /*
2209 * 0x04, Vaux1Disch
2210 * 0x08, Vaux2Disch
2211 * 0x10, Vaux3Disch
2212 * 0x20, Vintcore12Disch
2213 * 0x40, VTVoutDisch
2214 * 0x80, VaudioDisch
2215 */
2216 REG_INIT(AB8505_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
2217 /*
2218 * 0x02, VanaDisch
2219 * 0x04, VdmicPullDownEna
2220 * 0x10, VdmicDisch
2221 */
2222 REG_INIT(AB8505_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
2223 /*
2224 * 0x01, Vaux4Disch
2225 */
2226 REG_INIT(AB8505_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2227 /*
2228 * 0x07, Vaux5Sel
2229 * 0x08, Vaux5LP
2230 * 0x10, Vaux5Ena
2231 * 0x20, Vaux5Disch
2232 * 0x40, Vaux5DisSfst
2233 * 0x80, Vaux5DisPulld
2234 */
2235 REG_INIT(AB8505_CTRLVAUX5, 0x01, 0x55, 0xff),
2236 /*
2237 * 0x07, Vaux6Sel
2238 * 0x08, Vaux6LP
2239 * 0x10, Vaux6Ena
2240 * 0x80, Vaux6DisPulld
2241 */
2242 REG_INIT(AB8505_CTRLVAUX6, 0x01, 0x56, 0x9f),
2243};
2244
8e6a8d7d
LJ		 2245/* AB9540 register init */
2246static struct ab8500_reg_init ab9540_reg_init[] = {
2247 /*
2248 * 0x03, VarmRequestCtrl
2249 * 0x0c, VapeRequestCtrl
2250 * 0x30, Vsmps1RequestCtrl
2251 * 0xc0, Vsmps2RequestCtrl
2252 */
2253 REG_INIT(AB9540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
2254 /*
2255 * 0x03, Vsmps3RequestCtrl
2256 * 0x0c, VpllRequestCtrl
2257 * 0x30, VanaRequestCtrl
2258 * 0xc0, VextSupply1RequestCtrl
2259 */
2260 REG_INIT(AB9540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff),
2261 /*
2262 * 0x03, VextSupply2RequestCtrl
2263 * 0x0c, VextSupply3RequestCtrl
2264 * 0x30, Vaux1RequestCtrl
2265 * 0xc0, Vaux2RequestCtrl
2266 */
2267 REG_INIT(AB9540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
2268 /*
2269 * 0x03, Vaux3RequestCtrl
2270 * 0x04, SwHPReq
2271 */
2272 REG_INIT(AB9540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
2273 /*
2274 * 0x01, Vsmps1SysClkReq1HPValid
2275 * 0x02, Vsmps2SysClkReq1HPValid
2276 * 0x04, Vsmps3SysClkReq1HPValid
2277 * 0x08, VanaSysClkReq1HPValid
2278 * 0x10, VpllSysClkReq1HPValid
2279 * 0x20, Vaux1SysClkReq1HPValid
2280 * 0x40, Vaux2SysClkReq1HPValid
2281 * 0x80, Vaux3SysClkReq1HPValid
2282 */
2283 REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2284 /*
2285 * 0x01, VapeSysClkReq1HPValid
2286 * 0x02, VarmSysClkReq1HPValid
2287 * 0x04, VbbSysClkReq1HPValid
2288 * 0x08, VmodSysClkReq1HPValid
2289 * 0x10, VextSupply1SysClkReq1HPValid
2290 * 0x20, VextSupply2SysClkReq1HPValid
2291 * 0x40, VextSupply3SysClkReq1HPValid
2292 */
2293 REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x7f),
2294 /*
2295 * 0x01, Vsmps1HwHPReq1Valid
2296 * 0x02, Vsmps2HwHPReq1Valid
2297 * 0x04, Vsmps3HwHPReq1Valid
2298 * 0x08, VanaHwHPReq1Valid
2299 * 0x10, VpllHwHPReq1Valid
2300 * 0x20, Vaux1HwHPReq1Valid
2301 * 0x40, Vaux2HwHPReq1Valid
2302 * 0x80, Vaux3HwHPReq1Valid
2303 */
2304 REG_INIT(AB9540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2305 /*
2306 * 0x01, VextSupply1HwHPReq1Valid
2307 * 0x02, VextSupply2HwHPReq1Valid
2308 * 0x04, VextSupply3HwHPReq1Valid
2309 * 0x08, VmodHwHPReq1Valid
2310 */
2311 REG_INIT(AB9540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x0f),
2312 /*
2313 * 0x01, Vsmps1HwHPReq2Valid
2314 * 0x02, Vsmps2HwHPReq2Valid
2315 * 0x03, Vsmps3HwHPReq2Valid
2316 * 0x08, VanaHwHPReq2Valid
2317 * 0x10, VpllHwHPReq2Valid
2318 * 0x20, Vaux1HwHPReq2Valid
2319 * 0x40, Vaux2HwHPReq2Valid
2320 * 0x80, Vaux3HwHPReq2Valid
2321 */
2322 REG_INIT(AB9540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2323 /*
2324 * 0x01, VextSupply1HwHPReq2Valid
2325 * 0x02, VextSupply2HwHPReq2Valid
2326 * 0x04, VextSupply3HwHPReq2Valid
2327 * 0x08, VmodHwHPReq2Valid
2328 */
2329 REG_INIT(AB9540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x0f),
2330 /*
2331 * 0x01, VapeSwHPReqValid
2332 * 0x02, VarmSwHPReqValid
2333 * 0x04, Vsmps1SwHPReqValid
2334 * 0x08, Vsmps2SwHPReqValid
2335 * 0x10, Vsmps3SwHPReqValid
2336 * 0x20, VanaSwHPReqValid
2337 * 0x40, VpllSwHPReqValid
2338 * 0x80, Vaux1SwHPReqValid
2339 */
2340 REG_INIT(AB9540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2341 /*
2342 * 0x01, Vaux2SwHPReqValid
2343 * 0x02, Vaux3SwHPReqValid
2344 * 0x04, VextSupply1SwHPReqValid
2345 * 0x08, VextSupply2SwHPReqValid
2346 * 0x10, VextSupply3SwHPReqValid
2347 * 0x20, VmodSwHPReqValid
2348 */
2349 REG_INIT(AB9540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x3f),
2350 /*
2351 * 0x02, SysClkReq2Valid1
2352 * ...
2353 * 0x80, SysClkReq8Valid1
2354 */
2355 REG_INIT(AB9540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
2356 /*
2357 * 0x02, SysClkReq2Valid2
2358 * ...
2359 * 0x80, SysClkReq8Valid2
2360 */
2361 REG_INIT(AB9540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
2362 /*
2363 * 0x01, Vaux4SwHPReqValid
2364 * 0x02, Vaux4HwHPReq2Valid
2365 * 0x04, Vaux4HwHPReq1Valid
2366 * 0x08, Vaux4SysClkReq1HPValid
2367 */
2368 REG_INIT(AB9540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2369 /*
2370 * 0x02, VTVoutEna
2371 * 0x04, Vintcore12Ena
2372 * 0x38, Vintcore12Sel
2373 * 0x40, Vintcore12LP
2374 * 0x80, VTVoutLP
2375 */
2376 REG_INIT(AB9540_REGUMISC1, 0x03, 0x80, 0xfe),
2377 /*
2378 * 0x02, VaudioEna
2379 * 0x04, VdmicEna
2380 * 0x08, Vamic1Ena
2381 * 0x10, Vamic2Ena
2382 */
2383 REG_INIT(AB9540_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
2384 /*
2385 * 0x01, Vamic1_dzout
2386 * 0x02, Vamic2_dzout
2387 */
2388 REG_INIT(AB9540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2389 /*
2390 * 0x03, Vsmps1Regu
2391 * 0x0c, Vsmps1SelCtrl
2392 * 0x10, Vsmps1AutoMode
2393 * 0x20, Vsmps1PWMMode
2394 */
2395 REG_INIT(AB9540_VSMPS1REGU, 0x04, 0x03, 0x3f),
2396 /*
2397 * 0x03, Vsmps2Regu
2398 * 0x0c, Vsmps2SelCtrl
2399 * 0x10, Vsmps2AutoMode
2400 * 0x20, Vsmps2PWMMode
2401 */
2402 REG_INIT(AB9540_VSMPS2REGU, 0x04, 0x04, 0x3f),
2403 /*
2404 * 0x03, Vsmps3Regu
2405 * 0x0c, Vsmps3SelCtrl
2406 * NOTE! PRCMU register
2407 */
2408 REG_INIT(AB9540_VSMPS3REGU, 0x04, 0x05, 0x0f),
2409 /*
2410 * 0x03, VpllRegu
2411 * 0x0c, VanaRegu
2412 */
2413 REG_INIT(AB9540_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2414 /*
2415 * 0x03, VextSupply1Regu
2416 * 0x0c, VextSupply2Regu
2417 * 0x30, VextSupply3Regu
2418 * 0x40, ExtSupply2Bypass
2419 * 0x80, ExtSupply3Bypass
2420 */
2421 REG_INIT(AB9540_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2422 /*
2423 * 0x03, Vaux1Regu
2424 * 0x0c, Vaux2Regu
2425 */
2426 REG_INIT(AB9540_VAUX12REGU, 0x04, 0x09, 0x0f),
2427 /*
2428 * 0x0c, Vrf1Regu
2429 * 0x03, Vaux3Regu
2430 */
2431 REG_INIT(AB9540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2432 /*
2433 * 0x3f, Vsmps1Sel1
2434 */
2435 REG_INIT(AB9540_VSMPS1SEL1, 0x04, 0x13, 0x3f),
2436 /*
2437 * 0x3f, Vsmps1Sel2
2438 */
2439 REG_INIT(AB9540_VSMPS1SEL2, 0x04, 0x14, 0x3f),
2440 /*
2441 * 0x3f, Vsmps1Sel3
2442 */
2443 REG_INIT(AB9540_VSMPS1SEL3, 0x04, 0x15, 0x3f),
2444 /*
2445 * 0x3f, Vsmps2Sel1
2446 */
2447 REG_INIT(AB9540_VSMPS2SEL1, 0x04, 0x17, 0x3f),
2448 /*
2449 * 0x3f, Vsmps2Sel2
2450 */
2451 REG_INIT(AB9540_VSMPS2SEL2, 0x04, 0x18, 0x3f),
2452 /*
2453 * 0x3f, Vsmps2Sel3
2454 */
2455 REG_INIT(AB9540_VSMPS2SEL3, 0x04, 0x19, 0x3f),
2456 /*
2457 * 0x7f, Vsmps3Sel1
2458 * NOTE! PRCMU register
2459 */
2460 REG_INIT(AB9540_VSMPS3SEL1, 0x04, 0x1b, 0x7f),
2461 /*
2462 * 0x7f, Vsmps3Sel2
2463 * NOTE! PRCMU register
2464 */
2465 REG_INIT(AB9540_VSMPS3SEL2, 0x04, 0x1c, 0x7f),
2466 /*
2467 * 0x0f, Vaux1Sel
2468 */
2469 REG_INIT(AB9540_VAUX1SEL, 0x04, 0x1f, 0x0f),
2470 /*
2471 * 0x0f, Vaux2Sel
2472 */
2473 REG_INIT(AB9540_VAUX2SEL, 0x04, 0x20, 0x0f),
2474 /*
2475 * 0x07, Vaux3Sel
2476 * 0x30, Vrf1Sel
2477 */
2478 REG_INIT(AB9540_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
2479 /*
2480 * 0x01, VextSupply12LP
2481 */
2482 REG_INIT(AB9540_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
2483 /*
2484 * 0x03, Vaux4RequestCtrl
2485 */
2486 REG_INIT(AB9540_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2487 /*
2488 * 0x03, Vaux4Regu
2489 */
2490 REG_INIT(AB9540_VAUX4REGU, 0x04, 0x2e, 0x03),
2491 /*
2492 * 0x08, Vaux4Sel
2493 */
2494 REG_INIT(AB9540_VAUX4SEL, 0x04, 0x2f, 0x0f),
2495 /*
2496 * 0x01, VpllDisch
2497 * 0x02, Vrf1Disch
2498 * 0x04, Vaux1Disch
2499 * 0x08, Vaux2Disch
2500 * 0x10, Vaux3Disch
2501 * 0x20, Vintcore12Disch
2502 * 0x40, VTVoutDisch
2503 * 0x80, VaudioDisch
2504 */
2505 REG_INIT(AB9540_REGUCTRLDISCH, 0x04, 0x43, 0xff),
2506 /*
2507 * 0x01, VsimDisch
2508 * 0x02, VanaDisch
2509 * 0x04, VdmicPullDownEna
2510 * 0x08, VpllPullDownEna
2511 * 0x10, VdmicDisch
2512 */
2513 REG_INIT(AB9540_REGUCTRLDISCH2, 0x04, 0x44, 0x1f),
2514 /*
2515 * 0x01, Vaux4Disch
2516 */
2517 REG_INIT(AB9540_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2518};
2519
ae0a9a3e
LJ		 2520/* AB8540 register init */
2521static struct ab8500_reg_init ab8540_reg_init[] = {
2522 /*
2523 * 0x01, VSimSycClkReq1Valid
2524 * 0x02, VSimSycClkReq2Valid
2525 * 0x04, VSimSycClkReq3Valid
2526 * 0x08, VSimSycClkReq4Valid
2527 * 0x10, VSimSycClkReq5Valid
2528 * 0x20, VSimSycClkReq6Valid
2529 * 0x40, VSimSycClkReq7Valid
2530 * 0x80, VSimSycClkReq8Valid
2531 */
2532 REG_INIT(AB8540_VSIMSYSCLKCTRL, 0x02, 0x33, 0xff),
2533 /*
2534 * 0x03, VarmRequestCtrl
2535 * 0x0c, VapeRequestCtrl
2536 * 0x30, Vsmps1RequestCtrl
2537 * 0xc0, Vsmps2RequestCtrl
2538 */
2539 REG_INIT(AB8540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
2540 /*
2541 * 0x03, Vsmps3RequestCtrl
2542 * 0x0c, VpllRequestCtrl
2543 * 0x30, VanaRequestCtrl
2544 * 0xc0, VextSupply1RequestCtrl
2545 */
2546 REG_INIT(AB8540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff),
2547 /*
2548 * 0x03, VextSupply2RequestCtrl
2549 * 0x0c, VextSupply3RequestCtrl
2550 * 0x30, Vaux1RequestCtrl
2551 * 0xc0, Vaux2RequestCtrl
2552 */
2553 REG_INIT(AB8540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
2554 /*
2555 * 0x03, Vaux3RequestCtrl
2556 * 0x04, SwHPReq
2557 */
2558 REG_INIT(AB8540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
2559 /*
2560 * 0x01, Vsmps1SysClkReq1HPValid
2561 * 0x02, Vsmps2SysClkReq1HPValid
2562 * 0x04, Vsmps3SysClkReq1HPValid
2563 * 0x08, VanaSysClkReq1HPValid
2564 * 0x10, VpllSysClkReq1HPValid
2565 * 0x20, Vaux1SysClkReq1HPValid
2566 * 0x40, Vaux2SysClkReq1HPValid
2567 * 0x80, Vaux3SysClkReq1HPValid
2568 */
2569 REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2570 /*
2571 * 0x01, VapeSysClkReq1HPValid
2572 * 0x02, VarmSysClkReq1HPValid
2573 * 0x04, VbbSysClkReq1HPValid
2574 * 0x10, VextSupply1SysClkReq1HPValid
2575 * 0x20, VextSupply2SysClkReq1HPValid
2576 * 0x40, VextSupply3SysClkReq1HPValid
2577 */
2578 REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x77),
2579 /*
2580 * 0x01, Vsmps1HwHPReq1Valid
2581 * 0x02, Vsmps2HwHPReq1Valid
2582 * 0x04, Vsmps3HwHPReq1Valid
2583 * 0x08, VanaHwHPReq1Valid
2584 * 0x10, VpllHwHPReq1Valid
2585 * 0x20, Vaux1HwHPReq1Valid
2586 * 0x40, Vaux2HwHPReq1Valid
2587 * 0x80, Vaux3HwHPReq1Valid
2588 */
2589 REG_INIT(AB8540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2590 /*
2591 * 0x01, VextSupply1HwHPReq1Valid
2592 * 0x02, VextSupply2HwHPReq1Valid
2593 * 0x04, VextSupply3HwHPReq1Valid
2594 */
2595 REG_INIT(AB8540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
2596 /*
2597 * 0x01, Vsmps1HwHPReq2Valid
2598 * 0x02, Vsmps2HwHPReq2Valid
2599 * 0x03, Vsmps3HwHPReq2Valid
2600 * 0x08, VanaHwHPReq2Valid
2601 * 0x10, VpllHwHPReq2Valid
2602 * 0x20, Vaux1HwHPReq2Valid
2603 * 0x40, Vaux2HwHPReq2Valid
2604 * 0x80, Vaux3HwHPReq2Valid
2605 */
2606 REG_INIT(AB8540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2607 /*
2608 * 0x01, VextSupply1HwHPReq2Valid
2609 * 0x02, VextSupply2HwHPReq2Valid
2610 * 0x04, VextSupply3HwHPReq2Valid
2611 */
2612 REG_INIT(AB8540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
2613 /*
2614 * 0x01, VapeSwHPReqValid
2615 * 0x02, VarmSwHPReqValid
2616 * 0x04, Vsmps1SwHPReqValid
2617 * 0x08, Vsmps2SwHPReqValid
2618 * 0x10, Vsmps3SwHPReqValid
2619 * 0x20, VanaSwHPReqValid
2620 * 0x40, VpllSwHPReqValid
2621 * 0x80, Vaux1SwHPReqValid
2622 */
2623 REG_INIT(AB8540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2624 /*
2625 * 0x01, Vaux2SwHPReqValid
2626 * 0x02, Vaux3SwHPReqValid
2627 * 0x04, VextSupply1SwHPReqValid
2628 * 0x08, VextSupply2SwHPReqValid
2629 * 0x10, VextSupply3SwHPReqValid
2630 */
2631 REG_INIT(AB8540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
2632 /*
2633 * 0x02, SysClkReq2Valid1
2634 * ...
2635 * 0x80, SysClkReq8Valid1
2636 */
2637 REG_INIT(AB8540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xff),
2638 /*
2639 * 0x02, SysClkReq2Valid2
2640 * ...
2641 * 0x80, SysClkReq8Valid2
2642 */
2643 REG_INIT(AB8540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xff),
2644 /*
2645 * 0x01, Vaux4SwHPReqValid
2646 * 0x02, Vaux4HwHPReq2Valid
2647 * 0x04, Vaux4HwHPReq1Valid
2648 * 0x08, Vaux4SysClkReq1HPValid
2649 */
2650 REG_INIT(AB8540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2651 /*
2652 * 0x01, Vaux5SwHPReqValid
2653 * 0x02, Vaux5HwHPReq2Valid
2654 * 0x04, Vaux5HwHPReq1Valid
2655 * 0x08, Vaux5SysClkReq1HPValid
2656 */
2657 REG_INIT(AB8540_REGUVAUX5REQVALID, 0x03, 0x12, 0x0f),
2658 /*
2659 * 0x01, Vaux6SwHPReqValid
2660 * 0x02, Vaux6HwHPReq2Valid
2661 * 0x04, Vaux6HwHPReq1Valid
2662 * 0x08, Vaux6SysClkReq1HPValid
2663 */
2664 REG_INIT(AB8540_REGUVAUX6REQVALID, 0x03, 0x13, 0x0f),
2665 /*
2666 * 0x01, VclkbSwHPReqValid
2667 * 0x02, VclkbHwHPReq2Valid
2668 * 0x04, VclkbHwHPReq1Valid
2669 * 0x08, VclkbSysClkReq1HPValid
2670 */
2671 REG_INIT(AB8540_REGUVCLKBREQVALID, 0x03, 0x14, 0x0f),
2672 /*
2673 * 0x01, Vrf1SwHPReqValid
2674 * 0x02, Vrf1HwHPReq2Valid
2675 * 0x04, Vrf1HwHPReq1Valid
2676 * 0x08, Vrf1SysClkReq1HPValid
2677 */
2678 REG_INIT(AB8540_REGUVRF1REQVALID, 0x03, 0x15, 0x0f),
2679 /*
2680 * 0x02, VTVoutEna
2681 * 0x04, Vintcore12Ena
2682 * 0x38, Vintcore12Sel
2683 * 0x40, Vintcore12LP
2684 * 0x80, VTVoutLP
2685 */
2686 REG_INIT(AB8540_REGUMISC1, 0x03, 0x80, 0xfe),
2687 /*
2688 * 0x02, VaudioEna
2689 * 0x04, VdmicEna
2690 * 0x08, Vamic1Ena
2691 * 0x10, Vamic2Ena
2692 * 0x20, Vamic12LP
2693 * 0xC0, VdmicSel
2694 */
2695 REG_INIT(AB8540_VAUDIOSUPPLY, 0x03, 0x83, 0xfe),
2696 /*
2697 * 0x01, Vamic1_dzout
2698 * 0x02, Vamic2_dzout
2699 */
2700 REG_INIT(AB8540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2701 /*
2702 * 0x07, VHSICSel
2703 * 0x08, VHSICOffState
2704 * 0x10, VHSIEna
2705 * 0x20, VHSICLP
2706 */
2707 REG_INIT(AB8540_VHSIC, 0x03, 0x87, 0x3f),
2708 /*
2709 * 0x07, VSDIOSel
2710 * 0x08, VSDIOOffState
2711 * 0x10, VSDIOEna
2712 * 0x20, VSDIOLP
2713 */
2714 REG_INIT(AB8540_VSDIO, 0x03, 0x88, 0x3f),
2715 /*
2716 * 0x03, Vsmps1Regu
2717 * 0x0c, Vsmps1SelCtrl
2718 * 0x10, Vsmps1AutoMode
2719 * 0x20, Vsmps1PWMMode
2720 */
2721 REG_INIT(AB8540_VSMPS1REGU, 0x04, 0x03, 0x3f),
2722 /*
2723 * 0x03, Vsmps2Regu
2724 * 0x0c, Vsmps2SelCtrl
2725 * 0x10, Vsmps2AutoMode
2726 * 0x20, Vsmps2PWMMode
2727 */
2728 REG_INIT(AB8540_VSMPS2REGU, 0x04, 0x04, 0x3f),
2729 /*
2730 * 0x03, Vsmps3Regu
2731 * 0x0c, Vsmps3SelCtrl
2732 * 0x10, Vsmps3AutoMode
2733 * 0x20, Vsmps3PWMMode
2734 * NOTE! PRCMU register
2735 */
2736 REG_INIT(AB8540_VSMPS3REGU, 0x04, 0x05, 0x0f),
2737 /*
2738 * 0x03, VpllRegu
2739 * 0x0c, VanaRegu
2740 */
2741 REG_INIT(AB8540_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2742 /*
2743 * 0x03, VextSupply1Regu
2744 * 0x0c, VextSupply2Regu
2745 * 0x30, VextSupply3Regu
2746 * 0x40, ExtSupply2Bypass
2747 * 0x80, ExtSupply3Bypass
2748 */
2749 REG_INIT(AB8540_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2750 /*
2751 * 0x03, Vaux1Regu
2752 * 0x0c, Vaux2Regu
2753 */
2754 REG_INIT(AB8540_VAUX12REGU, 0x04, 0x09, 0x0f),
2755 /*
2756 * 0x0c, VRF1Regu
2757 * 0x03, Vaux3Regu
2758 */
2759 REG_INIT(AB8540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2760 /*
2761 * 0x3f, Vsmps1Sel1
2762 */
2763 REG_INIT(AB8540_VSMPS1SEL1, 0x04, 0x13, 0x3f),
2764 /*
2765 * 0x3f, Vsmps1Sel2
2766 */
2767 REG_INIT(AB8540_VSMPS1SEL2, 0x04, 0x14, 0x3f),
2768 /*
2769 * 0x3f, Vsmps1Sel3
2770 */
2771 REG_INIT(AB8540_VSMPS1SEL3, 0x04, 0x15, 0x3f),
2772 /*
2773 * 0x3f, Vsmps2Sel1
2774 */
2775 REG_INIT(AB8540_VSMPS2SEL1, 0x04, 0x17, 0x3f),
2776 /*
2777 * 0x3f, Vsmps2Sel2
2778 */
2779 REG_INIT(AB8540_VSMPS2SEL2, 0x04, 0x18, 0x3f),
2780 /*
2781 * 0x3f, Vsmps2Sel3
2782 */
2783 REG_INIT(AB8540_VSMPS2SEL3, 0x04, 0x19, 0x3f),
2784 /*
2785 * 0x7f, Vsmps3Sel1
2786 * NOTE! PRCMU register
2787 */
2788 REG_INIT(AB8540_VSMPS3SEL1, 0x04, 0x1b, 0x7f),
2789 /*
2790 * 0x7f, Vsmps3Sel2
2791 * NOTE! PRCMU register
2792 */
2793 REG_INIT(AB8540_VSMPS3SEL2, 0x04, 0x1c, 0x7f),
2794 /*
2795 * 0x0f, Vaux1Sel
2796 */
2797 REG_INIT(AB8540_VAUX1SEL, 0x04, 0x1f, 0x0f),
2798 /*
2799 * 0x0f, Vaux2Sel
2800 */
2801 REG_INIT(AB8540_VAUX2SEL, 0x04, 0x20, 0x0f),
2802 /*
2803 * 0x07, Vaux3Sel
2804 * 0x70, Vrf1Sel
2805 */
2806 REG_INIT(AB8540_VRF1VAUX3SEL, 0x04, 0x21, 0x77),
2807 /*
2808 * 0x01, VextSupply12LP
2809 */
2810 REG_INIT(AB8540_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
2811 /*
2812 * 0x07, Vanasel
2813 * 0x30, Vpllsel
2814 */
2815 REG_INIT(AB8540_VANAVPLLSEL, 0x04, 0x29, 0x37),
2816 /*
2817 * 0x03, Vaux4RequestCtrl
2818 */
2819 REG_INIT(AB8540_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2820 /*
2821 * 0x03, Vaux4Regu
2822 */
2823 REG_INIT(AB8540_VAUX4REGU, 0x04, 0x2e, 0x03),
2824 /*
2825 * 0x0f, Vaux4Sel
2826 */
2827 REG_INIT(AB8540_VAUX4SEL, 0x04, 0x2f, 0x0f),
2828 /*
2829 * 0x03, Vaux5RequestCtrl
2830 */
2831 REG_INIT(AB8540_VAUX5REQCTRL, 0x04, 0x31, 0x03),
2832 /*
2833 * 0x03, Vaux5Regu
2834 */
2835 REG_INIT(AB8540_VAUX5REGU, 0x04, 0x32, 0x03),
2836 /*
2837 * 0x3f, Vaux5Sel
2838 */
2839 REG_INIT(AB8540_VAUX5SEL, 0x04, 0x33, 0x3f),
2840 /*
2841 * 0x03, Vaux6RequestCtrl
2842 */
2843 REG_INIT(AB8540_VAUX6REQCTRL, 0x04, 0x34, 0x03),
2844 /*
2845 * 0x03, Vaux6Regu
2846 */
2847 REG_INIT(AB8540_VAUX6REGU, 0x04, 0x35, 0x03),
2848 /*
2849 * 0x3f, Vaux6Sel
2850 */
2851 REG_INIT(AB8540_VAUX6SEL, 0x04, 0x36, 0x3f),
2852 /*
2853 * 0x03, VCLKBRequestCtrl
2854 */
2855 REG_INIT(AB8540_VCLKBREQCTRL, 0x04, 0x37, 0x03),
2856 /*
2857 * 0x03, VCLKBRegu
2858 */
2859 REG_INIT(AB8540_VCLKBREGU, 0x04, 0x38, 0x03),
2860 /*
2861 * 0x07, VCLKBSel
2862 */
2863 REG_INIT(AB8540_VCLKBSEL, 0x04, 0x39, 0x07),
2864 /*
2865 * 0x03, Vrf1RequestCtrl
2866 */
2867 REG_INIT(AB8540_VRF1REQCTRL, 0x04, 0x3a, 0x03),
2868 /*
2869 * 0x01, VpllDisch
2870 * 0x02, Vrf1Disch
2871 * 0x04, Vaux1Disch
2872 * 0x08, Vaux2Disch
2873 * 0x10, Vaux3Disch
2874 * 0x20, Vintcore12Disch
2875 * 0x40, VTVoutDisch
2876 * 0x80, VaudioDisch
2877 */
2878 REG_INIT(AB8540_REGUCTRLDISCH, 0x04, 0x43, 0xff),
2879 /*
2880 * 0x02, VanaDisch
2881 * 0x04, VdmicPullDownEna
2882 * 0x08, VpllPullDownEna
2883 * 0x10, VdmicDisch
2884 */
2885 REG_INIT(AB8540_REGUCTRLDISCH2, 0x04, 0x44, 0x1e),
2886 /*
2887 * 0x01, Vaux4Disch
2888 */
2889 REG_INIT(AB8540_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2890 /*
2891 * 0x01, Vaux5Disch
2892 * 0x02, Vaux6Disch
2893 * 0x04, VCLKBDisch
2894 */
2895 REG_INIT(AB8540_REGUCTRLDISCH4, 0x04, 0x49, 0x07),
2896};
2897
b54969ac 2898static struct of_regulator_match ab8500_regulator_match[] = {
7e715b95
LJ		 2899 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8500_LDO_AUX1, },
2900 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8500_LDO_AUX2, },
2901 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8500_LDO_AUX3, },
2902 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8500_LDO_INTCORE, },
2903 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8500_LDO_TVOUT, },
7e715b95
LJ		 2904 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8500_LDO_AUDIO, },
2905 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8500_LDO_ANAMIC1, },
2906 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, },
2907 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8500_LDO_DMIC, },
2908 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8500_LDO_ANA, },
3a8334b9
LJ		 2909};
2910
547f384f
LJ		 2911static struct of_regulator_match ab8505_regulator_match[] = {
2912 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8505_LDO_AUX1, },
2913 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8505_LDO_AUX2, },
2914 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8505_LDO_AUX3, },
2915 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8505_LDO_AUX4, },
2916 { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8505_LDO_AUX5, },
2917 { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8505_LDO_AUX6, },
2918 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8505_LDO_INTCORE, },
2919 { .name = "ab8500_ldo_adc", .driver_data = (void *) AB8505_LDO_ADC, },
2920 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8505_LDO_AUDIO, },
2921 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8505_LDO_ANAMIC1, },
2922 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, },
2923 { .name = "ab8500_ldo_aux8", .driver_data = (void *) AB8505_LDO_AUX8, },
2924 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8505_LDO_ANA, },
2925};
2926
ae0a9a3e
LJ		 2927static struct of_regulator_match ab8540_regulator_match[] = {
2928 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8540_LDO_AUX1, },
2929 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8540_LDO_AUX2, },
2930 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8540_LDO_AUX3, },
2931 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8540_LDO_AUX4, },
684d5ce4
ZH		 2932 { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8540_LDO_AUX5, },
2933 { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8540_LDO_AUX6, },
ae0a9a3e
LJ		 2934 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8540_LDO_INTCORE, },
2935 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8540_LDO_TVOUT, },
2936 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8540_LDO_AUDIO, },
2937 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8540_LDO_ANAMIC1, },
2938 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8540_LDO_ANAMIC2, },
2939 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8540_LDO_DMIC, },
2940 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8540_LDO_ANA, },
2941 { .name = "ab8500_ldo_sdio", .driver_data = (void *) AB8540_LDO_SDIO, },
2942};
2943
8e6a8d7d
LJ		 2944static struct of_regulator_match ab9540_regulator_match[] = {
2945 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB9540_LDO_AUX1, },
2946 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB9540_LDO_AUX2, },
2947 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB9540_LDO_AUX3, },
2948 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB9540_LDO_AUX4, },
2949 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB9540_LDO_INTCORE, },
2950 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB9540_LDO_TVOUT, },
2951 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB9540_LDO_AUDIO, },
2952 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB9540_LDO_ANAMIC1, },
2953 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB9540_LDO_ANAMIC2, },
2954 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB9540_LDO_DMIC, },
2955 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB9540_LDO_ANA, },
2956};
2957
da45edc7
LJ		 2958static struct {
2959 struct ab8500_regulator_info *info;
2960 int info_size;
2961 struct ab8500_reg_init *init;
2962 int init_size;
2963 struct of_regulator_match *match;
2964 int match_size;
2965} abx500_regulator;
2966
33aeb49e
LJ		 2967static void abx500_get_regulator_info(struct ab8500 *ab8500)
2968{
2969 if (is_ab9540(ab8500)) {
2970 abx500_regulator.info = ab9540_regulator_info;
2971 abx500_regulator.info_size = ARRAY_SIZE(ab9540_regulator_info);
2972 abx500_regulator.init = ab9540_reg_init;
2973 abx500_regulator.init_size = AB9540_NUM_REGULATOR_REGISTERS;
2974 abx500_regulator.match = ab9540_regulator_match;
2975 abx500_regulator.match_size = ARRAY_SIZE(ab9540_regulator_match);
2976 } else if (is_ab8505(ab8500)) {
2977 abx500_regulator.info = ab8505_regulator_info;
2978 abx500_regulator.info_size = ARRAY_SIZE(ab8505_regulator_info);
2979 abx500_regulator.init = ab8505_reg_init;
2980 abx500_regulator.init_size = AB8505_NUM_REGULATOR_REGISTERS;
2981 abx500_regulator.match = ab8505_regulator_match;
2982 abx500_regulator.match_size = ARRAY_SIZE(ab8505_regulator_match);
2983 } else if (is_ab8540(ab8500)) {
2984 abx500_regulator.info = ab8540_regulator_info;
2985 abx500_regulator.info_size = ARRAY_SIZE(ab8540_regulator_info);
2986 abx500_regulator.init = ab8540_reg_init;
2987 abx500_regulator.init_size = AB8540_NUM_REGULATOR_REGISTERS;
2988 abx500_regulator.match = ab8540_regulator_match;
2989 abx500_regulator.match_size = ARRAY_SIZE(ab8540_regulator_match);
2990 } else {
2991 abx500_regulator.info = ab8500_regulator_info;
2992 abx500_regulator.info_size = ARRAY_SIZE(ab8500_regulator_info);
2993 abx500_regulator.init = ab8500_reg_init;
2994 abx500_regulator.init_size = AB8500_NUM_REGULATOR_REGISTERS;
2995 abx500_regulator.match = ab8500_regulator_match;
2996 abx500_regulator.match_size = ARRAY_SIZE(ab8500_regulator_match);
2997 }
2998}
2999
da45edc7
LJ		 3000static int ab8500_regulator_init_registers(struct platform_device *pdev,
3001 int id, int mask, int value)
3002{
3003 struct ab8500_reg_init *reg_init = abx500_regulator.init;
3004 int err;
3005
3006 BUG_ON(value & ~mask);
3007 BUG_ON(mask & ~reg_init[id].mask);
3008
3009 /* initialize register */
3010 err = abx500_mask_and_set_register_interruptible(
3011 &pdev->dev,
3012 reg_init[id].bank,
3013 reg_init[id].addr,
3014 mask, value);
3015 if (err < 0) {
3016 dev_err(&pdev->dev,
3017 "Failed to initialize 0x%02x, 0x%02x.\n",
3018 reg_init[id].bank,
3019 reg_init[id].addr);
3020 return err;
3021 }
3022 dev_vdbg(&pdev->dev,
3023 " init: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",
3024 reg_init[id].bank,
3025 reg_init[id].addr,
3026 mask, value);
3027
3028 return 0;
3029}
3030
3031static int ab8500_regulator_register(struct platform_device *pdev,
3032 struct regulator_init_data *init_data,
3033 int id, struct device_node *np)
3034{
3035 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
3036 struct ab8500_regulator_info *info = NULL;
3037 struct regulator_config config = { };
3038 int err;
3039
3040 /* assign per-regulator data */
3041 info = &abx500_regulator.info[id];
3042 info->dev = &pdev->dev;
3043
3044 config.dev = &pdev->dev;
3045 config.init_data = init_data;
3046 config.driver_data = info;
3047 config.of_node = np;
3048
3049 /* fix for hardware before ab8500v2.0 */
3050 if (is_ab8500_1p1_or_earlier(ab8500)) {
3051 if (info->desc.id == AB8500_LDO_AUX3) {
3052 info->desc.n_voltages =
3053 ARRAY_SIZE(ldo_vauxn_voltages);
3054 info->desc.volt_table = ldo_vauxn_voltages;
3055 info->voltage_mask = 0xf;
3056 }
3057 }
3058
3059 /* register regulator with framework */
3060 info->regulator = regulator_register(&info->desc, &config);
3061 if (IS_ERR(info->regulator)) {
3062 err = PTR_ERR(info->regulator);
3063 dev_err(&pdev->dev, "failed to register regulator %s\n",
3064 info->desc.name);
3065 /* when we fail, un-register all earlier regulators */
3066 while (--id >= 0) {
3067 info = &abx500_regulator.info[id];
3068 regulator_unregister(info->regulator);
3069 }
3070 return err;
3071 }
3072
3073 return 0;
3074}
3075
a5023574 3076static int
b54969ac 3077ab8500_regulator_of_probe(struct platform_device *pdev,
b54969ac 3078 struct device_node *np)
3a8334b9 3079{
33aeb49e 3080 struct of_regulator_match *match = abx500_regulator.match;
3a8334b9
LJ		 3081 int err, i;
3082
33aeb49e 3083 for (i = 0; i < abx500_regulator.info_size; i++) {
3a8334b9 3084 err = ab8500_regulator_register(
33aeb49e 3085 pdev, match[i].init_data, i, match[i].of_node);
3a8334b9
LJ		 3086 if (err)
3087 return err;
3088 }
3089
3090 return 0;
3091}
3092
a5023574 3093static int ab8500_regulator_probe(struct platform_device *pdev)
c789ca20
SI		 3094{
3095 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
3a8334b9 3096 struct device_node *np = pdev->dev.of_node;
732805a5
BJ		 3097 struct ab8500_platform_data *ppdata;
3098 struct ab8500_regulator_platform_data *pdata;
c789ca20 3099 int i, err;
b54969ac 3100
33aeb49e
LJ		 3101 if (!ab8500) {
3102 dev_err(&pdev->dev, "null mfd parent\n");
3103 return -EINVAL;
8e6a8d7d 3104 }
c789ca20 3105
33aeb49e
LJ		 3106 abx500_get_regulator_info(ab8500);
3107
3a8334b9 3108 if (np) {
33aeb49e
LJ		 3109 err = of_regulator_match(&pdev->dev, np,
3110 abx500_regulator.match,
3111 abx500_regulator.match_size);
3a8334b9
LJ		 3112 if (err < 0) {
3113 dev_err(&pdev->dev,
3114 "Error parsing regulator init data: %d\n", err);
3115 return err;
3116 }
3117
33aeb49e 3118 err = ab8500_regulator_of_probe(pdev, np);
3a8334b9
LJ		 3119 return err;
3120 }
3121
732805a5
BJ		 3122 ppdata = dev_get_platdata(ab8500->dev);
3123 if (!ppdata) {
3124 dev_err(&pdev->dev, "null parent pdata\n");
3125 return -EINVAL;
3126 }
3127
3128 pdata = ppdata->regulator;
fc24b426
BJ		 3129 if (!pdata) {
3130 dev_err(&pdev->dev, "null pdata\n");
3131 return -EINVAL;
3132 }
c789ca20 3133
cb189b07 3134 /* make sure the platform data has the correct size */
33aeb49e 3135 if (pdata->num_regulator != abx500_regulator.info_size) {
79568b94 3136 dev_err(&pdev->dev, "Configuration error: size mismatch.\n");
cb189b07
BJ		 3137 return -EINVAL;
3138 }
3139
da0b0c47
LJ		 3140 /* initialize debug (initial state is recorded with this call) */
3141 err = ab8500_regulator_debug_init(pdev);
3142 if (err)
3143 return err;
3144
79568b94 3145 /* initialize registers */
732805a5 3146 for (i = 0; i < pdata->num_reg_init; i++) {
3c1b8438 3147 int id, mask, value;
79568b94 3148
732805a5
BJ		 3149 id = pdata->reg_init[i].id;
3150 mask = pdata->reg_init[i].mask;
3151 value = pdata->reg_init[i].value;
79568b94
BJ		 3152
3153 /* check for configuration errors */
33aeb49e 3154 BUG_ON(id >= abx500_regulator.init_size);
79568b94 3155
33aeb49e 3156 err = ab8500_regulator_init_registers(pdev, id, mask, value);
a7ac1d9e 3157 if (err < 0)
79568b94 3158 return err;
79568b94
BJ		 3159 }
3160
f7eae37f
RV		 3161 if (!is_ab8505(ab8500)) {
3162 /* register external regulators (before Vaux1, 2 and 3) */
3163 err = ab8500_ext_regulator_init(pdev);
3164 if (err)
3165 return err;
3166 }
d1a82001 3167
c789ca20 3168 /* register all regulators */
33aeb49e 3169 for (i = 0; i < abx500_regulator.info_size; i++) {
b54969ac 3170 err = ab8500_regulator_register(pdev, &pdata->regulator[i],
33aeb49e 3171 i, NULL);
42e8c811
AL		 3172 if (err < 0) {
3173 if (!is_ab8505(ab8500))
3174 ab8500_ext_regulator_exit(pdev);
c789ca20 3175 return err;
42e8c811 3176 }
c789ca20
SI		 3177 }
3178
3179 return 0;
3180}
3181
8dc995f5 3182static int ab8500_regulator_remove(struct platform_device *pdev)
c789ca20 3183{
d1a82001 3184 int i, err;
8e6a8d7d 3185 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
b54969ac 3186
33aeb49e 3187 for (i = 0; i < abx500_regulator.info_size; i++) {
c789ca20 3188 struct ab8500_regulator_info *info = NULL;
33aeb49e 3189 info = &abx500_regulator.info[i];
09aefa12
BJ		 3190
3191 dev_vdbg(rdev_get_dev(info->regulator),
3192 "%s-remove\n", info->desc.name);
3193
c789ca20
SI		 3194 regulator_unregister(info->regulator);
3195 }
3196
3480c0ca
AL		 3197 /* remove external regulators (after Vaux1, 2 and 3) */
3198 if (!is_ab8505(ab8500))
3199 ab8500_ext_regulator_exit(pdev);
d1a82001 3200
da0b0c47
LJ		 3201 /* remove regulator debug */
3202 err = ab8500_regulator_debug_exit(pdev);
3203 if (err)
3204 return err;
3205
c789ca20
SI		 3206 return 0;
3207}
3208
3209static struct platform_driver ab8500_regulator_driver = {
3210 .probe = ab8500_regulator_probe,
5eb9f2b9 3211 .remove = ab8500_regulator_remove,
c789ca20
SI		 3212 .driver = {
3213 .name = "ab8500-regulator",
3214 .owner = THIS_MODULE,
3215 },
3216};
3217
3218static int __init ab8500_regulator_init(void)
3219{
3220 int ret;
3221
3222 ret = platform_driver_register(&ab8500_regulator_driver);
3223 if (ret != 0)
3224 pr_err("Failed to register ab8500 regulator: %d\n", ret);
3225
3226 return ret;
3227}
3228subsys_initcall(ab8500_regulator_init);
3229
3230static void __exit ab8500_regulator_exit(void)
3231{
3232 platform_driver_unregister(&ab8500_regulator_driver);
3233}
3234module_exit(ab8500_regulator_exit);
3235
3236MODULE_LICENSE("GPL v2");
3237MODULE_AUTHOR("Sundar Iyer <sundar.iyer@stericsson.com>");
732805a5 3238MODULE_AUTHOR("Bengt Jonsson <bengt.g.jonsson@stericsson.com>");
547f384f 3239MODULE_AUTHOR("Daniel Willerud <daniel.willerud@stericsson.com>");
c789ca20
SI		 3240MODULE_DESCRIPTION("Regulator Driver for ST-Ericsson AB8500 Mixed-Sig PMIC");
3241MODULE_ALIAS("platform:ab8500-regulator");
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