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regulator: ab8500: Don't update is_enabled flag in error paths
[mirror_ubuntu-zesty-kernel.git] / drivers / regulator / ab8500.c
CommitLineData
c789ca20
SI		 1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 *
e1159e6d
BJ		 6 * Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson
7 * Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson
c789ca20
SI		 8 *
9 * AB8500 peripheral regulators
10 *
e1159e6d 11 * AB8500 supports the following regulators:
ea05ef31 12 * VAUX1/2/3, VINTCORE, VTVOUT, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
c789ca20
SI		 13 */
14#include <linux/init.h>
15#include <linux/kernel.h>
65602c32 16#include <linux/module.h>
c789ca20
SI		 17#include <linux/err.h>
18#include <linux/platform_device.h>
47c16975 19#include <linux/mfd/abx500.h>
ee66e653 20#include <linux/mfd/abx500/ab8500.h>
3a8334b9
LJ		 21#include <linux/of.h>
22#include <linux/regulator/of_regulator.h>
c789ca20
SI		 23#include <linux/regulator/driver.h>
24#include <linux/regulator/machine.h>
25#include <linux/regulator/ab8500.h>
3a8334b9 26#include <linux/slab.h>
c789ca20
SI		 27
28/**
29 * struct ab8500_regulator_info - ab8500 regulator information
e1159e6d 30 * @dev: device pointer
c789ca20 31 * @desc: regulator description
c789ca20 32 * @regulator_dev: regulator device
bd28a157 33 * @is_enabled: status of regulator (on/off)
7ce4669c 34 * @load_lp_uA: maximum load in idle (low power) mode
47c16975 35 * @update_bank: bank to control on/off
c789ca20 36 * @update_reg: register to control on/off
bd28a157
EV		 37 * @update_mask: mask to enable/disable and set mode of regulator
38 * @update_val: bits holding the regulator current mode
39 * @update_val_idle: bits to enable the regulator in idle (low power) mode
40 * @update_val_normal: bits to enable the regulator in normal (high power) mode
47c16975 41 * @voltage_bank: bank to control regulator voltage
c789ca20
SI		 42 * @voltage_reg: register to control regulator voltage
43 * @voltage_mask: mask to control regulator voltage
a0a7014c 44 * @voltage_shift: shift to control regulator voltage
42ab616a 45 * @delay: startup/set voltage delay in us
c789ca20
SI		 46 */
47struct ab8500_regulator_info {
48 struct device *dev;
49 struct regulator_desc desc;
c789ca20 50 struct regulator_dev *regulator;
bd28a157 51 bool is_enabled;
7ce4669c 52 int load_lp_uA;
47c16975
MW		 53 u8 update_bank;
54 u8 update_reg;
e1159e6d 55 u8 update_mask;
bd28a157
EV		 56 u8 update_val;
57 u8 update_val_idle;
58 u8 update_val_normal;
47c16975
MW		 59 u8 voltage_bank;
60 u8 voltage_reg;
61 u8 voltage_mask;
a0a7014c 62 u8 voltage_shift;
42ab616a 63 unsigned int delay;
c789ca20
SI		 64};
65
66/* voltage tables for the vauxn/vintcore supplies */
ec1cc4d9 67static const unsigned int ldo_vauxn_voltages[] = {
c789ca20
SI		 68 1100000,
69 1200000,
70 1300000,
71 1400000,
72 1500000,
73 1800000,
74 1850000,
75 1900000,
76 2500000,
77 2650000,
78 2700000,
79 2750000,
80 2800000,
81 2900000,
82 3000000,
83 3300000,
84};
85
ec1cc4d9 86static const unsigned int ldo_vaux3_voltages[] = {
2b75151a
BJ		 87 1200000,
88 1500000,
89 1800000,
90 2100000,
91 2500000,
92 2750000,
93 2790000,
94 2910000,
95};
96
ec1cc4d9 97static const unsigned int ldo_vintcore_voltages[] = {
c789ca20
SI		 98 1200000,
99 1225000,
100 1250000,
101 1275000,
102 1300000,
103 1325000,
104 1350000,
105};
106
107static int ab8500_regulator_enable(struct regulator_dev *rdev)
108{
fc24b426 109 int ret;
c789ca20
SI		 110 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
111
fc24b426
BJ		 112 if (info == NULL) {
113 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 114 return -EINVAL;
fc24b426 115 }
c789ca20 116
47c16975 117 ret = abx500_mask_and_set_register_interruptible(info->dev,
e1159e6d 118 info->update_bank, info->update_reg,
bd28a157 119 info->update_mask, info->update_val);
f71bf528 120 if (ret < 0) {
c789ca20
SI		 121 dev_err(rdev_get_dev(rdev),
122 "couldn't set enable bits for regulator\n");
f71bf528
AL		 123 return ret;
124 }
09aefa12 125
bd28a157
EV		 126 info->is_enabled = true;
127
09aefa12
BJ		 128 dev_vdbg(rdev_get_dev(rdev),
129 "%s-enable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
130 info->desc.name, info->update_bank, info->update_reg,
bd28a157 131 info->update_mask, info->update_val);
09aefa12 132
c789ca20
SI		 133 return ret;
134}
135
136static int ab8500_regulator_disable(struct regulator_dev *rdev)
137{
fc24b426 138 int ret;
c789ca20
SI		 139 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
140
fc24b426
BJ		 141 if (info == NULL) {
142 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 143 return -EINVAL;
fc24b426 144 }
c789ca20 145
47c16975 146 ret = abx500_mask_and_set_register_interruptible(info->dev,
e1159e6d
BJ		 147 info->update_bank, info->update_reg,
148 info->update_mask, 0x0);
f71bf528 149 if (ret < 0) {
c789ca20
SI		 150 dev_err(rdev_get_dev(rdev),
151 "couldn't set disable bits for regulator\n");
f71bf528
AL		 152 return ret;
153 }
09aefa12 154
bd28a157
EV		 155 info->is_enabled = false;
156
09aefa12
BJ		 157 dev_vdbg(rdev_get_dev(rdev),
158 "%s-disable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
159 info->desc.name, info->update_bank, info->update_reg,
160 info->update_mask, 0x0);
161
c789ca20
SI		 162 return ret;
163}
164
7ce4669c
BJ		 165static unsigned int ab8500_regulator_get_optimum_mode(
166 struct regulator_dev *rdev, int input_uV,
167 int output_uV, int load_uA)
168{
169 unsigned int mode;
170
171 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
172
173 if (info == NULL) {
174 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
175 return -EINVAL;
176 }
177
178 if (load_uA <= info->load_lp_uA)
179 mode = REGULATOR_MODE_IDLE;
180 else
181 mode = REGULATOR_MODE_NORMAL;
182
183 return mode;
184}
185
bd28a157
EV		 186static int ab8500_regulator_set_mode(struct regulator_dev *rdev,
187 unsigned int mode)
188{
189 int ret = 0;
190
191 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
192
193 if (info == NULL) {
194 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
195 return -EINVAL;
196 }
197
198 switch (mode) {
199 case REGULATOR_MODE_NORMAL:
200 info->update_val = info->update_val_normal;
201 break;
202 case REGULATOR_MODE_IDLE:
203 info->update_val = info->update_val_idle;
204 break;
205 default:
206 return -EINVAL;
207 }
208
209 if (info->is_enabled) {
210 ret = abx500_mask_and_set_register_interruptible(info->dev,
211 info->update_bank, info->update_reg,
212 info->update_mask, info->update_val);
213 if (ret < 0)
214 dev_err(rdev_get_dev(rdev),
215 "couldn't set regulator mode\n");
7ce4669c
BJ		 216
217 dev_vdbg(rdev_get_dev(rdev),
218 "%s-set_mode (bank, reg, mask, value): "
219 "0x%x, 0x%x, 0x%x, 0x%x\n",
220 info->desc.name, info->update_bank, info->update_reg,
221 info->update_mask, info->update_val);
bd28a157
EV		 222 }
223
224 return ret;
225}
226
227static unsigned int ab8500_regulator_get_mode(struct regulator_dev *rdev)
228{
229 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
230 int ret;
231
232 if (info == NULL) {
233 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
234 return -EINVAL;
235 }
236
237 if (info->update_val == info->update_val_normal)
238 ret = REGULATOR_MODE_NORMAL;
239 else if (info->update_val == info->update_val_idle)
240 ret = REGULATOR_MODE_IDLE;
241 else
242 ret = -EINVAL;
243
244 return ret;
245}
246
c789ca20
SI		 247static int ab8500_regulator_is_enabled(struct regulator_dev *rdev)
248{
fc24b426 249 int ret;
c789ca20 250 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
09aefa12 251 u8 regval;
c789ca20 252
fc24b426
BJ		 253 if (info == NULL) {
254 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 255 return -EINVAL;
fc24b426 256 }
c789ca20 257
47c16975 258 ret = abx500_get_register_interruptible(info->dev,
09aefa12 259 info->update_bank, info->update_reg, &regval);
c789ca20
SI		 260 if (ret < 0) {
261 dev_err(rdev_get_dev(rdev),
262 "couldn't read 0x%x register\n", info->update_reg);
263 return ret;
264 }
265
09aefa12
BJ		 266 dev_vdbg(rdev_get_dev(rdev),
267 "%s-is_enabled (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
268 " 0x%x\n",
269 info->desc.name, info->update_bank, info->update_reg,
270 info->update_mask, regval);
271
272 if (regval & info->update_mask)
bd28a157 273 info->is_enabled = true;
c789ca20 274 else
bd28a157
EV		 275 info->is_enabled = false;
276
277 return info->is_enabled;
c789ca20
SI		 278}
279
3bf6e90e 280static int ab8500_regulator_get_voltage_sel(struct regulator_dev *rdev)
c789ca20 281{
09aefa12 282 int ret, val;
c789ca20 283 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
09aefa12 284 u8 regval;
c789ca20 285
fc24b426
BJ		 286 if (info == NULL) {
287 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 288 return -EINVAL;
fc24b426 289 }
c789ca20 290
09aefa12
BJ		 291 ret = abx500_get_register_interruptible(info->dev,
292 info->voltage_bank, info->voltage_reg, &regval);
c789ca20
SI		 293 if (ret < 0) {
294 dev_err(rdev_get_dev(rdev),
295 "couldn't read voltage reg for regulator\n");
296 return ret;
297 }
298
09aefa12 299 dev_vdbg(rdev_get_dev(rdev),
a0a7014c
LW		 300 "%s-get_voltage (bank, reg, mask, shift, value): "
301 "0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
302 info->desc.name, info->voltage_bank,
303 info->voltage_reg, info->voltage_mask,
304 info->voltage_shift, regval);
09aefa12 305
09aefa12 306 val = regval & info->voltage_mask;
a0a7014c 307 return val >> info->voltage_shift;
c789ca20
SI		 308}
309
ae713d39
AL		 310static int ab8500_regulator_set_voltage_sel(struct regulator_dev *rdev,
311 unsigned selector)
c789ca20 312{
fc24b426 313 int ret;
c789ca20 314 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
09aefa12 315 u8 regval;
c789ca20 316
fc24b426
BJ		 317 if (info == NULL) {
318 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 319 return -EINVAL;
fc24b426 320 }
c789ca20 321
c789ca20 322 /* set the registers for the request */
a0a7014c 323 regval = (u8)selector << info->voltage_shift;
47c16975 324 ret = abx500_mask_and_set_register_interruptible(info->dev,
09aefa12
BJ		 325 info->voltage_bank, info->voltage_reg,
326 info->voltage_mask, regval);
c789ca20
SI		 327 if (ret < 0)
328 dev_err(rdev_get_dev(rdev),
329 "couldn't set voltage reg for regulator\n");
330
09aefa12
BJ		 331 dev_vdbg(rdev_get_dev(rdev),
332 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
333 " 0x%x\n",
334 info->desc.name, info->voltage_bank, info->voltage_reg,
335 info->voltage_mask, regval);
336
c789ca20
SI		 337 return ret;
338}
339
42ab616a
LW		 340static int ab8500_regulator_set_voltage_time_sel(struct regulator_dev *rdev,
341 unsigned int old_sel,
342 unsigned int new_sel)
343{
344 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
42ab616a 345
42ab616a
LW		 346 return info->delay;
347}
348
7ce4669c
BJ		 349static struct regulator_ops ab8500_regulator_volt_mode_ops = {
350 .enable = ab8500_regulator_enable,
351 .disable = ab8500_regulator_disable,
352 .is_enabled = ab8500_regulator_is_enabled,
353 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
354 .set_mode = ab8500_regulator_set_mode,
355 .get_mode = ab8500_regulator_get_mode,
356 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
357 .set_voltage_sel = ab8500_regulator_set_voltage_sel,
358 .list_voltage = regulator_list_voltage_table,
359 .set_voltage_time_sel = ab8500_regulator_set_voltage_time_sel,
c789ca20
SI		 360};
361
7ce4669c
BJ		 362static struct regulator_ops ab8500_regulator_mode_ops = {
363 .enable = ab8500_regulator_enable,
364 .disable = ab8500_regulator_disable,
365 .is_enabled = ab8500_regulator_is_enabled,
366 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
367 .set_mode = ab8500_regulator_set_mode,
368 .get_mode = ab8500_regulator_get_mode,
369 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
5689e830 370 .list_voltage = regulator_list_voltage_linear,
7ce4669c
BJ		 371};
372
373static struct regulator_ops ab8500_regulator_ops = {
374 .enable = ab8500_regulator_enable,
375 .disable = ab8500_regulator_disable,
376 .is_enabled = ab8500_regulator_is_enabled,
377 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
5689e830 378 .list_voltage = regulator_list_voltage_linear,
c789ca20
SI		 379};
380
6909b452
BJ		 381static struct ab8500_regulator_info
382 ab8500_regulator_info[AB8500_NUM_REGULATORS] = {
c789ca20 383 /*
e1159e6d
BJ		 384 * Variable Voltage Regulators
385 * name, min mV, max mV,
386 * update bank, reg, mask, enable val
ec1cc4d9 387 * volt bank, reg, mask
c789ca20 388 */
6909b452
BJ		 389 [AB8500_LDO_AUX1] = {
390 .desc = {
391 .name = "LDO-AUX1",
7ce4669c 392 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 393 .type = REGULATOR_VOLTAGE,
394 .id = AB8500_LDO_AUX1,
395 .owner = THIS_MODULE,
396 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
ec1cc4d9 397 .volt_table = ldo_vauxn_voltages,
6909b452 398 },
7ce4669c 399 .load_lp_uA = 5000,
6909b452
BJ		 400 .update_bank = 0x04,
401 .update_reg = 0x09,
402 .update_mask = 0x03,
bd28a157
EV		 403 .update_val = 0x01,
404 .update_val_idle = 0x03,
405 .update_val_normal = 0x01,
6909b452
BJ		 406 .voltage_bank = 0x04,
407 .voltage_reg = 0x1f,
408 .voltage_mask = 0x0f,
6909b452
BJ		 409 },
410 [AB8500_LDO_AUX2] = {
411 .desc = {
412 .name = "LDO-AUX2",
7ce4669c 413 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 414 .type = REGULATOR_VOLTAGE,
415 .id = AB8500_LDO_AUX2,
416 .owner = THIS_MODULE,
417 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
ec1cc4d9 418 .volt_table = ldo_vauxn_voltages,
6909b452 419 },
7ce4669c 420 .load_lp_uA = 5000,
6909b452
BJ		 421 .update_bank = 0x04,
422 .update_reg = 0x09,
423 .update_mask = 0x0c,
bd28a157
EV		 424 .update_val = 0x04,
425 .update_val_idle = 0x0c,
426 .update_val_normal = 0x04,
6909b452
BJ		 427 .voltage_bank = 0x04,
428 .voltage_reg = 0x20,
429 .voltage_mask = 0x0f,
6909b452
BJ		 430 },
431 [AB8500_LDO_AUX3] = {
432 .desc = {
433 .name = "LDO-AUX3",
7ce4669c 434 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 435 .type = REGULATOR_VOLTAGE,
436 .id = AB8500_LDO_AUX3,
437 .owner = THIS_MODULE,
438 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
ec1cc4d9 439 .volt_table = ldo_vaux3_voltages,
6909b452 440 },
7ce4669c 441 .load_lp_uA = 5000,
6909b452
BJ		 442 .update_bank = 0x04,
443 .update_reg = 0x0a,
444 .update_mask = 0x03,
bd28a157
EV		 445 .update_val = 0x01,
446 .update_val_idle = 0x03,
447 .update_val_normal = 0x01,
6909b452
BJ		 448 .voltage_bank = 0x04,
449 .voltage_reg = 0x21,
450 .voltage_mask = 0x07,
6909b452
BJ		 451 },
452 [AB8500_LDO_INTCORE] = {
453 .desc = {
454 .name = "LDO-INTCORE",
7ce4669c 455 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 456 .type = REGULATOR_VOLTAGE,
457 .id = AB8500_LDO_INTCORE,
458 .owner = THIS_MODULE,
459 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
ec1cc4d9 460 .volt_table = ldo_vintcore_voltages,
6909b452 461 },
7ce4669c 462 .load_lp_uA = 5000,
6909b452
BJ		 463 .update_bank = 0x03,
464 .update_reg = 0x80,
465 .update_mask = 0x44,
bd28a157
EV		 466 .update_val = 0x04,
467 .update_val_idle = 0x44,
468 .update_val_normal = 0x04,
6909b452
BJ		 469 .voltage_bank = 0x03,
470 .voltage_reg = 0x80,
471 .voltage_mask = 0x38,
a0a7014c 472 .voltage_shift = 3,
6909b452 473 },
c789ca20
SI		 474
475 /*
e1159e6d
BJ		 476 * Fixed Voltage Regulators
477 * name, fixed mV,
478 * update bank, reg, mask, enable val
c789ca20 479 */
6909b452
BJ		 480 [AB8500_LDO_TVOUT] = {
481 .desc = {
482 .name = "LDO-TVOUT",
7ce4669c 483 .ops = &ab8500_regulator_mode_ops,
6909b452
BJ		 484 .type = REGULATOR_VOLTAGE,
485 .id = AB8500_LDO_TVOUT,
486 .owner = THIS_MODULE,
487 .n_voltages = 1,
7142e213 488 .min_uV = 2000000,
7fee2afb 489 .enable_time = 10000,
6909b452 490 },
42ab616a 491 .delay = 10000,
7ce4669c 492 .load_lp_uA = 1000,
6909b452
BJ		 493 .update_bank = 0x03,
494 .update_reg = 0x80,
495 .update_mask = 0x82,
bd28a157 496 .update_val = 0x02,
7ce4669c
BJ		 497 .update_val_idle = 0x82,
498 .update_val_normal = 0x02,
6909b452 499 },
328a5369
AL		 500
501 /*
502 * Regulators with fixed voltage and normal mode
503 */
ea05ef31
BJ		 504 [AB8500_LDO_USB] = {
505 .desc = {
506 .name = "LDO-USB",
328a5369 507 .ops = &ab8500_regulator_ops,
ea05ef31
BJ		 508 .type = REGULATOR_VOLTAGE,
509 .id = AB8500_LDO_USB,
510 .owner = THIS_MODULE,
511 .n_voltages = 1,
7142e213 512 .min_uV = 3300000,
ea05ef31 513 },
ea05ef31
BJ		 514 .update_bank = 0x03,
515 .update_reg = 0x82,
516 .update_mask = 0x03,
ea05ef31 517 },
6909b452
BJ		 518 [AB8500_LDO_AUDIO] = {
519 .desc = {
520 .name = "LDO-AUDIO",
7ce4669c 521 .ops = &ab8500_regulator_ops,
6909b452
BJ		 522 .type = REGULATOR_VOLTAGE,
523 .id = AB8500_LDO_AUDIO,
524 .owner = THIS_MODULE,
525 .n_voltages = 1,
7142e213 526 .min_uV = 2000000,
6909b452 527 },
6909b452
BJ		 528 .update_bank = 0x03,
529 .update_reg = 0x83,
530 .update_mask = 0x02,
bd28a157 531 .update_val = 0x02,
6909b452
BJ		 532 },
533 [AB8500_LDO_ANAMIC1] = {
534 .desc = {
535 .name = "LDO-ANAMIC1",
7ce4669c 536 .ops = &ab8500_regulator_ops,
6909b452
BJ		 537 .type = REGULATOR_VOLTAGE,
538 .id = AB8500_LDO_ANAMIC1,
539 .owner = THIS_MODULE,
540 .n_voltages = 1,
7142e213 541 .min_uV = 2050000,
6909b452 542 },
6909b452
BJ		 543 .update_bank = 0x03,
544 .update_reg = 0x83,
545 .update_mask = 0x08,
bd28a157 546 .update_val = 0x08,
6909b452
BJ		 547 },
548 [AB8500_LDO_ANAMIC2] = {
549 .desc = {
550 .name = "LDO-ANAMIC2",
7ce4669c 551 .ops = &ab8500_regulator_ops,
6909b452
BJ		 552 .type = REGULATOR_VOLTAGE,
553 .id = AB8500_LDO_ANAMIC2,
554 .owner = THIS_MODULE,
555 .n_voltages = 1,
7142e213 556 .min_uV = 2050000,
6909b452 557 },
6909b452
BJ		 558 .update_bank = 0x03,
559 .update_reg = 0x83,
560 .update_mask = 0x10,
bd28a157 561 .update_val = 0x10,
6909b452
BJ		 562 },
563 [AB8500_LDO_DMIC] = {
564 .desc = {
565 .name = "LDO-DMIC",
7ce4669c 566 .ops = &ab8500_regulator_ops,
6909b452
BJ		 567 .type = REGULATOR_VOLTAGE,
568 .id = AB8500_LDO_DMIC,
569 .owner = THIS_MODULE,
570 .n_voltages = 1,
7142e213 571 .min_uV = 1800000,
6909b452 572 },
6909b452
BJ		 573 .update_bank = 0x03,
574 .update_reg = 0x83,
575 .update_mask = 0x04,
bd28a157 576 .update_val = 0x04,
6909b452 577 },
7ce4669c
BJ		 578
579 /*
580 * Regulators with fixed voltage and normal/idle modes
581 */
6909b452
BJ		 582 [AB8500_LDO_ANA] = {
583 .desc = {
584 .name = "LDO-ANA",
7ce4669c 585 .ops = &ab8500_regulator_mode_ops,
6909b452
BJ		 586 .type = REGULATOR_VOLTAGE,
587 .id = AB8500_LDO_ANA,
588 .owner = THIS_MODULE,
589 .n_voltages = 1,
7142e213 590 .min_uV = 1200000,
6909b452 591 },
7ce4669c 592 .load_lp_uA = 1000,
6909b452
BJ		 593 .update_bank = 0x04,
594 .update_reg = 0x06,
595 .update_mask = 0x0c,
bd28a157 596 .update_val = 0x04,
7ce4669c
BJ		 597 .update_val_idle = 0x0c,
598 .update_val_normal = 0x04,
6909b452
BJ		 599 },
600
601
c789ca20
SI		 602};
603
79568b94
BJ		 604struct ab8500_reg_init {
605 u8 bank;
606 u8 addr;
607 u8 mask;
608};
609
610#define REG_INIT(_id, _bank, _addr, _mask) \
611 [_id] = { \
612 .bank = _bank, \
613 .addr = _addr, \
614 .mask = _mask, \
615 }
616
617static struct ab8500_reg_init ab8500_reg_init[] = {
618 /*
33bc8f46
LJ		 619 * 0x03, VarmRequestCtrl
620 * 0x0c, VapeRequestCtrl
621 * 0x30, Vsmps1RequestCtrl
622 * 0xc0, Vsmps2RequestCtrl
623 */
624 REG_INIT(AB8500_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
625 /*
626 * 0x03, Vsmps3RequestCtrl
d79df329 627 * 0x0c, VpllRequestCtrl
33bc8f46 628 * 0x30, VanaRequestCtrl
79568b94
BJ		 629 * 0xc0, VextSupply1RequestCtrl
630 */
33bc8f46 631 REG_INIT(AB8500_REGUREQUESTCTRL2, 0x03, 0x04, 0xff),
79568b94
BJ		 632 /*
633 * 0x03, VextSupply2RequestCtrl
634 * 0x0c, VextSupply3RequestCtrl
635 * 0x30, Vaux1RequestCtrl
636 * 0xc0, Vaux2RequestCtrl
637 */
638 REG_INIT(AB8500_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
639 /*
640 * 0x03, Vaux3RequestCtrl
641 * 0x04, SwHPReq
642 */
643 REG_INIT(AB8500_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
644 /*
d79df329
LJ		 645 * 0x01, Vsmps1SysClkReq1HPValid
646 * 0x02, Vsmps2SysClkReq1HPValid
647 * 0x04, Vsmps3SysClkReq1HPValid
79568b94 648 * 0x08, VanaSysClkReq1HPValid
d79df329 649 * 0x10, VpllSysClkReq1HPValid
79568b94
BJ		 650 * 0x20, Vaux1SysClkReq1HPValid
651 * 0x40, Vaux2SysClkReq1HPValid
652 * 0x80, Vaux3SysClkReq1HPValid
653 */
d79df329 654 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
79568b94 655 /*
33bc8f46
LJ		 656 * 0x01, VapeSysClkReq1HPValid
657 * 0x02, VarmSysClkReq1HPValid
658 * 0x04, VbbSysClkReq1HPValid
659 * 0x08, VmodSysClkReq1HPValid
79568b94
BJ		 660 * 0x10, VextSupply1SysClkReq1HPValid
661 * 0x20, VextSupply2SysClkReq1HPValid
662 * 0x40, VextSupply3SysClkReq1HPValid
663 */
33bc8f46 664 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x7f),
79568b94 665 /*
33bc8f46
LJ		 666 * 0x01, Vsmps1HwHPReq1Valid
667 * 0x02, Vsmps2HwHPReq1Valid
668 * 0x04, Vsmps3HwHPReq1Valid
79568b94 669 * 0x08, VanaHwHPReq1Valid
33bc8f46 670 * 0x10, VpllHwHPReq1Valid
79568b94
BJ		 671 * 0x20, Vaux1HwHPReq1Valid
672 * 0x40, Vaux2HwHPReq1Valid
673 * 0x80, Vaux3HwHPReq1Valid
674 */
33bc8f46 675 REG_INIT(AB8500_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
79568b94
BJ		 676 /*
677 * 0x01, VextSupply1HwHPReq1Valid
678 * 0x02, VextSupply2HwHPReq1Valid
679 * 0x04, VextSupply3HwHPReq1Valid
33bc8f46 680 * 0x08, VmodHwHPReq1Valid
79568b94 681 */
33bc8f46 682 REG_INIT(AB8500_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x0f),
79568b94 683 /*
33bc8f46
LJ		 684 * 0x01, Vsmps1HwHPReq2Valid
685 * 0x02, Vsmps2HwHPReq2Valid
686 * 0x03, Vsmps3HwHPReq2Valid
79568b94 687 * 0x08, VanaHwHPReq2Valid
33bc8f46 688 * 0x10, VpllHwHPReq2Valid
79568b94
BJ		 689 * 0x20, Vaux1HwHPReq2Valid
690 * 0x40, Vaux2HwHPReq2Valid
691 * 0x80, Vaux3HwHPReq2Valid
692 */
33bc8f46 693 REG_INIT(AB8500_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
79568b94
BJ		 694 /*
695 * 0x01, VextSupply1HwHPReq2Valid
696 * 0x02, VextSupply2HwHPReq2Valid
697 * 0x04, VextSupply3HwHPReq2Valid
33bc8f46 698 * 0x08, VmodHwHPReq2Valid
79568b94 699 */
33bc8f46 700 REG_INIT(AB8500_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x0f),
79568b94 701 /*
33bc8f46
LJ		 702 * 0x01, VapeSwHPReqValid
703 * 0x02, VarmSwHPReqValid
704 * 0x04, Vsmps1SwHPReqValid
705 * 0x08, Vsmps2SwHPReqValid
706 * 0x10, Vsmps3SwHPReqValid
79568b94 707 * 0x20, VanaSwHPReqValid
33bc8f46 708 * 0x40, VpllSwHPReqValid
79568b94
BJ		 709 * 0x80, Vaux1SwHPReqValid
710 */
33bc8f46 711 REG_INIT(AB8500_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
79568b94
BJ		 712 /*
713 * 0x01, Vaux2SwHPReqValid
714 * 0x02, Vaux3SwHPReqValid
715 * 0x04, VextSupply1SwHPReqValid
716 * 0x08, VextSupply2SwHPReqValid
717 * 0x10, VextSupply3SwHPReqValid
33bc8f46 718 * 0x20, VmodSwHPReqValid
79568b94 719 */
33bc8f46 720 REG_INIT(AB8500_REGUSWHPREQVALID2, 0x03, 0x0e, 0x3f),
79568b94
BJ		 721 /*
722 * 0x02, SysClkReq2Valid1
723 * ...
724 * 0x80, SysClkReq8Valid1
725 */
726 REG_INIT(AB8500_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
727 /*
728 * 0x02, SysClkReq2Valid2
729 * ...
730 * 0x80, SysClkReq8Valid2
731 */
732 REG_INIT(AB8500_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
733 /*
734 * 0x02, VTVoutEna
735 * 0x04, Vintcore12Ena
736 * 0x38, Vintcore12Sel
737 * 0x40, Vintcore12LP
738 * 0x80, VTVoutLP
739 */
740 REG_INIT(AB8500_REGUMISC1, 0x03, 0x80, 0xfe),
741 /*
742 * 0x02, VaudioEna
743 * 0x04, VdmicEna
744 * 0x08, Vamic1Ena
745 * 0x10, Vamic2Ena
746 */
747 REG_INIT(AB8500_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
748 /*
749 * 0x01, Vamic1_dzout
750 * 0x02, Vamic2_dzout
751 */
752 REG_INIT(AB8500_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
d79df329
LJ		 753 /*
754 * 0x03, Vsmps1Regu
755 * 0x0c, Vsmps1SelCtrl
33bc8f46
LJ		 756 * 0x10, Vsmps1AutoMode
757 * 0x20, Vsmps1PWMMode
d79df329 758 */
33bc8f46 759 REG_INIT(AB8500_VSMPS1REGU, 0x04, 0x03, 0x3f),
d79df329
LJ		 760 /*
761 * 0x03, Vsmps2Regu
762 * 0x0c, Vsmps2SelCtrl
33bc8f46
LJ		 763 * 0x10, Vsmps2AutoMode
764 * 0x20, Vsmps2PWMMode
d79df329 765 */
33bc8f46 766 REG_INIT(AB8500_VSMPS2REGU, 0x04, 0x04, 0x3f),
79568b94 767 /*
79568b94 768 * 0x03, VpllRegu
33bc8f46 769 * 0x0c, VanaRegu
79568b94
BJ		 770 */
771 REG_INIT(AB8500_VPLLVANAREGU, 0x04, 0x06, 0x0f),
772 /*
773 * 0x01, VrefDDREna
774 * 0x02, VrefDDRSleepMode
775 */
776 REG_INIT(AB8500_VREFDDR, 0x04, 0x07, 0x03),
777 /*
778 * 0x03, VextSupply1Regu
779 * 0x0c, VextSupply2Regu
780 * 0x30, VextSupply3Regu
781 * 0x40, ExtSupply2Bypass
782 * 0x80, ExtSupply3Bypass
783 */
784 REG_INIT(AB8500_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
785 /*
786 * 0x03, Vaux1Regu
787 * 0x0c, Vaux2Regu
788 */
789 REG_INIT(AB8500_VAUX12REGU, 0x04, 0x09, 0x0f),
790 /*
d79df329 791 * 0x0c, Vrf1Regu
79568b94
BJ		 792 * 0x03, Vaux3Regu
793 */
d79df329 794 REG_INIT(AB8500_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
79568b94
BJ		 795 /*
796 * 0x3f, Vsmps1Sel1
797 */
798 REG_INIT(AB8500_VSMPS1SEL1, 0x04, 0x13, 0x3f),
799 /*
800 * 0x0f, Vaux1Sel
801 */
802 REG_INIT(AB8500_VAUX1SEL, 0x04, 0x1f, 0x0f),
803 /*
804 * 0x0f, Vaux2Sel
805 */
806 REG_INIT(AB8500_VAUX2SEL, 0x04, 0x20, 0x0f),
807 /*
808 * 0x07, Vaux3Sel
33bc8f46 809 * 0x30, Vrf1Sel
79568b94 810 */
33bc8f46 811 REG_INIT(AB8500_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
79568b94
BJ		 812 /*
813 * 0x01, VextSupply12LP
814 */
815 REG_INIT(AB8500_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
816 /*
33bc8f46
LJ		 817 * 0x01, VpllDisch
818 * 0x02, Vrf1Disch
79568b94
BJ		 819 * 0x04, Vaux1Disch
820 * 0x08, Vaux2Disch
821 * 0x10, Vaux3Disch
822 * 0x20, Vintcore12Disch
823 * 0x40, VTVoutDisch
824 * 0x80, VaudioDisch
825 */
33bc8f46 826 REG_INIT(AB8500_REGUCTRLDISCH, 0x04, 0x43, 0xff),
79568b94 827 /*
33bc8f46 828 * 0x01, VsimDisch
79568b94
BJ		 829 * 0x02, VanaDisch
830 * 0x04, VdmicPullDownEna
33bc8f46 831 * 0x08, VpllPullDownEna
79568b94
BJ		 832 * 0x10, VdmicDisch
833 */
33bc8f46 834 REG_INIT(AB8500_REGUCTRLDISCH2, 0x04, 0x44, 0x1f),
79568b94
BJ		 835};
836
3c1b8438
LJ		 837static int ab8500_regulator_init_registers(struct platform_device *pdev,
838 int id, int mask, int value)
a7ac1d9e
LJ		 839{
840 int err;
841
3c1b8438
LJ		 842 BUG_ON(value & ~mask);
843 BUG_ON(mask & ~ab8500_reg_init[id].mask);
a7ac1d9e 844
3c1b8438 845 /* initialize register */
a7ac1d9e
LJ		 846 err = abx500_mask_and_set_register_interruptible(
847 &pdev->dev,
848 ab8500_reg_init[id].bank,
849 ab8500_reg_init[id].addr,
3c1b8438 850 mask, value);
a7ac1d9e
LJ		 851 if (err < 0) {
852 dev_err(&pdev->dev,
853 "Failed to initialize 0x%02x, 0x%02x.\n",
854 ab8500_reg_init[id].bank,
855 ab8500_reg_init[id].addr);
856 return err;
857 }
a7ac1d9e 858 dev_vdbg(&pdev->dev,
3c1b8438
LJ		 859 " init: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",
860 ab8500_reg_init[id].bank,
861 ab8500_reg_init[id].addr,
862 mask, value);
a7ac1d9e
LJ		 863
864 return 0;
865}
866
a5023574 867static int ab8500_regulator_register(struct platform_device *pdev,
a7ac1d9e
LJ		 868 struct regulator_init_data *init_data,
869 int id,
870 struct device_node *np)
871{
872 struct ab8500_regulator_info *info = NULL;
873 struct regulator_config config = { };
874 int err;
875
876 /* assign per-regulator data */
877 info = &ab8500_regulator_info[id];
878 info->dev = &pdev->dev;
879
880 config.dev = &pdev->dev;
881 config.init_data = init_data;
882 config.driver_data = info;
883 config.of_node = np;
884
885 /* fix for hardware before ab8500v2.0 */
886 if (abx500_get_chip_id(info->dev) < 0x20) {
887 if (info->desc.id == AB8500_LDO_AUX3) {
888 info->desc.n_voltages =
889 ARRAY_SIZE(ldo_vauxn_voltages);
ec1cc4d9 890 info->desc.volt_table = ldo_vauxn_voltages;
a7ac1d9e
LJ		 891 info->voltage_mask = 0xf;
892 }
893 }
894
895 /* register regulator with framework */
896 info->regulator = regulator_register(&info->desc, &config);
897 if (IS_ERR(info->regulator)) {
898 err = PTR_ERR(info->regulator);
899 dev_err(&pdev->dev, "failed to register regulator %s\n",
900 info->desc.name);
901 /* when we fail, un-register all earlier regulators */
902 while (--id >= 0) {
903 info = &ab8500_regulator_info[id];
904 regulator_unregister(info->regulator);
905 }
906 return err;
907 }
908
909 return 0;
910}
911
3a8334b9 912static struct of_regulator_match ab8500_regulator_matches[] = {
7e715b95
LJ		 913 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8500_LDO_AUX1, },
914 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8500_LDO_AUX2, },
915 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8500_LDO_AUX3, },
916 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8500_LDO_INTCORE, },
917 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8500_LDO_TVOUT, },
918 { .name = "ab8500_ldo_usb", .driver_data = (void *) AB8500_LDO_USB, },
919 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8500_LDO_AUDIO, },
920 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8500_LDO_ANAMIC1, },
921 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, },
922 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8500_LDO_DMIC, },
923 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8500_LDO_ANA, },
3a8334b9
LJ		 924};
925
a5023574 926static int
3a8334b9
LJ		 927ab8500_regulator_of_probe(struct platform_device *pdev, struct device_node *np)
928{
929 int err, i;
930
931 for (i = 0; i < ARRAY_SIZE(ab8500_regulator_info); i++) {
932 err = ab8500_regulator_register(
933 pdev, ab8500_regulator_matches[i].init_data,
934 i, ab8500_regulator_matches[i].of_node);
935 if (err)
936 return err;
937 }
938
939 return 0;
940}
941
a5023574 942static int ab8500_regulator_probe(struct platform_device *pdev)
c789ca20
SI		 943{
944 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
3a8334b9 945 struct device_node *np = pdev->dev.of_node;
732805a5
BJ		 946 struct ab8500_platform_data *ppdata;
947 struct ab8500_regulator_platform_data *pdata;
c789ca20
SI		 948 int i, err;
949
3a8334b9
LJ		 950 if (np) {
951 err = of_regulator_match(&pdev->dev, np,
952 ab8500_regulator_matches,
953 ARRAY_SIZE(ab8500_regulator_matches));
954 if (err < 0) {
955 dev_err(&pdev->dev,
956 "Error parsing regulator init data: %d\n", err);
957 return err;
958 }
959
960 err = ab8500_regulator_of_probe(pdev, np);
961 return err;
962 }
963
c789ca20
SI		 964 if (!ab8500) {
965 dev_err(&pdev->dev, "null mfd parent\n");
966 return -EINVAL;
967 }
732805a5
BJ		 968
969 ppdata = dev_get_platdata(ab8500->dev);
970 if (!ppdata) {
971 dev_err(&pdev->dev, "null parent pdata\n");
972 return -EINVAL;
973 }
974
975 pdata = ppdata->regulator;
fc24b426
BJ		 976 if (!pdata) {
977 dev_err(&pdev->dev, "null pdata\n");
978 return -EINVAL;
979 }
c789ca20 980
cb189b07
BJ		 981 /* make sure the platform data has the correct size */
982 if (pdata->num_regulator != ARRAY_SIZE(ab8500_regulator_info)) {
79568b94 983 dev_err(&pdev->dev, "Configuration error: size mismatch.\n");
cb189b07
BJ		 984 return -EINVAL;
985 }
986
79568b94 987 /* initialize registers */
732805a5 988 for (i = 0; i < pdata->num_reg_init; i++) {
3c1b8438 989 int id, mask, value;
79568b94 990
732805a5
BJ		 991 id = pdata->reg_init[i].id;
992 mask = pdata->reg_init[i].mask;
993 value = pdata->reg_init[i].value;
79568b94
BJ		 994
995 /* check for configuration errors */
3c1b8438 996 BUG_ON(id >= AB8500_NUM_REGULATOR_REGISTERS);
79568b94 997
3c1b8438 998 err = ab8500_regulator_init_registers(pdev, id, mask, value);
a7ac1d9e 999 if (err < 0)
79568b94 1000 return err;
79568b94
BJ		 1001 }
1002
c789ca20
SI		 1003 /* register all regulators */
1004 for (i = 0; i < ARRAY_SIZE(ab8500_regulator_info); i++) {
a7ac1d9e
LJ		 1005 err = ab8500_regulator_register(pdev, &pdata->regulator[i], i, NULL);
1006 if (err < 0)
c789ca20 1007 return err;
c789ca20
SI		 1008 }
1009
1010 return 0;
1011}
1012
8dc995f5 1013static int ab8500_regulator_remove(struct platform_device *pdev)
c789ca20
SI		 1014{
1015 int i;
1016
1017 for (i = 0; i < ARRAY_SIZE(ab8500_regulator_info); i++) {
1018 struct ab8500_regulator_info *info = NULL;
1019 info = &ab8500_regulator_info[i];
09aefa12
BJ		 1020
1021 dev_vdbg(rdev_get_dev(info->regulator),
1022 "%s-remove\n", info->desc.name);
1023
c789ca20
SI		 1024 regulator_unregister(info->regulator);
1025 }
1026
1027 return 0;
1028}
1029
1030static struct platform_driver ab8500_regulator_driver = {
1031 .probe = ab8500_regulator_probe,
5eb9f2b9 1032 .remove = ab8500_regulator_remove,
c789ca20
SI		 1033 .driver = {
1034 .name = "ab8500-regulator",
1035 .owner = THIS_MODULE,
1036 },
1037};
1038
1039static int __init ab8500_regulator_init(void)
1040{
1041 int ret;
1042
1043 ret = platform_driver_register(&ab8500_regulator_driver);
1044 if (ret != 0)
1045 pr_err("Failed to register ab8500 regulator: %d\n", ret);
1046
1047 return ret;
1048}
1049subsys_initcall(ab8500_regulator_init);
1050
1051static void __exit ab8500_regulator_exit(void)
1052{
1053 platform_driver_unregister(&ab8500_regulator_driver);
1054}
1055module_exit(ab8500_regulator_exit);
1056
1057MODULE_LICENSE("GPL v2");
1058MODULE_AUTHOR("Sundar Iyer <sundar.iyer@stericsson.com>");
732805a5 1059MODULE_AUTHOR("Bengt Jonsson <bengt.g.jonsson@stericsson.com>");
c789ca20
SI		 1060MODULE_DESCRIPTION("Regulator Driver for ST-Ericsson AB8500 Mixed-Sig PMIC");
1061MODULE_ALIAS("platform:ab8500-regulator");
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