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c789ca20 SI |
1 | /* |
2 | * Copyright (C) ST-Ericsson SA 2010 | |
3 | * | |
4 | * License Terms: GNU General Public License v2 | |
5 | * | |
e1159e6d BJ |
6 | * Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson |
7 | * Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson | |
547f384f | 8 | * Daniel Willerud <daniel.willerud@stericsson.com> for ST-Ericsson |
c789ca20 SI |
9 | * |
10 | * AB8500 peripheral regulators | |
11 | * | |
e1159e6d | 12 | * AB8500 supports the following regulators: |
ea05ef31 | 13 | * VAUX1/2/3, VINTCORE, VTVOUT, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA |
547f384f LJ |
14 | * |
15 | * AB8505 supports the following regulators: | |
16 | * VAUX1/2/3/4/5/6, VINTCORE, VADC, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA | |
c789ca20 SI |
17 | */ |
18 | #include <linux/init.h> | |
19 | #include <linux/kernel.h> | |
65602c32 | 20 | #include <linux/module.h> |
c789ca20 SI |
21 | #include <linux/err.h> |
22 | #include <linux/platform_device.h> | |
47c16975 | 23 | #include <linux/mfd/abx500.h> |
ee66e653 | 24 | #include <linux/mfd/abx500/ab8500.h> |
3a8334b9 LJ |
25 | #include <linux/of.h> |
26 | #include <linux/regulator/of_regulator.h> | |
c789ca20 SI |
27 | #include <linux/regulator/driver.h> |
28 | #include <linux/regulator/machine.h> | |
29 | #include <linux/regulator/ab8500.h> | |
3a8334b9 | 30 | #include <linux/slab.h> |
c789ca20 SI |
31 | |
32 | /** | |
33 | * struct ab8500_regulator_info - ab8500 regulator information | |
e1159e6d | 34 | * @dev: device pointer |
c789ca20 | 35 | * @desc: regulator description |
c789ca20 | 36 | * @regulator_dev: regulator device |
bd28a157 | 37 | * @is_enabled: status of regulator (on/off) |
7ce4669c | 38 | * @load_lp_uA: maximum load in idle (low power) mode |
47c16975 | 39 | * @update_bank: bank to control on/off |
c789ca20 | 40 | * @update_reg: register to control on/off |
bd28a157 EV |
41 | * @update_mask: mask to enable/disable and set mode of regulator |
42 | * @update_val: bits holding the regulator current mode | |
43 | * @update_val_idle: bits to enable the regulator in idle (low power) mode | |
44 | * @update_val_normal: bits to enable the regulator in normal (high power) mode | |
47c16975 | 45 | * @voltage_bank: bank to control regulator voltage |
c789ca20 SI |
46 | * @voltage_reg: register to control regulator voltage |
47 | * @voltage_mask: mask to control regulator voltage | |
a0a7014c | 48 | * @voltage_shift: shift to control regulator voltage |
c789ca20 SI |
49 | */ |
50 | struct ab8500_regulator_info { | |
51 | struct device *dev; | |
52 | struct regulator_desc desc; | |
c789ca20 | 53 | struct regulator_dev *regulator; |
bd28a157 | 54 | bool is_enabled; |
7ce4669c | 55 | int load_lp_uA; |
47c16975 MW |
56 | u8 update_bank; |
57 | u8 update_reg; | |
e1159e6d | 58 | u8 update_mask; |
bd28a157 EV |
59 | u8 update_val; |
60 | u8 update_val_idle; | |
61 | u8 update_val_normal; | |
47c16975 MW |
62 | u8 voltage_bank; |
63 | u8 voltage_reg; | |
64 | u8 voltage_mask; | |
a0a7014c | 65 | u8 voltage_shift; |
c789ca20 SI |
66 | }; |
67 | ||
68 | /* voltage tables for the vauxn/vintcore supplies */ | |
ec1cc4d9 | 69 | static const unsigned int ldo_vauxn_voltages[] = { |
c789ca20 SI |
70 | 1100000, |
71 | 1200000, | |
72 | 1300000, | |
73 | 1400000, | |
74 | 1500000, | |
75 | 1800000, | |
76 | 1850000, | |
77 | 1900000, | |
78 | 2500000, | |
79 | 2650000, | |
80 | 2700000, | |
81 | 2750000, | |
82 | 2800000, | |
83 | 2900000, | |
84 | 3000000, | |
85 | 3300000, | |
86 | }; | |
87 | ||
ec1cc4d9 | 88 | static const unsigned int ldo_vaux3_voltages[] = { |
2b75151a BJ |
89 | 1200000, |
90 | 1500000, | |
91 | 1800000, | |
92 | 2100000, | |
93 | 2500000, | |
94 | 2750000, | |
95 | 2790000, | |
96 | 2910000, | |
97 | }; | |
98 | ||
62ab4111 | 99 | static const unsigned int ldo_vaux56_voltages[] = { |
547f384f LJ |
100 | 1800000, |
101 | 1050000, | |
102 | 1100000, | |
103 | 1200000, | |
104 | 1500000, | |
105 | 2200000, | |
106 | 2500000, | |
107 | 2790000, | |
108 | }; | |
109 | ||
62ab4111 | 110 | static const unsigned int ldo_vaux3_ab8540_voltages[] = { |
ae0a9a3e LJ |
111 | 1200000, |
112 | 1500000, | |
113 | 1800000, | |
114 | 2100000, | |
115 | 2500000, | |
116 | 2750000, | |
117 | 2790000, | |
118 | 2910000, | |
119 | 3050000, | |
120 | }; | |
121 | ||
ec1cc4d9 | 122 | static const unsigned int ldo_vintcore_voltages[] = { |
c789ca20 SI |
123 | 1200000, |
124 | 1225000, | |
125 | 1250000, | |
126 | 1275000, | |
127 | 1300000, | |
128 | 1325000, | |
129 | 1350000, | |
130 | }; | |
131 | ||
62ab4111 | 132 | static const unsigned int ldo_sdio_voltages[] = { |
ae0a9a3e LJ |
133 | 1160000, |
134 | 1050000, | |
135 | 1100000, | |
136 | 1500000, | |
137 | 1800000, | |
138 | 2200000, | |
139 | 2910000, | |
140 | 3050000, | |
141 | }; | |
142 | ||
b080c78a LJ |
143 | static const unsigned int fixed_1200000_voltage[] = { |
144 | 1200000, | |
145 | }; | |
146 | ||
147 | static const unsigned int fixed_1800000_voltage[] = { | |
148 | 1800000, | |
149 | }; | |
150 | ||
151 | static const unsigned int fixed_2000000_voltage[] = { | |
152 | 2000000, | |
153 | }; | |
154 | ||
155 | static const unsigned int fixed_2050000_voltage[] = { | |
156 | 2050000, | |
157 | }; | |
158 | ||
159 | static const unsigned int fixed_3300000_voltage[] = { | |
160 | 3300000, | |
161 | }; | |
162 | ||
c789ca20 SI |
163 | static int ab8500_regulator_enable(struct regulator_dev *rdev) |
164 | { | |
fc24b426 | 165 | int ret; |
c789ca20 SI |
166 | struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); |
167 | ||
fc24b426 BJ |
168 | if (info == NULL) { |
169 | dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); | |
c789ca20 | 170 | return -EINVAL; |
fc24b426 | 171 | } |
c789ca20 | 172 | |
47c16975 | 173 | ret = abx500_mask_and_set_register_interruptible(info->dev, |
e1159e6d | 174 | info->update_bank, info->update_reg, |
bd28a157 | 175 | info->update_mask, info->update_val); |
f71bf528 | 176 | if (ret < 0) { |
c789ca20 SI |
177 | dev_err(rdev_get_dev(rdev), |
178 | "couldn't set enable bits for regulator\n"); | |
f71bf528 AL |
179 | return ret; |
180 | } | |
09aefa12 | 181 | |
bd28a157 EV |
182 | info->is_enabled = true; |
183 | ||
09aefa12 BJ |
184 | dev_vdbg(rdev_get_dev(rdev), |
185 | "%s-enable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n", | |
186 | info->desc.name, info->update_bank, info->update_reg, | |
bd28a157 | 187 | info->update_mask, info->update_val); |
09aefa12 | 188 | |
c789ca20 SI |
189 | return ret; |
190 | } | |
191 | ||
192 | static int ab8500_regulator_disable(struct regulator_dev *rdev) | |
193 | { | |
fc24b426 | 194 | int ret; |
c789ca20 SI |
195 | struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); |
196 | ||
fc24b426 BJ |
197 | if (info == NULL) { |
198 | dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); | |
c789ca20 | 199 | return -EINVAL; |
fc24b426 | 200 | } |
c789ca20 | 201 | |
47c16975 | 202 | ret = abx500_mask_and_set_register_interruptible(info->dev, |
e1159e6d BJ |
203 | info->update_bank, info->update_reg, |
204 | info->update_mask, 0x0); | |
f71bf528 | 205 | if (ret < 0) { |
c789ca20 SI |
206 | dev_err(rdev_get_dev(rdev), |
207 | "couldn't set disable bits for regulator\n"); | |
f71bf528 AL |
208 | return ret; |
209 | } | |
09aefa12 | 210 | |
bd28a157 EV |
211 | info->is_enabled = false; |
212 | ||
09aefa12 BJ |
213 | dev_vdbg(rdev_get_dev(rdev), |
214 | "%s-disable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n", | |
215 | info->desc.name, info->update_bank, info->update_reg, | |
216 | info->update_mask, 0x0); | |
217 | ||
c789ca20 SI |
218 | return ret; |
219 | } | |
220 | ||
7ce4669c BJ |
221 | static unsigned int ab8500_regulator_get_optimum_mode( |
222 | struct regulator_dev *rdev, int input_uV, | |
223 | int output_uV, int load_uA) | |
224 | { | |
225 | unsigned int mode; | |
226 | ||
227 | struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); | |
228 | ||
229 | if (info == NULL) { | |
230 | dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); | |
231 | return -EINVAL; | |
232 | } | |
233 | ||
234 | if (load_uA <= info->load_lp_uA) | |
235 | mode = REGULATOR_MODE_IDLE; | |
236 | else | |
237 | mode = REGULATOR_MODE_NORMAL; | |
238 | ||
239 | return mode; | |
240 | } | |
241 | ||
bd28a157 EV |
242 | static int ab8500_regulator_set_mode(struct regulator_dev *rdev, |
243 | unsigned int mode) | |
244 | { | |
742a7325 AL |
245 | int ret; |
246 | u8 update_val; | |
bd28a157 EV |
247 | struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); |
248 | ||
249 | if (info == NULL) { | |
250 | dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); | |
251 | return -EINVAL; | |
252 | } | |
253 | ||
254 | switch (mode) { | |
255 | case REGULATOR_MODE_NORMAL: | |
742a7325 | 256 | update_val = info->update_val_normal; |
bd28a157 EV |
257 | break; |
258 | case REGULATOR_MODE_IDLE: | |
742a7325 | 259 | update_val = info->update_val_idle; |
bd28a157 EV |
260 | break; |
261 | default: | |
262 | return -EINVAL; | |
263 | } | |
264 | ||
742a7325 AL |
265 | /* ab8500 regulators share mode and enable in the same register bits. |
266 | off = 0b00 | |
267 | low power mode= 0b11 | |
268 | full powermode = 0b01 | |
269 | (HW control mode = 0b10) | |
270 | Thus we don't write to the register when regulator is disabled. | |
271 | */ | |
bd28a157 EV |
272 | if (info->is_enabled) { |
273 | ret = abx500_mask_and_set_register_interruptible(info->dev, | |
274 | info->update_bank, info->update_reg, | |
742a7325 AL |
275 | info->update_mask, update_val); |
276 | if (ret < 0) { | |
bd28a157 EV |
277 | dev_err(rdev_get_dev(rdev), |
278 | "couldn't set regulator mode\n"); | |
742a7325 AL |
279 | return ret; |
280 | } | |
7ce4669c BJ |
281 | |
282 | dev_vdbg(rdev_get_dev(rdev), | |
283 | "%s-set_mode (bank, reg, mask, value): " | |
284 | "0x%x, 0x%x, 0x%x, 0x%x\n", | |
285 | info->desc.name, info->update_bank, info->update_reg, | |
742a7325 | 286 | info->update_mask, update_val); |
bd28a157 EV |
287 | } |
288 | ||
742a7325 AL |
289 | info->update_val = update_val; |
290 | ||
291 | return 0; | |
bd28a157 EV |
292 | } |
293 | ||
294 | static unsigned int ab8500_regulator_get_mode(struct regulator_dev *rdev) | |
295 | { | |
296 | struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); | |
297 | int ret; | |
298 | ||
299 | if (info == NULL) { | |
300 | dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); | |
301 | return -EINVAL; | |
302 | } | |
303 | ||
304 | if (info->update_val == info->update_val_normal) | |
305 | ret = REGULATOR_MODE_NORMAL; | |
306 | else if (info->update_val == info->update_val_idle) | |
307 | ret = REGULATOR_MODE_IDLE; | |
308 | else | |
309 | ret = -EINVAL; | |
310 | ||
311 | return ret; | |
312 | } | |
313 | ||
c789ca20 SI |
314 | static int ab8500_regulator_is_enabled(struct regulator_dev *rdev) |
315 | { | |
fc24b426 | 316 | int ret; |
c789ca20 | 317 | struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); |
09aefa12 | 318 | u8 regval; |
c789ca20 | 319 | |
fc24b426 BJ |
320 | if (info == NULL) { |
321 | dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); | |
c789ca20 | 322 | return -EINVAL; |
fc24b426 | 323 | } |
c789ca20 | 324 | |
47c16975 | 325 | ret = abx500_get_register_interruptible(info->dev, |
09aefa12 | 326 | info->update_bank, info->update_reg, ®val); |
c789ca20 SI |
327 | if (ret < 0) { |
328 | dev_err(rdev_get_dev(rdev), | |
329 | "couldn't read 0x%x register\n", info->update_reg); | |
330 | return ret; | |
331 | } | |
332 | ||
09aefa12 BJ |
333 | dev_vdbg(rdev_get_dev(rdev), |
334 | "%s-is_enabled (bank, reg, mask, value): 0x%x, 0x%x, 0x%x," | |
335 | " 0x%x\n", | |
336 | info->desc.name, info->update_bank, info->update_reg, | |
337 | info->update_mask, regval); | |
338 | ||
339 | if (regval & info->update_mask) | |
bd28a157 | 340 | info->is_enabled = true; |
c789ca20 | 341 | else |
bd28a157 EV |
342 | info->is_enabled = false; |
343 | ||
344 | return info->is_enabled; | |
c789ca20 SI |
345 | } |
346 | ||
3bf6e90e | 347 | static int ab8500_regulator_get_voltage_sel(struct regulator_dev *rdev) |
c789ca20 | 348 | { |
09aefa12 | 349 | int ret, val; |
c789ca20 | 350 | struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); |
09aefa12 | 351 | u8 regval; |
c789ca20 | 352 | |
fc24b426 BJ |
353 | if (info == NULL) { |
354 | dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); | |
c789ca20 | 355 | return -EINVAL; |
fc24b426 | 356 | } |
c789ca20 | 357 | |
09aefa12 BJ |
358 | ret = abx500_get_register_interruptible(info->dev, |
359 | info->voltage_bank, info->voltage_reg, ®val); | |
c789ca20 SI |
360 | if (ret < 0) { |
361 | dev_err(rdev_get_dev(rdev), | |
362 | "couldn't read voltage reg for regulator\n"); | |
363 | return ret; | |
364 | } | |
365 | ||
09aefa12 | 366 | dev_vdbg(rdev_get_dev(rdev), |
a0a7014c LW |
367 | "%s-get_voltage (bank, reg, mask, shift, value): " |
368 | "0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", | |
369 | info->desc.name, info->voltage_bank, | |
370 | info->voltage_reg, info->voltage_mask, | |
371 | info->voltage_shift, regval); | |
09aefa12 | 372 | |
09aefa12 | 373 | val = regval & info->voltage_mask; |
a0a7014c | 374 | return val >> info->voltage_shift; |
c789ca20 SI |
375 | } |
376 | ||
ae713d39 AL |
377 | static int ab8500_regulator_set_voltage_sel(struct regulator_dev *rdev, |
378 | unsigned selector) | |
c789ca20 | 379 | { |
fc24b426 | 380 | int ret; |
c789ca20 | 381 | struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); |
09aefa12 | 382 | u8 regval; |
c789ca20 | 383 | |
fc24b426 BJ |
384 | if (info == NULL) { |
385 | dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); | |
c789ca20 | 386 | return -EINVAL; |
fc24b426 | 387 | } |
c789ca20 | 388 | |
c789ca20 | 389 | /* set the registers for the request */ |
a0a7014c | 390 | regval = (u8)selector << info->voltage_shift; |
47c16975 | 391 | ret = abx500_mask_and_set_register_interruptible(info->dev, |
09aefa12 BJ |
392 | info->voltage_bank, info->voltage_reg, |
393 | info->voltage_mask, regval); | |
c789ca20 SI |
394 | if (ret < 0) |
395 | dev_err(rdev_get_dev(rdev), | |
396 | "couldn't set voltage reg for regulator\n"); | |
397 | ||
09aefa12 BJ |
398 | dev_vdbg(rdev_get_dev(rdev), |
399 | "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x," | |
400 | " 0x%x\n", | |
401 | info->desc.name, info->voltage_bank, info->voltage_reg, | |
402 | info->voltage_mask, regval); | |
403 | ||
c789ca20 SI |
404 | return ret; |
405 | } | |
406 | ||
7ce4669c BJ |
407 | static struct regulator_ops ab8500_regulator_volt_mode_ops = { |
408 | .enable = ab8500_regulator_enable, | |
409 | .disable = ab8500_regulator_disable, | |
410 | .is_enabled = ab8500_regulator_is_enabled, | |
411 | .get_optimum_mode = ab8500_regulator_get_optimum_mode, | |
412 | .set_mode = ab8500_regulator_set_mode, | |
413 | .get_mode = ab8500_regulator_get_mode, | |
414 | .get_voltage_sel = ab8500_regulator_get_voltage_sel, | |
415 | .set_voltage_sel = ab8500_regulator_set_voltage_sel, | |
416 | .list_voltage = regulator_list_voltage_table, | |
c789ca20 SI |
417 | }; |
418 | ||
7ce4669c BJ |
419 | static struct regulator_ops ab8500_regulator_mode_ops = { |
420 | .enable = ab8500_regulator_enable, | |
421 | .disable = ab8500_regulator_disable, | |
422 | .is_enabled = ab8500_regulator_is_enabled, | |
423 | .get_optimum_mode = ab8500_regulator_get_optimum_mode, | |
424 | .set_mode = ab8500_regulator_set_mode, | |
425 | .get_mode = ab8500_regulator_get_mode, | |
5689e830 | 426 | .list_voltage = regulator_list_voltage_linear, |
7ce4669c BJ |
427 | }; |
428 | ||
429 | static struct regulator_ops ab8500_regulator_ops = { | |
430 | .enable = ab8500_regulator_enable, | |
431 | .disable = ab8500_regulator_disable, | |
432 | .is_enabled = ab8500_regulator_is_enabled, | |
5689e830 | 433 | .list_voltage = regulator_list_voltage_linear, |
c789ca20 SI |
434 | }; |
435 | ||
8e6a8d7d | 436 | /* AB8500 regulator information */ |
6909b452 BJ |
437 | static struct ab8500_regulator_info |
438 | ab8500_regulator_info[AB8500_NUM_REGULATORS] = { | |
c789ca20 | 439 | /* |
e1159e6d BJ |
440 | * Variable Voltage Regulators |
441 | * name, min mV, max mV, | |
442 | * update bank, reg, mask, enable val | |
ec1cc4d9 | 443 | * volt bank, reg, mask |
c789ca20 | 444 | */ |
6909b452 BJ |
445 | [AB8500_LDO_AUX1] = { |
446 | .desc = { | |
447 | .name = "LDO-AUX1", | |
7ce4669c | 448 | .ops = &ab8500_regulator_volt_mode_ops, |
6909b452 BJ |
449 | .type = REGULATOR_VOLTAGE, |
450 | .id = AB8500_LDO_AUX1, | |
451 | .owner = THIS_MODULE, | |
452 | .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), | |
ec1cc4d9 | 453 | .volt_table = ldo_vauxn_voltages, |
530158b6 | 454 | .enable_time = 200, |
6909b452 | 455 | }, |
7ce4669c | 456 | .load_lp_uA = 5000, |
6909b452 BJ |
457 | .update_bank = 0x04, |
458 | .update_reg = 0x09, | |
459 | .update_mask = 0x03, | |
bd28a157 EV |
460 | .update_val = 0x01, |
461 | .update_val_idle = 0x03, | |
462 | .update_val_normal = 0x01, | |
6909b452 BJ |
463 | .voltage_bank = 0x04, |
464 | .voltage_reg = 0x1f, | |
465 | .voltage_mask = 0x0f, | |
6909b452 BJ |
466 | }, |
467 | [AB8500_LDO_AUX2] = { | |
468 | .desc = { | |
469 | .name = "LDO-AUX2", | |
7ce4669c | 470 | .ops = &ab8500_regulator_volt_mode_ops, |
6909b452 BJ |
471 | .type = REGULATOR_VOLTAGE, |
472 | .id = AB8500_LDO_AUX2, | |
473 | .owner = THIS_MODULE, | |
474 | .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), | |
ec1cc4d9 | 475 | .volt_table = ldo_vauxn_voltages, |
530158b6 | 476 | .enable_time = 200, |
6909b452 | 477 | }, |
7ce4669c | 478 | .load_lp_uA = 5000, |
6909b452 BJ |
479 | .update_bank = 0x04, |
480 | .update_reg = 0x09, | |
481 | .update_mask = 0x0c, | |
bd28a157 EV |
482 | .update_val = 0x04, |
483 | .update_val_idle = 0x0c, | |
484 | .update_val_normal = 0x04, | |
6909b452 BJ |
485 | .voltage_bank = 0x04, |
486 | .voltage_reg = 0x20, | |
487 | .voltage_mask = 0x0f, | |
6909b452 BJ |
488 | }, |
489 | [AB8500_LDO_AUX3] = { | |
490 | .desc = { | |
491 | .name = "LDO-AUX3", | |
7ce4669c | 492 | .ops = &ab8500_regulator_volt_mode_ops, |
6909b452 BJ |
493 | .type = REGULATOR_VOLTAGE, |
494 | .id = AB8500_LDO_AUX3, | |
495 | .owner = THIS_MODULE, | |
496 | .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages), | |
ec1cc4d9 | 497 | .volt_table = ldo_vaux3_voltages, |
530158b6 | 498 | .enable_time = 450, |
6909b452 | 499 | }, |
7ce4669c | 500 | .load_lp_uA = 5000, |
6909b452 BJ |
501 | .update_bank = 0x04, |
502 | .update_reg = 0x0a, | |
503 | .update_mask = 0x03, | |
bd28a157 EV |
504 | .update_val = 0x01, |
505 | .update_val_idle = 0x03, | |
506 | .update_val_normal = 0x01, | |
6909b452 BJ |
507 | .voltage_bank = 0x04, |
508 | .voltage_reg = 0x21, | |
509 | .voltage_mask = 0x07, | |
6909b452 BJ |
510 | }, |
511 | [AB8500_LDO_INTCORE] = { | |
512 | .desc = { | |
513 | .name = "LDO-INTCORE", | |
7ce4669c | 514 | .ops = &ab8500_regulator_volt_mode_ops, |
6909b452 BJ |
515 | .type = REGULATOR_VOLTAGE, |
516 | .id = AB8500_LDO_INTCORE, | |
517 | .owner = THIS_MODULE, | |
518 | .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages), | |
ec1cc4d9 | 519 | .volt_table = ldo_vintcore_voltages, |
530158b6 | 520 | .enable_time = 750, |
6909b452 | 521 | }, |
7ce4669c | 522 | .load_lp_uA = 5000, |
6909b452 BJ |
523 | .update_bank = 0x03, |
524 | .update_reg = 0x80, | |
525 | .update_mask = 0x44, | |
cc40dc29 | 526 | .update_val = 0x44, |
bd28a157 EV |
527 | .update_val_idle = 0x44, |
528 | .update_val_normal = 0x04, | |
6909b452 BJ |
529 | .voltage_bank = 0x03, |
530 | .voltage_reg = 0x80, | |
531 | .voltage_mask = 0x38, | |
a0a7014c | 532 | .voltage_shift = 3, |
6909b452 | 533 | }, |
c789ca20 SI |
534 | |
535 | /* | |
e1159e6d BJ |
536 | * Fixed Voltage Regulators |
537 | * name, fixed mV, | |
538 | * update bank, reg, mask, enable val | |
c789ca20 | 539 | */ |
6909b452 BJ |
540 | [AB8500_LDO_TVOUT] = { |
541 | .desc = { | |
542 | .name = "LDO-TVOUT", | |
7ce4669c | 543 | .ops = &ab8500_regulator_mode_ops, |
6909b452 BJ |
544 | .type = REGULATOR_VOLTAGE, |
545 | .id = AB8500_LDO_TVOUT, | |
546 | .owner = THIS_MODULE, | |
547 | .n_voltages = 1, | |
b080c78a | 548 | .volt_table = fixed_2000000_voltage, |
ed3c138e | 549 | .enable_time = 500, |
6909b452 | 550 | }, |
7ce4669c | 551 | .load_lp_uA = 1000, |
6909b452 BJ |
552 | .update_bank = 0x03, |
553 | .update_reg = 0x80, | |
554 | .update_mask = 0x82, | |
bd28a157 | 555 | .update_val = 0x02, |
7ce4669c BJ |
556 | .update_val_idle = 0x82, |
557 | .update_val_normal = 0x02, | |
6909b452 BJ |
558 | }, |
559 | [AB8500_LDO_AUDIO] = { | |
560 | .desc = { | |
561 | .name = "LDO-AUDIO", | |
7ce4669c | 562 | .ops = &ab8500_regulator_ops, |
6909b452 BJ |
563 | .type = REGULATOR_VOLTAGE, |
564 | .id = AB8500_LDO_AUDIO, | |
565 | .owner = THIS_MODULE, | |
566 | .n_voltages = 1, | |
530158b6 | 567 | .enable_time = 140, |
b080c78a | 568 | .volt_table = fixed_2000000_voltage, |
6909b452 | 569 | }, |
6909b452 BJ |
570 | .update_bank = 0x03, |
571 | .update_reg = 0x83, | |
572 | .update_mask = 0x02, | |
bd28a157 | 573 | .update_val = 0x02, |
6909b452 BJ |
574 | }, |
575 | [AB8500_LDO_ANAMIC1] = { | |
576 | .desc = { | |
577 | .name = "LDO-ANAMIC1", | |
7ce4669c | 578 | .ops = &ab8500_regulator_ops, |
6909b452 BJ |
579 | .type = REGULATOR_VOLTAGE, |
580 | .id = AB8500_LDO_ANAMIC1, | |
581 | .owner = THIS_MODULE, | |
582 | .n_voltages = 1, | |
530158b6 | 583 | .enable_time = 500, |
b080c78a | 584 | .volt_table = fixed_2050000_voltage, |
6909b452 | 585 | }, |
6909b452 BJ |
586 | .update_bank = 0x03, |
587 | .update_reg = 0x83, | |
588 | .update_mask = 0x08, | |
bd28a157 | 589 | .update_val = 0x08, |
6909b452 BJ |
590 | }, |
591 | [AB8500_LDO_ANAMIC2] = { | |
592 | .desc = { | |
593 | .name = "LDO-ANAMIC2", | |
7ce4669c | 594 | .ops = &ab8500_regulator_ops, |
6909b452 BJ |
595 | .type = REGULATOR_VOLTAGE, |
596 | .id = AB8500_LDO_ANAMIC2, | |
597 | .owner = THIS_MODULE, | |
598 | .n_voltages = 1, | |
530158b6 | 599 | .enable_time = 500, |
b080c78a | 600 | .volt_table = fixed_2050000_voltage, |
6909b452 | 601 | }, |
6909b452 BJ |
602 | .update_bank = 0x03, |
603 | .update_reg = 0x83, | |
604 | .update_mask = 0x10, | |
bd28a157 | 605 | .update_val = 0x10, |
6909b452 BJ |
606 | }, |
607 | [AB8500_LDO_DMIC] = { | |
608 | .desc = { | |
609 | .name = "LDO-DMIC", | |
7ce4669c | 610 | .ops = &ab8500_regulator_ops, |
6909b452 BJ |
611 | .type = REGULATOR_VOLTAGE, |
612 | .id = AB8500_LDO_DMIC, | |
613 | .owner = THIS_MODULE, | |
614 | .n_voltages = 1, | |
530158b6 | 615 | .enable_time = 420, |
b080c78a | 616 | .volt_table = fixed_1800000_voltage, |
6909b452 | 617 | }, |
6909b452 BJ |
618 | .update_bank = 0x03, |
619 | .update_reg = 0x83, | |
620 | .update_mask = 0x04, | |
bd28a157 | 621 | .update_val = 0x04, |
6909b452 | 622 | }, |
7ce4669c BJ |
623 | |
624 | /* | |
625 | * Regulators with fixed voltage and normal/idle modes | |
626 | */ | |
6909b452 BJ |
627 | [AB8500_LDO_ANA] = { |
628 | .desc = { | |
629 | .name = "LDO-ANA", | |
7ce4669c | 630 | .ops = &ab8500_regulator_mode_ops, |
6909b452 BJ |
631 | .type = REGULATOR_VOLTAGE, |
632 | .id = AB8500_LDO_ANA, | |
633 | .owner = THIS_MODULE, | |
634 | .n_voltages = 1, | |
530158b6 | 635 | .enable_time = 140, |
b080c78a | 636 | .volt_table = fixed_1200000_voltage, |
6909b452 | 637 | }, |
7ce4669c | 638 | .load_lp_uA = 1000, |
6909b452 BJ |
639 | .update_bank = 0x04, |
640 | .update_reg = 0x06, | |
641 | .update_mask = 0x0c, | |
bd28a157 | 642 | .update_val = 0x04, |
7ce4669c BJ |
643 | .update_val_idle = 0x0c, |
644 | .update_val_normal = 0x04, | |
6909b452 | 645 | }, |
8e6a8d7d | 646 | }; |
6909b452 | 647 | |
547f384f LJ |
648 | /* AB8505 regulator information */ |
649 | static struct ab8500_regulator_info | |
650 | ab8505_regulator_info[AB8505_NUM_REGULATORS] = { | |
651 | /* | |
652 | * Variable Voltage Regulators | |
653 | * name, min mV, max mV, | |
654 | * update bank, reg, mask, enable val | |
655 | * volt bank, reg, mask, table, table length | |
656 | */ | |
657 | [AB8505_LDO_AUX1] = { | |
658 | .desc = { | |
659 | .name = "LDO-AUX1", | |
660 | .ops = &ab8500_regulator_volt_mode_ops, | |
661 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 662 | .id = AB8505_LDO_AUX1, |
547f384f LJ |
663 | .owner = THIS_MODULE, |
664 | .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), | |
62ab4111 | 665 | .volt_table = ldo_vauxn_voltages, |
547f384f | 666 | }, |
547f384f LJ |
667 | .load_lp_uA = 5000, |
668 | .update_bank = 0x04, | |
669 | .update_reg = 0x09, | |
670 | .update_mask = 0x03, | |
671 | .update_val = 0x01, | |
672 | .update_val_idle = 0x03, | |
673 | .update_val_normal = 0x01, | |
674 | .voltage_bank = 0x04, | |
675 | .voltage_reg = 0x1f, | |
676 | .voltage_mask = 0x0f, | |
547f384f LJ |
677 | }, |
678 | [AB8505_LDO_AUX2] = { | |
679 | .desc = { | |
680 | .name = "LDO-AUX2", | |
681 | .ops = &ab8500_regulator_volt_mode_ops, | |
682 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 683 | .id = AB8505_LDO_AUX2, |
547f384f LJ |
684 | .owner = THIS_MODULE, |
685 | .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), | |
62ab4111 | 686 | .volt_table = ldo_vauxn_voltages, |
547f384f | 687 | }, |
547f384f LJ |
688 | .load_lp_uA = 5000, |
689 | .update_bank = 0x04, | |
690 | .update_reg = 0x09, | |
691 | .update_mask = 0x0c, | |
692 | .update_val = 0x04, | |
693 | .update_val_idle = 0x0c, | |
694 | .update_val_normal = 0x04, | |
695 | .voltage_bank = 0x04, | |
696 | .voltage_reg = 0x20, | |
697 | .voltage_mask = 0x0f, | |
547f384f LJ |
698 | }, |
699 | [AB8505_LDO_AUX3] = { | |
700 | .desc = { | |
701 | .name = "LDO-AUX3", | |
702 | .ops = &ab8500_regulator_volt_mode_ops, | |
703 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 704 | .id = AB8505_LDO_AUX3, |
547f384f LJ |
705 | .owner = THIS_MODULE, |
706 | .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages), | |
62ab4111 | 707 | .volt_table = ldo_vaux3_voltages, |
547f384f | 708 | }, |
547f384f LJ |
709 | .load_lp_uA = 5000, |
710 | .update_bank = 0x04, | |
711 | .update_reg = 0x0a, | |
712 | .update_mask = 0x03, | |
713 | .update_val = 0x01, | |
714 | .update_val_idle = 0x03, | |
715 | .update_val_normal = 0x01, | |
716 | .voltage_bank = 0x04, | |
717 | .voltage_reg = 0x21, | |
718 | .voltage_mask = 0x07, | |
547f384f LJ |
719 | }, |
720 | [AB8505_LDO_AUX4] = { | |
721 | .desc = { | |
722 | .name = "LDO-AUX4", | |
723 | .ops = &ab8500_regulator_volt_mode_ops, | |
724 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 725 | .id = AB8505_LDO_AUX4, |
547f384f LJ |
726 | .owner = THIS_MODULE, |
727 | .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), | |
62ab4111 | 728 | .volt_table = ldo_vauxn_voltages, |
547f384f | 729 | }, |
547f384f LJ |
730 | .load_lp_uA = 5000, |
731 | /* values for Vaux4Regu register */ | |
732 | .update_bank = 0x04, | |
733 | .update_reg = 0x2e, | |
734 | .update_mask = 0x03, | |
735 | .update_val = 0x01, | |
736 | .update_val_idle = 0x03, | |
737 | .update_val_normal = 0x01, | |
738 | /* values for Vaux4SEL register */ | |
739 | .voltage_bank = 0x04, | |
740 | .voltage_reg = 0x2f, | |
741 | .voltage_mask = 0x0f, | |
547f384f LJ |
742 | }, |
743 | [AB8505_LDO_AUX5] = { | |
744 | .desc = { | |
745 | .name = "LDO-AUX5", | |
746 | .ops = &ab8500_regulator_volt_mode_ops, | |
747 | .type = REGULATOR_VOLTAGE, | |
748 | .id = AB8505_LDO_AUX5, | |
749 | .owner = THIS_MODULE, | |
750 | .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages), | |
62ab4111 | 751 | .volt_table = ldo_vaux56_voltages, |
547f384f | 752 | }, |
547f384f LJ |
753 | .load_lp_uA = 2000, |
754 | /* values for CtrlVaux5 register */ | |
755 | .update_bank = 0x01, | |
756 | .update_reg = 0x55, | |
ae0a9a3e LJ |
757 | .update_mask = 0x18, |
758 | .update_val = 0x10, | |
759 | .update_val_idle = 0x18, | |
760 | .update_val_normal = 0x10, | |
547f384f LJ |
761 | .voltage_bank = 0x01, |
762 | .voltage_reg = 0x55, | |
763 | .voltage_mask = 0x07, | |
547f384f LJ |
764 | }, |
765 | [AB8505_LDO_AUX6] = { | |
766 | .desc = { | |
767 | .name = "LDO-AUX6", | |
768 | .ops = &ab8500_regulator_volt_mode_ops, | |
769 | .type = REGULATOR_VOLTAGE, | |
770 | .id = AB8505_LDO_AUX6, | |
771 | .owner = THIS_MODULE, | |
772 | .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages), | |
62ab4111 | 773 | .volt_table = ldo_vaux56_voltages, |
547f384f | 774 | }, |
547f384f LJ |
775 | .load_lp_uA = 2000, |
776 | /* values for CtrlVaux6 register */ | |
777 | .update_bank = 0x01, | |
778 | .update_reg = 0x56, | |
ae0a9a3e LJ |
779 | .update_mask = 0x18, |
780 | .update_val = 0x10, | |
781 | .update_val_idle = 0x18, | |
782 | .update_val_normal = 0x10, | |
547f384f LJ |
783 | .voltage_bank = 0x01, |
784 | .voltage_reg = 0x56, | |
785 | .voltage_mask = 0x07, | |
547f384f LJ |
786 | }, |
787 | [AB8505_LDO_INTCORE] = { | |
788 | .desc = { | |
789 | .name = "LDO-INTCORE", | |
790 | .ops = &ab8500_regulator_volt_mode_ops, | |
791 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 792 | .id = AB8505_LDO_INTCORE, |
547f384f LJ |
793 | .owner = THIS_MODULE, |
794 | .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages), | |
62ab4111 | 795 | .volt_table = ldo_vintcore_voltages, |
547f384f | 796 | }, |
547f384f LJ |
797 | .load_lp_uA = 5000, |
798 | .update_bank = 0x03, | |
799 | .update_reg = 0x80, | |
800 | .update_mask = 0x44, | |
801 | .update_val = 0x04, | |
802 | .update_val_idle = 0x44, | |
803 | .update_val_normal = 0x04, | |
804 | .voltage_bank = 0x03, | |
805 | .voltage_reg = 0x80, | |
806 | .voltage_mask = 0x38, | |
547f384f LJ |
807 | .voltage_shift = 3, |
808 | }, | |
809 | ||
810 | /* | |
811 | * Fixed Voltage Regulators | |
812 | * name, fixed mV, | |
813 | * update bank, reg, mask, enable val | |
814 | */ | |
815 | [AB8505_LDO_ADC] = { | |
816 | .desc = { | |
817 | .name = "LDO-ADC", | |
818 | .ops = &ab8500_regulator_mode_ops, | |
819 | .type = REGULATOR_VOLTAGE, | |
820 | .id = AB8505_LDO_ADC, | |
821 | .owner = THIS_MODULE, | |
822 | .n_voltages = 1, | |
b080c78a | 823 | .volt_table = fixed_2000000_voltage, |
547f384f LJ |
824 | }, |
825 | .delay = 10000, | |
547f384f LJ |
826 | .load_lp_uA = 1000, |
827 | .update_bank = 0x03, | |
828 | .update_reg = 0x80, | |
829 | .update_mask = 0x82, | |
830 | .update_val = 0x02, | |
831 | .update_val_idle = 0x82, | |
832 | .update_val_normal = 0x02, | |
833 | }, | |
834 | [AB8505_LDO_USB] = { | |
835 | .desc = { | |
836 | .name = "LDO-USB", | |
837 | .ops = &ab8500_regulator_mode_ops, | |
838 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 839 | .id = AB8505_LDO_USB, |
547f384f LJ |
840 | .owner = THIS_MODULE, |
841 | .n_voltages = 1, | |
b080c78a | 842 | .volt_table = fixed_3300000_voltage, |
547f384f | 843 | }, |
547f384f LJ |
844 | .update_bank = 0x03, |
845 | .update_reg = 0x82, | |
846 | .update_mask = 0x03, | |
847 | .update_val = 0x01, | |
848 | .update_val_idle = 0x03, | |
849 | .update_val_normal = 0x01, | |
850 | }, | |
851 | [AB8505_LDO_AUDIO] = { | |
852 | .desc = { | |
853 | .name = "LDO-AUDIO", | |
854 | .ops = &ab8500_regulator_ops, | |
855 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 856 | .id = AB8505_LDO_AUDIO, |
547f384f LJ |
857 | .owner = THIS_MODULE, |
858 | .n_voltages = 1, | |
b080c78a | 859 | .volt_table = fixed_2000000_voltage, |
547f384f | 860 | }, |
547f384f LJ |
861 | .update_bank = 0x03, |
862 | .update_reg = 0x83, | |
863 | .update_mask = 0x02, | |
864 | .update_val = 0x02, | |
865 | }, | |
866 | [AB8505_LDO_ANAMIC1] = { | |
867 | .desc = { | |
868 | .name = "LDO-ANAMIC1", | |
869 | .ops = &ab8500_regulator_ops, | |
870 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 871 | .id = AB8505_LDO_ANAMIC1, |
547f384f LJ |
872 | .owner = THIS_MODULE, |
873 | .n_voltages = 1, | |
b080c78a | 874 | .volt_table = fixed_2050000_voltage, |
547f384f | 875 | }, |
547f384f LJ |
876 | .update_bank = 0x03, |
877 | .update_reg = 0x83, | |
878 | .update_mask = 0x08, | |
879 | .update_val = 0x08, | |
880 | }, | |
881 | [AB8505_LDO_ANAMIC2] = { | |
882 | .desc = { | |
883 | .name = "LDO-ANAMIC2", | |
884 | .ops = &ab8500_regulator_ops, | |
885 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 886 | .id = AB8505_LDO_ANAMIC2, |
547f384f LJ |
887 | .owner = THIS_MODULE, |
888 | .n_voltages = 1, | |
b080c78a | 889 | .volt_table = fixed_2050000_voltage, |
547f384f | 890 | }, |
547f384f LJ |
891 | .update_bank = 0x03, |
892 | .update_reg = 0x83, | |
893 | .update_mask = 0x10, | |
894 | .update_val = 0x10, | |
895 | }, | |
896 | [AB8505_LDO_AUX8] = { | |
897 | .desc = { | |
898 | .name = "LDO-AUX8", | |
899 | .ops = &ab8500_regulator_ops, | |
900 | .type = REGULATOR_VOLTAGE, | |
901 | .id = AB8505_LDO_AUX8, | |
902 | .owner = THIS_MODULE, | |
903 | .n_voltages = 1, | |
b080c78a | 904 | .volt_table = fixed_1800000_voltage, |
547f384f | 905 | }, |
547f384f LJ |
906 | .update_bank = 0x03, |
907 | .update_reg = 0x83, | |
908 | .update_mask = 0x04, | |
909 | .update_val = 0x04, | |
910 | }, | |
911 | /* | |
912 | * Regulators with fixed voltage and normal/idle modes | |
913 | */ | |
914 | [AB8505_LDO_ANA] = { | |
915 | .desc = { | |
916 | .name = "LDO-ANA", | |
917 | .ops = &ab8500_regulator_mode_ops, | |
918 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 919 | .id = AB8505_LDO_ANA, |
547f384f LJ |
920 | .owner = THIS_MODULE, |
921 | .n_voltages = 1, | |
b080c78a | 922 | .volt_table = fixed_1200000_voltage, |
547f384f | 923 | }, |
547f384f LJ |
924 | .load_lp_uA = 1000, |
925 | .update_bank = 0x04, | |
926 | .update_reg = 0x06, | |
927 | .update_mask = 0x0c, | |
928 | .update_val = 0x04, | |
929 | .update_val_idle = 0x0c, | |
930 | .update_val_normal = 0x04, | |
931 | }, | |
932 | }; | |
933 | ||
8e6a8d7d LJ |
934 | /* AB9540 regulator information */ |
935 | static struct ab8500_regulator_info | |
936 | ab9540_regulator_info[AB9540_NUM_REGULATORS] = { | |
937 | /* | |
938 | * Variable Voltage Regulators | |
939 | * name, min mV, max mV, | |
940 | * update bank, reg, mask, enable val | |
941 | * volt bank, reg, mask, table, table length | |
942 | */ | |
943 | [AB9540_LDO_AUX1] = { | |
944 | .desc = { | |
945 | .name = "LDO-AUX1", | |
946 | .ops = &ab8500_regulator_volt_mode_ops, | |
947 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 948 | .id = AB9540_LDO_AUX1, |
8e6a8d7d LJ |
949 | .owner = THIS_MODULE, |
950 | .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), | |
62ab4111 | 951 | .volt_table = ldo_vauxn_voltages, |
8e6a8d7d | 952 | }, |
8e6a8d7d LJ |
953 | .load_lp_uA = 5000, |
954 | .update_bank = 0x04, | |
955 | .update_reg = 0x09, | |
956 | .update_mask = 0x03, | |
957 | .update_val = 0x01, | |
958 | .update_val_idle = 0x03, | |
959 | .update_val_normal = 0x01, | |
960 | .voltage_bank = 0x04, | |
961 | .voltage_reg = 0x1f, | |
962 | .voltage_mask = 0x0f, | |
8e6a8d7d LJ |
963 | }, |
964 | [AB9540_LDO_AUX2] = { | |
965 | .desc = { | |
966 | .name = "LDO-AUX2", | |
967 | .ops = &ab8500_regulator_volt_mode_ops, | |
968 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 969 | .id = AB9540_LDO_AUX2, |
8e6a8d7d LJ |
970 | .owner = THIS_MODULE, |
971 | .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), | |
62ab4111 | 972 | .volt_table = ldo_vauxn_voltages, |
8e6a8d7d | 973 | }, |
8e6a8d7d LJ |
974 | .load_lp_uA = 5000, |
975 | .update_bank = 0x04, | |
976 | .update_reg = 0x09, | |
977 | .update_mask = 0x0c, | |
978 | .update_val = 0x04, | |
979 | .update_val_idle = 0x0c, | |
980 | .update_val_normal = 0x04, | |
981 | .voltage_bank = 0x04, | |
982 | .voltage_reg = 0x20, | |
983 | .voltage_mask = 0x0f, | |
8e6a8d7d LJ |
984 | }, |
985 | [AB9540_LDO_AUX3] = { | |
986 | .desc = { | |
987 | .name = "LDO-AUX3", | |
988 | .ops = &ab8500_regulator_volt_mode_ops, | |
989 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 990 | .id = AB9540_LDO_AUX3, |
8e6a8d7d LJ |
991 | .owner = THIS_MODULE, |
992 | .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages), | |
62ab4111 | 993 | .volt_table = ldo_vaux3_voltages, |
8e6a8d7d | 994 | }, |
8e6a8d7d LJ |
995 | .load_lp_uA = 5000, |
996 | .update_bank = 0x04, | |
997 | .update_reg = 0x0a, | |
998 | .update_mask = 0x03, | |
999 | .update_val = 0x01, | |
1000 | .update_val_idle = 0x03, | |
1001 | .update_val_normal = 0x01, | |
1002 | .voltage_bank = 0x04, | |
1003 | .voltage_reg = 0x21, | |
1004 | .voltage_mask = 0x07, | |
8e6a8d7d LJ |
1005 | }, |
1006 | [AB9540_LDO_AUX4] = { | |
1007 | .desc = { | |
1008 | .name = "LDO-AUX4", | |
1009 | .ops = &ab8500_regulator_volt_mode_ops, | |
1010 | .type = REGULATOR_VOLTAGE, | |
1011 | .id = AB9540_LDO_AUX4, | |
1012 | .owner = THIS_MODULE, | |
1013 | .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), | |
62ab4111 | 1014 | .volt_table = ldo_vauxn_voltages, |
8e6a8d7d | 1015 | }, |
8e6a8d7d LJ |
1016 | .load_lp_uA = 5000, |
1017 | /* values for Vaux4Regu register */ | |
1018 | .update_bank = 0x04, | |
1019 | .update_reg = 0x2e, | |
1020 | .update_mask = 0x03, | |
1021 | .update_val = 0x01, | |
1022 | .update_val_idle = 0x03, | |
1023 | .update_val_normal = 0x01, | |
1024 | /* values for Vaux4SEL register */ | |
1025 | .voltage_bank = 0x04, | |
1026 | .voltage_reg = 0x2f, | |
1027 | .voltage_mask = 0x0f, | |
8e6a8d7d LJ |
1028 | }, |
1029 | [AB9540_LDO_INTCORE] = { | |
1030 | .desc = { | |
1031 | .name = "LDO-INTCORE", | |
1032 | .ops = &ab8500_regulator_volt_mode_ops, | |
1033 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 1034 | .id = AB9540_LDO_INTCORE, |
8e6a8d7d LJ |
1035 | .owner = THIS_MODULE, |
1036 | .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages), | |
62ab4111 | 1037 | .volt_table = ldo_vintcore_voltages, |
8e6a8d7d | 1038 | }, |
8e6a8d7d LJ |
1039 | .load_lp_uA = 5000, |
1040 | .update_bank = 0x03, | |
1041 | .update_reg = 0x80, | |
1042 | .update_mask = 0x44, | |
1043 | .update_val = 0x44, | |
1044 | .update_val_idle = 0x44, | |
1045 | .update_val_normal = 0x04, | |
1046 | .voltage_bank = 0x03, | |
1047 | .voltage_reg = 0x80, | |
1048 | .voltage_mask = 0x38, | |
8e6a8d7d LJ |
1049 | .voltage_shift = 3, |
1050 | }, | |
6909b452 | 1051 | |
8e6a8d7d LJ |
1052 | /* |
1053 | * Fixed Voltage Regulators | |
1054 | * name, fixed mV, | |
1055 | * update bank, reg, mask, enable val | |
1056 | */ | |
1057 | [AB9540_LDO_TVOUT] = { | |
1058 | .desc = { | |
1059 | .name = "LDO-TVOUT", | |
1060 | .ops = &ab8500_regulator_mode_ops, | |
1061 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 1062 | .id = AB9540_LDO_TVOUT, |
8e6a8d7d LJ |
1063 | .owner = THIS_MODULE, |
1064 | .n_voltages = 1, | |
b080c78a | 1065 | .volt_table = fixed_2000000_voltage, |
8e6a8d7d LJ |
1066 | }, |
1067 | .delay = 10000, | |
8e6a8d7d LJ |
1068 | .load_lp_uA = 1000, |
1069 | .update_bank = 0x03, | |
1070 | .update_reg = 0x80, | |
1071 | .update_mask = 0x82, | |
1072 | .update_val = 0x02, | |
1073 | .update_val_idle = 0x82, | |
1074 | .update_val_normal = 0x02, | |
1075 | }, | |
1076 | [AB9540_LDO_USB] = { | |
1077 | .desc = { | |
1078 | .name = "LDO-USB", | |
1079 | .ops = &ab8500_regulator_ops, | |
1080 | .type = REGULATOR_VOLTAGE, | |
1081 | .id = AB9540_LDO_USB, | |
1082 | .owner = THIS_MODULE, | |
1083 | .n_voltages = 1, | |
b080c78a | 1084 | .volt_table = fixed_3300000_voltage, |
8e6a8d7d | 1085 | }, |
8e6a8d7d LJ |
1086 | .update_bank = 0x03, |
1087 | .update_reg = 0x82, | |
1088 | .update_mask = 0x03, | |
1089 | .update_val = 0x01, | |
1090 | .update_val_idle = 0x03, | |
1091 | .update_val_normal = 0x01, | |
1092 | }, | |
1093 | [AB9540_LDO_AUDIO] = { | |
1094 | .desc = { | |
1095 | .name = "LDO-AUDIO", | |
1096 | .ops = &ab8500_regulator_ops, | |
1097 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 1098 | .id = AB9540_LDO_AUDIO, |
8e6a8d7d LJ |
1099 | .owner = THIS_MODULE, |
1100 | .n_voltages = 1, | |
b080c78a | 1101 | .volt_table = fixed_2000000_voltage, |
8e6a8d7d | 1102 | }, |
8e6a8d7d LJ |
1103 | .update_bank = 0x03, |
1104 | .update_reg = 0x83, | |
1105 | .update_mask = 0x02, | |
1106 | .update_val = 0x02, | |
1107 | }, | |
1108 | [AB9540_LDO_ANAMIC1] = { | |
1109 | .desc = { | |
1110 | .name = "LDO-ANAMIC1", | |
1111 | .ops = &ab8500_regulator_ops, | |
1112 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 1113 | .id = AB9540_LDO_ANAMIC1, |
8e6a8d7d LJ |
1114 | .owner = THIS_MODULE, |
1115 | .n_voltages = 1, | |
b080c78a | 1116 | .volt_table = fixed_2050000_voltage, |
8e6a8d7d | 1117 | }, |
8e6a8d7d LJ |
1118 | .update_bank = 0x03, |
1119 | .update_reg = 0x83, | |
1120 | .update_mask = 0x08, | |
1121 | .update_val = 0x08, | |
1122 | }, | |
1123 | [AB9540_LDO_ANAMIC2] = { | |
1124 | .desc = { | |
1125 | .name = "LDO-ANAMIC2", | |
1126 | .ops = &ab8500_regulator_ops, | |
1127 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 1128 | .id = AB9540_LDO_ANAMIC2, |
8e6a8d7d LJ |
1129 | .owner = THIS_MODULE, |
1130 | .n_voltages = 1, | |
b080c78a | 1131 | .volt_table = fixed_2050000_voltage, |
8e6a8d7d | 1132 | }, |
8e6a8d7d LJ |
1133 | .update_bank = 0x03, |
1134 | .update_reg = 0x83, | |
1135 | .update_mask = 0x10, | |
1136 | .update_val = 0x10, | |
1137 | }, | |
1138 | [AB9540_LDO_DMIC] = { | |
1139 | .desc = { | |
1140 | .name = "LDO-DMIC", | |
1141 | .ops = &ab8500_regulator_ops, | |
1142 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 1143 | .id = AB9540_LDO_DMIC, |
8e6a8d7d LJ |
1144 | .owner = THIS_MODULE, |
1145 | .n_voltages = 1, | |
b080c78a | 1146 | .volt_table = fixed_1800000_voltage, |
8e6a8d7d | 1147 | }, |
8e6a8d7d LJ |
1148 | .update_bank = 0x03, |
1149 | .update_reg = 0x83, | |
1150 | .update_mask = 0x04, | |
1151 | .update_val = 0x04, | |
1152 | }, | |
1153 | ||
1154 | /* | |
1155 | * Regulators with fixed voltage and normal/idle modes | |
1156 | */ | |
1157 | [AB9540_LDO_ANA] = { | |
1158 | .desc = { | |
1159 | .name = "LDO-ANA", | |
1160 | .ops = &ab8500_regulator_mode_ops, | |
1161 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 1162 | .id = AB9540_LDO_ANA, |
8e6a8d7d LJ |
1163 | .owner = THIS_MODULE, |
1164 | .n_voltages = 1, | |
b080c78a | 1165 | .volt_table = fixed_1200000_voltage, |
8e6a8d7d | 1166 | }, |
8e6a8d7d LJ |
1167 | .load_lp_uA = 1000, |
1168 | .update_bank = 0x04, | |
1169 | .update_reg = 0x06, | |
1170 | .update_mask = 0x0c, | |
1171 | .update_val = 0x08, | |
1172 | .update_val_idle = 0x0c, | |
1173 | .update_val_normal = 0x08, | |
1174 | }, | |
c789ca20 SI |
1175 | }; |
1176 | ||
ae0a9a3e LJ |
1177 | /* AB8540 regulator information */ |
1178 | static struct ab8500_regulator_info | |
1179 | ab8540_regulator_info[AB8540_NUM_REGULATORS] = { | |
1180 | /* | |
1181 | * Variable Voltage Regulators | |
1182 | * name, min mV, max mV, | |
1183 | * update bank, reg, mask, enable val | |
1184 | * volt bank, reg, mask, table, table length | |
1185 | */ | |
1186 | [AB8540_LDO_AUX1] = { | |
1187 | .desc = { | |
1188 | .name = "LDO-AUX1", | |
1189 | .ops = &ab8500_regulator_volt_mode_ops, | |
1190 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 1191 | .id = AB8540_LDO_AUX1, |
ae0a9a3e LJ |
1192 | .owner = THIS_MODULE, |
1193 | .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), | |
62ab4111 | 1194 | .volt_table = ldo_vauxn_voltages, |
ae0a9a3e LJ |
1195 | }, |
1196 | .load_lp_uA = 5000, | |
1197 | .update_bank = 0x04, | |
1198 | .update_reg = 0x09, | |
1199 | .update_mask = 0x03, | |
1200 | .update_val = 0x01, | |
1201 | .update_val_idle = 0x03, | |
1202 | .update_val_normal = 0x01, | |
1203 | .voltage_bank = 0x04, | |
1204 | .voltage_reg = 0x1f, | |
1205 | .voltage_mask = 0x0f, | |
ae0a9a3e LJ |
1206 | }, |
1207 | [AB8540_LDO_AUX2] = { | |
1208 | .desc = { | |
1209 | .name = "LDO-AUX2", | |
1210 | .ops = &ab8500_regulator_volt_mode_ops, | |
1211 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 1212 | .id = AB8540_LDO_AUX2, |
ae0a9a3e LJ |
1213 | .owner = THIS_MODULE, |
1214 | .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), | |
62ab4111 | 1215 | .volt_table = ldo_vauxn_voltages, |
ae0a9a3e LJ |
1216 | }, |
1217 | .load_lp_uA = 5000, | |
1218 | .update_bank = 0x04, | |
1219 | .update_reg = 0x09, | |
1220 | .update_mask = 0x0c, | |
1221 | .update_val = 0x04, | |
1222 | .update_val_idle = 0x0c, | |
1223 | .update_val_normal = 0x04, | |
1224 | .voltage_bank = 0x04, | |
1225 | .voltage_reg = 0x20, | |
1226 | .voltage_mask = 0x0f, | |
ae0a9a3e LJ |
1227 | }, |
1228 | [AB8540_LDO_AUX3] = { | |
1229 | .desc = { | |
1230 | .name = "LDO-AUX3", | |
1231 | .ops = &ab8500_regulator_volt_mode_ops, | |
1232 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 1233 | .id = AB8540_LDO_AUX3, |
ae0a9a3e LJ |
1234 | .owner = THIS_MODULE, |
1235 | .n_voltages = ARRAY_SIZE(ldo_vaux3_ab8540_voltages), | |
62ab4111 | 1236 | .volt_table = ldo_vaux3_ab8540_voltages, |
ae0a9a3e LJ |
1237 | }, |
1238 | .load_lp_uA = 5000, | |
1239 | .update_bank = 0x04, | |
1240 | .update_reg = 0x0a, | |
1241 | .update_mask = 0x03, | |
1242 | .update_val = 0x01, | |
1243 | .update_val_idle = 0x03, | |
1244 | .update_val_normal = 0x01, | |
1245 | .voltage_bank = 0x04, | |
1246 | .voltage_reg = 0x21, | |
1247 | .voltage_mask = 0x07, | |
ae0a9a3e LJ |
1248 | }, |
1249 | [AB8540_LDO_AUX4] = { | |
1250 | .desc = { | |
1251 | .name = "LDO-AUX4", | |
1252 | .ops = &ab8500_regulator_volt_mode_ops, | |
1253 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 1254 | .id = AB8540_LDO_AUX4, |
ae0a9a3e LJ |
1255 | .owner = THIS_MODULE, |
1256 | .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), | |
62ab4111 | 1257 | .volt_table = ldo_vauxn_voltages, |
ae0a9a3e LJ |
1258 | }, |
1259 | .load_lp_uA = 5000, | |
1260 | /* values for Vaux4Regu register */ | |
1261 | .update_bank = 0x04, | |
1262 | .update_reg = 0x2e, | |
1263 | .update_mask = 0x03, | |
1264 | .update_val = 0x01, | |
1265 | .update_val_idle = 0x03, | |
1266 | .update_val_normal = 0x01, | |
1267 | /* values for Vaux4SEL register */ | |
1268 | .voltage_bank = 0x04, | |
1269 | .voltage_reg = 0x2f, | |
1270 | .voltage_mask = 0x0f, | |
ae0a9a3e LJ |
1271 | }, |
1272 | [AB8540_LDO_INTCORE] = { | |
1273 | .desc = { | |
1274 | .name = "LDO-INTCORE", | |
1275 | .ops = &ab8500_regulator_volt_mode_ops, | |
1276 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 1277 | .id = AB8540_LDO_INTCORE, |
ae0a9a3e LJ |
1278 | .owner = THIS_MODULE, |
1279 | .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages), | |
62ab4111 | 1280 | .volt_table = ldo_vintcore_voltages, |
ae0a9a3e LJ |
1281 | }, |
1282 | .load_lp_uA = 5000, | |
1283 | .update_bank = 0x03, | |
1284 | .update_reg = 0x80, | |
1285 | .update_mask = 0x44, | |
1286 | .update_val = 0x44, | |
1287 | .update_val_idle = 0x44, | |
1288 | .update_val_normal = 0x04, | |
1289 | .voltage_bank = 0x03, | |
1290 | .voltage_reg = 0x80, | |
1291 | .voltage_mask = 0x38, | |
ae0a9a3e LJ |
1292 | .voltage_shift = 3, |
1293 | }, | |
1294 | ||
1295 | /* | |
1296 | * Fixed Voltage Regulators | |
1297 | * name, fixed mV, | |
1298 | * update bank, reg, mask, enable val | |
1299 | */ | |
1300 | [AB8540_LDO_TVOUT] = { | |
1301 | .desc = { | |
1302 | .name = "LDO-TVOUT", | |
1303 | .ops = &ab8500_regulator_mode_ops, | |
1304 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 1305 | .id = AB8540_LDO_TVOUT, |
ae0a9a3e LJ |
1306 | .owner = THIS_MODULE, |
1307 | .n_voltages = 1, | |
1308 | }, | |
1309 | .delay = 10000, | |
1310 | .load_lp_uA = 1000, | |
1311 | .update_bank = 0x03, | |
1312 | .update_reg = 0x80, | |
1313 | .update_mask = 0x82, | |
1314 | .update_val = 0x02, | |
1315 | .update_val_idle = 0x82, | |
1316 | .update_val_normal = 0x02, | |
1317 | }, | |
1318 | [AB8540_LDO_AUDIO] = { | |
1319 | .desc = { | |
1320 | .name = "LDO-AUDIO", | |
1321 | .ops = &ab8500_regulator_ops, | |
1322 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 1323 | .id = AB8540_LDO_AUDIO, |
ae0a9a3e LJ |
1324 | .owner = THIS_MODULE, |
1325 | .n_voltages = 1, | |
b080c78a | 1326 | .volt_table = fixed_2000000_voltage, |
ae0a9a3e LJ |
1327 | }, |
1328 | .update_bank = 0x03, | |
1329 | .update_reg = 0x83, | |
1330 | .update_mask = 0x02, | |
1331 | .update_val = 0x02, | |
1332 | }, | |
1333 | [AB8540_LDO_ANAMIC1] = { | |
1334 | .desc = { | |
1335 | .name = "LDO-ANAMIC1", | |
1336 | .ops = &ab8500_regulator_ops, | |
1337 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 1338 | .id = AB8540_LDO_ANAMIC1, |
ae0a9a3e LJ |
1339 | .owner = THIS_MODULE, |
1340 | .n_voltages = 1, | |
b080c78a | 1341 | .volt_table = fixed_2050000_voltage, |
ae0a9a3e LJ |
1342 | }, |
1343 | .update_bank = 0x03, | |
1344 | .update_reg = 0x83, | |
1345 | .update_mask = 0x08, | |
1346 | .update_val = 0x08, | |
1347 | }, | |
1348 | [AB8540_LDO_ANAMIC2] = { | |
1349 | .desc = { | |
1350 | .name = "LDO-ANAMIC2", | |
1351 | .ops = &ab8500_regulator_ops, | |
1352 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 1353 | .id = AB8540_LDO_ANAMIC2, |
ae0a9a3e LJ |
1354 | .owner = THIS_MODULE, |
1355 | .n_voltages = 1, | |
b080c78a | 1356 | .volt_table = fixed_2050000_voltage, |
ae0a9a3e LJ |
1357 | }, |
1358 | .update_bank = 0x03, | |
1359 | .update_reg = 0x83, | |
1360 | .update_mask = 0x10, | |
1361 | .update_val = 0x10, | |
1362 | }, | |
1363 | [AB8540_LDO_DMIC] = { | |
1364 | .desc = { | |
1365 | .name = "LDO-DMIC", | |
1366 | .ops = &ab8500_regulator_ops, | |
1367 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 1368 | .id = AB8540_LDO_DMIC, |
ae0a9a3e LJ |
1369 | .owner = THIS_MODULE, |
1370 | .n_voltages = 1, | |
1371 | }, | |
1372 | .update_bank = 0x03, | |
1373 | .update_reg = 0x83, | |
1374 | .update_mask = 0x04, | |
1375 | .update_val = 0x04, | |
1376 | }, | |
1377 | ||
1378 | /* | |
1379 | * Regulators with fixed voltage and normal/idle modes | |
1380 | */ | |
1381 | [AB8540_LDO_ANA] = { | |
1382 | .desc = { | |
1383 | .name = "LDO-ANA", | |
1384 | .ops = &ab8500_regulator_mode_ops, | |
1385 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 1386 | .id = AB8540_LDO_ANA, |
ae0a9a3e LJ |
1387 | .owner = THIS_MODULE, |
1388 | .n_voltages = 1, | |
b080c78a | 1389 | .volt_table = fixed_1200000_voltage, |
ae0a9a3e LJ |
1390 | }, |
1391 | .load_lp_uA = 1000, | |
1392 | .update_bank = 0x04, | |
1393 | .update_reg = 0x06, | |
1394 | .update_mask = 0x0c, | |
1395 | .update_val = 0x04, | |
1396 | .update_val_idle = 0x0c, | |
1397 | .update_val_normal = 0x04, | |
1398 | }, | |
1399 | [AB8540_LDO_SDIO] = { | |
1400 | .desc = { | |
1401 | .name = "LDO-SDIO", | |
1402 | .ops = &ab8500_regulator_volt_mode_ops, | |
1403 | .type = REGULATOR_VOLTAGE, | |
1404 | .id = AB8540_LDO_SDIO, | |
1405 | .owner = THIS_MODULE, | |
62ab4111 LJ |
1406 | .n_voltages = ARRAY_SIZE(ldo_sdio_voltages), |
1407 | .volt_table = ldo_sdio_voltages, | |
ae0a9a3e | 1408 | }, |
ae0a9a3e LJ |
1409 | .load_lp_uA = 5000, |
1410 | .update_bank = 0x03, | |
1411 | .update_reg = 0x88, | |
1412 | .update_mask = 0x30, | |
1413 | .update_val = 0x10, | |
1414 | .update_val_idle = 0x30, | |
1415 | .update_val_normal = 0x10, | |
1416 | .voltage_bank = 0x03, | |
1417 | .voltage_reg = 0x88, | |
1418 | .voltage_mask = 0x07, | |
ae0a9a3e LJ |
1419 | }, |
1420 | }; | |
1421 | ||
79568b94 BJ |
1422 | struct ab8500_reg_init { |
1423 | u8 bank; | |
1424 | u8 addr; | |
1425 | u8 mask; | |
1426 | }; | |
1427 | ||
1428 | #define REG_INIT(_id, _bank, _addr, _mask) \ | |
1429 | [_id] = { \ | |
1430 | .bank = _bank, \ | |
1431 | .addr = _addr, \ | |
1432 | .mask = _mask, \ | |
1433 | } | |
1434 | ||
8e6a8d7d | 1435 | /* AB8500 register init */ |
79568b94 BJ |
1436 | static struct ab8500_reg_init ab8500_reg_init[] = { |
1437 | /* | |
33bc8f46 | 1438 | * 0x30, VanaRequestCtrl |
79568b94 BJ |
1439 | * 0xc0, VextSupply1RequestCtrl |
1440 | */ | |
43a5911b | 1441 | REG_INIT(AB8500_REGUREQUESTCTRL2, 0x03, 0x04, 0xf0), |
79568b94 BJ |
1442 | /* |
1443 | * 0x03, VextSupply2RequestCtrl | |
1444 | * 0x0c, VextSupply3RequestCtrl | |
1445 | * 0x30, Vaux1RequestCtrl | |
1446 | * 0xc0, Vaux2RequestCtrl | |
1447 | */ | |
1448 | REG_INIT(AB8500_REGUREQUESTCTRL3, 0x03, 0x05, 0xff), | |
1449 | /* | |
1450 | * 0x03, Vaux3RequestCtrl | |
1451 | * 0x04, SwHPReq | |
1452 | */ | |
1453 | REG_INIT(AB8500_REGUREQUESTCTRL4, 0x03, 0x06, 0x07), | |
1454 | /* | |
1455 | * 0x08, VanaSysClkReq1HPValid | |
1456 | * 0x20, Vaux1SysClkReq1HPValid | |
1457 | * 0x40, Vaux2SysClkReq1HPValid | |
1458 | * 0x80, Vaux3SysClkReq1HPValid | |
1459 | */ | |
43a5911b | 1460 | REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xe8), |
79568b94 BJ |
1461 | /* |
1462 | * 0x10, VextSupply1SysClkReq1HPValid | |
1463 | * 0x20, VextSupply2SysClkReq1HPValid | |
1464 | * 0x40, VextSupply3SysClkReq1HPValid | |
1465 | */ | |
43a5911b | 1466 | REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x70), |
79568b94 BJ |
1467 | /* |
1468 | * 0x08, VanaHwHPReq1Valid | |
1469 | * 0x20, Vaux1HwHPReq1Valid | |
1470 | * 0x40, Vaux2HwHPReq1Valid | |
1471 | * 0x80, Vaux3HwHPReq1Valid | |
1472 | */ | |
43a5911b | 1473 | REG_INIT(AB8500_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xe8), |
79568b94 BJ |
1474 | /* |
1475 | * 0x01, VextSupply1HwHPReq1Valid | |
1476 | * 0x02, VextSupply2HwHPReq1Valid | |
1477 | * 0x04, VextSupply3HwHPReq1Valid | |
1478 | */ | |
43a5911b | 1479 | REG_INIT(AB8500_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07), |
79568b94 BJ |
1480 | /* |
1481 | * 0x08, VanaHwHPReq2Valid | |
1482 | * 0x20, Vaux1HwHPReq2Valid | |
1483 | * 0x40, Vaux2HwHPReq2Valid | |
1484 | * 0x80, Vaux3HwHPReq2Valid | |
1485 | */ | |
43a5911b | 1486 | REG_INIT(AB8500_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xe8), |
79568b94 BJ |
1487 | /* |
1488 | * 0x01, VextSupply1HwHPReq2Valid | |
1489 | * 0x02, VextSupply2HwHPReq2Valid | |
1490 | * 0x04, VextSupply3HwHPReq2Valid | |
1491 | */ | |
43a5911b | 1492 | REG_INIT(AB8500_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07), |
79568b94 BJ |
1493 | /* |
1494 | * 0x20, VanaSwHPReqValid | |
1495 | * 0x80, Vaux1SwHPReqValid | |
1496 | */ | |
43a5911b | 1497 | REG_INIT(AB8500_REGUSWHPREQVALID1, 0x03, 0x0d, 0xa0), |
79568b94 BJ |
1498 | /* |
1499 | * 0x01, Vaux2SwHPReqValid | |
1500 | * 0x02, Vaux3SwHPReqValid | |
1501 | * 0x04, VextSupply1SwHPReqValid | |
1502 | * 0x08, VextSupply2SwHPReqValid | |
1503 | * 0x10, VextSupply3SwHPReqValid | |
1504 | */ | |
43a5911b | 1505 | REG_INIT(AB8500_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f), |
79568b94 BJ |
1506 | /* |
1507 | * 0x02, SysClkReq2Valid1 | |
43a5911b LJ |
1508 | * 0x04, SysClkReq3Valid1 |
1509 | * 0x08, SysClkReq4Valid1 | |
1510 | * 0x10, SysClkReq5Valid1 | |
1511 | * 0x20, SysClkReq6Valid1 | |
1512 | * 0x40, SysClkReq7Valid1 | |
79568b94 BJ |
1513 | * 0x80, SysClkReq8Valid1 |
1514 | */ | |
1515 | REG_INIT(AB8500_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe), | |
1516 | /* | |
1517 | * 0x02, SysClkReq2Valid2 | |
43a5911b LJ |
1518 | * 0x04, SysClkReq3Valid2 |
1519 | * 0x08, SysClkReq4Valid2 | |
1520 | * 0x10, SysClkReq5Valid2 | |
1521 | * 0x20, SysClkReq6Valid2 | |
1522 | * 0x40, SysClkReq7Valid2 | |
79568b94 BJ |
1523 | * 0x80, SysClkReq8Valid2 |
1524 | */ | |
1525 | REG_INIT(AB8500_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe), | |
1526 | /* | |
1527 | * 0x02, VTVoutEna | |
1528 | * 0x04, Vintcore12Ena | |
1529 | * 0x38, Vintcore12Sel | |
1530 | * 0x40, Vintcore12LP | |
1531 | * 0x80, VTVoutLP | |
1532 | */ | |
1533 | REG_INIT(AB8500_REGUMISC1, 0x03, 0x80, 0xfe), | |
1534 | /* | |
1535 | * 0x02, VaudioEna | |
1536 | * 0x04, VdmicEna | |
1537 | * 0x08, Vamic1Ena | |
1538 | * 0x10, Vamic2Ena | |
1539 | */ | |
1540 | REG_INIT(AB8500_VAUDIOSUPPLY, 0x03, 0x83, 0x1e), | |
1541 | /* | |
1542 | * 0x01, Vamic1_dzout | |
1543 | * 0x02, Vamic2_dzout | |
1544 | */ | |
1545 | REG_INIT(AB8500_REGUCTRL1VAMIC, 0x03, 0x84, 0x03), | |
d79df329 | 1546 | /* |
43a5911b | 1547 | * 0x03, VpllRegu (NOTE! PRCMU register bits) |
33bc8f46 | 1548 | * 0x0c, VanaRegu |
79568b94 BJ |
1549 | */ |
1550 | REG_INIT(AB8500_VPLLVANAREGU, 0x04, 0x06, 0x0f), | |
1551 | /* | |
1552 | * 0x01, VrefDDREna | |
1553 | * 0x02, VrefDDRSleepMode | |
1554 | */ | |
1555 | REG_INIT(AB8500_VREFDDR, 0x04, 0x07, 0x03), | |
1556 | /* | |
1557 | * 0x03, VextSupply1Regu | |
1558 | * 0x0c, VextSupply2Regu | |
1559 | * 0x30, VextSupply3Regu | |
1560 | * 0x40, ExtSupply2Bypass | |
1561 | * 0x80, ExtSupply3Bypass | |
1562 | */ | |
1563 | REG_INIT(AB8500_EXTSUPPLYREGU, 0x04, 0x08, 0xff), | |
1564 | /* | |
1565 | * 0x03, Vaux1Regu | |
1566 | * 0x0c, Vaux2Regu | |
1567 | */ | |
1568 | REG_INIT(AB8500_VAUX12REGU, 0x04, 0x09, 0x0f), | |
1569 | /* | |
1570 | * 0x03, Vaux3Regu | |
1571 | */ | |
43a5911b | 1572 | REG_INIT(AB8500_VRF1VAUX3REGU, 0x04, 0x0a, 0x03), |
79568b94 BJ |
1573 | /* |
1574 | * 0x0f, Vaux1Sel | |
1575 | */ | |
1576 | REG_INIT(AB8500_VAUX1SEL, 0x04, 0x1f, 0x0f), | |
1577 | /* | |
1578 | * 0x0f, Vaux2Sel | |
1579 | */ | |
1580 | REG_INIT(AB8500_VAUX2SEL, 0x04, 0x20, 0x0f), | |
1581 | /* | |
1582 | * 0x07, Vaux3Sel | |
1583 | */ | |
43a5911b | 1584 | REG_INIT(AB8500_VRF1VAUX3SEL, 0x04, 0x21, 0x07), |
79568b94 BJ |
1585 | /* |
1586 | * 0x01, VextSupply12LP | |
1587 | */ | |
1588 | REG_INIT(AB8500_REGUCTRL2SPARE, 0x04, 0x22, 0x01), | |
1589 | /* | |
1590 | * 0x04, Vaux1Disch | |
1591 | * 0x08, Vaux2Disch | |
1592 | * 0x10, Vaux3Disch | |
1593 | * 0x20, Vintcore12Disch | |
1594 | * 0x40, VTVoutDisch | |
1595 | * 0x80, VaudioDisch | |
1596 | */ | |
43a5911b | 1597 | REG_INIT(AB8500_REGUCTRLDISCH, 0x04, 0x43, 0xfc), |
79568b94 BJ |
1598 | /* |
1599 | * 0x02, VanaDisch | |
1600 | * 0x04, VdmicPullDownEna | |
1601 | * 0x10, VdmicDisch | |
1602 | */ | |
43a5911b | 1603 | REG_INIT(AB8500_REGUCTRLDISCH2, 0x04, 0x44, 0x16), |
79568b94 BJ |
1604 | }; |
1605 | ||
547f384f LJ |
1606 | /* AB8505 register init */ |
1607 | static struct ab8500_reg_init ab8505_reg_init[] = { | |
1608 | /* | |
1609 | * 0x03, VarmRequestCtrl | |
1610 | * 0x0c, VsmpsCRequestCtrl | |
1611 | * 0x30, VsmpsARequestCtrl | |
1612 | * 0xc0, VsmpsBRequestCtrl | |
1613 | */ | |
1614 | REG_INIT(AB8505_REGUREQUESTCTRL1, 0x03, 0x03, 0xff), | |
1615 | /* | |
1616 | * 0x03, VsafeRequestCtrl | |
1617 | * 0x0c, VpllRequestCtrl | |
1618 | * 0x30, VanaRequestCtrl | |
1619 | */ | |
1620 | REG_INIT(AB8505_REGUREQUESTCTRL2, 0x03, 0x04, 0x3f), | |
1621 | /* | |
1622 | * 0x30, Vaux1RequestCtrl | |
1623 | * 0xc0, Vaux2RequestCtrl | |
1624 | */ | |
1625 | REG_INIT(AB8505_REGUREQUESTCTRL3, 0x03, 0x05, 0xf0), | |
1626 | /* | |
1627 | * 0x03, Vaux3RequestCtrl | |
1628 | * 0x04, SwHPReq | |
1629 | */ | |
1630 | REG_INIT(AB8505_REGUREQUESTCTRL4, 0x03, 0x06, 0x07), | |
1631 | /* | |
1632 | * 0x01, VsmpsASysClkReq1HPValid | |
1633 | * 0x02, VsmpsBSysClkReq1HPValid | |
1634 | * 0x04, VsafeSysClkReq1HPValid | |
1635 | * 0x08, VanaSysClkReq1HPValid | |
1636 | * 0x10, VpllSysClkReq1HPValid | |
1637 | * 0x20, Vaux1SysClkReq1HPValid | |
1638 | * 0x40, Vaux2SysClkReq1HPValid | |
1639 | * 0x80, Vaux3SysClkReq1HPValid | |
1640 | */ | |
1641 | REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff), | |
1642 | /* | |
1643 | * 0x01, VsmpsCSysClkReq1HPValid | |
1644 | * 0x02, VarmSysClkReq1HPValid | |
1645 | * 0x04, VbbSysClkReq1HPValid | |
1646 | * 0x08, VsmpsMSysClkReq1HPValid | |
1647 | */ | |
1648 | REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x0f), | |
1649 | /* | |
1650 | * 0x01, VsmpsAHwHPReq1Valid | |
1651 | * 0x02, VsmpsBHwHPReq1Valid | |
1652 | * 0x04, VsafeHwHPReq1Valid | |
1653 | * 0x08, VanaHwHPReq1Valid | |
1654 | * 0x10, VpllHwHPReq1Valid | |
1655 | * 0x20, Vaux1HwHPReq1Valid | |
1656 | * 0x40, Vaux2HwHPReq1Valid | |
1657 | * 0x80, Vaux3HwHPReq1Valid | |
1658 | */ | |
1659 | REG_INIT(AB8505_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff), | |
1660 | /* | |
1661 | * 0x08, VsmpsMHwHPReq1Valid | |
1662 | */ | |
1663 | REG_INIT(AB8505_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x08), | |
1664 | /* | |
1665 | * 0x01, VsmpsAHwHPReq2Valid | |
1666 | * 0x02, VsmpsBHwHPReq2Valid | |
1667 | * 0x04, VsafeHwHPReq2Valid | |
1668 | * 0x08, VanaHwHPReq2Valid | |
1669 | * 0x10, VpllHwHPReq2Valid | |
1670 | * 0x20, Vaux1HwHPReq2Valid | |
1671 | * 0x40, Vaux2HwHPReq2Valid | |
1672 | * 0x80, Vaux3HwHPReq2Valid | |
1673 | */ | |
1674 | REG_INIT(AB8505_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff), | |
1675 | /* | |
1676 | * 0x08, VsmpsMHwHPReq2Valid | |
1677 | */ | |
1678 | REG_INIT(AB8505_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x08), | |
1679 | /* | |
1680 | * 0x01, VsmpsCSwHPReqValid | |
1681 | * 0x02, VarmSwHPReqValid | |
1682 | * 0x04, VsmpsASwHPReqValid | |
1683 | * 0x08, VsmpsBSwHPReqValid | |
1684 | * 0x10, VsafeSwHPReqValid | |
1685 | * 0x20, VanaSwHPReqValid | |
1686 | * 0x40, VpllSwHPReqValid | |
1687 | * 0x80, Vaux1SwHPReqValid | |
1688 | */ | |
1689 | REG_INIT(AB8505_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff), | |
1690 | /* | |
1691 | * 0x01, Vaux2SwHPReqValid | |
1692 | * 0x02, Vaux3SwHPReqValid | |
1693 | * 0x20, VsmpsMSwHPReqValid | |
1694 | */ | |
1695 | REG_INIT(AB8505_REGUSWHPREQVALID2, 0x03, 0x0e, 0x23), | |
1696 | /* | |
1697 | * 0x02, SysClkReq2Valid1 | |
1698 | * 0x04, SysClkReq3Valid1 | |
1699 | * 0x08, SysClkReq4Valid1 | |
1700 | */ | |
1701 | REG_INIT(AB8505_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0x0e), | |
1702 | /* | |
1703 | * 0x02, SysClkReq2Valid2 | |
1704 | * 0x04, SysClkReq3Valid2 | |
1705 | * 0x08, SysClkReq4Valid2 | |
1706 | */ | |
1707 | REG_INIT(AB8505_REGUSYSCLKREQVALID2, 0x03, 0x10, 0x0e), | |
1708 | /* | |
1709 | * 0x01, Vaux4SwHPReqValid | |
1710 | * 0x02, Vaux4HwHPReq2Valid | |
1711 | * 0x04, Vaux4HwHPReq1Valid | |
1712 | * 0x08, Vaux4SysClkReq1HPValid | |
1713 | */ | |
1714 | REG_INIT(AB8505_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f), | |
1715 | /* | |
1716 | * 0x02, VadcEna | |
1717 | * 0x04, VintCore12Ena | |
1718 | * 0x38, VintCore12Sel | |
1719 | * 0x40, VintCore12LP | |
1720 | * 0x80, VadcLP | |
1721 | */ | |
1722 | REG_INIT(AB8505_REGUMISC1, 0x03, 0x80, 0xfe), | |
1723 | /* | |
1724 | * 0x02, VaudioEna | |
1725 | * 0x04, VdmicEna | |
1726 | * 0x08, Vamic1Ena | |
1727 | * 0x10, Vamic2Ena | |
1728 | */ | |
1729 | REG_INIT(AB8505_VAUDIOSUPPLY, 0x03, 0x83, 0x1e), | |
1730 | /* | |
1731 | * 0x01, Vamic1_dzout | |
1732 | * 0x02, Vamic2_dzout | |
1733 | */ | |
1734 | REG_INIT(AB8505_REGUCTRL1VAMIC, 0x03, 0x84, 0x03), | |
1735 | /* | |
1736 | * 0x03, VsmpsARegu | |
1737 | * 0x0c, VsmpsASelCtrl | |
1738 | * 0x10, VsmpsAAutoMode | |
1739 | * 0x20, VsmpsAPWMMode | |
1740 | */ | |
1741 | REG_INIT(AB8505_VSMPSAREGU, 0x04, 0x03, 0x3f), | |
1742 | /* | |
1743 | * 0x03, VsmpsBRegu | |
1744 | * 0x0c, VsmpsBSelCtrl | |
1745 | * 0x10, VsmpsBAutoMode | |
1746 | * 0x20, VsmpsBPWMMode | |
1747 | */ | |
1748 | REG_INIT(AB8505_VSMPSBREGU, 0x04, 0x04, 0x3f), | |
1749 | /* | |
1750 | * 0x03, VsafeRegu | |
1751 | * 0x0c, VsafeSelCtrl | |
1752 | * 0x10, VsafeAutoMode | |
1753 | * 0x20, VsafePWMMode | |
1754 | */ | |
1755 | REG_INIT(AB8505_VSAFEREGU, 0x04, 0x05, 0x3f), | |
1756 | /* | |
1757 | * 0x03, VpllRegu (NOTE! PRCMU register bits) | |
1758 | * 0x0c, VanaRegu | |
1759 | */ | |
1760 | REG_INIT(AB8505_VPLLVANAREGU, 0x04, 0x06, 0x0f), | |
1761 | /* | |
1762 | * 0x03, VextSupply1Regu | |
1763 | * 0x0c, VextSupply2Regu | |
1764 | * 0x30, VextSupply3Regu | |
1765 | * 0x40, ExtSupply2Bypass | |
1766 | * 0x80, ExtSupply3Bypass | |
1767 | */ | |
1768 | REG_INIT(AB8505_EXTSUPPLYREGU, 0x04, 0x08, 0xff), | |
1769 | /* | |
1770 | * 0x03, Vaux1Regu | |
1771 | * 0x0c, Vaux2Regu | |
1772 | */ | |
1773 | REG_INIT(AB8505_VAUX12REGU, 0x04, 0x09, 0x0f), | |
1774 | /* | |
1775 | * 0x0f, Vaux3Regu | |
1776 | */ | |
1777 | REG_INIT(AB8505_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f), | |
1778 | /* | |
1779 | * 0x3f, VsmpsASel1 | |
1780 | */ | |
1781 | REG_INIT(AB8505_VSMPSASEL1, 0x04, 0x13, 0x3f), | |
1782 | /* | |
1783 | * 0x3f, VsmpsASel2 | |
1784 | */ | |
1785 | REG_INIT(AB8505_VSMPSASEL2, 0x04, 0x14, 0x3f), | |
1786 | /* | |
1787 | * 0x3f, VsmpsASel3 | |
1788 | */ | |
1789 | REG_INIT(AB8505_VSMPSASEL3, 0x04, 0x15, 0x3f), | |
1790 | /* | |
1791 | * 0x3f, VsmpsBSel1 | |
1792 | */ | |
1793 | REG_INIT(AB8505_VSMPSBSEL1, 0x04, 0x17, 0x3f), | |
1794 | /* | |
1795 | * 0x3f, VsmpsBSel2 | |
1796 | */ | |
1797 | REG_INIT(AB8505_VSMPSBSEL2, 0x04, 0x18, 0x3f), | |
1798 | /* | |
1799 | * 0x3f, VsmpsBSel3 | |
1800 | */ | |
1801 | REG_INIT(AB8505_VSMPSBSEL3, 0x04, 0x19, 0x3f), | |
1802 | /* | |
1803 | * 0x7f, VsafeSel1 | |
1804 | */ | |
1805 | REG_INIT(AB8505_VSAFESEL1, 0x04, 0x1b, 0x7f), | |
1806 | /* | |
1807 | * 0x3f, VsafeSel2 | |
1808 | */ | |
1809 | REG_INIT(AB8505_VSAFESEL2, 0x04, 0x1c, 0x7f), | |
1810 | /* | |
1811 | * 0x3f, VsafeSel3 | |
1812 | */ | |
1813 | REG_INIT(AB8505_VSAFESEL3, 0x04, 0x1d, 0x7f), | |
1814 | /* | |
1815 | * 0x0f, Vaux1Sel | |
1816 | */ | |
1817 | REG_INIT(AB8505_VAUX1SEL, 0x04, 0x1f, 0x0f), | |
1818 | /* | |
1819 | * 0x0f, Vaux2Sel | |
1820 | */ | |
1821 | REG_INIT(AB8505_VAUX2SEL, 0x04, 0x20, 0x0f), | |
1822 | /* | |
1823 | * 0x07, Vaux3Sel | |
1824 | * 0x30, VRF1Sel | |
1825 | */ | |
1826 | REG_INIT(AB8505_VRF1VAUX3SEL, 0x04, 0x21, 0x37), | |
1827 | /* | |
1828 | * 0x03, Vaux4RequestCtrl | |
1829 | */ | |
1830 | REG_INIT(AB8505_VAUX4REQCTRL, 0x04, 0x2d, 0x03), | |
1831 | /* | |
1832 | * 0x03, Vaux4Regu | |
1833 | */ | |
1834 | REG_INIT(AB8505_VAUX4REGU, 0x04, 0x2e, 0x03), | |
1835 | /* | |
1836 | * 0x0f, Vaux4Sel | |
1837 | */ | |
1838 | REG_INIT(AB8505_VAUX4SEL, 0x04, 0x2f, 0x0f), | |
1839 | /* | |
1840 | * 0x04, Vaux1Disch | |
1841 | * 0x08, Vaux2Disch | |
1842 | * 0x10, Vaux3Disch | |
1843 | * 0x20, Vintcore12Disch | |
1844 | * 0x40, VTVoutDisch | |
1845 | * 0x80, VaudioDisch | |
1846 | */ | |
1847 | REG_INIT(AB8505_REGUCTRLDISCH, 0x04, 0x43, 0xfc), | |
1848 | /* | |
1849 | * 0x02, VanaDisch | |
1850 | * 0x04, VdmicPullDownEna | |
1851 | * 0x10, VdmicDisch | |
1852 | */ | |
1853 | REG_INIT(AB8505_REGUCTRLDISCH2, 0x04, 0x44, 0x16), | |
1854 | /* | |
1855 | * 0x01, Vaux4Disch | |
1856 | */ | |
1857 | REG_INIT(AB8505_REGUCTRLDISCH3, 0x04, 0x48, 0x01), | |
1858 | /* | |
1859 | * 0x07, Vaux5Sel | |
1860 | * 0x08, Vaux5LP | |
1861 | * 0x10, Vaux5Ena | |
1862 | * 0x20, Vaux5Disch | |
1863 | * 0x40, Vaux5DisSfst | |
1864 | * 0x80, Vaux5DisPulld | |
1865 | */ | |
1866 | REG_INIT(AB8505_CTRLVAUX5, 0x01, 0x55, 0xff), | |
1867 | /* | |
1868 | * 0x07, Vaux6Sel | |
1869 | * 0x08, Vaux6LP | |
1870 | * 0x10, Vaux6Ena | |
1871 | * 0x80, Vaux6DisPulld | |
1872 | */ | |
1873 | REG_INIT(AB8505_CTRLVAUX6, 0x01, 0x56, 0x9f), | |
1874 | }; | |
1875 | ||
8e6a8d7d LJ |
1876 | /* AB9540 register init */ |
1877 | static struct ab8500_reg_init ab9540_reg_init[] = { | |
1878 | /* | |
1879 | * 0x03, VarmRequestCtrl | |
1880 | * 0x0c, VapeRequestCtrl | |
1881 | * 0x30, Vsmps1RequestCtrl | |
1882 | * 0xc0, Vsmps2RequestCtrl | |
1883 | */ | |
1884 | REG_INIT(AB9540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff), | |
1885 | /* | |
1886 | * 0x03, Vsmps3RequestCtrl | |
1887 | * 0x0c, VpllRequestCtrl | |
1888 | * 0x30, VanaRequestCtrl | |
1889 | * 0xc0, VextSupply1RequestCtrl | |
1890 | */ | |
1891 | REG_INIT(AB9540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff), | |
1892 | /* | |
1893 | * 0x03, VextSupply2RequestCtrl | |
1894 | * 0x0c, VextSupply3RequestCtrl | |
1895 | * 0x30, Vaux1RequestCtrl | |
1896 | * 0xc0, Vaux2RequestCtrl | |
1897 | */ | |
1898 | REG_INIT(AB9540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff), | |
1899 | /* | |
1900 | * 0x03, Vaux3RequestCtrl | |
1901 | * 0x04, SwHPReq | |
1902 | */ | |
1903 | REG_INIT(AB9540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07), | |
1904 | /* | |
1905 | * 0x01, Vsmps1SysClkReq1HPValid | |
1906 | * 0x02, Vsmps2SysClkReq1HPValid | |
1907 | * 0x04, Vsmps3SysClkReq1HPValid | |
1908 | * 0x08, VanaSysClkReq1HPValid | |
1909 | * 0x10, VpllSysClkReq1HPValid | |
1910 | * 0x20, Vaux1SysClkReq1HPValid | |
1911 | * 0x40, Vaux2SysClkReq1HPValid | |
1912 | * 0x80, Vaux3SysClkReq1HPValid | |
1913 | */ | |
1914 | REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff), | |
1915 | /* | |
1916 | * 0x01, VapeSysClkReq1HPValid | |
1917 | * 0x02, VarmSysClkReq1HPValid | |
1918 | * 0x04, VbbSysClkReq1HPValid | |
1919 | * 0x08, VmodSysClkReq1HPValid | |
1920 | * 0x10, VextSupply1SysClkReq1HPValid | |
1921 | * 0x20, VextSupply2SysClkReq1HPValid | |
1922 | * 0x40, VextSupply3SysClkReq1HPValid | |
1923 | */ | |
1924 | REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x7f), | |
1925 | /* | |
1926 | * 0x01, Vsmps1HwHPReq1Valid | |
1927 | * 0x02, Vsmps2HwHPReq1Valid | |
1928 | * 0x04, Vsmps3HwHPReq1Valid | |
1929 | * 0x08, VanaHwHPReq1Valid | |
1930 | * 0x10, VpllHwHPReq1Valid | |
1931 | * 0x20, Vaux1HwHPReq1Valid | |
1932 | * 0x40, Vaux2HwHPReq1Valid | |
1933 | * 0x80, Vaux3HwHPReq1Valid | |
1934 | */ | |
1935 | REG_INIT(AB9540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff), | |
1936 | /* | |
1937 | * 0x01, VextSupply1HwHPReq1Valid | |
1938 | * 0x02, VextSupply2HwHPReq1Valid | |
1939 | * 0x04, VextSupply3HwHPReq1Valid | |
1940 | * 0x08, VmodHwHPReq1Valid | |
1941 | */ | |
1942 | REG_INIT(AB9540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x0f), | |
1943 | /* | |
1944 | * 0x01, Vsmps1HwHPReq2Valid | |
1945 | * 0x02, Vsmps2HwHPReq2Valid | |
1946 | * 0x03, Vsmps3HwHPReq2Valid | |
1947 | * 0x08, VanaHwHPReq2Valid | |
1948 | * 0x10, VpllHwHPReq2Valid | |
1949 | * 0x20, Vaux1HwHPReq2Valid | |
1950 | * 0x40, Vaux2HwHPReq2Valid | |
1951 | * 0x80, Vaux3HwHPReq2Valid | |
1952 | */ | |
1953 | REG_INIT(AB9540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff), | |
1954 | /* | |
1955 | * 0x01, VextSupply1HwHPReq2Valid | |
1956 | * 0x02, VextSupply2HwHPReq2Valid | |
1957 | * 0x04, VextSupply3HwHPReq2Valid | |
1958 | * 0x08, VmodHwHPReq2Valid | |
1959 | */ | |
1960 | REG_INIT(AB9540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x0f), | |
1961 | /* | |
1962 | * 0x01, VapeSwHPReqValid | |
1963 | * 0x02, VarmSwHPReqValid | |
1964 | * 0x04, Vsmps1SwHPReqValid | |
1965 | * 0x08, Vsmps2SwHPReqValid | |
1966 | * 0x10, Vsmps3SwHPReqValid | |
1967 | * 0x20, VanaSwHPReqValid | |
1968 | * 0x40, VpllSwHPReqValid | |
1969 | * 0x80, Vaux1SwHPReqValid | |
1970 | */ | |
1971 | REG_INIT(AB9540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff), | |
1972 | /* | |
1973 | * 0x01, Vaux2SwHPReqValid | |
1974 | * 0x02, Vaux3SwHPReqValid | |
1975 | * 0x04, VextSupply1SwHPReqValid | |
1976 | * 0x08, VextSupply2SwHPReqValid | |
1977 | * 0x10, VextSupply3SwHPReqValid | |
1978 | * 0x20, VmodSwHPReqValid | |
1979 | */ | |
1980 | REG_INIT(AB9540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x3f), | |
1981 | /* | |
1982 | * 0x02, SysClkReq2Valid1 | |
1983 | * ... | |
1984 | * 0x80, SysClkReq8Valid1 | |
1985 | */ | |
1986 | REG_INIT(AB9540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe), | |
1987 | /* | |
1988 | * 0x02, SysClkReq2Valid2 | |
1989 | * ... | |
1990 | * 0x80, SysClkReq8Valid2 | |
1991 | */ | |
1992 | REG_INIT(AB9540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe), | |
1993 | /* | |
1994 | * 0x01, Vaux4SwHPReqValid | |
1995 | * 0x02, Vaux4HwHPReq2Valid | |
1996 | * 0x04, Vaux4HwHPReq1Valid | |
1997 | * 0x08, Vaux4SysClkReq1HPValid | |
1998 | */ | |
1999 | REG_INIT(AB9540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f), | |
2000 | /* | |
2001 | * 0x02, VTVoutEna | |
2002 | * 0x04, Vintcore12Ena | |
2003 | * 0x38, Vintcore12Sel | |
2004 | * 0x40, Vintcore12LP | |
2005 | * 0x80, VTVoutLP | |
2006 | */ | |
2007 | REG_INIT(AB9540_REGUMISC1, 0x03, 0x80, 0xfe), | |
2008 | /* | |
2009 | * 0x02, VaudioEna | |
2010 | * 0x04, VdmicEna | |
2011 | * 0x08, Vamic1Ena | |
2012 | * 0x10, Vamic2Ena | |
2013 | */ | |
2014 | REG_INIT(AB9540_VAUDIOSUPPLY, 0x03, 0x83, 0x1e), | |
2015 | /* | |
2016 | * 0x01, Vamic1_dzout | |
2017 | * 0x02, Vamic2_dzout | |
2018 | */ | |
2019 | REG_INIT(AB9540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03), | |
2020 | /* | |
2021 | * 0x03, Vsmps1Regu | |
2022 | * 0x0c, Vsmps1SelCtrl | |
2023 | * 0x10, Vsmps1AutoMode | |
2024 | * 0x20, Vsmps1PWMMode | |
2025 | */ | |
2026 | REG_INIT(AB9540_VSMPS1REGU, 0x04, 0x03, 0x3f), | |
2027 | /* | |
2028 | * 0x03, Vsmps2Regu | |
2029 | * 0x0c, Vsmps2SelCtrl | |
2030 | * 0x10, Vsmps2AutoMode | |
2031 | * 0x20, Vsmps2PWMMode | |
2032 | */ | |
2033 | REG_INIT(AB9540_VSMPS2REGU, 0x04, 0x04, 0x3f), | |
2034 | /* | |
2035 | * 0x03, Vsmps3Regu | |
2036 | * 0x0c, Vsmps3SelCtrl | |
2037 | * NOTE! PRCMU register | |
2038 | */ | |
2039 | REG_INIT(AB9540_VSMPS3REGU, 0x04, 0x05, 0x0f), | |
2040 | /* | |
2041 | * 0x03, VpllRegu | |
2042 | * 0x0c, VanaRegu | |
2043 | */ | |
2044 | REG_INIT(AB9540_VPLLVANAREGU, 0x04, 0x06, 0x0f), | |
2045 | /* | |
2046 | * 0x03, VextSupply1Regu | |
2047 | * 0x0c, VextSupply2Regu | |
2048 | * 0x30, VextSupply3Regu | |
2049 | * 0x40, ExtSupply2Bypass | |
2050 | * 0x80, ExtSupply3Bypass | |
2051 | */ | |
2052 | REG_INIT(AB9540_EXTSUPPLYREGU, 0x04, 0x08, 0xff), | |
2053 | /* | |
2054 | * 0x03, Vaux1Regu | |
2055 | * 0x0c, Vaux2Regu | |
2056 | */ | |
2057 | REG_INIT(AB9540_VAUX12REGU, 0x04, 0x09, 0x0f), | |
2058 | /* | |
2059 | * 0x0c, Vrf1Regu | |
2060 | * 0x03, Vaux3Regu | |
2061 | */ | |
2062 | REG_INIT(AB9540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f), | |
2063 | /* | |
2064 | * 0x3f, Vsmps1Sel1 | |
2065 | */ | |
2066 | REG_INIT(AB9540_VSMPS1SEL1, 0x04, 0x13, 0x3f), | |
2067 | /* | |
2068 | * 0x3f, Vsmps1Sel2 | |
2069 | */ | |
2070 | REG_INIT(AB9540_VSMPS1SEL2, 0x04, 0x14, 0x3f), | |
2071 | /* | |
2072 | * 0x3f, Vsmps1Sel3 | |
2073 | */ | |
2074 | REG_INIT(AB9540_VSMPS1SEL3, 0x04, 0x15, 0x3f), | |
2075 | /* | |
2076 | * 0x3f, Vsmps2Sel1 | |
2077 | */ | |
2078 | REG_INIT(AB9540_VSMPS2SEL1, 0x04, 0x17, 0x3f), | |
2079 | /* | |
2080 | * 0x3f, Vsmps2Sel2 | |
2081 | */ | |
2082 | REG_INIT(AB9540_VSMPS2SEL2, 0x04, 0x18, 0x3f), | |
2083 | /* | |
2084 | * 0x3f, Vsmps2Sel3 | |
2085 | */ | |
2086 | REG_INIT(AB9540_VSMPS2SEL3, 0x04, 0x19, 0x3f), | |
2087 | /* | |
2088 | * 0x7f, Vsmps3Sel1 | |
2089 | * NOTE! PRCMU register | |
2090 | */ | |
2091 | REG_INIT(AB9540_VSMPS3SEL1, 0x04, 0x1b, 0x7f), | |
2092 | /* | |
2093 | * 0x7f, Vsmps3Sel2 | |
2094 | * NOTE! PRCMU register | |
2095 | */ | |
2096 | REG_INIT(AB9540_VSMPS3SEL2, 0x04, 0x1c, 0x7f), | |
2097 | /* | |
2098 | * 0x0f, Vaux1Sel | |
2099 | */ | |
2100 | REG_INIT(AB9540_VAUX1SEL, 0x04, 0x1f, 0x0f), | |
2101 | /* | |
2102 | * 0x0f, Vaux2Sel | |
2103 | */ | |
2104 | REG_INIT(AB9540_VAUX2SEL, 0x04, 0x20, 0x0f), | |
2105 | /* | |
2106 | * 0x07, Vaux3Sel | |
2107 | * 0x30, Vrf1Sel | |
2108 | */ | |
2109 | REG_INIT(AB9540_VRF1VAUX3SEL, 0x04, 0x21, 0x37), | |
2110 | /* | |
2111 | * 0x01, VextSupply12LP | |
2112 | */ | |
2113 | REG_INIT(AB9540_REGUCTRL2SPARE, 0x04, 0x22, 0x01), | |
2114 | /* | |
2115 | * 0x03, Vaux4RequestCtrl | |
2116 | */ | |
2117 | REG_INIT(AB9540_VAUX4REQCTRL, 0x04, 0x2d, 0x03), | |
2118 | /* | |
2119 | * 0x03, Vaux4Regu | |
2120 | */ | |
2121 | REG_INIT(AB9540_VAUX4REGU, 0x04, 0x2e, 0x03), | |
2122 | /* | |
2123 | * 0x08, Vaux4Sel | |
2124 | */ | |
2125 | REG_INIT(AB9540_VAUX4SEL, 0x04, 0x2f, 0x0f), | |
2126 | /* | |
2127 | * 0x01, VpllDisch | |
2128 | * 0x02, Vrf1Disch | |
2129 | * 0x04, Vaux1Disch | |
2130 | * 0x08, Vaux2Disch | |
2131 | * 0x10, Vaux3Disch | |
2132 | * 0x20, Vintcore12Disch | |
2133 | * 0x40, VTVoutDisch | |
2134 | * 0x80, VaudioDisch | |
2135 | */ | |
2136 | REG_INIT(AB9540_REGUCTRLDISCH, 0x04, 0x43, 0xff), | |
2137 | /* | |
2138 | * 0x01, VsimDisch | |
2139 | * 0x02, VanaDisch | |
2140 | * 0x04, VdmicPullDownEna | |
2141 | * 0x08, VpllPullDownEna | |
2142 | * 0x10, VdmicDisch | |
2143 | */ | |
2144 | REG_INIT(AB9540_REGUCTRLDISCH2, 0x04, 0x44, 0x1f), | |
2145 | /* | |
2146 | * 0x01, Vaux4Disch | |
2147 | */ | |
2148 | REG_INIT(AB9540_REGUCTRLDISCH3, 0x04, 0x48, 0x01), | |
2149 | }; | |
2150 | ||
ae0a9a3e LJ |
2151 | /* AB8540 register init */ |
2152 | static struct ab8500_reg_init ab8540_reg_init[] = { | |
2153 | /* | |
2154 | * 0x01, VSimSycClkReq1Valid | |
2155 | * 0x02, VSimSycClkReq2Valid | |
2156 | * 0x04, VSimSycClkReq3Valid | |
2157 | * 0x08, VSimSycClkReq4Valid | |
2158 | * 0x10, VSimSycClkReq5Valid | |
2159 | * 0x20, VSimSycClkReq6Valid | |
2160 | * 0x40, VSimSycClkReq7Valid | |
2161 | * 0x80, VSimSycClkReq8Valid | |
2162 | */ | |
2163 | REG_INIT(AB8540_VSIMSYSCLKCTRL, 0x02, 0x33, 0xff), | |
2164 | /* | |
2165 | * 0x03, VarmRequestCtrl | |
2166 | * 0x0c, VapeRequestCtrl | |
2167 | * 0x30, Vsmps1RequestCtrl | |
2168 | * 0xc0, Vsmps2RequestCtrl | |
2169 | */ | |
2170 | REG_INIT(AB8540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff), | |
2171 | /* | |
2172 | * 0x03, Vsmps3RequestCtrl | |
2173 | * 0x0c, VpllRequestCtrl | |
2174 | * 0x30, VanaRequestCtrl | |
2175 | * 0xc0, VextSupply1RequestCtrl | |
2176 | */ | |
2177 | REG_INIT(AB8540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff), | |
2178 | /* | |
2179 | * 0x03, VextSupply2RequestCtrl | |
2180 | * 0x0c, VextSupply3RequestCtrl | |
2181 | * 0x30, Vaux1RequestCtrl | |
2182 | * 0xc0, Vaux2RequestCtrl | |
2183 | */ | |
2184 | REG_INIT(AB8540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff), | |
2185 | /* | |
2186 | * 0x03, Vaux3RequestCtrl | |
2187 | * 0x04, SwHPReq | |
2188 | */ | |
2189 | REG_INIT(AB8540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07), | |
2190 | /* | |
2191 | * 0x01, Vsmps1SysClkReq1HPValid | |
2192 | * 0x02, Vsmps2SysClkReq1HPValid | |
2193 | * 0x04, Vsmps3SysClkReq1HPValid | |
2194 | * 0x08, VanaSysClkReq1HPValid | |
2195 | * 0x10, VpllSysClkReq1HPValid | |
2196 | * 0x20, Vaux1SysClkReq1HPValid | |
2197 | * 0x40, Vaux2SysClkReq1HPValid | |
2198 | * 0x80, Vaux3SysClkReq1HPValid | |
2199 | */ | |
2200 | REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff), | |
2201 | /* | |
2202 | * 0x01, VapeSysClkReq1HPValid | |
2203 | * 0x02, VarmSysClkReq1HPValid | |
2204 | * 0x04, VbbSysClkReq1HPValid | |
2205 | * 0x10, VextSupply1SysClkReq1HPValid | |
2206 | * 0x20, VextSupply2SysClkReq1HPValid | |
2207 | * 0x40, VextSupply3SysClkReq1HPValid | |
2208 | */ | |
2209 | REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x77), | |
2210 | /* | |
2211 | * 0x01, Vsmps1HwHPReq1Valid | |
2212 | * 0x02, Vsmps2HwHPReq1Valid | |
2213 | * 0x04, Vsmps3HwHPReq1Valid | |
2214 | * 0x08, VanaHwHPReq1Valid | |
2215 | * 0x10, VpllHwHPReq1Valid | |
2216 | * 0x20, Vaux1HwHPReq1Valid | |
2217 | * 0x40, Vaux2HwHPReq1Valid | |
2218 | * 0x80, Vaux3HwHPReq1Valid | |
2219 | */ | |
2220 | REG_INIT(AB8540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff), | |
2221 | /* | |
2222 | * 0x01, VextSupply1HwHPReq1Valid | |
2223 | * 0x02, VextSupply2HwHPReq1Valid | |
2224 | * 0x04, VextSupply3HwHPReq1Valid | |
2225 | */ | |
2226 | REG_INIT(AB8540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07), | |
2227 | /* | |
2228 | * 0x01, Vsmps1HwHPReq2Valid | |
2229 | * 0x02, Vsmps2HwHPReq2Valid | |
2230 | * 0x03, Vsmps3HwHPReq2Valid | |
2231 | * 0x08, VanaHwHPReq2Valid | |
2232 | * 0x10, VpllHwHPReq2Valid | |
2233 | * 0x20, Vaux1HwHPReq2Valid | |
2234 | * 0x40, Vaux2HwHPReq2Valid | |
2235 | * 0x80, Vaux3HwHPReq2Valid | |
2236 | */ | |
2237 | REG_INIT(AB8540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff), | |
2238 | /* | |
2239 | * 0x01, VextSupply1HwHPReq2Valid | |
2240 | * 0x02, VextSupply2HwHPReq2Valid | |
2241 | * 0x04, VextSupply3HwHPReq2Valid | |
2242 | */ | |
2243 | REG_INIT(AB8540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07), | |
2244 | /* | |
2245 | * 0x01, VapeSwHPReqValid | |
2246 | * 0x02, VarmSwHPReqValid | |
2247 | * 0x04, Vsmps1SwHPReqValid | |
2248 | * 0x08, Vsmps2SwHPReqValid | |
2249 | * 0x10, Vsmps3SwHPReqValid | |
2250 | * 0x20, VanaSwHPReqValid | |
2251 | * 0x40, VpllSwHPReqValid | |
2252 | * 0x80, Vaux1SwHPReqValid | |
2253 | */ | |
2254 | REG_INIT(AB8540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff), | |
2255 | /* | |
2256 | * 0x01, Vaux2SwHPReqValid | |
2257 | * 0x02, Vaux3SwHPReqValid | |
2258 | * 0x04, VextSupply1SwHPReqValid | |
2259 | * 0x08, VextSupply2SwHPReqValid | |
2260 | * 0x10, VextSupply3SwHPReqValid | |
2261 | */ | |
2262 | REG_INIT(AB8540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f), | |
2263 | /* | |
2264 | * 0x02, SysClkReq2Valid1 | |
2265 | * ... | |
2266 | * 0x80, SysClkReq8Valid1 | |
2267 | */ | |
2268 | REG_INIT(AB8540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xff), | |
2269 | /* | |
2270 | * 0x02, SysClkReq2Valid2 | |
2271 | * ... | |
2272 | * 0x80, SysClkReq8Valid2 | |
2273 | */ | |
2274 | REG_INIT(AB8540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xff), | |
2275 | /* | |
2276 | * 0x01, Vaux4SwHPReqValid | |
2277 | * 0x02, Vaux4HwHPReq2Valid | |
2278 | * 0x04, Vaux4HwHPReq1Valid | |
2279 | * 0x08, Vaux4SysClkReq1HPValid | |
2280 | */ | |
2281 | REG_INIT(AB8540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f), | |
2282 | /* | |
2283 | * 0x01, Vaux5SwHPReqValid | |
2284 | * 0x02, Vaux5HwHPReq2Valid | |
2285 | * 0x04, Vaux5HwHPReq1Valid | |
2286 | * 0x08, Vaux5SysClkReq1HPValid | |
2287 | */ | |
2288 | REG_INIT(AB8540_REGUVAUX5REQVALID, 0x03, 0x12, 0x0f), | |
2289 | /* | |
2290 | * 0x01, Vaux6SwHPReqValid | |
2291 | * 0x02, Vaux6HwHPReq2Valid | |
2292 | * 0x04, Vaux6HwHPReq1Valid | |
2293 | * 0x08, Vaux6SysClkReq1HPValid | |
2294 | */ | |
2295 | REG_INIT(AB8540_REGUVAUX6REQVALID, 0x03, 0x13, 0x0f), | |
2296 | /* | |
2297 | * 0x01, VclkbSwHPReqValid | |
2298 | * 0x02, VclkbHwHPReq2Valid | |
2299 | * 0x04, VclkbHwHPReq1Valid | |
2300 | * 0x08, VclkbSysClkReq1HPValid | |
2301 | */ | |
2302 | REG_INIT(AB8540_REGUVCLKBREQVALID, 0x03, 0x14, 0x0f), | |
2303 | /* | |
2304 | * 0x01, Vrf1SwHPReqValid | |
2305 | * 0x02, Vrf1HwHPReq2Valid | |
2306 | * 0x04, Vrf1HwHPReq1Valid | |
2307 | * 0x08, Vrf1SysClkReq1HPValid | |
2308 | */ | |
2309 | REG_INIT(AB8540_REGUVRF1REQVALID, 0x03, 0x15, 0x0f), | |
2310 | /* | |
2311 | * 0x02, VTVoutEna | |
2312 | * 0x04, Vintcore12Ena | |
2313 | * 0x38, Vintcore12Sel | |
2314 | * 0x40, Vintcore12LP | |
2315 | * 0x80, VTVoutLP | |
2316 | */ | |
2317 | REG_INIT(AB8540_REGUMISC1, 0x03, 0x80, 0xfe), | |
2318 | /* | |
2319 | * 0x02, VaudioEna | |
2320 | * 0x04, VdmicEna | |
2321 | * 0x08, Vamic1Ena | |
2322 | * 0x10, Vamic2Ena | |
2323 | * 0x20, Vamic12LP | |
2324 | * 0xC0, VdmicSel | |
2325 | */ | |
2326 | REG_INIT(AB8540_VAUDIOSUPPLY, 0x03, 0x83, 0xfe), | |
2327 | /* | |
2328 | * 0x01, Vamic1_dzout | |
2329 | * 0x02, Vamic2_dzout | |
2330 | */ | |
2331 | REG_INIT(AB8540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03), | |
2332 | /* | |
2333 | * 0x07, VHSICSel | |
2334 | * 0x08, VHSICOffState | |
2335 | * 0x10, VHSIEna | |
2336 | * 0x20, VHSICLP | |
2337 | */ | |
2338 | REG_INIT(AB8540_VHSIC, 0x03, 0x87, 0x3f), | |
2339 | /* | |
2340 | * 0x07, VSDIOSel | |
2341 | * 0x08, VSDIOOffState | |
2342 | * 0x10, VSDIOEna | |
2343 | * 0x20, VSDIOLP | |
2344 | */ | |
2345 | REG_INIT(AB8540_VSDIO, 0x03, 0x88, 0x3f), | |
2346 | /* | |
2347 | * 0x03, Vsmps1Regu | |
2348 | * 0x0c, Vsmps1SelCtrl | |
2349 | * 0x10, Vsmps1AutoMode | |
2350 | * 0x20, Vsmps1PWMMode | |
2351 | */ | |
2352 | REG_INIT(AB8540_VSMPS1REGU, 0x04, 0x03, 0x3f), | |
2353 | /* | |
2354 | * 0x03, Vsmps2Regu | |
2355 | * 0x0c, Vsmps2SelCtrl | |
2356 | * 0x10, Vsmps2AutoMode | |
2357 | * 0x20, Vsmps2PWMMode | |
2358 | */ | |
2359 | REG_INIT(AB8540_VSMPS2REGU, 0x04, 0x04, 0x3f), | |
2360 | /* | |
2361 | * 0x03, Vsmps3Regu | |
2362 | * 0x0c, Vsmps3SelCtrl | |
2363 | * 0x10, Vsmps3AutoMode | |
2364 | * 0x20, Vsmps3PWMMode | |
2365 | * NOTE! PRCMU register | |
2366 | */ | |
2367 | REG_INIT(AB8540_VSMPS3REGU, 0x04, 0x05, 0x0f), | |
2368 | /* | |
2369 | * 0x03, VpllRegu | |
2370 | * 0x0c, VanaRegu | |
2371 | */ | |
2372 | REG_INIT(AB8540_VPLLVANAREGU, 0x04, 0x06, 0x0f), | |
2373 | /* | |
2374 | * 0x03, VextSupply1Regu | |
2375 | * 0x0c, VextSupply2Regu | |
2376 | * 0x30, VextSupply3Regu | |
2377 | * 0x40, ExtSupply2Bypass | |
2378 | * 0x80, ExtSupply3Bypass | |
2379 | */ | |
2380 | REG_INIT(AB8540_EXTSUPPLYREGU, 0x04, 0x08, 0xff), | |
2381 | /* | |
2382 | * 0x03, Vaux1Regu | |
2383 | * 0x0c, Vaux2Regu | |
2384 | */ | |
2385 | REG_INIT(AB8540_VAUX12REGU, 0x04, 0x09, 0x0f), | |
2386 | /* | |
2387 | * 0x0c, VRF1Regu | |
2388 | * 0x03, Vaux3Regu | |
2389 | */ | |
2390 | REG_INIT(AB8540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f), | |
2391 | /* | |
2392 | * 0x3f, Vsmps1Sel1 | |
2393 | */ | |
2394 | REG_INIT(AB8540_VSMPS1SEL1, 0x04, 0x13, 0x3f), | |
2395 | /* | |
2396 | * 0x3f, Vsmps1Sel2 | |
2397 | */ | |
2398 | REG_INIT(AB8540_VSMPS1SEL2, 0x04, 0x14, 0x3f), | |
2399 | /* | |
2400 | * 0x3f, Vsmps1Sel3 | |
2401 | */ | |
2402 | REG_INIT(AB8540_VSMPS1SEL3, 0x04, 0x15, 0x3f), | |
2403 | /* | |
2404 | * 0x3f, Vsmps2Sel1 | |
2405 | */ | |
2406 | REG_INIT(AB8540_VSMPS2SEL1, 0x04, 0x17, 0x3f), | |
2407 | /* | |
2408 | * 0x3f, Vsmps2Sel2 | |
2409 | */ | |
2410 | REG_INIT(AB8540_VSMPS2SEL2, 0x04, 0x18, 0x3f), | |
2411 | /* | |
2412 | * 0x3f, Vsmps2Sel3 | |
2413 | */ | |
2414 | REG_INIT(AB8540_VSMPS2SEL3, 0x04, 0x19, 0x3f), | |
2415 | /* | |
2416 | * 0x7f, Vsmps3Sel1 | |
2417 | * NOTE! PRCMU register | |
2418 | */ | |
2419 | REG_INIT(AB8540_VSMPS3SEL1, 0x04, 0x1b, 0x7f), | |
2420 | /* | |
2421 | * 0x7f, Vsmps3Sel2 | |
2422 | * NOTE! PRCMU register | |
2423 | */ | |
2424 | REG_INIT(AB8540_VSMPS3SEL2, 0x04, 0x1c, 0x7f), | |
2425 | /* | |
2426 | * 0x0f, Vaux1Sel | |
2427 | */ | |
2428 | REG_INIT(AB8540_VAUX1SEL, 0x04, 0x1f, 0x0f), | |
2429 | /* | |
2430 | * 0x0f, Vaux2Sel | |
2431 | */ | |
2432 | REG_INIT(AB8540_VAUX2SEL, 0x04, 0x20, 0x0f), | |
2433 | /* | |
2434 | * 0x07, Vaux3Sel | |
2435 | * 0x70, Vrf1Sel | |
2436 | */ | |
2437 | REG_INIT(AB8540_VRF1VAUX3SEL, 0x04, 0x21, 0x77), | |
2438 | /* | |
2439 | * 0x01, VextSupply12LP | |
2440 | */ | |
2441 | REG_INIT(AB8540_REGUCTRL2SPARE, 0x04, 0x22, 0x01), | |
2442 | /* | |
2443 | * 0x07, Vanasel | |
2444 | * 0x30, Vpllsel | |
2445 | */ | |
2446 | REG_INIT(AB8540_VANAVPLLSEL, 0x04, 0x29, 0x37), | |
2447 | /* | |
2448 | * 0x03, Vaux4RequestCtrl | |
2449 | */ | |
2450 | REG_INIT(AB8540_VAUX4REQCTRL, 0x04, 0x2d, 0x03), | |
2451 | /* | |
2452 | * 0x03, Vaux4Regu | |
2453 | */ | |
2454 | REG_INIT(AB8540_VAUX4REGU, 0x04, 0x2e, 0x03), | |
2455 | /* | |
2456 | * 0x0f, Vaux4Sel | |
2457 | */ | |
2458 | REG_INIT(AB8540_VAUX4SEL, 0x04, 0x2f, 0x0f), | |
2459 | /* | |
2460 | * 0x03, Vaux5RequestCtrl | |
2461 | */ | |
2462 | REG_INIT(AB8540_VAUX5REQCTRL, 0x04, 0x31, 0x03), | |
2463 | /* | |
2464 | * 0x03, Vaux5Regu | |
2465 | */ | |
2466 | REG_INIT(AB8540_VAUX5REGU, 0x04, 0x32, 0x03), | |
2467 | /* | |
2468 | * 0x3f, Vaux5Sel | |
2469 | */ | |
2470 | REG_INIT(AB8540_VAUX5SEL, 0x04, 0x33, 0x3f), | |
2471 | /* | |
2472 | * 0x03, Vaux6RequestCtrl | |
2473 | */ | |
2474 | REG_INIT(AB8540_VAUX6REQCTRL, 0x04, 0x34, 0x03), | |
2475 | /* | |
2476 | * 0x03, Vaux6Regu | |
2477 | */ | |
2478 | REG_INIT(AB8540_VAUX6REGU, 0x04, 0x35, 0x03), | |
2479 | /* | |
2480 | * 0x3f, Vaux6Sel | |
2481 | */ | |
2482 | REG_INIT(AB8540_VAUX6SEL, 0x04, 0x36, 0x3f), | |
2483 | /* | |
2484 | * 0x03, VCLKBRequestCtrl | |
2485 | */ | |
2486 | REG_INIT(AB8540_VCLKBREQCTRL, 0x04, 0x37, 0x03), | |
2487 | /* | |
2488 | * 0x03, VCLKBRegu | |
2489 | */ | |
2490 | REG_INIT(AB8540_VCLKBREGU, 0x04, 0x38, 0x03), | |
2491 | /* | |
2492 | * 0x07, VCLKBSel | |
2493 | */ | |
2494 | REG_INIT(AB8540_VCLKBSEL, 0x04, 0x39, 0x07), | |
2495 | /* | |
2496 | * 0x03, Vrf1RequestCtrl | |
2497 | */ | |
2498 | REG_INIT(AB8540_VRF1REQCTRL, 0x04, 0x3a, 0x03), | |
2499 | /* | |
2500 | * 0x01, VpllDisch | |
2501 | * 0x02, Vrf1Disch | |
2502 | * 0x04, Vaux1Disch | |
2503 | * 0x08, Vaux2Disch | |
2504 | * 0x10, Vaux3Disch | |
2505 | * 0x20, Vintcore12Disch | |
2506 | * 0x40, VTVoutDisch | |
2507 | * 0x80, VaudioDisch | |
2508 | */ | |
2509 | REG_INIT(AB8540_REGUCTRLDISCH, 0x04, 0x43, 0xff), | |
2510 | /* | |
2511 | * 0x02, VanaDisch | |
2512 | * 0x04, VdmicPullDownEna | |
2513 | * 0x08, VpllPullDownEna | |
2514 | * 0x10, VdmicDisch | |
2515 | */ | |
2516 | REG_INIT(AB8540_REGUCTRLDISCH2, 0x04, 0x44, 0x1e), | |
2517 | /* | |
2518 | * 0x01, Vaux4Disch | |
2519 | */ | |
2520 | REG_INIT(AB8540_REGUCTRLDISCH3, 0x04, 0x48, 0x01), | |
2521 | /* | |
2522 | * 0x01, Vaux5Disch | |
2523 | * 0x02, Vaux6Disch | |
2524 | * 0x04, VCLKBDisch | |
2525 | */ | |
2526 | REG_INIT(AB8540_REGUCTRLDISCH4, 0x04, 0x49, 0x07), | |
2527 | }; | |
2528 | ||
3c1b8438 | 2529 | static int ab8500_regulator_init_registers(struct platform_device *pdev, |
b54969ac | 2530 | struct ab8500_reg_init *reg_init, |
3c1b8438 | 2531 | int id, int mask, int value) |
a7ac1d9e LJ |
2532 | { |
2533 | int err; | |
2534 | ||
3c1b8438 | 2535 | BUG_ON(value & ~mask); |
b54969ac | 2536 | BUG_ON(mask & ~reg_init[id].mask); |
a7ac1d9e | 2537 | |
3c1b8438 | 2538 | /* initialize register */ |
a7ac1d9e LJ |
2539 | err = abx500_mask_and_set_register_interruptible( |
2540 | &pdev->dev, | |
b54969ac LJ |
2541 | reg_init[id].bank, |
2542 | reg_init[id].addr, | |
3c1b8438 | 2543 | mask, value); |
a7ac1d9e LJ |
2544 | if (err < 0) { |
2545 | dev_err(&pdev->dev, | |
2546 | "Failed to initialize 0x%02x, 0x%02x.\n", | |
b54969ac LJ |
2547 | reg_init[id].bank, |
2548 | reg_init[id].addr); | |
a7ac1d9e LJ |
2549 | return err; |
2550 | } | |
a7ac1d9e | 2551 | dev_vdbg(&pdev->dev, |
3c1b8438 | 2552 | " init: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n", |
b54969ac LJ |
2553 | reg_init[id].bank, |
2554 | reg_init[id].addr, | |
3c1b8438 | 2555 | mask, value); |
a7ac1d9e LJ |
2556 | |
2557 | return 0; | |
2558 | } | |
2559 | ||
a5023574 | 2560 | static int ab8500_regulator_register(struct platform_device *pdev, |
b54969ac LJ |
2561 | struct regulator_init_data *init_data, |
2562 | struct ab8500_regulator_info *regulator_info, | |
2563 | int id, struct device_node *np) | |
a7ac1d9e | 2564 | { |
8e6a8d7d | 2565 | struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent); |
a7ac1d9e LJ |
2566 | struct ab8500_regulator_info *info = NULL; |
2567 | struct regulator_config config = { }; | |
2568 | int err; | |
2569 | ||
2570 | /* assign per-regulator data */ | |
b54969ac | 2571 | info = ®ulator_info[id]; |
a7ac1d9e LJ |
2572 | info->dev = &pdev->dev; |
2573 | ||
2574 | config.dev = &pdev->dev; | |
2575 | config.init_data = init_data; | |
2576 | config.driver_data = info; | |
2577 | config.of_node = np; | |
2578 | ||
2579 | /* fix for hardware before ab8500v2.0 */ | |
8e6a8d7d | 2580 | if (is_ab8500_1p1_or_earlier(ab8500)) { |
a7ac1d9e LJ |
2581 | if (info->desc.id == AB8500_LDO_AUX3) { |
2582 | info->desc.n_voltages = | |
2583 | ARRAY_SIZE(ldo_vauxn_voltages); | |
ec1cc4d9 | 2584 | info->desc.volt_table = ldo_vauxn_voltages; |
a7ac1d9e LJ |
2585 | info->voltage_mask = 0xf; |
2586 | } | |
2587 | } | |
2588 | ||
2589 | /* register regulator with framework */ | |
2590 | info->regulator = regulator_register(&info->desc, &config); | |
2591 | if (IS_ERR(info->regulator)) { | |
2592 | err = PTR_ERR(info->regulator); | |
2593 | dev_err(&pdev->dev, "failed to register regulator %s\n", | |
2594 | info->desc.name); | |
2595 | /* when we fail, un-register all earlier regulators */ | |
2596 | while (--id >= 0) { | |
b54969ac | 2597 | info = ®ulator_info[id]; |
a7ac1d9e LJ |
2598 | regulator_unregister(info->regulator); |
2599 | } | |
2600 | return err; | |
2601 | } | |
2602 | ||
2603 | return 0; | |
2604 | } | |
2605 | ||
b54969ac | 2606 | static struct of_regulator_match ab8500_regulator_match[] = { |
7e715b95 LJ |
2607 | { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8500_LDO_AUX1, }, |
2608 | { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8500_LDO_AUX2, }, | |
2609 | { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8500_LDO_AUX3, }, | |
2610 | { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8500_LDO_INTCORE, }, | |
2611 | { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8500_LDO_TVOUT, }, | |
7e715b95 LJ |
2612 | { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8500_LDO_AUDIO, }, |
2613 | { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8500_LDO_ANAMIC1, }, | |
2614 | { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, }, | |
2615 | { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8500_LDO_DMIC, }, | |
2616 | { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8500_LDO_ANA, }, | |
3a8334b9 LJ |
2617 | }; |
2618 | ||
547f384f LJ |
2619 | static struct of_regulator_match ab8505_regulator_match[] = { |
2620 | { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8505_LDO_AUX1, }, | |
2621 | { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8505_LDO_AUX2, }, | |
2622 | { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8505_LDO_AUX3, }, | |
2623 | { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8505_LDO_AUX4, }, | |
2624 | { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8505_LDO_AUX5, }, | |
2625 | { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8505_LDO_AUX6, }, | |
2626 | { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8505_LDO_INTCORE, }, | |
2627 | { .name = "ab8500_ldo_adc", .driver_data = (void *) AB8505_LDO_ADC, }, | |
2628 | { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8505_LDO_AUDIO, }, | |
2629 | { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8505_LDO_ANAMIC1, }, | |
2630 | { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, }, | |
2631 | { .name = "ab8500_ldo_aux8", .driver_data = (void *) AB8505_LDO_AUX8, }, | |
2632 | { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8505_LDO_ANA, }, | |
2633 | }; | |
2634 | ||
ae0a9a3e LJ |
2635 | static struct of_regulator_match ab8540_regulator_match[] = { |
2636 | { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8540_LDO_AUX1, }, | |
2637 | { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8540_LDO_AUX2, }, | |
2638 | { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8540_LDO_AUX3, }, | |
2639 | { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8540_LDO_AUX4, }, | |
2640 | { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8540_LDO_INTCORE, }, | |
2641 | { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8540_LDO_TVOUT, }, | |
2642 | { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8540_LDO_AUDIO, }, | |
2643 | { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8540_LDO_ANAMIC1, }, | |
2644 | { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8540_LDO_ANAMIC2, }, | |
2645 | { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8540_LDO_DMIC, }, | |
2646 | { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8540_LDO_ANA, }, | |
2647 | { .name = "ab8500_ldo_sdio", .driver_data = (void *) AB8540_LDO_SDIO, }, | |
2648 | }; | |
2649 | ||
8e6a8d7d LJ |
2650 | static struct of_regulator_match ab9540_regulator_match[] = { |
2651 | { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB9540_LDO_AUX1, }, | |
2652 | { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB9540_LDO_AUX2, }, | |
2653 | { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB9540_LDO_AUX3, }, | |
2654 | { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB9540_LDO_AUX4, }, | |
2655 | { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB9540_LDO_INTCORE, }, | |
2656 | { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB9540_LDO_TVOUT, }, | |
2657 | { .name = "ab8500_ldo_audio", .driver_data = (void *) AB9540_LDO_AUDIO, }, | |
2658 | { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB9540_LDO_ANAMIC1, }, | |
2659 | { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB9540_LDO_ANAMIC2, }, | |
2660 | { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB9540_LDO_DMIC, }, | |
2661 | { .name = "ab8500_ldo_ana", .driver_data = (void *) AB9540_LDO_ANA, }, | |
2662 | }; | |
2663 | ||
a5023574 | 2664 | static int |
b54969ac LJ |
2665 | ab8500_regulator_of_probe(struct platform_device *pdev, |
2666 | struct ab8500_regulator_info *regulator_info, | |
2667 | int regulator_info_size, | |
2668 | struct of_regulator_match *match, | |
2669 | struct device_node *np) | |
3a8334b9 LJ |
2670 | { |
2671 | int err, i; | |
2672 | ||
b54969ac | 2673 | for (i = 0; i < regulator_info_size; i++) { |
3a8334b9 | 2674 | err = ab8500_regulator_register( |
b54969ac LJ |
2675 | pdev, match[i].init_data, regulator_info, |
2676 | i, match[i].of_node); | |
3a8334b9 LJ |
2677 | if (err) |
2678 | return err; | |
2679 | } | |
2680 | ||
2681 | return 0; | |
2682 | } | |
2683 | ||
a5023574 | 2684 | static int ab8500_regulator_probe(struct platform_device *pdev) |
c789ca20 SI |
2685 | { |
2686 | struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent); | |
3a8334b9 | 2687 | struct device_node *np = pdev->dev.of_node; |
b54969ac | 2688 | struct of_regulator_match *match; |
732805a5 BJ |
2689 | struct ab8500_platform_data *ppdata; |
2690 | struct ab8500_regulator_platform_data *pdata; | |
c789ca20 | 2691 | int i, err; |
b54969ac LJ |
2692 | struct ab8500_regulator_info *regulator_info; |
2693 | int regulator_info_size; | |
2694 | struct ab8500_reg_init *reg_init; | |
2695 | int reg_init_size; | |
2696 | ||
8e6a8d7d LJ |
2697 | if (is_ab9540(ab8500)) { |
2698 | regulator_info = ab9540_regulator_info; | |
2699 | regulator_info_size = ARRAY_SIZE(ab9540_regulator_info); | |
2700 | reg_init = ab9540_reg_init; | |
2701 | reg_init_size = AB9540_NUM_REGULATOR_REGISTERS; | |
2702 | match = ab9540_regulator_match; | |
2703 | match_size = ARRAY_SIZE(ab9540_regulator_match) | |
547f384f LJ |
2704 | } else if (is_ab8505(ab8500)) { |
2705 | regulator_info = ab8505_regulator_info; | |
2706 | regulator_info_size = ARRAY_SIZE(ab8505_regulator_info); | |
2707 | reg_init = ab8505_reg_init; | |
2708 | reg_init_size = AB8505_NUM_REGULATOR_REGISTERS; | |
ae0a9a3e LJ |
2709 | } else if (is_ab8540(ab8500)) { |
2710 | regulator_info = ab8540_regulator_info; | |
2711 | regulator_info_size = ARRAY_SIZE(ab8540_regulator_info); | |
2712 | reg_init = ab8540_reg_init; | |
2713 | reg_init_size = AB8540_NUM_REGULATOR_REGISTERS; | |
8e6a8d7d LJ |
2714 | } else { |
2715 | regulator_info = ab8500_regulator_info; | |
2716 | regulator_info_size = ARRAY_SIZE(ab8500_regulator_info); | |
2717 | reg_init = ab8500_reg_init; | |
2718 | reg_init_size = AB8500_NUM_REGULATOR_REGISTERS; | |
2719 | match = ab8500_regulator_match; | |
2720 | match_size = ARRAY_SIZE(ab8500_regulator_match) | |
2721 | } | |
c789ca20 | 2722 | |
3a8334b9 | 2723 | if (np) { |
b54969ac | 2724 | err = of_regulator_match(&pdev->dev, np, match, match_size); |
3a8334b9 LJ |
2725 | if (err < 0) { |
2726 | dev_err(&pdev->dev, | |
2727 | "Error parsing regulator init data: %d\n", err); | |
2728 | return err; | |
2729 | } | |
2730 | ||
b54969ac LJ |
2731 | err = ab8500_regulator_of_probe(pdev, regulator_info, |
2732 | regulator_info_size, match, np); | |
3a8334b9 LJ |
2733 | return err; |
2734 | } | |
2735 | ||
c789ca20 SI |
2736 | if (!ab8500) { |
2737 | dev_err(&pdev->dev, "null mfd parent\n"); | |
2738 | return -EINVAL; | |
2739 | } | |
732805a5 BJ |
2740 | |
2741 | ppdata = dev_get_platdata(ab8500->dev); | |
2742 | if (!ppdata) { | |
2743 | dev_err(&pdev->dev, "null parent pdata\n"); | |
2744 | return -EINVAL; | |
2745 | } | |
2746 | ||
2747 | pdata = ppdata->regulator; | |
fc24b426 BJ |
2748 | if (!pdata) { |
2749 | dev_err(&pdev->dev, "null pdata\n"); | |
2750 | return -EINVAL; | |
2751 | } | |
c789ca20 | 2752 | |
cb189b07 | 2753 | /* make sure the platform data has the correct size */ |
b54969ac | 2754 | if (pdata->num_regulator != regulator_info_size) { |
79568b94 | 2755 | dev_err(&pdev->dev, "Configuration error: size mismatch.\n"); |
cb189b07 BJ |
2756 | return -EINVAL; |
2757 | } | |
2758 | ||
da0b0c47 LJ |
2759 | /* initialize debug (initial state is recorded with this call) */ |
2760 | err = ab8500_regulator_debug_init(pdev); | |
2761 | if (err) | |
2762 | return err; | |
2763 | ||
79568b94 | 2764 | /* initialize registers */ |
732805a5 | 2765 | for (i = 0; i < pdata->num_reg_init; i++) { |
3c1b8438 | 2766 | int id, mask, value; |
79568b94 | 2767 | |
732805a5 BJ |
2768 | id = pdata->reg_init[i].id; |
2769 | mask = pdata->reg_init[i].mask; | |
2770 | value = pdata->reg_init[i].value; | |
79568b94 BJ |
2771 | |
2772 | /* check for configuration errors */ | |
3c1b8438 | 2773 | BUG_ON(id >= AB8500_NUM_REGULATOR_REGISTERS); |
79568b94 | 2774 | |
b54969ac | 2775 | err = ab8500_regulator_init_registers(pdev, reg_init, id, mask, value); |
a7ac1d9e | 2776 | if (err < 0) |
79568b94 | 2777 | return err; |
79568b94 BJ |
2778 | } |
2779 | ||
f7eae37f RV |
2780 | if (!is_ab8505(ab8500)) { |
2781 | /* register external regulators (before Vaux1, 2 and 3) */ | |
2782 | err = ab8500_ext_regulator_init(pdev); | |
2783 | if (err) | |
2784 | return err; | |
2785 | } | |
d1a82001 | 2786 | |
c789ca20 | 2787 | /* register all regulators */ |
b54969ac LJ |
2788 | for (i = 0; i < regulator_info_size; i++) { |
2789 | err = ab8500_regulator_register(pdev, &pdata->regulator[i], | |
2790 | regulator_info, i, NULL); | |
a7ac1d9e | 2791 | if (err < 0) |
c789ca20 | 2792 | return err; |
c789ca20 SI |
2793 | } |
2794 | ||
2795 | return 0; | |
2796 | } | |
2797 | ||
8dc995f5 | 2798 | static int ab8500_regulator_remove(struct platform_device *pdev) |
c789ca20 | 2799 | { |
d1a82001 | 2800 | int i, err; |
8e6a8d7d | 2801 | struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent); |
b54969ac LJ |
2802 | struct ab8500_regulator_info *regulator_info; |
2803 | int regulator_info_size; | |
c789ca20 | 2804 | |
8e6a8d7d LJ |
2805 | |
2806 | if (is_ab9540(ab8500)) { | |
2807 | regulator_info = ab9540_regulator_info; | |
2808 | regulator_info_size = ARRAY_SIZE(ab9540_regulator_info); | |
547f384f LJ |
2809 | } else if (is_ab8505(ab8500)) { |
2810 | regulator_info = ab8505_regulator_info; | |
2811 | regulator_info_size = ARRAY_SIZE(ab8505_regulator_info); | |
8e6a8d7d LJ |
2812 | } else { |
2813 | regulator_info = ab8500_regulator_info; | |
2814 | regulator_info_size = ARRAY_SIZE(ab8500_regulator_info); | |
2815 | } | |
b54969ac LJ |
2816 | |
2817 | for (i = 0; i < regulator_info_size; i++) { | |
c789ca20 | 2818 | struct ab8500_regulator_info *info = NULL; |
b54969ac | 2819 | info = ®ulator_info[i]; |
09aefa12 BJ |
2820 | |
2821 | dev_vdbg(rdev_get_dev(info->regulator), | |
2822 | "%s-remove\n", info->desc.name); | |
2823 | ||
c789ca20 SI |
2824 | regulator_unregister(info->regulator); |
2825 | } | |
2826 | ||
f7eae37f RV |
2827 | if (!is_ab8505(ab8500)) { |
2828 | /* remove external regulators (after Vaux1, 2 and 3) */ | |
2829 | err = ab8500_ext_regulator_exit(pdev); | |
2830 | if (err) | |
2831 | return err; | |
2832 | } | |
d1a82001 | 2833 | |
da0b0c47 LJ |
2834 | /* remove regulator debug */ |
2835 | err = ab8500_regulator_debug_exit(pdev); | |
2836 | if (err) | |
2837 | return err; | |
2838 | ||
c789ca20 SI |
2839 | return 0; |
2840 | } | |
2841 | ||
2842 | static struct platform_driver ab8500_regulator_driver = { | |
2843 | .probe = ab8500_regulator_probe, | |
5eb9f2b9 | 2844 | .remove = ab8500_regulator_remove, |
c789ca20 SI |
2845 | .driver = { |
2846 | .name = "ab8500-regulator", | |
2847 | .owner = THIS_MODULE, | |
2848 | }, | |
2849 | }; | |
2850 | ||
2851 | static int __init ab8500_regulator_init(void) | |
2852 | { | |
2853 | int ret; | |
2854 | ||
2855 | ret = platform_driver_register(&ab8500_regulator_driver); | |
2856 | if (ret != 0) | |
2857 | pr_err("Failed to register ab8500 regulator: %d\n", ret); | |
2858 | ||
2859 | return ret; | |
2860 | } | |
2861 | subsys_initcall(ab8500_regulator_init); | |
2862 | ||
2863 | static void __exit ab8500_regulator_exit(void) | |
2864 | { | |
2865 | platform_driver_unregister(&ab8500_regulator_driver); | |
2866 | } | |
2867 | module_exit(ab8500_regulator_exit); | |
2868 | ||
2869 | MODULE_LICENSE("GPL v2"); | |
2870 | MODULE_AUTHOR("Sundar Iyer <sundar.iyer@stericsson.com>"); | |
732805a5 | 2871 | MODULE_AUTHOR("Bengt Jonsson <bengt.g.jonsson@stericsson.com>"); |
547f384f | 2872 | MODULE_AUTHOR("Daniel Willerud <daniel.willerud@stericsson.com>"); |
c789ca20 SI |
2873 | MODULE_DESCRIPTION("Regulator Driver for ST-Ericsson AB8500 Mixed-Sig PMIC"); |
2874 | MODULE_ALIAS("platform:ab8500-regulator"); |