[mirror_ubuntu-artful-kernel.git] / drivers / regulator / anatop-regulator.c

/*
 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
 */

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.

 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.

 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 */

#include <linux/slab.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/mfd/syscon.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/regmap.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/of_regulator.h>
#include <linux/regulator/machine.h>

#define LDO_RAMP_UP_UNIT_IN_CYCLES      64 /* 64 cycles per step */
#define LDO_RAMP_UP_FREQ_IN_MHZ         24 /* cycle based on 24M OSC */

#define LDO_POWER_GATE			0x00
#define LDO_FET_FULL_ON			0x1f

struct anatop_regulator {
	const char *name;
	u32 control_reg;
	struct regmap *anatop;
	int vol_bit_shift;
	int vol_bit_width;
	u32 delay_reg;
	int delay_bit_shift;
	int delay_bit_width;
	int min_bit_val;
	int min_voltage;
	int max_voltage;
	struct regulator_desc rdesc;
	struct regulator_init_data *initdata;
	bool bypass;
	int sel;
};

static int anatop_regmap_set_voltage_time_sel(struct regulator_dev *reg,
	unsigned int old_sel,
	unsigned int new_sel)
{
	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	u32 val;
	int ret = 0;

	/* check whether need to care about LDO ramp up speed */
	if (anatop_reg->delay_bit_width && new_sel > old_sel) {
		/*
		 * the delay for LDO ramp up time is
		 * based on the register setting, we need
		 * to calculate how many steps LDO need to
		 * ramp up, and how much delay needed. (us)
		 */
		regmap_read(anatop_reg->anatop, anatop_reg->delay_reg, &val);
		val = (val >> anatop_reg->delay_bit_shift) &
			((1 << anatop_reg->delay_bit_width) - 1);
		ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES <<
			val) / LDO_RAMP_UP_FREQ_IN_MHZ + 1;
	}

	return ret;
}

static int anatop_regmap_enable(struct regulator_dev *reg)
{
	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	int sel;

	sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel;
	return regulator_set_voltage_sel_regmap(reg, sel);
}

static int anatop_regmap_disable(struct regulator_dev *reg)
{
	return regulator_set_voltage_sel_regmap(reg, LDO_POWER_GATE);
}

static int anatop_regmap_is_enabled(struct regulator_dev *reg)
{
	return regulator_get_voltage_sel_regmap(reg) != LDO_POWER_GATE;
}

static int anatop_regmap_core_set_voltage_sel(struct regulator_dev *reg,
					      unsigned selector)
{
	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	int ret;

	if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) {
		anatop_reg->sel = selector;
		return 0;
	}

	ret = regulator_set_voltage_sel_regmap(reg, selector);
	if (!ret)
		anatop_reg->sel = selector;
	return ret;
}

static int anatop_regmap_core_get_voltage_sel(struct regulator_dev *reg)
{
	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);

	if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg))
		return anatop_reg->sel;

	return regulator_get_voltage_sel_regmap(reg);
}

static int anatop_regmap_get_bypass(struct regulator_dev *reg, bool *enable)
{
	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	int sel;

	sel = regulator_get_voltage_sel_regmap(reg);
	if (sel == LDO_FET_FULL_ON)
		WARN_ON(!anatop_reg->bypass);
	else if (sel != LDO_POWER_GATE)
		WARN_ON(anatop_reg->bypass);

	*enable = anatop_reg->bypass;
	return 0;
}

static int anatop_regmap_set_bypass(struct regulator_dev *reg, bool enable)
{
	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	int sel;

	if (enable == anatop_reg->bypass)
		return 0;

	sel = enable ? LDO_FET_FULL_ON : anatop_reg->sel;
	anatop_reg->bypass = enable;

	return regulator_set_voltage_sel_regmap(reg, sel);
}

static struct regulator_ops anatop_rops = {
	.set_voltage_sel = regulator_set_voltage_sel_regmap,
	.get_voltage_sel = regulator_get_voltage_sel_regmap,
	.list_voltage = regulator_list_voltage_linear,
	.map_voltage = regulator_map_voltage_linear,
};

static struct regulator_ops anatop_core_rops = {
	.enable = anatop_regmap_enable,
	.disable = anatop_regmap_disable,
	.is_enabled = anatop_regmap_is_enabled,
	.set_voltage_sel = anatop_regmap_core_set_voltage_sel,
	.set_voltage_time_sel = anatop_regmap_set_voltage_time_sel,
	.get_voltage_sel = anatop_regmap_core_get_voltage_sel,
	.list_voltage = regulator_list_voltage_linear,
	.map_voltage = regulator_map_voltage_linear,
	.get_bypass = anatop_regmap_get_bypass,
	.set_bypass = anatop_regmap_set_bypass,
};

static int anatop_regulator_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	struct device_node *anatop_np;
	struct regulator_desc *rdesc;
	struct regulator_dev *rdev;
	struct anatop_regulator *sreg;
	struct regulator_init_data *initdata;
	struct regulator_config config = { };
	int ret = 0;
	u32 val;

	sreg = devm_kzalloc(dev, sizeof(*sreg), GFP_KERNEL);
	if (!sreg)
		return -ENOMEM;
	sreg->name = of_get_property(np, "regulator-name", NULL);
	rdesc = &sreg->rdesc;
	rdesc->name = sreg->name;
	rdesc->type = REGULATOR_VOLTAGE;
	rdesc->owner = THIS_MODULE;

	initdata = of_get_regulator_init_data(dev, np, rdesc);
	initdata->supply_regulator = "vin";
	sreg->initdata = initdata;

	anatop_np = of_get_parent(np);
	if (!anatop_np)
		return -ENODEV;
	sreg->anatop = syscon_node_to_regmap(anatop_np);
	of_node_put(anatop_np);
	if (IS_ERR(sreg->anatop))
		return PTR_ERR(sreg->anatop);

	ret = of_property_read_u32(np, "anatop-reg-offset",
				   &sreg->control_reg);
	if (ret) {
		dev_err(dev, "no anatop-reg-offset property set\n");
		return ret;
	}
	ret = of_property_read_u32(np, "anatop-vol-bit-width",
				   &sreg->vol_bit_width);
	if (ret) {
		dev_err(dev, "no anatop-vol-bit-width property set\n");
		return ret;
	}
	ret = of_property_read_u32(np, "anatop-vol-bit-shift",
				   &sreg->vol_bit_shift);
	if (ret) {
		dev_err(dev, "no anatop-vol-bit-shift property set\n");
		return ret;
	}
	ret = of_property_read_u32(np, "anatop-min-bit-val",
				   &sreg->min_bit_val);
	if (ret) {
		dev_err(dev, "no anatop-min-bit-val property set\n");
		return ret;
	}
	ret = of_property_read_u32(np, "anatop-min-voltage",
				   &sreg->min_voltage);
	if (ret) {
		dev_err(dev, "no anatop-min-voltage property set\n");
		return ret;
	}
	ret = of_property_read_u32(np, "anatop-max-voltage",
				   &sreg->max_voltage);
	if (ret) {
		dev_err(dev, "no anatop-max-voltage property set\n");
		return ret;
	}

	/* read LDO ramp up setting, only for core reg */
	of_property_read_u32(np, "anatop-delay-reg-offset",
			     &sreg->delay_reg);
	of_property_read_u32(np, "anatop-delay-bit-width",
			     &sreg->delay_bit_width);
	of_property_read_u32(np, "anatop-delay-bit-shift",
			     &sreg->delay_bit_shift);

	rdesc->n_voltages = (sreg->max_voltage - sreg->min_voltage) / 25000 + 1
			    + sreg->min_bit_val;
	rdesc->min_uV = sreg->min_voltage;
	rdesc->uV_step = 25000;
	rdesc->linear_min_sel = sreg->min_bit_val;
	rdesc->vsel_reg = sreg->control_reg;
	rdesc->vsel_mask = ((1 << sreg->vol_bit_width) - 1) <<
			   sreg->vol_bit_shift;
	rdesc->min_dropout_uV = 125000;

	config.dev = &pdev->dev;
	config.init_data = initdata;
	config.driver_data = sreg;
	config.of_node = pdev->dev.of_node;
	config.regmap = sreg->anatop;

	/* Only core regulators have the ramp up delay configuration. */
	if (sreg->control_reg && sreg->delay_bit_width) {
		rdesc->ops = &anatop_core_rops;

		ret = regmap_read(config.regmap, rdesc->vsel_reg, &val);
		if (ret) {
			dev_err(dev, "failed to read initial state\n");
			return ret;
		}

		sreg->sel = (val & rdesc->vsel_mask) >> sreg->vol_bit_shift;
		if (sreg->sel == LDO_FET_FULL_ON) {
			sreg->sel = 0;
			sreg->bypass = true;
		}

		/*
		 * In case vddpu was disabled by the bootloader, we need to set
		 * a sane default until imx6-cpufreq was probed and changes the
		 * voltage to the correct value. In this case we set 1.25V.
		 */
		if (!sreg->sel && !strcmp(sreg->name, "vddpu"))
			sreg->sel = 22;

		if (!sreg->bypass && !sreg->sel) {
			dev_err(&pdev->dev, "Failed to read a valid default voltage selector.\n");
			return -EINVAL;
		}
	} else {
		u32 enable_bit;

		rdesc->ops = &anatop_rops;

		if (!of_property_read_u32(np, "anatop-enable-bit",
					  &enable_bit)) {
			anatop_rops.enable  = regulator_enable_regmap;
			anatop_rops.disable = regulator_disable_regmap;
			anatop_rops.is_enabled = regulator_is_enabled_regmap;

			rdesc->enable_reg = sreg->control_reg;
			rdesc->enable_mask = BIT(enable_bit);
		}
	}

	/* register regulator */
	rdev = devm_regulator_register(dev, rdesc, &config);
	if (IS_ERR(rdev)) {
		dev_err(dev, "failed to register %s\n",
			rdesc->name);
		return PTR_ERR(rdev);
	}

	platform_set_drvdata(pdev, rdev);

	return 0;
}

static const struct of_device_id of_anatop_regulator_match_tbl[] = {
	{ .compatible = "fsl,anatop-regulator", },
	{ /* end */ }
};
MODULE_DEVICE_TABLE(of, of_anatop_regulator_match_tbl);

static struct platform_driver anatop_regulator_driver = {
	.driver = {
		.name	= "anatop_regulator",
		.of_match_table = of_anatop_regulator_match_tbl,
	},
	.probe	= anatop_regulator_probe,
};

static int __init anatop_regulator_init(void)
{
	return platform_driver_register(&anatop_regulator_driver);
}
postcore_initcall(anatop_regulator_init);

static void __exit anatop_regulator_exit(void)
{
	platform_driver_unregister(&anatop_regulator_driver);
}
module_exit(anatop_regulator_exit);

MODULE_AUTHOR("Nancy Chen <Nancy.Chen@freescale.com>");
MODULE_AUTHOR("Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>");
MODULE_DESCRIPTION("ANATOP Regulator driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:anatop_regulator");
Commit	Line	Data
e3e5aff7 YCLP	1	/*
	2	* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
	3	*/
	4
	5	/*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15
	16	* You should have received a copy of the GNU General Public License along
	17	* with this program; if not, write to the Free Software Foundation, Inc.,
	18	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
	19	*/
	20
	21	#include <linux/slab.h>
	22	#include <linux/device.h>
	23	#include <linux/module.h>
baa64151	24	#include <linux/mfd/syscon.h>
e3e5aff7 YCLP	25	#include <linux/err.h>
	26	#include <linux/io.h>
	27	#include <linux/platform_device.h>
	28	#include <linux/of.h>
	29	#include <linux/of_address.h>
baa64151	30	#include <linux/regmap.h>
e3e5aff7 YCLP	31	#include <linux/regulator/driver.h>
e3e5aff7 YCLP	32	#include <linux/regulator/of_regulator.h>
0d19208e	33	#include <linux/regulator/machine.h>
e3e5aff7	34
9ee417c0 AH	35	#define LDO_RAMP_UP_UNIT_IN_CYCLES 64 /* 64 cycles per step */
	36	#define LDO_RAMP_UP_FREQ_IN_MHZ 24 /* cycle based on 24M OSC */
	37
605ebd35	38	#define LDO_POWER_GATE 0x00
d38018f2	39	#define LDO_FET_FULL_ON 0x1f
605ebd35	40
e3e5aff7 YCLP	41	struct anatop_regulator {
	42	const char *name;
	43	u32 control_reg;
baa64151	44	struct regmap *anatop;
e3e5aff7 YCLP	45	int vol_bit_shift;
e3e5aff7 YCLP	46	int vol_bit_width;
9ee417c0 AH	47	u32 delay_reg;
	48	int delay_bit_shift;
	49	int delay_bit_width;
e3e5aff7 YCLP	50	int min_bit_val;
	51	int min_voltage;
	52	int max_voltage;
	53	struct regulator_desc rdesc;
	54	struct regulator_init_data *initdata;
d38018f2	55	bool bypass;
605ebd35	56	int sel;
e3e5aff7 YCLP	57	};
e3e5aff7 YCLP	58
9ee417c0 AH	59	static int anatop_regmap_set_voltage_time_sel(struct regulator_dev *reg,
	60	unsigned int old_sel,
	61	unsigned int new_sel)
	62	{
	63	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	64	u32 val;
	65	int ret = 0;
	66
	67	/* check whether need to care about LDO ramp up speed */
	68	if (anatop_reg->delay_bit_width && new_sel > old_sel) {
	69	/*
	70	* the delay for LDO ramp up time is
	71	* based on the register setting, we need
	72	* to calculate how many steps LDO need to
	73	* ramp up, and how much delay needed. (us)
	74	*/
	75	regmap_read(anatop_reg->anatop, anatop_reg->delay_reg, &val);
	76	val = (val >> anatop_reg->delay_bit_shift) &
	77	((1 << anatop_reg->delay_bit_width) - 1);
ff1ce057 SG	78	ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES <<
ff1ce057 SG	79	val) / LDO_RAMP_UP_FREQ_IN_MHZ + 1;
9ee417c0 AH	80	}
	81
	82	return ret;
	83	}
	84
605ebd35 PZ	85	static int anatop_regmap_enable(struct regulator_dev *reg)
	86	{
	87	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
d38018f2	88	int sel;
605ebd35	89
d38018f2 PZ	90	sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel;
d38018f2 PZ	91	return regulator_set_voltage_sel_regmap(reg, sel);
605ebd35 PZ	92	}
	93
	94	static int anatop_regmap_disable(struct regulator_dev *reg)
	95	{
	96	return regulator_set_voltage_sel_regmap(reg, LDO_POWER_GATE);
	97	}
	98
	99	static int anatop_regmap_is_enabled(struct regulator_dev *reg)
	100	{
	101	return regulator_get_voltage_sel_regmap(reg) != LDO_POWER_GATE;
	102	}
	103
	104	static int anatop_regmap_core_set_voltage_sel(struct regulator_dev *reg,
	105	unsigned selector)
	106	{
	107	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	108	int ret;
	109
d38018f2	110	if (anatop_reg->bypass \|\| !anatop_regmap_is_enabled(reg)) {
605ebd35 PZ	111	anatop_reg->sel = selector;
	112	return 0;
	113	}
	114
	115	ret = regulator_set_voltage_sel_regmap(reg, selector);
	116	if (!ret)
	117	anatop_reg->sel = selector;
	118	return ret;
	119	}
	120
	121	static int anatop_regmap_core_get_voltage_sel(struct regulator_dev *reg)
	122	{
	123	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	124
d38018f2	125	if (anatop_reg->bypass \|\| !anatop_regmap_is_enabled(reg))
605ebd35 PZ	126	return anatop_reg->sel;
	127
	128	return regulator_get_voltage_sel_regmap(reg);
	129	}
	130
d38018f2 PZ	131	static int anatop_regmap_get_bypass(struct regulator_dev reg, bool enable)
	132	{
	133	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	134	int sel;
	135
	136	sel = regulator_get_voltage_sel_regmap(reg);
	137	if (sel == LDO_FET_FULL_ON)
	138	WARN_ON(!anatop_reg->bypass);
	139	else if (sel != LDO_POWER_GATE)
	140	WARN_ON(anatop_reg->bypass);
	141
	142	*enable = anatop_reg->bypass;
	143	return 0;
	144	}
	145
	146	static int anatop_regmap_set_bypass(struct regulator_dev *reg, bool enable)
	147	{
	148	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	149	int sel;
	150
	151	if (enable == anatop_reg->bypass)
	152	return 0;
	153
	154	sel = enable ? LDO_FET_FULL_ON : anatop_reg->sel;
	155	anatop_reg->bypass = enable;
	156
	157	return regulator_set_voltage_sel_regmap(reg, sel);
	158	}
	159
e3e5aff7	160	static struct regulator_ops anatop_rops = {
114c5748 AL	161	.set_voltage_sel = regulator_set_voltage_sel_regmap,
114c5748 AL	162	.get_voltage_sel = regulator_get_voltage_sel_regmap,
d01c3a1e AL	163	.list_voltage = regulator_list_voltage_linear,
d01c3a1e AL	164	.map_voltage = regulator_map_voltage_linear,
e3e5aff7 YCLP	165	};
e3e5aff7 YCLP	166
605ebd35 PZ	167	static struct regulator_ops anatop_core_rops = {
	168	.enable = anatop_regmap_enable,
	169	.disable = anatop_regmap_disable,
	170	.is_enabled = anatop_regmap_is_enabled,
	171	.set_voltage_sel = anatop_regmap_core_set_voltage_sel,
	172	.set_voltage_time_sel = anatop_regmap_set_voltage_time_sel,
	173	.get_voltage_sel = anatop_regmap_core_get_voltage_sel,
	174	.list_voltage = regulator_list_voltage_linear,
	175	.map_voltage = regulator_map_voltage_linear,
d38018f2 PZ	176	.get_bypass = anatop_regmap_get_bypass,
d38018f2 PZ	177	.set_bypass = anatop_regmap_set_bypass,
605ebd35 PZ	178	};
605ebd35 PZ	179
a5023574	180	static int anatop_regulator_probe(struct platform_device *pdev)
e3e5aff7 YCLP	181	{
	182	struct device *dev = &pdev->dev;
	183	struct device_node *np = dev->of_node;
baa64151	184	struct device_node *anatop_np;
e3e5aff7 YCLP	185	struct regulator_desc *rdesc;
	186	struct regulator_dev *rdev;
	187	struct anatop_regulator *sreg;
	188	struct regulator_init_data *initdata;
d914d81b	189	struct regulator_config config = { };
e3e5aff7	190	int ret = 0;
605ebd35	191	u32 val;
e3e5aff7	192
e3e5aff7 YCLP	193	sreg = devm_kzalloc(dev, sizeof(*sreg), GFP_KERNEL);
	194	if (!sreg)
	195	return -ENOMEM;
f2b269b8	196	sreg->name = of_get_property(np, "regulator-name", NULL);
e3e5aff7	197	rdesc = &sreg->rdesc;
e3e5aff7	198	rdesc->name = sreg->name;
e3e5aff7 YCLP	199	rdesc->type = REGULATOR_VOLTAGE;
e3e5aff7 YCLP	200	rdesc->owner = THIS_MODULE;
baa64151	201
072e78b1	202	initdata = of_get_regulator_init_data(dev, np, rdesc);
0d19208e	203	initdata->supply_regulator = "vin";
072e78b1 JMC	204	sreg->initdata = initdata;
072e78b1 JMC	205
baa64151 DA	206	anatop_np = of_get_parent(np);
	207	if (!anatop_np)
	208	return -ENODEV;
	209	sreg->anatop = syscon_node_to_regmap(anatop_np);
	210	of_node_put(anatop_np);
	211	if (IS_ERR(sreg->anatop))
	212	return PTR_ERR(sreg->anatop);
	213
2f2cc27f YCLP	214	ret = of_property_read_u32(np, "anatop-reg-offset",
2f2cc27f YCLP	215	&sreg->control_reg);
e3e5aff7	216	if (ret) {
2f2cc27f	217	dev_err(dev, "no anatop-reg-offset property set\n");
f2b269b8	218	return ret;
e3e5aff7 YCLP	219	}
	220	ret = of_property_read_u32(np, "anatop-vol-bit-width",
	221	&sreg->vol_bit_width);
	222	if (ret) {
	223	dev_err(dev, "no anatop-vol-bit-width property set\n");
f2b269b8	224	return ret;
e3e5aff7 YCLP	225	}
	226	ret = of_property_read_u32(np, "anatop-vol-bit-shift",
	227	&sreg->vol_bit_shift);
	228	if (ret) {
	229	dev_err(dev, "no anatop-vol-bit-shift property set\n");
f2b269b8	230	return ret;
e3e5aff7 YCLP	231	}
	232	ret = of_property_read_u32(np, "anatop-min-bit-val",
	233	&sreg->min_bit_val);
	234	if (ret) {
	235	dev_err(dev, "no anatop-min-bit-val property set\n");
f2b269b8	236	return ret;
e3e5aff7 YCLP	237	}
	238	ret = of_property_read_u32(np, "anatop-min-voltage",
	239	&sreg->min_voltage);
	240	if (ret) {
	241	dev_err(dev, "no anatop-min-voltage property set\n");
f2b269b8	242	return ret;
e3e5aff7 YCLP	243	}
	244	ret = of_property_read_u32(np, "anatop-max-voltage",
	245	&sreg->max_voltage);
	246	if (ret) {
	247	dev_err(dev, "no anatop-max-voltage property set\n");
f2b269b8	248	return ret;
e3e5aff7 YCLP	249	}
e3e5aff7 YCLP	250
9ee417c0 AH	251	/* read LDO ramp up setting, only for core reg */
	252	of_property_read_u32(np, "anatop-delay-reg-offset",
	253	&sreg->delay_reg);
	254	of_property_read_u32(np, "anatop-delay-bit-width",
	255	&sreg->delay_bit_width);
	256	of_property_read_u32(np, "anatop-delay-bit-shift",
	257	&sreg->delay_bit_shift);
	258
985884db AL	259	rdesc->n_voltages = (sreg->max_voltage - sreg->min_voltage) / 25000 + 1
985884db AL	260	+ sreg->min_bit_val;
0713e6ab AL	261	rdesc->min_uV = sreg->min_voltage;
0713e6ab AL	262	rdesc->uV_step = 25000;
985884db	263	rdesc->linear_min_sel = sreg->min_bit_val;
e1b0144f AL	264	rdesc->vsel_reg = sreg->control_reg;
	265	rdesc->vsel_mask = ((1 << sreg->vol_bit_width) - 1) <<
	266	sreg->vol_bit_shift;
0d19208e	267	rdesc->min_dropout_uV = 125000;
e3e5aff7	268
d914d81b AL	269	config.dev = &pdev->dev;
	270	config.init_data = initdata;
	271	config.driver_data = sreg;
	272	config.of_node = pdev->dev.of_node;
e1b0144f	273	config.regmap = sreg->anatop;
d914d81b	274
605ebd35 PZ	275	/* Only core regulators have the ramp up delay configuration. */
	276	if (sreg->control_reg && sreg->delay_bit_width) {
	277	rdesc->ops = &anatop_core_rops;
	278
	279	ret = regmap_read(config.regmap, rdesc->vsel_reg, &val);
	280	if (ret) {
	281	dev_err(dev, "failed to read initial state\n");
	282	return ret;
	283	}
	284
	285	sreg->sel = (val & rdesc->vsel_mask) >> sreg->vol_bit_shift;
d38018f2 PZ	286	if (sreg->sel == LDO_FET_FULL_ON) {
	287	sreg->sel = 0;
	288	sreg->bypass = true;
	289	}
fe08be3e MP	290
	291	/*
	292	* In case vddpu was disabled by the bootloader, we need to set
	293	* a sane default until imx6-cpufreq was probed and changes the
	294	* voltage to the correct value. In this case we set 1.25V.
	295	*/
	296	if (!sreg->sel && !strcmp(sreg->name, "vddpu"))
	297	sreg->sel = 22;
da0607c8	298
8a092e68	299	if (!sreg->bypass && !sreg->sel) {
da0607c8 MP	300	dev_err(&pdev->dev, "Failed to read a valid default voltage selector.\n");
	301	return -EINVAL;
	302	}
605ebd35	303	} else {
ca7734ad AS	304	u32 enable_bit;
ca7734ad AS	305
605ebd35	306	rdesc->ops = &anatop_rops;
ca7734ad AS	307
	308	if (!of_property_read_u32(np, "anatop-enable-bit",
	309	&enable_bit)) {
	310	anatop_rops.enable = regulator_enable_regmap;
	311	anatop_rops.disable = regulator_disable_regmap;
	312	anatop_rops.is_enabled = regulator_is_enabled_regmap;
	313
	314	rdesc->enable_reg = sreg->control_reg;
	315	rdesc->enable_mask = BIT(enable_bit);
	316	}
605ebd35 PZ	317	}
605ebd35 PZ	318
e3e5aff7	319	/* register regulator */
be1221e8	320	rdev = devm_regulator_register(dev, rdesc, &config);
e3e5aff7 YCLP	321	if (IS_ERR(rdev)) {
	322	dev_err(dev, "failed to register %s\n",
	323	rdesc->name);
f2b269b8	324	return PTR_ERR(rdev);
e3e5aff7 YCLP	325	}
	326
	327	platform_set_drvdata(pdev, rdev);
	328
e3e5aff7 YCLP	329	return 0;
	330	}
	331
a799baab	332	static const struct of_device_id of_anatop_regulator_match_tbl[] = {
e3e5aff7 YCLP	333	{ .compatible = "fsl,anatop-regulator", },
	334	{ /* end */ }
	335	};
d702ffd4	336	MODULE_DEVICE_TABLE(of, of_anatop_regulator_match_tbl);
e3e5aff7	337
c0d78c23	338	static struct platform_driver anatop_regulator_driver = {
e3e5aff7 YCLP	339	.driver = {
e3e5aff7 YCLP	340	.name = "anatop_regulator",
e3e5aff7 YCLP	341	.of_match_table = of_anatop_regulator_match_tbl,
	342	},
	343	.probe = anatop_regulator_probe,
e3e5aff7 YCLP	344	};
	345
	346	static int __init anatop_regulator_init(void)
	347	{
c0d78c23	348	return platform_driver_register(&anatop_regulator_driver);
e3e5aff7 YCLP	349	}
	350	postcore_initcall(anatop_regulator_init);
	351
	352	static void __exit anatop_regulator_exit(void)
	353	{
c0d78c23	354	platform_driver_unregister(&anatop_regulator_driver);
e3e5aff7 YCLP	355	}
	356	module_exit(anatop_regulator_exit);
	357
34f75685 JH	358	MODULE_AUTHOR("Nancy Chen <Nancy.Chen@freescale.com>");
34f75685 JH	359	MODULE_AUTHOR("Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>");
e3e5aff7 YCLP	360	MODULE_DESCRIPTION("ANATOP Regulator driver");
e3e5aff7 YCLP	361	MODULE_LICENSE("GPL v2");
89705b9e	362	MODULE_ALIAS("platform:anatop_regulator");