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UBUNTU: [Config] Set CONFIG_PWM_PCA9685=m for amd64 and i386
[mirror_ubuntu-zesty-kernel.git] / drivers / regulator / axp20x-regulator.c
CommitLineData
dfe7a1b0
CC		 1/*
2 * AXP20x regulators driver.
3 *
4 * Copyright (C) 2013 Carlo Caione <carlo@caione.org>
5 *
6 * This file is subject to the terms and conditions of the GNU General
7 * Public License. See the file "COPYING" in the main directory of this
8 * archive for more details.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/err.h>
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/platform_device.h>
22#include <linux/regmap.h>
23#include <linux/mfd/axp20x.h>
24#include <linux/regulator/driver.h>
25#include <linux/regulator/of_regulator.h>
26
27#define AXP20X_IO_ENABLED 0x03
28#define AXP20X_IO_DISABLED 0x07
29
3cb99e2e
CYT		 30#define AXP22X_IO_ENABLED 0x03
31#define AXP22X_IO_DISABLED 0x04
1b82b4e4 32
dfe7a1b0
CC		 33#define AXP20X_WORKMODE_DCDC2_MASK BIT(2)
34#define AXP20X_WORKMODE_DCDC3_MASK BIT(1)
1b82b4e4 35#define AXP22X_WORKMODE_DCDCX_MASK(x) BIT(x)
dfe7a1b0
CC		 36
37#define AXP20X_FREQ_DCDC_MASK 0x0f
38
636e2a39
HG		 39#define AXP22X_MISC_N_VBUSEN_FUNC BIT(4)
40
866bd951
BB		 41#define AXP_DESC_IO(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
42 _vmask, _ereg, _emask, _enable_val, _disable_val) \
43 [_family##_##_id] = { \
e0bbb38c 44 .name = (_match), \
dfe7a1b0 45 .supply_name = (_supply), \
880fe82d
CYT		 46 .of_match = of_match_ptr(_match), \
47 .regulators_node = of_match_ptr("regulators"), \
dfe7a1b0 48 .type = REGULATOR_VOLTAGE, \
866bd951 49 .id = _family##_##_id, \
dfe7a1b0
CC		 50 .n_voltages = (((_max) - (_min)) / (_step) + 1), \
51 .owner = THIS_MODULE, \
52 .min_uV = (_min) * 1000, \
53 .uV_step = (_step) * 1000, \
54 .vsel_reg = (_vreg), \
55 .vsel_mask = (_vmask), \
56 .enable_reg = (_ereg), \
57 .enable_mask = (_emask), \
58 .enable_val = (_enable_val), \
59 .disable_val = (_disable_val), \
60 .ops = &axp20x_ops, \
61 }
62
866bd951
BB		 63#define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
64 _vmask, _ereg, _emask) \
65 [_family##_##_id] = { \
e0bbb38c 66 .name = (_match), \
dfe7a1b0 67 .supply_name = (_supply), \
880fe82d
CYT		 68 .of_match = of_match_ptr(_match), \
69 .regulators_node = of_match_ptr("regulators"), \
dfe7a1b0 70 .type = REGULATOR_VOLTAGE, \
866bd951 71 .id = _family##_##_id, \
dfe7a1b0
CC		 72 .n_voltages = (((_max) - (_min)) / (_step) + 1), \
73 .owner = THIS_MODULE, \
74 .min_uV = (_min) * 1000, \
75 .uV_step = (_step) * 1000, \
76 .vsel_reg = (_vreg), \
77 .vsel_mask = (_vmask), \
78 .enable_reg = (_ereg), \
79 .enable_mask = (_emask), \
80 .ops = &axp20x_ops, \
81 }
82
94c39041 83#define AXP_DESC_SW(_family, _id, _match, _supply, _ereg, _emask) \
1b82b4e4 84 [_family##_##_id] = { \
e0bbb38c 85 .name = (_match), \
1b82b4e4
BB		 86 .supply_name = (_supply), \
87 .of_match = of_match_ptr(_match), \
88 .regulators_node = of_match_ptr("regulators"), \
89 .type = REGULATOR_VOLTAGE, \
90 .id = _family##_##_id, \
1b82b4e4 91 .owner = THIS_MODULE, \
1b82b4e4
BB		 92 .enable_reg = (_ereg), \
93 .enable_mask = (_emask), \
94 .ops = &axp20x_ops_sw, \
95 }
96
866bd951
BB		 97#define AXP_DESC_FIXED(_family, _id, _match, _supply, _volt) \
98 [_family##_##_id] = { \
e0bbb38c 99 .name = (_match), \
dfe7a1b0 100 .supply_name = (_supply), \
880fe82d
CYT		 101 .of_match = of_match_ptr(_match), \
102 .regulators_node = of_match_ptr("regulators"), \
dfe7a1b0 103 .type = REGULATOR_VOLTAGE, \
866bd951 104 .id = _family##_##_id, \
dfe7a1b0
CC		 105 .n_voltages = 1, \
106 .owner = THIS_MODULE, \
107 .min_uV = (_volt) * 1000, \
108 .ops = &axp20x_ops_fixed \
109 }
110
13d57e64
CYT		 111#define AXP_DESC_RANGES(_family, _id, _match, _supply, _ranges, _n_voltages, \
112 _vreg, _vmask, _ereg, _emask) \
866bd951 113 [_family##_##_id] = { \
e0bbb38c 114 .name = (_match), \
dfe7a1b0 115 .supply_name = (_supply), \
880fe82d
CYT		 116 .of_match = of_match_ptr(_match), \
117 .regulators_node = of_match_ptr("regulators"), \
dfe7a1b0 118 .type = REGULATOR_VOLTAGE, \
866bd951 119 .id = _family##_##_id, \
13d57e64 120 .n_voltages = (_n_voltages), \
dfe7a1b0
CC		 121 .owner = THIS_MODULE, \
122 .vsel_reg = (_vreg), \
123 .vsel_mask = (_vmask), \
124 .enable_reg = (_ereg), \
125 .enable_mask = (_emask), \
13d57e64
CYT		 126 .linear_ranges = (_ranges), \
127 .n_linear_ranges = ARRAY_SIZE(_ranges), \
128 .ops = &axp20x_ops_range, \
dfe7a1b0
CC		 129 }
130
dfe7a1b0
CC		 131static struct regulator_ops axp20x_ops_fixed = {
132 .list_voltage = regulator_list_voltage_linear,
133};
134
13d57e64 135static struct regulator_ops axp20x_ops_range = {
dfe7a1b0
CC		 136 .set_voltage_sel = regulator_set_voltage_sel_regmap,
137 .get_voltage_sel = regulator_get_voltage_sel_regmap,
13d57e64 138 .list_voltage = regulator_list_voltage_linear_range,
dfe7a1b0
CC		 139 .enable = regulator_enable_regmap,
140 .disable = regulator_disable_regmap,
141 .is_enabled = regulator_is_enabled_regmap,
142};
143
144static struct regulator_ops axp20x_ops = {
145 .set_voltage_sel = regulator_set_voltage_sel_regmap,
146 .get_voltage_sel = regulator_get_voltage_sel_regmap,
147 .list_voltage = regulator_list_voltage_linear,
148 .enable = regulator_enable_regmap,
149 .disable = regulator_disable_regmap,
150 .is_enabled = regulator_is_enabled_regmap,
151};
152
1b82b4e4 153static struct regulator_ops axp20x_ops_sw = {
1b82b4e4
BB		 154 .enable = regulator_enable_regmap,
155 .disable = regulator_disable_regmap,
156 .is_enabled = regulator_is_enabled_regmap,
157};
158
13d57e64
CYT		 159static const struct regulator_linear_range axp20x_ldo4_ranges[] = {
160 REGULATOR_LINEAR_RANGE(1250000, 0x0, 0x0, 0),
161 REGULATOR_LINEAR_RANGE(1300000, 0x1, 0x8, 100000),
8d4d5c3a
MR		 162 REGULATOR_LINEAR_RANGE(2500000, 0x9, 0x9, 0),
163 REGULATOR_LINEAR_RANGE(2700000, 0xa, 0xb, 100000),
164 REGULATOR_LINEAR_RANGE(3000000, 0xc, 0xf, 100000),
13d57e64
CYT		 165};
166
dfe7a1b0 167static const struct regulator_desc axp20x_regulators[] = {
866bd951
BB		 168 AXP_DESC(AXP20X, DCDC2, "dcdc2", "vin2", 700, 2275, 25,
169 AXP20X_DCDC2_V_OUT, 0x3f, AXP20X_PWR_OUT_CTRL, 0x10),
170 AXP_DESC(AXP20X, DCDC3, "dcdc3", "vin3", 700, 3500, 25,
171 AXP20X_DCDC3_V_OUT, 0x7f, AXP20X_PWR_OUT_CTRL, 0x02),
172 AXP_DESC_FIXED(AXP20X, LDO1, "ldo1", "acin", 1300),
173 AXP_DESC(AXP20X, LDO2, "ldo2", "ldo24in", 1800, 3300, 100,
174 AXP20X_LDO24_V_OUT, 0xf0, AXP20X_PWR_OUT_CTRL, 0x04),
175 AXP_DESC(AXP20X, LDO3, "ldo3", "ldo3in", 700, 3500, 25,
176 AXP20X_LDO3_V_OUT, 0x7f, AXP20X_PWR_OUT_CTRL, 0x40),
13d57e64
CYT		 177 AXP_DESC_RANGES(AXP20X, LDO4, "ldo4", "ldo24in", axp20x_ldo4_ranges,
178 16, AXP20X_LDO24_V_OUT, 0x0f, AXP20X_PWR_OUT_CTRL,
179 0x08),
866bd951
BB		 180 AXP_DESC_IO(AXP20X, LDO5, "ldo5", "ldo5in", 1800, 3300, 100,
181 AXP20X_LDO5_V_OUT, 0xf0, AXP20X_GPIO0_CTRL, 0x07,
182 AXP20X_IO_ENABLED, AXP20X_IO_DISABLED),
dfe7a1b0
CC		 183};
184
1b82b4e4
BB		 185static const struct regulator_desc axp22x_regulators[] = {
186 AXP_DESC(AXP22X, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
187 AXP22X_DCDC1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(1)),
188 AXP_DESC(AXP22X, DCDC2, "dcdc2", "vin2", 600, 1540, 20,
189 AXP22X_DCDC2_V_OUT, 0x3f, AXP22X_PWR_OUT_CTRL1, BIT(2)),
190 AXP_DESC(AXP22X, DCDC3, "dcdc3", "vin3", 600, 1860, 20,
191 AXP22X_DCDC3_V_OUT, 0x3f, AXP22X_PWR_OUT_CTRL1, BIT(3)),
192 AXP_DESC(AXP22X, DCDC4, "dcdc4", "vin4", 600, 1540, 20,
6b3600b4 193 AXP22X_DCDC4_V_OUT, 0x3f, AXP22X_PWR_OUT_CTRL1, BIT(4)),
1b82b4e4 194 AXP_DESC(AXP22X, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,
6b3600b4 195 AXP22X_DCDC5_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(5)),
1b82b4e4 196 /* secondary switchable output of DCDC1 */
94c39041
CYT		 197 AXP_DESC_SW(AXP22X, DC1SW, "dc1sw", NULL, AXP22X_PWR_OUT_CTRL2,
198 BIT(7)),
1b82b4e4 199 /* LDO regulator internally chained to DCDC5 */
7118f19c 200 AXP_DESC(AXP22X, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,
1b82b4e4
BB		 201 AXP22X_DC5LDO_V_OUT, 0x7, AXP22X_PWR_OUT_CTRL1, BIT(0)),
202 AXP_DESC(AXP22X, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
203 AXP22X_ALDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(6)),
204 AXP_DESC(AXP22X, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
205 AXP22X_ALDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(7)),
206 AXP_DESC(AXP22X, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
207 AXP22X_ALDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL3, BIT(7)),
208 AXP_DESC(AXP22X, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
209 AXP22X_DLDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(3)),
210 AXP_DESC(AXP22X, DLDO2, "dldo2", "dldoin", 700, 3300, 100,
211 AXP22X_DLDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(4)),
212 AXP_DESC(AXP22X, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
213 AXP22X_DLDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(5)),
214 AXP_DESC(AXP22X, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
215 AXP22X_DLDO4_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(6)),
216 AXP_DESC(AXP22X, ELDO1, "eldo1", "eldoin", 700, 3300, 100,
217 AXP22X_ELDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(0)),
218 AXP_DESC(AXP22X, ELDO2, "eldo2", "eldoin", 700, 3300, 100,
219 AXP22X_ELDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(1)),
220 AXP_DESC(AXP22X, ELDO3, "eldo3", "eldoin", 700, 3300, 100,
221 AXP22X_ELDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(2)),
f40d4896
HG		 222 /* Note the datasheet only guarantees reliable operation up to
223 * 3.3V, this needs to be enforced via dts provided constraints */
224 AXP_DESC_IO(AXP22X, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100,
1b82b4e4
BB		 225 AXP22X_LDO_IO0_V_OUT, 0x1f, AXP20X_GPIO0_CTRL, 0x07,
226 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
f40d4896
HG		 227 /* Note the datasheet only guarantees reliable operation up to
228 * 3.3V, this needs to be enforced via dts provided constraints */
229 AXP_DESC_IO(AXP22X, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100,
1b82b4e4
BB		 230 AXP22X_LDO_IO1_V_OUT, 0x1f, AXP20X_GPIO1_CTRL, 0x07,
231 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
232 AXP_DESC_FIXED(AXP22X, RTC_LDO, "rtc_ldo", "ips", 3000),
233};
234
636e2a39
HG		 235static const struct regulator_desc axp22x_drivevbus_regulator = {
236 .name = "drivevbus",
237 .supply_name = "drivevbus",
238 .of_match = of_match_ptr("drivevbus"),
239 .regulators_node = of_match_ptr("regulators"),
240 .type = REGULATOR_VOLTAGE,
241 .owner = THIS_MODULE,
242 .enable_reg = AXP20X_VBUS_IPSOUT_MGMT,
243 .enable_mask = BIT(2),
244 .ops = &axp20x_ops_sw,
245};
246
2ca342d3
CYT		 247static const struct regulator_linear_range axp806_dcdca_ranges[] = {
248 REGULATOR_LINEAR_RANGE(600000, 0x0, 0x32, 10000),
249 REGULATOR_LINEAR_RANGE(1120000, 0x33, 0x47, 20000),
a51f9f46
CYT		 250};
251
2ca342d3
CYT		 252static const struct regulator_linear_range axp806_dcdcd_ranges[] = {
253 REGULATOR_LINEAR_RANGE(600000, 0x0, 0x2d, 20000),
254 REGULATOR_LINEAR_RANGE(1600000, 0x2e, 0x3f, 100000),
255};
256
257static const struct regulator_linear_range axp806_cldo2_ranges[] = {
a51f9f46
CYT		 258 REGULATOR_LINEAR_RANGE(700000, 0x0, 0x1a, 100000),
259 REGULATOR_LINEAR_RANGE(3400000, 0x1b, 0x1f, 200000),
260};
261
2ca342d3
CYT		 262static const struct regulator_desc axp806_regulators[] = {
263 AXP_DESC_RANGES(AXP806, DCDCA, "dcdca", "vina", axp806_dcdca_ranges,
264 72, AXP806_DCDCA_V_CTRL, 0x7f, AXP806_PWR_OUT_CTRL1,
265 BIT(0)),
266 AXP_DESC(AXP806, DCDCB, "dcdcb", "vinb", 1000, 2550, 50,
267 AXP806_DCDCB_V_CTRL, 0x1f, AXP806_PWR_OUT_CTRL1, BIT(1)),
268 AXP_DESC_RANGES(AXP806, DCDCC, "dcdcc", "vinc", axp806_dcdca_ranges,
269 72, AXP806_DCDCC_V_CTRL, 0x7f, AXP806_PWR_OUT_CTRL1,
270 BIT(2)),
271 AXP_DESC_RANGES(AXP806, DCDCD, "dcdcd", "vind", axp806_dcdcd_ranges,
272 64, AXP806_DCDCD_V_CTRL, 0x3f, AXP806_PWR_OUT_CTRL1,
273 BIT(3)),
274 AXP_DESC(AXP806, DCDCE, "dcdce", "vine", 1100, 3400, 100,
d0e287a4 275 AXP806_DCDCE_V_CTRL, 0x1f, AXP806_PWR_OUT_CTRL1, BIT(4)),
2ca342d3
CYT		 276 AXP_DESC(AXP806, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
277 AXP806_ALDO1_V_CTRL, 0x1f, AXP806_PWR_OUT_CTRL1, BIT(5)),
278 AXP_DESC(AXP806, ALDO2, "aldo2", "aldoin", 700, 3400, 100,
279 AXP806_ALDO2_V_CTRL, 0x1f, AXP806_PWR_OUT_CTRL1, BIT(6)),
280 AXP_DESC(AXP806, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
281 AXP806_ALDO3_V_CTRL, 0x1f, AXP806_PWR_OUT_CTRL1, BIT(7)),
282 AXP_DESC(AXP806, BLDO1, "bldo1", "bldoin", 700, 1900, 100,
283 AXP806_BLDO1_V_CTRL, 0x0f, AXP806_PWR_OUT_CTRL2, BIT(0)),
284 AXP_DESC(AXP806, BLDO2, "bldo2", "bldoin", 700, 1900, 100,
285 AXP806_BLDO2_V_CTRL, 0x0f, AXP806_PWR_OUT_CTRL2, BIT(1)),
286 AXP_DESC(AXP806, BLDO3, "bldo3", "bldoin", 700, 1900, 100,
287 AXP806_BLDO3_V_CTRL, 0x0f, AXP806_PWR_OUT_CTRL2, BIT(2)),
288 AXP_DESC(AXP806, BLDO4, "bldo4", "bldoin", 700, 1900, 100,
289 AXP806_BLDO4_V_CTRL, 0x0f, AXP806_PWR_OUT_CTRL2, BIT(3)),
290 AXP_DESC(AXP806, CLDO1, "cldo1", "cldoin", 700, 3300, 100,
291 AXP806_CLDO1_V_CTRL, 0x1f, AXP806_PWR_OUT_CTRL2, BIT(4)),
292 AXP_DESC_RANGES(AXP806, CLDO2, "cldo2", "cldoin", axp806_cldo2_ranges,
293 32, AXP806_CLDO2_V_CTRL, 0x1f, AXP806_PWR_OUT_CTRL2,
294 BIT(5)),
295 AXP_DESC(AXP806, CLDO3, "cldo3", "cldoin", 700, 3300, 100,
296 AXP806_CLDO3_V_CTRL, 0x1f, AXP806_PWR_OUT_CTRL2, BIT(6)),
297 AXP_DESC_SW(AXP806, SW, "sw", "swin", AXP806_PWR_OUT_CTRL2, BIT(7)),
298};
299
300static const struct regulator_linear_range axp809_dcdc4_ranges[] = {
301 REGULATOR_LINEAR_RANGE(600000, 0x0, 0x2f, 20000),
302 REGULATOR_LINEAR_RANGE(1800000, 0x30, 0x38, 100000),
303};
304
a51f9f46
CYT		 305static const struct regulator_desc axp809_regulators[] = {
306 AXP_DESC(AXP809, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
307 AXP22X_DCDC1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(1)),
308 AXP_DESC(AXP809, DCDC2, "dcdc2", "vin2", 600, 1540, 20,
309 AXP22X_DCDC2_V_OUT, 0x3f, AXP22X_PWR_OUT_CTRL1, BIT(2)),
310 AXP_DESC(AXP809, DCDC3, "dcdc3", "vin3", 600, 1860, 20,
311 AXP22X_DCDC3_V_OUT, 0x3f, AXP22X_PWR_OUT_CTRL1, BIT(3)),
312 AXP_DESC_RANGES(AXP809, DCDC4, "dcdc4", "vin4", axp809_dcdc4_ranges,
313 57, AXP22X_DCDC4_V_OUT, 0x3f, AXP22X_PWR_OUT_CTRL1,
314 BIT(4)),
315 AXP_DESC(AXP809, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,
316 AXP22X_DCDC5_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(5)),
317 /* secondary switchable output of DCDC1 */
318 AXP_DESC_SW(AXP809, DC1SW, "dc1sw", NULL, AXP22X_PWR_OUT_CTRL2,
319 BIT(7)),
320 /* LDO regulator internally chained to DCDC5 */
321 AXP_DESC(AXP809, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,
322 AXP22X_DC5LDO_V_OUT, 0x7, AXP22X_PWR_OUT_CTRL1, BIT(0)),
323 AXP_DESC(AXP809, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
324 AXP22X_ALDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(6)),
325 AXP_DESC(AXP809, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
326 AXP22X_ALDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(7)),
327 AXP_DESC(AXP809, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
328 AXP22X_ALDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(5)),
2ca342d3 329 AXP_DESC_RANGES(AXP809, DLDO1, "dldo1", "dldoin", axp806_cldo2_ranges,
a51f9f46
CYT		 330 32, AXP22X_DLDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2,
331 BIT(3)),
332 AXP_DESC(AXP809, DLDO2, "dldo2", "dldoin", 700, 3300, 100,
333 AXP22X_DLDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(4)),
334 AXP_DESC(AXP809, ELDO1, "eldo1", "eldoin", 700, 3300, 100,
335 AXP22X_ELDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(0)),
336 AXP_DESC(AXP809, ELDO2, "eldo2", "eldoin", 700, 3300, 100,
337 AXP22X_ELDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(1)),
338 AXP_DESC(AXP809, ELDO3, "eldo3", "eldoin", 700, 3300, 100,
339 AXP22X_ELDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(2)),
618c8089
CYT		 340 /*
341 * Note the datasheet only guarantees reliable operation up to
342 * 3.3V, this needs to be enforced via dts provided constraints
343 */
344 AXP_DESC_IO(AXP809, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100,
a51f9f46
CYT		 345 AXP22X_LDO_IO0_V_OUT, 0x1f, AXP20X_GPIO0_CTRL, 0x07,
346 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
618c8089
CYT		 347 /*
348 * Note the datasheet only guarantees reliable operation up to
349 * 3.3V, this needs to be enforced via dts provided constraints
350 */
351 AXP_DESC_IO(AXP809, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100,
a51f9f46
CYT		 352 AXP22X_LDO_IO1_V_OUT, 0x1f, AXP20X_GPIO1_CTRL, 0x07,
353 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
354 AXP_DESC_FIXED(AXP809, RTC_LDO, "rtc_ldo", "ips", 1800),
355 AXP_DESC_SW(AXP809, SW, "sw", "swin", AXP22X_PWR_OUT_CTRL2, BIT(6)),
356};
357
dfe7a1b0
CC		 358static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq)
359{
360 struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
2ca342d3 361 unsigned int reg = AXP20X_DCDC_FREQ;
866bd951
BB		 362 u32 min, max, def, step;
363
364 switch (axp20x->variant) {
365 case AXP202_ID:
366 case AXP209_ID:
367 min = 750;
368 max = 1875;
369 def = 1500;
370 step = 75;
371 break;
2ca342d3
CYT		 372 case AXP806_ID:
373 /*
374 * AXP806 DCDC work frequency setting has the same range and
375 * step as AXP22X, but at a different register.
376 * Fall through to the check below.
377 * (See include/linux/mfd/axp20x.h)
378 */
379 reg = AXP806_DCDC_FREQ_CTRL;
1b82b4e4 380 case AXP221_ID:
04e0981c 381 case AXP223_ID:
a51f9f46 382 case AXP809_ID:
1b82b4e4
BB		 383 min = 1800;
384 max = 4050;
385 def = 3000;
386 step = 150;
387 break;
866bd951
BB		 388 default:
389 dev_err(&pdev->dev,
390 "Setting DCDC frequency for unsupported AXP variant\n");
391 return -EINVAL;
392 }
393
394 if (dcdcfreq == 0)
395 dcdcfreq = def;
dfe7a1b0 396
866bd951
BB		 397 if (dcdcfreq < min) {
398 dcdcfreq = min;
399 dev_warn(&pdev->dev, "DCDC frequency too low. Set to %ukHz\n",
400 min);
dfe7a1b0
CC		 401 }
402
866bd951
BB		 403 if (dcdcfreq > max) {
404 dcdcfreq = max;
405 dev_warn(&pdev->dev, "DCDC frequency too high. Set to %ukHz\n",
406 max);
dfe7a1b0
CC		 407 }
408
866bd951 409 dcdcfreq = (dcdcfreq - min) / step;
dfe7a1b0 410
2ca342d3 411 return regmap_update_bits(axp20x->regmap, reg,
dfe7a1b0
CC		 412 AXP20X_FREQ_DCDC_MASK, dcdcfreq);
413}
414
415static int axp20x_regulator_parse_dt(struct platform_device *pdev)
416{
417 struct device_node *np, *regulators;
418 int ret;
866bd951 419 u32 dcdcfreq = 0;
dfe7a1b0
CC		 420
421 np = of_node_get(pdev->dev.parent->of_node);
422 if (!np)
423 return 0;
424
a6016c52 425 regulators = of_get_child_by_name(np, "regulators");
dfe7a1b0
CC		 426 if (!regulators) {
427 dev_warn(&pdev->dev, "regulators node not found\n");
428 } else {
dfe7a1b0
CC		 429 of_property_read_u32(regulators, "x-powers,dcdc-freq", &dcdcfreq);
430 ret = axp20x_set_dcdc_freq(pdev, dcdcfreq);
431 if (ret < 0) {
432 dev_err(&pdev->dev, "Error setting dcdc frequency: %d\n", ret);
433 return ret;
434 }
435
436 of_node_put(regulators);
437 }
438
439 return 0;
440}
441
442static int axp20x_set_dcdc_workmode(struct regulator_dev *rdev, int id, u32 workmode)
443{
866bd951 444 struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
2ca342d3 445 unsigned int reg = AXP20X_DCDC_MODE;
866bd951 446 unsigned int mask;
dfe7a1b0 447
866bd951
BB		 448 switch (axp20x->variant) {
449 case AXP202_ID:
450 case AXP209_ID:
451 if ((id != AXP20X_DCDC2) && (id != AXP20X_DCDC3))
452 return -EINVAL;
453
454 mask = AXP20X_WORKMODE_DCDC2_MASK;
455 if (id == AXP20X_DCDC3)
456 mask = AXP20X_WORKMODE_DCDC3_MASK;
dfe7a1b0 457
866bd951
BB		 458 workmode <<= ffs(mask) - 1;
459 break;
dfe7a1b0 460
2ca342d3
CYT		 461 case AXP806_ID:
462 reg = AXP806_DCDC_MODE_CTRL2;
463 /*
464 * AXP806 DCDC regulator IDs have the same range as AXP22X.
465 * Fall through to the check below.
466 * (See include/linux/mfd/axp20x.h)
467 */
1b82b4e4 468 case AXP221_ID:
04e0981c 469 case AXP223_ID:
a51f9f46 470 case AXP809_ID:
1b82b4e4
BB		 471 if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5)
472 return -EINVAL;
473
474 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP22X_DCDC1);
475 workmode <<= id - AXP22X_DCDC1;
476 break;
477
866bd951
BB		 478 default:
479 /* should not happen */
480 WARN_ON(1);
481 return -EINVAL;
482 }
dfe7a1b0 483
2ca342d3
CYT		 484 return regmap_update_bits(rdev->regmap, reg, mask, workmode);
485}
486
487/*
488 * This function checks whether a regulator is part of a poly-phase
489 * output setup based on the registers settings. Returns true if it is.
490 */
491static bool axp20x_is_polyphase_slave(struct axp20x_dev *axp20x, int id)
492{
493 u32 reg = 0;
494
495 /* Only AXP806 has poly-phase outputs */
496 if (axp20x->variant != AXP806_ID)
497 return false;
498
499 regmap_read(axp20x->regmap, AXP806_DCDC_MODE_CTRL2, &reg);
500
501 switch (id) {
502 case AXP806_DCDCB:
503 return (((reg & GENMASK(7, 6)) == BIT(6)) ||
504 ((reg & GENMASK(7, 6)) == BIT(7)));
505 case AXP806_DCDCC:
506 return ((reg & GENMASK(7, 6)) == BIT(7));
507 case AXP806_DCDCE:
508 return !!(reg & BIT(5));
509 }
510
511 return false;
dfe7a1b0
CC		 512}
513
514static int axp20x_regulator_probe(struct platform_device *pdev)
515{
516 struct regulator_dev *rdev;
517 struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
866bd951 518 const struct regulator_desc *regulators;
765e8023
CYT		 519 struct regulator_config config = {
520 .dev = pdev->dev.parent,
521 .regmap = axp20x->regmap,
866bd951 522 .driver_data = axp20x,
765e8023 523 };
866bd951 524 int ret, i, nregulators;
dfe7a1b0 525 u32 workmode;
a51f9f46
CYT		 526 const char *dcdc1_name = axp22x_regulators[AXP22X_DCDC1].name;
527 const char *dcdc5_name = axp22x_regulators[AXP22X_DCDC5].name;
636e2a39 528 bool drivevbus = false;
dfe7a1b0 529
866bd951
BB		 530 switch (axp20x->variant) {
531 case AXP202_ID:
532 case AXP209_ID:
533 regulators = axp20x_regulators;
534 nregulators = AXP20X_REG_ID_MAX;
535 break;
1b82b4e4 536 case AXP221_ID:
04e0981c 537 case AXP223_ID:
1b82b4e4
BB		 538 regulators = axp22x_regulators;
539 nregulators = AXP22X_REG_ID_MAX;
636e2a39
HG		 540 drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
541 "x-powers,drive-vbus-en");
1b82b4e4 542 break;
2ca342d3
CYT		 543 case AXP806_ID:
544 regulators = axp806_regulators;
545 nregulators = AXP806_REG_ID_MAX;
546 break;
a51f9f46
CYT		 547 case AXP809_ID:
548 regulators = axp809_regulators;
549 nregulators = AXP809_REG_ID_MAX;
550 break;
866bd951
BB		 551 default:
552 dev_err(&pdev->dev, "Unsupported AXP variant: %ld\n",
553 axp20x->variant);
554 return -EINVAL;
555 }
556
765e8023
CYT		 557 /* This only sets the dcdc freq. Ignore any errors */
558 axp20x_regulator_parse_dt(pdev);
dfe7a1b0 559
866bd951 560 for (i = 0; i < nregulators; i++) {
7118f19c
CYT		 561 const struct regulator_desc *desc = &regulators[i];
562 struct regulator_desc *new_desc;
563
2ca342d3
CYT		 564 /*
565 * If this regulator is a slave in a poly-phase setup,
566 * skip it, as its controls are bound to the master
567 * regulator and won't work.
568 */
569 if (axp20x_is_polyphase_slave(axp20x, i))
570 continue;
571
7118f19c
CYT		 572 /*
573 * Regulators DC1SW and DC5LDO are connected internally,
574 * so we have to handle their supply names separately.
575 *
576 * We always register the regulators in proper sequence,
577 * so the supply names are correctly read. See the last
578 * part of this loop to see where we save the DT defined
579 * name.
580 */
a51f9f46
CYT		 581 if ((regulators == axp22x_regulators && i == AXP22X_DC1SW) ||
582 (regulators == axp809_regulators && i == AXP809_DC1SW)) {
583 new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
584 GFP_KERNEL);
585 *new_desc = regulators[i];
586 new_desc->supply_name = dcdc1_name;
587 desc = new_desc;
588 }
589
590 if ((regulators == axp22x_regulators && i == AXP22X_DC5LDO) ||
591 (regulators == axp809_regulators && i == AXP809_DC5LDO)) {
592 new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
593 GFP_KERNEL);
594 *new_desc = regulators[i];
595 new_desc->supply_name = dcdc5_name;
596 desc = new_desc;
7118f19c
CYT		 597 }
598
599 rdev = devm_regulator_register(&pdev->dev, desc, &config);
dfe7a1b0
CC		 600 if (IS_ERR(rdev)) {
601 dev_err(&pdev->dev, "Failed to register %s\n",
866bd951 602 regulators[i].name);
dfe7a1b0
CC		 603
604 return PTR_ERR(rdev);
605 }
606
765e8023
CYT		 607 ret = of_property_read_u32(rdev->dev.of_node,
608 "x-powers,dcdc-workmode",
dfe7a1b0
CC		 609 &workmode);
610 if (!ret) {
611 if (axp20x_set_dcdc_workmode(rdev, i, workmode))
612 dev_err(&pdev->dev, "Failed to set workmode on %s\n",
866bd951 613 rdev->desc->name);
dfe7a1b0 614 }
7118f19c
CYT		 615
616 /*
617 * Save AXP22X DCDC1 / DCDC5 regulator names for later.
618 */
a51f9f46
CYT		 619 if ((regulators == axp22x_regulators && i == AXP22X_DCDC1) ||
620 (regulators == axp809_regulators && i == AXP809_DCDC1))
621 of_property_read_string(rdev->dev.of_node,
622 "regulator-name",
623 &dcdc1_name);
624
625 if ((regulators == axp22x_regulators && i == AXP22X_DCDC5) ||
626 (regulators == axp809_regulators && i == AXP809_DCDC5))
627 of_property_read_string(rdev->dev.of_node,
628 "regulator-name",
629 &dcdc5_name);
dfe7a1b0
CC		 630 }
631
636e2a39
HG		 632 if (drivevbus) {
633 /* Change N_VBUSEN sense pin to DRIVEVBUS output pin */
634 regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP,
635 AXP22X_MISC_N_VBUSEN_FUNC, 0);
636 rdev = devm_regulator_register(&pdev->dev,
637 &axp22x_drivevbus_regulator,
638 &config);
639 if (IS_ERR(rdev)) {
640 dev_err(&pdev->dev, "Failed to register drivevbus\n");
641 return PTR_ERR(rdev);
642 }
643 }
644
dfe7a1b0
CC		 645 return 0;
646}
647
648static struct platform_driver axp20x_regulator_driver = {
649 .probe = axp20x_regulator_probe,
650 .driver = {
651 .name = "axp20x-regulator",
dfe7a1b0
CC		 652 },
653};
654
655module_platform_driver(axp20x_regulator_driver);
656
657MODULE_LICENSE("GPL v2");
658MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
659MODULE_DESCRIPTION("Regulator Driver for AXP20X PMIC");
d4ea7d86 660MODULE_ALIAS("platform:axp20x-regulator");
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