[mirror_ubuntu-artful-kernel.git] / drivers / regulator / cpcap-regulator.c

/*
 * Motorola CPCAP PMIC regulator driver
 *
 * Based on cpcap-regulator.c from Motorola Linux kernel tree
 * Copyright (C) 2009-2011 Motorola, Inc.
 *
 * Rewritten for mainline kernel to use device tree and regmap
 * Copyright (C) 2017 Tony Lindgren <tony@atomide.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */

#include <linux/err.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/regmap.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/of_regulator.h>
#include <linux/mfd/motorola-cpcap.h>

/*
 * Resource assignment register bits. These seem to control the state
 * idle modes adn are used at least for omap4.
 */

/* CPCAP_REG_ASSIGN2 bits - Resource Assignment 2 */
#define CPCAP_BIT_VSDIO_SEL		BIT(15)
#define CPCAP_BIT_VDIG_SEL		BIT(14)
#define CPCAP_BIT_VCAM_SEL		BIT(13)
#define CPCAP_BIT_SW6_SEL		BIT(12)
#define CPCAP_BIT_SW5_SEL		BIT(11)
#define CPCAP_BIT_SW4_SEL		BIT(10)
#define CPCAP_BIT_SW3_SEL		BIT(9)
#define CPCAP_BIT_SW2_SEL		BIT(8)
#define CPCAP_BIT_SW1_SEL		BIT(7)

/* CPCAP_REG_ASSIGN3 bits - Resource Assignment 3 */
#define CPCAP_BIT_VUSBINT2_SEL		BIT(15)
#define CPCAP_BIT_VUSBINT1_SEL		BIT(14)
#define CPCAP_BIT_VVIB_SEL		BIT(13)
#define CPCAP_BIT_VWLAN1_SEL		BIT(12)
#define CPCAP_BIT_VRF1_SEL		BIT(11)
#define CPCAP_BIT_VHVIO_SEL		BIT(10)
#define CPCAP_BIT_VDAC_SEL		BIT(9)
#define CPCAP_BIT_VUSB_SEL		BIT(8)
#define CPCAP_BIT_VSIM_SEL		BIT(7)
#define CPCAP_BIT_VRFREF_SEL		BIT(6)
#define CPCAP_BIT_VPLL_SEL		BIT(5)
#define CPCAP_BIT_VFUSE_SEL		BIT(4)
#define CPCAP_BIT_VCSI_SEL		BIT(3)
#define CPCAP_BIT_SPARE_14_2		BIT(2)
#define CPCAP_BIT_VWLAN2_SEL		BIT(1)
#define CPCAP_BIT_VRF2_SEL		BIT(0)

/* CPCAP_REG_ASSIGN4 bits - Resource Assignment 4 */
#define CPCAP_BIT_VAUDIO_SEL		BIT(0)

/*
 * Enable register bits. At least CPCAP_BIT_AUDIO_LOW_PWR is generic,
 * and not limited to audio regulator. Let's use the Motorola kernel
 * naming for now until we have a better understanding of the other
 * enable register bits. No idea why BIT(3) is not defined.
 */
#define CPCAP_BIT_AUDIO_LOW_PWR		BIT(6)
#define CPCAP_BIT_AUD_LOWPWR_SPEED	BIT(5)
#define CPCAP_BIT_VAUDIOPRISTBY		BIT(4)
#define CPCAP_BIT_VAUDIO_MODE1		BIT(2)
#define CPCAP_BIT_VAUDIO_MODE0		BIT(1)
#define CPCAP_BIT_V_AUDIO_EN		BIT(0)

#define CPCAP_BIT_AUDIO_NORMAL_MODE	0x00

/*
 * Off mode configuration bit. Used currently only by SW5 on omap4. There's
 * the following comment in Motorola Linux kernel tree for it:
 *
 * When set in the regulator mode, the regulator assignment will be changed
 * to secondary when the regulator is disabled. The mode will be set back to
 * primary when the regulator is turned on.
 */
#define CPCAP_REG_OFF_MODE_SEC		BIT(15)

/**
 * SoC specific configuraion for CPCAP regulator. There are at least three
 * different SoCs each with their own parameters: omap3, omap4 and tegra2.
 *
 * The assign_reg and assign_mask seem to allow toggling between primary
 * and secondary mode that at least omap4 uses for off mode.
 */
struct cpcap_regulator {
	struct regulator_desc rdesc;
	const u16 assign_reg;
	const u16 assign_mask;
	const u16 vsel_shift;
};

#define CPCAP_REG(_ID, reg, assignment_reg, assignment_mask, val_tbl,	\
		mode_mask, volt_mask, volt_shft,			\
		mode_val, off_val, volt_trans_time) {			\
	.rdesc = {							\
		.name = #_ID,						\
		.of_match = of_match_ptr(#_ID),				\
		.ops = &cpcap_regulator_ops,				\
		.regulators_node = of_match_ptr("regulators"),		\
		.type = REGULATOR_VOLTAGE,				\
		.id = CPCAP_##_ID,					\
		.owner = THIS_MODULE,					\
		.n_voltages = ARRAY_SIZE(val_tbl),			\
		.volt_table = (val_tbl),				\
		.vsel_reg = (reg),					\
		.vsel_mask = (volt_mask),				\
		.enable_reg = (reg),					\
		.enable_mask = (mode_mask),				\
		.enable_val = (mode_val),				\
		.disable_val = (off_val),				\
		.ramp_delay = (volt_trans_time),			\
	},								\
	.assign_reg = (assignment_reg),					\
	.assign_mask = (assignment_mask),				\
	.vsel_shift = (volt_shft),					\
}

struct cpcap_ddata {
	struct regmap *reg;
	struct device *dev;
	const struct cpcap_regulator *soc;
};

enum cpcap_regulator_id {
	CPCAP_SW1,
	CPCAP_SW2,
	CPCAP_SW3,
	CPCAP_SW4,
	CPCAP_SW5,
	CPCAP_SW6,
	CPCAP_VCAM,
	CPCAP_VCSI,
	CPCAP_VDAC,
	CPCAP_VDIG,
	CPCAP_VFUSE,
	CPCAP_VHVIO,
	CPCAP_VSDIO,
	CPCAP_VPLL,
	CPCAP_VRF1,
	CPCAP_VRF2,
	CPCAP_VRFREF,
	CPCAP_VWLAN1,
	CPCAP_VWLAN2,
	CPCAP_VSIM,
	CPCAP_VSIMCARD,
	CPCAP_VVIB,
	CPCAP_VUSB,
	CPCAP_VAUDIO,
	CPCAP_NR_REGULATORS,
};

/*
 * We need to also configure regulator idle mode for SoC off mode if
 * CPCAP_REG_OFF_MODE_SEC is set.
 */
static int cpcap_regulator_enable(struct regulator_dev *rdev)
{
	struct cpcap_regulator *regulator = rdev_get_drvdata(rdev);
	int error, ignore;

	error = regulator_enable_regmap(rdev);
	if (error)
		return error;

	if (rdev->desc->enable_val & CPCAP_REG_OFF_MODE_SEC) {
		error = regmap_update_bits(rdev->regmap, regulator->assign_reg,
					   regulator->assign_mask,
					   regulator->assign_mask);
		if (error)
			ignore = regulator_disable_regmap(rdev);
	}

	return error;
}

/*
 * We need to also configure regulator idle mode for SoC off mode if
 * CPCAP_REG_OFF_MODE_SEC is set.
 */
static int cpcap_regulator_disable(struct regulator_dev *rdev)
{
	struct cpcap_regulator *regulator = rdev_get_drvdata(rdev);
	int error, ignore;

	if (rdev->desc->enable_val & CPCAP_REG_OFF_MODE_SEC) {
		error = regmap_update_bits(rdev->regmap, regulator->assign_reg,
					   regulator->assign_mask, 0);
		if (error)
			return error;
	}

	error = regulator_disable_regmap(rdev);
	if (error && (rdev->desc->enable_val & CPCAP_REG_OFF_MODE_SEC)) {
		ignore = regmap_update_bits(rdev->regmap, regulator->assign_reg,
					    regulator->assign_mask,
					    regulator->assign_mask);
	}

	return error;
}

static unsigned int cpcap_regulator_get_mode(struct regulator_dev *rdev)
{
	int value;

	regmap_read(rdev->regmap, rdev->desc->enable_reg, &value);

	if (value & CPCAP_BIT_AUDIO_LOW_PWR)
		return REGULATOR_MODE_STANDBY;

	return REGULATOR_MODE_NORMAL;
}

static int cpcap_regulator_set_mode(struct regulator_dev *rdev,
				    unsigned int mode)
{
	int value;

	switch (mode) {
	case REGULATOR_MODE_NORMAL:
		value = CPCAP_BIT_AUDIO_NORMAL_MODE;
		break;
	case REGULATOR_MODE_STANDBY:
		value = CPCAP_BIT_AUDIO_LOW_PWR;
		break;
	default:
		return -EINVAL;
	}

	return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg,
				  CPCAP_BIT_AUDIO_LOW_PWR, value);
}

static struct regulator_ops cpcap_regulator_ops = {
	.enable = cpcap_regulator_enable,
	.disable = cpcap_regulator_disable,
	.is_enabled = regulator_is_enabled_regmap,
	.list_voltage = regulator_list_voltage_table,
	.map_voltage = regulator_map_voltage_iterate,
	.get_voltage_sel = regulator_get_voltage_sel_regmap,
	.set_voltage_sel = regulator_set_voltage_sel_regmap,
	.get_mode = cpcap_regulator_get_mode,
	.set_mode = cpcap_regulator_set_mode,
};

static const unsigned int unknown_val_tbl[] = { 0, };
static const unsigned int sw5_val_tbl[] = { 0, 5050000, };
static const unsigned int vcam_val_tbl[] = { 2600000, 2700000, 2800000,
					     2900000, };
static const unsigned int vcsi_val_tbl[] = { 1200000, 1800000, };
static const unsigned int vdac_val_tbl[] = { 1200000, 1500000, 1800000,
					     2500000,};
static const unsigned int vdig_val_tbl[] = { 1200000, 1350000, 1500000,
					     1875000, };
static const unsigned int vfuse_val_tbl[] = { 1500000, 1600000, 1700000,
					      1800000, 1900000, 2000000,
					      2100000, 2200000, 2300000,
					      2400000, 2500000, 2600000,
					      2700000, 3150000, };
static const unsigned int vhvio_val_tbl[] = { 2775000, };
static const unsigned int vsdio_val_tbl[] = { 1500000, 1600000, 1800000,
					      2600000, 2700000, 2800000,
					      2900000, 3000000, };
static const unsigned int vpll_val_tbl[] = { 1200000, 1300000, 1400000,
					     1800000, };
/* Quirk: 2775000 is before 2500000 for vrf1 regulator */
static const unsigned int vrf1_val_tbl[] = { 2775000, 2500000, };
static const unsigned int vrf2_val_tbl[] = { 0, 2775000, };
static const unsigned int vrfref_val_tbl[] = { 2500000, 2775000, };
static const unsigned int vwlan1_val_tbl[] = { 1800000, 1900000, };
static const unsigned int vwlan2_val_tbl[] = { 2775000, 3000000, 3300000,
					       3300000, };
static const unsigned int vsim_val_tbl[] = { 1800000, 2900000, };
static const unsigned int vsimcard_val_tbl[] = { 1800000, 2900000, };
static const unsigned int vvib_val_tbl[] = { 1300000, 1800000, 2000000,
					     3000000, };
static const unsigned int vusb_val_tbl[] = { 0, 3300000, };
static const unsigned int vaudio_val_tbl[] = { 0, 2775000, };

/**
 * SoC specific configuration for omap4. The data below is comes from Motorola
 * Linux kernel tree. It's basically the values of cpcap_regltr_data,
 * cpcap_regulator_mode_values and cpcap_regulator_off_mode_values, see
 * CPCAP_REG macro above.
 *
 * SW1 to SW4 and SW6 seems to be unused for mapphone. Note that VSIM and
 * VSIMCARD have a shared resource assignment bit.
 */
static struct cpcap_regulator omap4_regulators[] = {
	CPCAP_REG(SW1, CPCAP_REG_S1C1, CPCAP_REG_ASSIGN2,
		  CPCAP_BIT_SW1_SEL, unknown_val_tbl,
		  0, 0, 0, 0, 0, 0),
	CPCAP_REG(SW2, CPCAP_REG_S2C1, CPCAP_REG_ASSIGN2,
		  CPCAP_BIT_SW2_SEL, unknown_val_tbl,
		  0, 0, 0, 0, 0, 0),
	CPCAP_REG(SW3, CPCAP_REG_S3C, CPCAP_REG_ASSIGN2,
		  CPCAP_BIT_SW3_SEL, unknown_val_tbl,
		  0, 0, 0, 0, 0, 0),
	CPCAP_REG(SW4, CPCAP_REG_S4C1, CPCAP_REG_ASSIGN2,
		  CPCAP_BIT_SW4_SEL, unknown_val_tbl,
		  0, 0, 0, 0, 0, 0),
	CPCAP_REG(SW5, CPCAP_REG_S5C, CPCAP_REG_ASSIGN2,
		  CPCAP_BIT_SW5_SEL, sw5_val_tbl,
		  0x28, 0, 0, 0x20 | CPCAP_REG_OFF_MODE_SEC, 0, 0),
	CPCAP_REG(SW6, CPCAP_REG_S6C, CPCAP_REG_ASSIGN2,
		  CPCAP_BIT_SW6_SEL, unknown_val_tbl,
		  0, 0, 0, 0, 0, 0),
	CPCAP_REG(VCAM, CPCAP_REG_VCAMC, CPCAP_REG_ASSIGN2,
		  CPCAP_BIT_VCAM_SEL, vcam_val_tbl,
		  0x87, 0x30, 4, 0x3, 0, 420),
	CPCAP_REG(VCSI, CPCAP_REG_VCSIC, CPCAP_REG_ASSIGN3,
		  CPCAP_BIT_VCSI_SEL, vcsi_val_tbl,
		  0x47, 0x10, 4, 0x43, 0x41, 350),
	CPCAP_REG(VDAC, CPCAP_REG_VDACC, CPCAP_REG_ASSIGN3,
		  CPCAP_BIT_VDAC_SEL, vdac_val_tbl,
		  0x87, 0x30, 4, 0x3, 0, 420),
	CPCAP_REG(VDIG, CPCAP_REG_VDIGC, CPCAP_REG_ASSIGN2,
		  CPCAP_BIT_VDIG_SEL, vdig_val_tbl,
		  0x87, 0x30, 4, 0x82, 0, 420),
	CPCAP_REG(VFUSE, CPCAP_REG_VFUSEC, CPCAP_REG_ASSIGN3,
		  CPCAP_BIT_VFUSE_SEL, vfuse_val_tbl,
		  0x80, 0xf, 0, 0x80, 0, 420),
	CPCAP_REG(VHVIO, CPCAP_REG_VHVIOC, CPCAP_REG_ASSIGN3,
		  CPCAP_BIT_VHVIO_SEL, vhvio_val_tbl,
		  0x17, 0, 0, 0, 0x12, 0),
	CPCAP_REG(VSDIO, CPCAP_REG_VSDIOC, CPCAP_REG_ASSIGN2,
		  CPCAP_BIT_VSDIO_SEL, vsdio_val_tbl,
		  0x87, 0x38, 3, 0x82, 0, 420),
	CPCAP_REG(VPLL, CPCAP_REG_VPLLC, CPCAP_REG_ASSIGN3,
		  CPCAP_BIT_VPLL_SEL, vpll_val_tbl,
		  0x43, 0x18, 3, 0x2, 0, 420),
	CPCAP_REG(VRF1, CPCAP_REG_VRF1C, CPCAP_REG_ASSIGN3,
		  CPCAP_BIT_VRF1_SEL, vrf1_val_tbl,
		  0xac, 0x2, 1, 0x4, 0, 10),
	CPCAP_REG(VRF2, CPCAP_REG_VRF2C, CPCAP_REG_ASSIGN3,
		  CPCAP_BIT_VRF2_SEL, vrf2_val_tbl,
		  0x23, 0x8, 3, 0, 0, 10),
	CPCAP_REG(VRFREF, CPCAP_REG_VRFREFC, CPCAP_REG_ASSIGN3,
		  CPCAP_BIT_VRFREF_SEL, vrfref_val_tbl,
		  0x23, 0x8, 3, 0, 0, 420),
	CPCAP_REG(VWLAN1, CPCAP_REG_VWLAN1C, CPCAP_REG_ASSIGN3,
		  CPCAP_BIT_VWLAN1_SEL, vwlan1_val_tbl,
		  0x47, 0x10, 4, 0, 0, 420),
	CPCAP_REG(VWLAN2, CPCAP_REG_VWLAN2C, CPCAP_REG_ASSIGN3,
		  CPCAP_BIT_VWLAN2_SEL, vwlan2_val_tbl,
		  0x20c, 0xc0, 6, 0x20c, 0, 420),
	CPCAP_REG(VSIM, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3,
		  0xffff, vsim_val_tbl,
		  0x23, 0x8, 3, 0x3, 0, 420),
	CPCAP_REG(VSIMCARD, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3,
		  0xffff, vsimcard_val_tbl,
		  0x1e80, 0x8, 3, 0x1e00, 0, 420),
	CPCAP_REG(VVIB, CPCAP_REG_VVIBC, CPCAP_REG_ASSIGN3,
		  CPCAP_BIT_VVIB_SEL, vvib_val_tbl,
		  0x1, 0xc, 2, 0x1, 0, 500),
	CPCAP_REG(VUSB, CPCAP_REG_VUSBC, CPCAP_REG_ASSIGN3,
		  CPCAP_BIT_VUSB_SEL, vusb_val_tbl,
		  0x11c, 0x40, 6, 0xc, 0, 0),
	CPCAP_REG(VAUDIO, CPCAP_REG_VAUDIOC, CPCAP_REG_ASSIGN4,
		  CPCAP_BIT_VAUDIO_SEL, vaudio_val_tbl,
		  0x16, 0x1, 0, 0x4, 0, 0),
	{ /* sentinel */ },
};

static const struct of_device_id cpcap_regulator_id_table[] = {
	{
		.compatible = "motorola,cpcap-regulator",
	},
	{
		.compatible = "motorola,mapphone-cpcap-regulator",
		.data = omap4_regulators,
	},
	{},
};
MODULE_DEVICE_TABLE(of, cpcap_regulator_id_table);

static int cpcap_regulator_probe(struct platform_device *pdev)
{
	struct cpcap_ddata *ddata;
	const struct of_device_id *match;
	struct regulator_config config;
	struct regulator_init_data init_data;
	int i;

	match = of_match_device(of_match_ptr(cpcap_regulator_id_table),
				&pdev->dev);
	if (!match)
		return -EINVAL;

	if (!match->data) {
		dev_err(&pdev->dev, "no configuration data found\n");

		return -ENODEV;
	}

	ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
	if (!ddata)
		return -ENOMEM;

	ddata->reg = dev_get_regmap(pdev->dev.parent, NULL);
	if (!ddata->reg)
		return -ENODEV;

	ddata->dev = &pdev->dev;
	ddata->soc = match->data;
	platform_set_drvdata(pdev, ddata);

	memset(&config, 0, sizeof(config));
	memset(&init_data, 0, sizeof(init_data));
	config.dev = &pdev->dev;
	config.regmap = ddata->reg;
	config.init_data = &init_data;

	for (i = 0; i < CPCAP_NR_REGULATORS; i++) {
		const struct cpcap_regulator *regulator = &ddata->soc[i];
		struct regulator_dev *rdev;

		if (!regulator->rdesc.name)
			break;

		if (regulator->rdesc.volt_table == unknown_val_tbl)
			continue;

		config.driver_data = (void *)regulator;
		rdev = devm_regulator_register(&pdev->dev,
					       &regulator->rdesc,
					       &config);
		if (IS_ERR(rdev)) {
			dev_err(&pdev->dev, "failed to register regulator %s\n",
				regulator->rdesc.name);

			return PTR_ERR(rdev);
		}
	}

	return 0;
}

static struct platform_driver cpcap_regulator_driver = {
	.probe		= cpcap_regulator_probe,
	.driver		= {
		.name	= "cpcap-regulator",
		.of_match_table = of_match_ptr(cpcap_regulator_id_table),
	},
};

module_platform_driver(cpcap_regulator_driver);

MODULE_ALIAS("platform:cpcap-regulator");
MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
MODULE_DESCRIPTION("CPCAP regulator driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
0ad4c07e TL	1	/*
	2	* Motorola CPCAP PMIC regulator driver
	3	*
	4	* Based on cpcap-regulator.c from Motorola Linux kernel tree
	5	* Copyright (C) 2009-2011 Motorola, Inc.
	6	*
	7	* Rewritten for mainline kernel to use device tree and regmap
	8	* Copyright (C) 2017 Tony Lindgren <tony@atomide.com>
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation version 2.
	13	*
	14	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	15	* kind, whether express or implied; without even the implied warranty
	16	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*/
	19
	20	#include <linux/err.h>
	21	#include <linux/module.h>
	22	#include <linux/of.h>
	23	#include <linux/of_platform.h>
	24	#include <linux/regmap.h>
	25	#include <linux/regulator/driver.h>
	26	#include <linux/regulator/machine.h>
	27	#include <linux/regulator/of_regulator.h>
	28	#include <linux/mfd/motorola-cpcap.h>
	29
	30	/*
	31	* Resource assignment register bits. These seem to control the state
	32	* idle modes adn are used at least for omap4.
	33	*/
	34
	35	/* CPCAP_REG_ASSIGN2 bits - Resource Assignment 2 */
	36	#define CPCAP_BIT_VSDIO_SEL BIT(15)
	37	#define CPCAP_BIT_VDIG_SEL BIT(14)
	38	#define CPCAP_BIT_VCAM_SEL BIT(13)
	39	#define CPCAP_BIT_SW6_SEL BIT(12)
	40	#define CPCAP_BIT_SW5_SEL BIT(11)
	41	#define CPCAP_BIT_SW4_SEL BIT(10)
	42	#define CPCAP_BIT_SW3_SEL BIT(9)
	43	#define CPCAP_BIT_SW2_SEL BIT(8)
	44	#define CPCAP_BIT_SW1_SEL BIT(7)
	45
	46	/* CPCAP_REG_ASSIGN3 bits - Resource Assignment 3 */
	47	#define CPCAP_BIT_VUSBINT2_SEL BIT(15)
	48	#define CPCAP_BIT_VUSBINT1_SEL BIT(14)
	49	#define CPCAP_BIT_VVIB_SEL BIT(13)
	50	#define CPCAP_BIT_VWLAN1_SEL BIT(12)
	51	#define CPCAP_BIT_VRF1_SEL BIT(11)
	52	#define CPCAP_BIT_VHVIO_SEL BIT(10)
	53	#define CPCAP_BIT_VDAC_SEL BIT(9)
	54	#define CPCAP_BIT_VUSB_SEL BIT(8)
	55	#define CPCAP_BIT_VSIM_SEL BIT(7)
	56	#define CPCAP_BIT_VRFREF_SEL BIT(6)
	57	#define CPCAP_BIT_VPLL_SEL BIT(5)
	58	#define CPCAP_BIT_VFUSE_SEL BIT(4)
	59	#define CPCAP_BIT_VCSI_SEL BIT(3)
	60	#define CPCAP_BIT_SPARE_14_2 BIT(2)
	61	#define CPCAP_BIT_VWLAN2_SEL BIT(1)
	62	#define CPCAP_BIT_VRF2_SEL BIT(0)
	63
	64	/* CPCAP_REG_ASSIGN4 bits - Resource Assignment 4 */
65	#define CPCAP_BIT_VAUDIO_SEL BIT(0)
66
67	/*
68	* Enable register bits. At least CPCAP_BIT_AUDIO_LOW_PWR is generic,
69	* and not limited to audio regulator. Let's use the Motorola kernel
70	* naming for now until we have a better understanding of the other
71	* enable register bits. No idea why BIT(3) is not defined.
72	*/
73	#define CPCAP_BIT_AUDIO_LOW_PWR BIT(6)
74	#define CPCAP_BIT_AUD_LOWPWR_SPEED BIT(5)
75	#define CPCAP_BIT_VAUDIOPRISTBY BIT(4)
76	#define CPCAP_BIT_VAUDIO_MODE1 BIT(2)
77	#define CPCAP_BIT_VAUDIO_MODE0 BIT(1)
78	#define CPCAP_BIT_V_AUDIO_EN BIT(0)
79
9b1b2902 SR	80	#define CPCAP_BIT_AUDIO_NORMAL_MODE 0x00
9b1b2902 SR	81
0ad4c07e TL	82	/*
	83	* Off mode configuration bit. Used currently only by SW5 on omap4. There's
	84	* the following comment in Motorola Linux kernel tree for it:
	85	*
	86	* When set in the regulator mode, the regulator assignment will be changed
	87	* to secondary when the regulator is disabled. The mode will be set back to
	88	* primary when the regulator is turned on.
	89	*/
	90	#define CPCAP_REG_OFF_MODE_SEC BIT(15)
	91
	92	/**
	93	* SoC specific configuraion for CPCAP regulator. There are at least three
	94	* different SoCs each with their own parameters: omap3, omap4 and tegra2.
	95	*
	96	* The assign_reg and assign_mask seem to allow toggling between primary
	97	* and secondary mode that at least omap4 uses for off mode.
	98	*/
	99	struct cpcap_regulator {
	100	struct regulator_desc rdesc;
	101	const u16 assign_reg;
	102	const u16 assign_mask;
	103	const u16 vsel_shift;
	104	};
	105
	106	#define CPCAP_REG(_ID, reg, assignment_reg, assignment_mask, val_tbl, \
	107	mode_mask, volt_mask, volt_shft, \
	108	mode_val, off_val, volt_trans_time) { \
	109	.rdesc = { \
	110	.name = #_ID, \
	111	.of_match = of_match_ptr(#_ID), \
	112	.ops = &cpcap_regulator_ops, \
	113	.regulators_node = of_match_ptr("regulators"), \
	114	.type = REGULATOR_VOLTAGE, \
	115	.id = CPCAP_##_ID, \
	116	.owner = THIS_MODULE, \
	117	.n_voltages = ARRAY_SIZE(val_tbl), \
	118	.volt_table = (val_tbl), \
	119	.vsel_reg = (reg), \
	120	.vsel_mask = (volt_mask), \
	121	.enable_reg = (reg), \
	122	.enable_mask = (mode_mask), \
	123	.enable_val = (mode_val), \
	124	.disable_val = (off_val), \
	125	.ramp_delay = (volt_trans_time), \
	126	}, \
	127	.assign_reg = (assignment_reg), \
	128	.assign_mask = (assignment_mask), \
	129	.vsel_shift = (volt_shft), \
	130	}
	131
	132	struct cpcap_ddata {
	133	struct regmap *reg;
	134	struct device *dev;
	135	const struct cpcap_regulator *soc;
	136	};
	137
	138	enum cpcap_regulator_id {
	139	CPCAP_SW1,
	140	CPCAP_SW2,
	141	CPCAP_SW3,
	142	CPCAP_SW4,
	143	CPCAP_SW5,
	144	CPCAP_SW6,
	145	CPCAP_VCAM,
146	CPCAP_VCSI,
147	CPCAP_VDAC,
148	CPCAP_VDIG,
149	CPCAP_VFUSE,
150	CPCAP_VHVIO,
151	CPCAP_VSDIO,
152	CPCAP_VPLL,
153	CPCAP_VRF1,
154	CPCAP_VRF2,
155	CPCAP_VRFREF,
156	CPCAP_VWLAN1,
157	CPCAP_VWLAN2,
158	CPCAP_VSIM,
159	CPCAP_VSIMCARD,
160	CPCAP_VVIB,
161	CPCAP_VUSB,
162	CPCAP_VAUDIO,
163	CPCAP_NR_REGULATORS,
164	};
165
166	/*
167	* We need to also configure regulator idle mode for SoC off mode if
168	* CPCAP_REG_OFF_MODE_SEC is set.
169	*/
170	static int cpcap_regulator_enable(struct regulator_dev *rdev)
171	{
172	struct cpcap_regulator *regulator = rdev_get_drvdata(rdev);
173	int error, ignore;
174
175	error = regulator_enable_regmap(rdev);
176	if (error)
177	return error;
178
179	if (rdev->desc->enable_val & CPCAP_REG_OFF_MODE_SEC) {
180	error = regmap_update_bits(rdev->regmap, regulator->assign_reg,
181	regulator->assign_mask,
182	regulator->assign_mask);
183	if (error)
184	ignore = regulator_disable_regmap(rdev);
185	}
186
187	return error;
188	}
189
190	/*
191	* We need to also configure regulator idle mode for SoC off mode if
192	* CPCAP_REG_OFF_MODE_SEC is set.
193	*/
194	static int cpcap_regulator_disable(struct regulator_dev *rdev)
195	{
196	struct cpcap_regulator *regulator = rdev_get_drvdata(rdev);
197	int error, ignore;
198
199	if (rdev->desc->enable_val & CPCAP_REG_OFF_MODE_SEC) {
200	error = regmap_update_bits(rdev->regmap, regulator->assign_reg,
201	regulator->assign_mask, 0);
202	if (error)
203	return error;
204	}
205
206	error = regulator_disable_regmap(rdev);
207	if (error && (rdev->desc->enable_val & CPCAP_REG_OFF_MODE_SEC)) {
208	ignore = regmap_update_bits(rdev->regmap, regulator->assign_reg,
209	regulator->assign_mask,
210	regulator->assign_mask);
211	}
212
213	return error;
214	}
215
216	static unsigned int cpcap_regulator_get_mode(struct regulator_dev *rdev)
217	{
218	int value;
219
220	regmap_read(rdev->regmap, rdev->desc->enable_reg, &value);
221
9b1b2902	222	if (value & CPCAP_BIT_AUDIO_LOW_PWR)
0ad4c07e TL	223	return REGULATOR_MODE_STANDBY;
	224
	225	return REGULATOR_MODE_NORMAL;
	226	}
	227
	228	static int cpcap_regulator_set_mode(struct regulator_dev *rdev,
	229	unsigned int mode)
	230	{
	231	int value;
	232
	233	switch (mode) {
	234	case REGULATOR_MODE_NORMAL:
9b1b2902	235	value = CPCAP_BIT_AUDIO_NORMAL_MODE;
0ad4c07e TL	236	break;
0ad4c07e TL	237	case REGULATOR_MODE_STANDBY:
9b1b2902	238	value = CPCAP_BIT_AUDIO_LOW_PWR;
0ad4c07e TL	239	break;
	240	default:
	241	return -EINVAL;
	242	}
	243
	244	return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg,
	245	CPCAP_BIT_AUDIO_LOW_PWR, value);
	246	}
	247
	248	static struct regulator_ops cpcap_regulator_ops = {
	249	.enable = cpcap_regulator_enable,
	250	.disable = cpcap_regulator_disable,
	251	.is_enabled = regulator_is_enabled_regmap,
	252	.list_voltage = regulator_list_voltage_table,
	253	.map_voltage = regulator_map_voltage_iterate,
	254	.get_voltage_sel = regulator_get_voltage_sel_regmap,
	255	.set_voltage_sel = regulator_set_voltage_sel_regmap,
	256	.get_mode = cpcap_regulator_get_mode,
	257	.set_mode = cpcap_regulator_set_mode,
	258	};
	259
	260	static const unsigned int unknown_val_tbl[] = { 0, };
	261	static const unsigned int sw5_val_tbl[] = { 0, 5050000, };
	262	static const unsigned int vcam_val_tbl[] = { 2600000, 2700000, 2800000,
	263	2900000, };
	264	static const unsigned int vcsi_val_tbl[] = { 1200000, 1800000, };
	265	static const unsigned int vdac_val_tbl[] = { 1200000, 1500000, 1800000,
	266	2500000,};
	267	static const unsigned int vdig_val_tbl[] = { 1200000, 1350000, 1500000,
	268	1875000, };
	269	static const unsigned int vfuse_val_tbl[] = { 1500000, 1600000, 1700000,
	270	1800000, 1900000, 2000000,
	271	2100000, 2200000, 2300000,
	272	2400000, 2500000, 2600000,
	273	2700000, 3150000, };
	274	static const unsigned int vhvio_val_tbl[] = { 2775000, };
	275	static const unsigned int vsdio_val_tbl[] = { 1500000, 1600000, 1800000,
	276	2600000, 2700000, 2800000,
	277	2900000, 3000000, };
	278	static const unsigned int vpll_val_tbl[] = { 1200000, 1300000, 1400000,
	279	1800000, };
	280	/* Quirk: 2775000 is before 2500000 for vrf1 regulator */
	281	static const unsigned int vrf1_val_tbl[] = { 2775000, 2500000, };
	282	static const unsigned int vrf2_val_tbl[] = { 0, 2775000, };
	283	static const unsigned int vrfref_val_tbl[] = { 2500000, 2775000, };
	284	static const unsigned int vwlan1_val_tbl[] = { 1800000, 1900000, };
	285	static const unsigned int vwlan2_val_tbl[] = { 2775000, 3000000, 3300000,
	286	3300000, };
	287	static const unsigned int vsim_val_tbl[] = { 1800000, 2900000, };
	288	static const unsigned int vsimcard_val_tbl[] = { 1800000, 2900000, };
	289	static const unsigned int vvib_val_tbl[] = { 1300000, 1800000, 2000000,
	290	3000000, };
	291	static const unsigned int vusb_val_tbl[] = { 0, 3300000, };
	292	static const unsigned int vaudio_val_tbl[] = { 0, 2775000, };
	293
	294	/**
	295	* SoC specific configuration for omap4. The data below is comes from Motorola
	296	* Linux kernel tree. It's basically the values of cpcap_regltr_data,
	297	* cpcap_regulator_mode_values and cpcap_regulator_off_mode_values, see
	298	* CPCAP_REG macro above.
	299	*
	300	* SW1 to SW4 and SW6 seems to be unused for mapphone. Note that VSIM and
	301	* VSIMCARD have a shared resource assignment bit.
	302	*/
303	static struct cpcap_regulator omap4_regulators[] = {
304	CPCAP_REG(SW1, CPCAP_REG_S1C1, CPCAP_REG_ASSIGN2,
305	CPCAP_BIT_SW1_SEL, unknown_val_tbl,
306	0, 0, 0, 0, 0, 0),
307	CPCAP_REG(SW2, CPCAP_REG_S2C1, CPCAP_REG_ASSIGN2,
308	CPCAP_BIT_SW2_SEL, unknown_val_tbl,
309	0, 0, 0, 0, 0, 0),
310	CPCAP_REG(SW3, CPCAP_REG_S3C, CPCAP_REG_ASSIGN2,
311	CPCAP_BIT_SW3_SEL, unknown_val_tbl,
312	0, 0, 0, 0, 0, 0),
313	CPCAP_REG(SW4, CPCAP_REG_S4C1, CPCAP_REG_ASSIGN2,
314	CPCAP_BIT_SW4_SEL, unknown_val_tbl,
315	0, 0, 0, 0, 0, 0),
316	CPCAP_REG(SW5, CPCAP_REG_S5C, CPCAP_REG_ASSIGN2,
317	CPCAP_BIT_SW5_SEL, sw5_val_tbl,
318	0x28, 0, 0, 0x20 \| CPCAP_REG_OFF_MODE_SEC, 0, 0),
319	CPCAP_REG(SW6, CPCAP_REG_S6C, CPCAP_REG_ASSIGN2,
320	CPCAP_BIT_SW6_SEL, unknown_val_tbl,
321	0, 0, 0, 0, 0, 0),
322	CPCAP_REG(VCAM, CPCAP_REG_VCAMC, CPCAP_REG_ASSIGN2,
323	CPCAP_BIT_VCAM_SEL, vcam_val_tbl,
324	0x87, 0x30, 4, 0x3, 0, 420),
325	CPCAP_REG(VCSI, CPCAP_REG_VCSIC, CPCAP_REG_ASSIGN3,
326	CPCAP_BIT_VCSI_SEL, vcsi_val_tbl,
327	0x47, 0x10, 4, 0x43, 0x41, 350),
328	CPCAP_REG(VDAC, CPCAP_REG_VDACC, CPCAP_REG_ASSIGN3,
329	CPCAP_BIT_VDAC_SEL, vdac_val_tbl,
330	0x87, 0x30, 4, 0x3, 0, 420),
331	CPCAP_REG(VDIG, CPCAP_REG_VDIGC, CPCAP_REG_ASSIGN2,
332	CPCAP_BIT_VDIG_SEL, vdig_val_tbl,
333	0x87, 0x30, 4, 0x82, 0, 420),
334	CPCAP_REG(VFUSE, CPCAP_REG_VFUSEC, CPCAP_REG_ASSIGN3,
335	CPCAP_BIT_VFUSE_SEL, vfuse_val_tbl,
336	0x80, 0xf, 0, 0x80, 0, 420),
337	CPCAP_REG(VHVIO, CPCAP_REG_VHVIOC, CPCAP_REG_ASSIGN3,
338	CPCAP_BIT_VHVIO_SEL, vhvio_val_tbl,
339	0x17, 0, 0, 0, 0x12, 0),
340	CPCAP_REG(VSDIO, CPCAP_REG_VSDIOC, CPCAP_REG_ASSIGN2,
341	CPCAP_BIT_VSDIO_SEL, vsdio_val_tbl,
342	0x87, 0x38, 3, 0x82, 0, 420),
343	CPCAP_REG(VPLL, CPCAP_REG_VPLLC, CPCAP_REG_ASSIGN3,
344	CPCAP_BIT_VPLL_SEL, vpll_val_tbl,
345	0x43, 0x18, 3, 0x2, 0, 420),
346	CPCAP_REG(VRF1, CPCAP_REG_VRF1C, CPCAP_REG_ASSIGN3,
347	CPCAP_BIT_VRF1_SEL, vrf1_val_tbl,
348	0xac, 0x2, 1, 0x4, 0, 10),
349	CPCAP_REG(VRF2, CPCAP_REG_VRF2C, CPCAP_REG_ASSIGN3,
350	CPCAP_BIT_VRF2_SEL, vrf2_val_tbl,
351	0x23, 0x8, 3, 0, 0, 10),
352	CPCAP_REG(VRFREF, CPCAP_REG_VRFREFC, CPCAP_REG_ASSIGN3,
353	CPCAP_BIT_VRFREF_SEL, vrfref_val_tbl,
354	0x23, 0x8, 3, 0, 0, 420),
355	CPCAP_REG(VWLAN1, CPCAP_REG_VWLAN1C, CPCAP_REG_ASSIGN3,
356	CPCAP_BIT_VWLAN1_SEL, vwlan1_val_tbl,
357	0x47, 0x10, 4, 0, 0, 420),
358	CPCAP_REG(VWLAN2, CPCAP_REG_VWLAN2C, CPCAP_REG_ASSIGN3,
359	CPCAP_BIT_VWLAN2_SEL, vwlan2_val_tbl,
360	0x20c, 0xc0, 6, 0x20c, 0, 420),
361	CPCAP_REG(VSIM, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3,
362	0xffff, vsim_val_tbl,
363	0x23, 0x8, 3, 0x3, 0, 420),
364	CPCAP_REG(VSIMCARD, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3,
365	0xffff, vsimcard_val_tbl,
366	0x1e80, 0x8, 3, 0x1e00, 0, 420),
367	CPCAP_REG(VVIB, CPCAP_REG_VVIBC, CPCAP_REG_ASSIGN3,
368	CPCAP_BIT_VVIB_SEL, vvib_val_tbl,
369	0x1, 0xc, 2, 0x1, 0, 500),
370	CPCAP_REG(VUSB, CPCAP_REG_VUSBC, CPCAP_REG_ASSIGN3,
371	CPCAP_BIT_VUSB_SEL, vusb_val_tbl,
372	0x11c, 0x40, 6, 0xc, 0, 0),
373	CPCAP_REG(VAUDIO, CPCAP_REG_VAUDIOC, CPCAP_REG_ASSIGN4,
374	CPCAP_BIT_VAUDIO_SEL, vaudio_val_tbl,
375	0x16, 0x1, 0, 0x4, 0, 0),
376	{ /* sentinel */ },
377	};
378
379	static const struct of_device_id cpcap_regulator_id_table[] = {
380	{
381	.compatible = "motorola,cpcap-regulator",
382	},
383	{
384	.compatible = "motorola,mapphone-cpcap-regulator",
385	.data = omap4_regulators,
386	},
387	{},
388	};
389	MODULE_DEVICE_TABLE(of, cpcap_regulator_id_table);
390
391	static int cpcap_regulator_probe(struct platform_device *pdev)
392	{
393	struct cpcap_ddata *ddata;
394	const struct of_device_id *match;
395	struct regulator_config config;
396	struct regulator_init_data init_data;
397	int i;
398
399	match = of_match_device(of_match_ptr(cpcap_regulator_id_table),
400	&pdev->dev);
401	if (!match)
402	return -EINVAL;
403
404	if (!match->data) {
405	dev_err(&pdev->dev, "no configuration data found\n");
406
407	return -ENODEV;
408	}
409
410	ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
411	if (!ddata)
412	return -ENOMEM;
413
414	ddata->reg = dev_get_regmap(pdev->dev.parent, NULL);
415	if (!ddata->reg)
416	return -ENODEV;
417
418	ddata->dev = &pdev->dev;
419	ddata->soc = match->data;
420	platform_set_drvdata(pdev, ddata);
421
422	memset(&config, 0, sizeof(config));
423	memset(&init_data, 0, sizeof(init_data));
424	config.dev = &pdev->dev;
425	config.regmap = ddata->reg;
426	config.init_data = &init_data;
427
428	for (i = 0; i < CPCAP_NR_REGULATORS; i++) {
429	const struct cpcap_regulator *regulator = &ddata->soc[i];
430	struct regulator_dev *rdev;
431
432	if (!regulator->rdesc.name)
433	break;
434
435	if (regulator->rdesc.volt_table == unknown_val_tbl)
436	continue;
437
438	config.driver_data = (void *)regulator;
439	rdev = devm_regulator_register(&pdev->dev,
440	&regulator->rdesc,
441	&config);
442	if (IS_ERR(rdev)) {
443	dev_err(&pdev->dev, "failed to register regulator %s\n",
444	regulator->rdesc.name);
445
446	return PTR_ERR(rdev);
447	}
448	}
449
450	return 0;
451	}
452
453	static struct platform_driver cpcap_regulator_driver = {
454	.probe = cpcap_regulator_probe,
455	.driver = {
456	.name = "cpcap-regulator",
457	.of_match_table = of_match_ptr(cpcap_regulator_id_table),
458	},
459	};
460
461	module_platform_driver(cpcap_regulator_driver);
462
463	MODULE_ALIAS("platform:cpcap-regulator");
464	MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
465	MODULE_DESCRIPTION("CPCAP regulator driver");
466	MODULE_LICENSE("GPL v2");