[mirror_ubuntu-hirsute-kernel.git] / drivers / regulator / lp8788-ldo.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * TI LP8788 MFD - ldo regulator driver
 *
 * Copyright 2012 Texas Instruments
 *
 * Author: Milo(Woogyom) Kim <milo.kim@ti.com>
 */

#include <linux/module.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/regulator/driver.h>
#include <linux/gpio/consumer.h>
#include <linux/mfd/lp8788.h>

/* register address */
#define LP8788_EN_LDO_A			0x0D	/* DLDO 1 ~ 8 */
#define LP8788_EN_LDO_B			0x0E	/* DLDO 9 ~ 12, ALDO 1 ~ 4 */
#define LP8788_EN_LDO_C			0x0F	/* ALDO 5 ~ 10 */
#define LP8788_EN_SEL			0x10
#define LP8788_DLDO1_VOUT		0x2E
#define LP8788_DLDO2_VOUT		0x2F
#define LP8788_DLDO3_VOUT		0x30
#define LP8788_DLDO4_VOUT		0x31
#define LP8788_DLDO5_VOUT		0x32
#define LP8788_DLDO6_VOUT		0x33
#define LP8788_DLDO7_VOUT		0x34
#define LP8788_DLDO8_VOUT		0x35
#define LP8788_DLDO9_VOUT		0x36
#define LP8788_DLDO10_VOUT		0x37
#define LP8788_DLDO11_VOUT		0x38
#define LP8788_DLDO12_VOUT		0x39
#define LP8788_ALDO1_VOUT		0x3A
#define LP8788_ALDO2_VOUT		0x3B
#define LP8788_ALDO3_VOUT		0x3C
#define LP8788_ALDO4_VOUT		0x3D
#define LP8788_ALDO5_VOUT		0x3E
#define LP8788_ALDO6_VOUT		0x3F
#define LP8788_ALDO7_VOUT		0x40
#define LP8788_ALDO8_VOUT		0x41
#define LP8788_ALDO9_VOUT		0x42
#define LP8788_ALDO10_VOUT		0x43
#define LP8788_DLDO1_TIMESTEP		0x44

/* mask/shift bits */
#define LP8788_EN_DLDO1_M		BIT(0)	/* Addr 0Dh ~ 0Fh */
#define LP8788_EN_DLDO2_M		BIT(1)
#define LP8788_EN_DLDO3_M		BIT(2)
#define LP8788_EN_DLDO4_M		BIT(3)
#define LP8788_EN_DLDO5_M		BIT(4)
#define LP8788_EN_DLDO6_M		BIT(5)
#define LP8788_EN_DLDO7_M		BIT(6)
#define LP8788_EN_DLDO8_M		BIT(7)
#define LP8788_EN_DLDO9_M		BIT(0)
#define LP8788_EN_DLDO10_M		BIT(1)
#define LP8788_EN_DLDO11_M		BIT(2)
#define LP8788_EN_DLDO12_M		BIT(3)
#define LP8788_EN_ALDO1_M		BIT(4)
#define LP8788_EN_ALDO2_M		BIT(5)
#define LP8788_EN_ALDO3_M		BIT(6)
#define LP8788_EN_ALDO4_M		BIT(7)
#define LP8788_EN_ALDO5_M		BIT(0)
#define LP8788_EN_ALDO6_M		BIT(1)
#define LP8788_EN_ALDO7_M		BIT(2)
#define LP8788_EN_ALDO8_M		BIT(3)
#define LP8788_EN_ALDO9_M		BIT(4)
#define LP8788_EN_ALDO10_M		BIT(5)
#define LP8788_EN_SEL_DLDO911_M		BIT(0)	/* Addr 10h */
#define LP8788_EN_SEL_DLDO7_M		BIT(1)
#define LP8788_EN_SEL_ALDO7_M		BIT(2)
#define LP8788_EN_SEL_ALDO5_M		BIT(3)
#define LP8788_EN_SEL_ALDO234_M		BIT(4)
#define LP8788_EN_SEL_ALDO1_M		BIT(5)
#define LP8788_VOUT_5BIT_M		0x1F	/* Addr 2Eh ~ 43h */
#define LP8788_VOUT_4BIT_M		0x0F
#define LP8788_VOUT_3BIT_M		0x07
#define LP8788_VOUT_1BIT_M		0x01
#define LP8788_STARTUP_TIME_M		0xF8	/* Addr 44h ~ 59h */
#define LP8788_STARTUP_TIME_S		3

#define ENABLE_TIME_USEC		32

enum lp8788_ldo_id {
	DLDO1,
	DLDO2,
	DLDO3,
	DLDO4,
	DLDO5,
	DLDO6,
	DLDO7,
	DLDO8,
	DLDO9,
	DLDO10,
	DLDO11,
	DLDO12,
	ALDO1,
	ALDO2,
	ALDO3,
	ALDO4,
	ALDO5,
	ALDO6,
	ALDO7,
	ALDO8,
	ALDO9,
	ALDO10,
};

struct lp8788_ldo {
	struct lp8788 *lp;
	struct regulator_desc *desc;
	struct regulator_dev *regulator;
	struct gpio_desc *ena_gpiod;
};

/* DLDO 1, 2, 3, 9 voltage table */
static const int lp8788_dldo1239_vtbl[] = {
	1800000, 1900000, 2000000, 2100000, 2200000, 2300000, 2400000, 2500000,
	2600000, 2700000, 2800000, 2900000, 3000000, 2850000, 2850000, 2850000,
	2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000,
	2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000,
};

/* DLDO 4 voltage table */
static const int lp8788_dldo4_vtbl[] = { 1800000, 3000000 };

/* DLDO 5, 7, 8 and ALDO 6 voltage table */
static const int lp8788_dldo578_aldo6_vtbl[] = {
	1800000, 1900000, 2000000, 2100000, 2200000, 2300000, 2400000, 2500000,
	2600000, 2700000, 2800000, 2900000, 3000000, 3000000, 3000000, 3000000,
};

/* DLDO 6 voltage table */
static const int lp8788_dldo6_vtbl[] = {
	3000000, 3100000, 3200000, 3300000, 3400000, 3500000, 3600000, 3600000,
};

/* DLDO 10, 11 voltage table */
static const int lp8788_dldo1011_vtbl[] = {
	1100000, 1150000, 1200000, 1250000, 1300000, 1350000, 1400000, 1450000,
	1500000, 1500000, 1500000, 1500000, 1500000, 1500000, 1500000, 1500000,
};

/* ALDO 1 voltage table */
static const int lp8788_aldo1_vtbl[] = { 1800000, 2850000 };

/* ALDO 7 voltage table */
static const int lp8788_aldo7_vtbl[] = {
	1200000, 1300000, 1400000, 1500000, 1600000, 1700000, 1800000, 1800000,
};

static int lp8788_ldo_enable_time(struct regulator_dev *rdev)
{
	struct lp8788_ldo *ldo = rdev_get_drvdata(rdev);
	enum lp8788_ldo_id id = rdev_get_id(rdev);
	u8 val, addr = LP8788_DLDO1_TIMESTEP + id;

	if (lp8788_read_byte(ldo->lp, addr, &val))
		return -EINVAL;

	val = (val & LP8788_STARTUP_TIME_M) >> LP8788_STARTUP_TIME_S;

	return ENABLE_TIME_USEC * val;
}

static const struct regulator_ops lp8788_ldo_voltage_table_ops = {
	.list_voltage = regulator_list_voltage_table,
	.set_voltage_sel = regulator_set_voltage_sel_regmap,
	.get_voltage_sel = regulator_get_voltage_sel_regmap,
	.enable = regulator_enable_regmap,
	.disable = regulator_disable_regmap,
	.is_enabled = regulator_is_enabled_regmap,
	.enable_time = lp8788_ldo_enable_time,
};

static const struct regulator_ops lp8788_ldo_voltage_fixed_ops = {
	.list_voltage = regulator_list_voltage_linear,
	.enable = regulator_enable_regmap,
	.disable = regulator_disable_regmap,
	.is_enabled = regulator_is_enabled_regmap,
	.enable_time = lp8788_ldo_enable_time,
};

static const struct regulator_desc lp8788_dldo_desc[] = {
	{
		.name = "dldo1",
		.id = DLDO1,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
		.volt_table = lp8788_dldo1239_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_DLDO1_VOUT,
		.vsel_mask = LP8788_VOUT_5BIT_M,
		.enable_reg = LP8788_EN_LDO_A,
		.enable_mask = LP8788_EN_DLDO1_M,
	},
	{
		.name = "dldo2",
		.id = DLDO2,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
		.volt_table = lp8788_dldo1239_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_DLDO2_VOUT,
		.vsel_mask = LP8788_VOUT_5BIT_M,
		.enable_reg = LP8788_EN_LDO_A,
		.enable_mask = LP8788_EN_DLDO2_M,
	},
	{
		.name = "dldo3",
		.id = DLDO3,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
		.volt_table = lp8788_dldo1239_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_DLDO3_VOUT,
		.vsel_mask = LP8788_VOUT_5BIT_M,
		.enable_reg = LP8788_EN_LDO_A,
		.enable_mask = LP8788_EN_DLDO3_M,
	},
	{
		.name = "dldo4",
		.id = DLDO4,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_dldo4_vtbl),
		.volt_table = lp8788_dldo4_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_DLDO4_VOUT,
		.vsel_mask = LP8788_VOUT_1BIT_M,
		.enable_reg = LP8788_EN_LDO_A,
		.enable_mask = LP8788_EN_DLDO4_M,
	},
	{
		.name = "dldo5",
		.id = DLDO5,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
		.volt_table = lp8788_dldo578_aldo6_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_DLDO5_VOUT,
		.vsel_mask = LP8788_VOUT_4BIT_M,
		.enable_reg = LP8788_EN_LDO_A,
		.enable_mask = LP8788_EN_DLDO5_M,
	},
	{
		.name = "dldo6",
		.id = DLDO6,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_dldo6_vtbl),
		.volt_table = lp8788_dldo6_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_DLDO6_VOUT,
		.vsel_mask = LP8788_VOUT_3BIT_M,
		.enable_reg = LP8788_EN_LDO_A,
		.enable_mask = LP8788_EN_DLDO6_M,
	},
	{
		.name = "dldo7",
		.id = DLDO7,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
		.volt_table = lp8788_dldo578_aldo6_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_DLDO7_VOUT,
		.vsel_mask = LP8788_VOUT_4BIT_M,
		.enable_reg = LP8788_EN_LDO_A,
		.enable_mask = LP8788_EN_DLDO7_M,
	},
	{
		.name = "dldo8",
		.id = DLDO8,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
		.volt_table = lp8788_dldo578_aldo6_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_DLDO8_VOUT,
		.vsel_mask = LP8788_VOUT_4BIT_M,
		.enable_reg = LP8788_EN_LDO_A,
		.enable_mask = LP8788_EN_DLDO8_M,
	},
	{
		.name = "dldo9",
		.id = DLDO9,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
		.volt_table = lp8788_dldo1239_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_DLDO9_VOUT,
		.vsel_mask = LP8788_VOUT_5BIT_M,
		.enable_reg = LP8788_EN_LDO_B,
		.enable_mask = LP8788_EN_DLDO9_M,
	},
	{
		.name = "dldo10",
		.id = DLDO10,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_dldo1011_vtbl),
		.volt_table = lp8788_dldo1011_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_DLDO10_VOUT,
		.vsel_mask = LP8788_VOUT_4BIT_M,
		.enable_reg = LP8788_EN_LDO_B,
		.enable_mask = LP8788_EN_DLDO10_M,
	},
	{
		.name = "dldo11",
		.id = DLDO11,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_dldo1011_vtbl),
		.volt_table = lp8788_dldo1011_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_DLDO11_VOUT,
		.vsel_mask = LP8788_VOUT_4BIT_M,
		.enable_reg = LP8788_EN_LDO_B,
		.enable_mask = LP8788_EN_DLDO11_M,
	},
	{
		.name = "dldo12",
		.id = DLDO12,
		.ops = &lp8788_ldo_voltage_fixed_ops,
		.n_voltages = 1,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.enable_reg = LP8788_EN_LDO_B,
		.enable_mask = LP8788_EN_DLDO12_M,
		.min_uV = 2500000,
	},
};

static const struct regulator_desc lp8788_aldo_desc[] = {
	{
		.name = "aldo1",
		.id = ALDO1,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_aldo1_vtbl),
		.volt_table = lp8788_aldo1_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_ALDO1_VOUT,
		.vsel_mask = LP8788_VOUT_1BIT_M,
		.enable_reg = LP8788_EN_LDO_B,
		.enable_mask = LP8788_EN_ALDO1_M,
	},
	{
		.name = "aldo2",
		.id = ALDO2,
		.ops = &lp8788_ldo_voltage_fixed_ops,
		.n_voltages = 1,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.enable_reg = LP8788_EN_LDO_B,
		.enable_mask = LP8788_EN_ALDO2_M,
		.min_uV = 2850000,
	},
	{
		.name = "aldo3",
		.id = ALDO3,
		.ops = &lp8788_ldo_voltage_fixed_ops,
		.n_voltages = 1,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.enable_reg = LP8788_EN_LDO_B,
		.enable_mask = LP8788_EN_ALDO3_M,
		.min_uV = 2850000,
	},
	{
		.name = "aldo4",
		.id = ALDO4,
		.ops = &lp8788_ldo_voltage_fixed_ops,
		.n_voltages = 1,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.enable_reg = LP8788_EN_LDO_B,
		.enable_mask = LP8788_EN_ALDO4_M,
		.min_uV = 2850000,
	},
	{
		.name = "aldo5",
		.id = ALDO5,
		.ops = &lp8788_ldo_voltage_fixed_ops,
		.n_voltages = 1,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.enable_reg = LP8788_EN_LDO_C,
		.enable_mask = LP8788_EN_ALDO5_M,
		.min_uV = 2850000,
	},
	{
		.name = "aldo6",
		.id = ALDO6,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
		.volt_table = lp8788_dldo578_aldo6_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_ALDO6_VOUT,
		.vsel_mask = LP8788_VOUT_4BIT_M,
		.enable_reg = LP8788_EN_LDO_C,
		.enable_mask = LP8788_EN_ALDO6_M,
	},
	{
		.name = "aldo7",
		.id = ALDO7,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_aldo7_vtbl),
		.volt_table = lp8788_aldo7_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_ALDO7_VOUT,
		.vsel_mask = LP8788_VOUT_3BIT_M,
		.enable_reg = LP8788_EN_LDO_C,
		.enable_mask = LP8788_EN_ALDO7_M,
	},
	{
		.name = "aldo8",
		.id = ALDO8,
		.ops = &lp8788_ldo_voltage_fixed_ops,
		.n_voltages = 1,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.enable_reg = LP8788_EN_LDO_C,
		.enable_mask = LP8788_EN_ALDO8_M,
		.min_uV = 2500000,
	},
	{
		.name = "aldo9",
		.id = ALDO9,
		.ops = &lp8788_ldo_voltage_fixed_ops,
		.n_voltages = 1,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.enable_reg = LP8788_EN_LDO_C,
		.enable_mask = LP8788_EN_ALDO9_M,
		.min_uV = 2500000,
	},
	{
		.name = "aldo10",
		.id = ALDO10,
		.ops = &lp8788_ldo_voltage_fixed_ops,
		.n_voltages = 1,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.enable_reg = LP8788_EN_LDO_C,
		.enable_mask = LP8788_EN_ALDO10_M,
		.min_uV = 1100000,
	},
};

static int lp8788_config_ldo_enable_mode(struct platform_device *pdev,
					struct lp8788_ldo *ldo,
					enum lp8788_ldo_id id)
{
	struct lp8788 *lp = ldo->lp;
	enum lp8788_ext_ldo_en_id enable_id;
	u8 en_mask[] = {
		[EN_ALDO1]   = LP8788_EN_SEL_ALDO1_M,
		[EN_ALDO234] = LP8788_EN_SEL_ALDO234_M,
		[EN_ALDO5]   = LP8788_EN_SEL_ALDO5_M,
		[EN_ALDO7]   = LP8788_EN_SEL_ALDO7_M,
		[EN_DLDO7]   = LP8788_EN_SEL_DLDO7_M,
		[EN_DLDO911] = LP8788_EN_SEL_DLDO911_M,
	};

	switch (id) {
	case DLDO7:
		enable_id = EN_DLDO7;
		break;
	case DLDO9:
	case DLDO11:
		enable_id = EN_DLDO911;
		break;
	case ALDO1:
		enable_id = EN_ALDO1;
		break;
	case ALDO2 ... ALDO4:
		enable_id = EN_ALDO234;
		break;
	case ALDO5:
		enable_id = EN_ALDO5;
		break;
	case ALDO7:
		enable_id = EN_ALDO7;
		break;
	default:
		return 0;
	}

	/*
	 * Do not use devm* here: the regulator core takes over the
	 * lifecycle management of the GPIO descriptor.
	 * FIXME: check default mode for GPIO here: high or low?
	 */
	ldo->ena_gpiod = gpiod_get_index_optional(&pdev->dev,
					       "enable",
					       enable_id,
					       GPIOD_OUT_HIGH |
					       GPIOD_FLAGS_BIT_NONEXCLUSIVE);
	if (IS_ERR(ldo->ena_gpiod))
		return PTR_ERR(ldo->ena_gpiod);

	/* if no GPIO for ldo pin, then set default enable mode */
	if (!ldo->ena_gpiod)
		goto set_default_ldo_enable_mode;

	return 0;

set_default_ldo_enable_mode:
	return lp8788_update_bits(lp, LP8788_EN_SEL, en_mask[enable_id], 0);
}

static int lp8788_dldo_probe(struct platform_device *pdev)
{
	struct lp8788 *lp = dev_get_drvdata(pdev->dev.parent);
	int id = pdev->id;
	struct lp8788_ldo *ldo;
	struct regulator_config cfg = { };
	struct regulator_dev *rdev;
	int ret;

	ldo = devm_kzalloc(&pdev->dev, sizeof(struct lp8788_ldo), GFP_KERNEL);
	if (!ldo)
		return -ENOMEM;

	ldo->lp = lp;
	ret = lp8788_config_ldo_enable_mode(pdev, ldo, id);
	if (ret)
		return ret;

	if (ldo->ena_gpiod)
		cfg.ena_gpiod = ldo->ena_gpiod;

	cfg.dev = pdev->dev.parent;
	cfg.init_data = lp->pdata ? lp->pdata->dldo_data[id] : NULL;
	cfg.driver_data = ldo;
	cfg.regmap = lp->regmap;

	rdev = devm_regulator_register(&pdev->dev, &lp8788_dldo_desc[id], &cfg);
	if (IS_ERR(rdev)) {
		ret = PTR_ERR(rdev);
		dev_err(&pdev->dev, "DLDO%d regulator register err = %d\n",
				id + 1, ret);
		return ret;
	}

	ldo->regulator = rdev;
	platform_set_drvdata(pdev, ldo);

	return 0;
}

static struct platform_driver lp8788_dldo_driver = {
	.probe = lp8788_dldo_probe,
	.driver = {
		.name = LP8788_DEV_DLDO,
	},
};

static int lp8788_aldo_probe(struct platform_device *pdev)
{
	struct lp8788 *lp = dev_get_drvdata(pdev->dev.parent);
	int id = pdev->id;
	struct lp8788_ldo *ldo;
	struct regulator_config cfg = { };
	struct regulator_dev *rdev;
	int ret;

	ldo = devm_kzalloc(&pdev->dev, sizeof(struct lp8788_ldo), GFP_KERNEL);
	if (!ldo)
		return -ENOMEM;

	ldo->lp = lp;
	ret = lp8788_config_ldo_enable_mode(pdev, ldo, id + ALDO1);
	if (ret)
		return ret;

	if (ldo->ena_gpiod)
		cfg.ena_gpiod = ldo->ena_gpiod;

	cfg.dev = pdev->dev.parent;
	cfg.init_data = lp->pdata ? lp->pdata->aldo_data[id] : NULL;
	cfg.driver_data = ldo;
	cfg.regmap = lp->regmap;

	rdev = devm_regulator_register(&pdev->dev, &lp8788_aldo_desc[id], &cfg);
	if (IS_ERR(rdev)) {
		ret = PTR_ERR(rdev);
		dev_err(&pdev->dev, "ALDO%d regulator register err = %d\n",
				id + 1, ret);
		return ret;
	}

	ldo->regulator = rdev;
	platform_set_drvdata(pdev, ldo);

	return 0;
}

static struct platform_driver lp8788_aldo_driver = {
	.probe = lp8788_aldo_probe,
	.driver = {
		.name = LP8788_DEV_ALDO,
	},
};

static struct platform_driver * const drivers[] = {
	&lp8788_dldo_driver,
	&lp8788_aldo_driver,
};

static int __init lp8788_ldo_init(void)
{
	return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
}
subsys_initcall(lp8788_ldo_init);

static void __exit lp8788_ldo_exit(void)
{
	platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
}
module_exit(lp8788_ldo_exit);

MODULE_DESCRIPTION("TI LP8788 LDO Driver");
MODULE_AUTHOR("Milo Kim");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:lp8788-dldo");
MODULE_ALIAS("platform:lp8788-aldo");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
ade7515f KM	2	/*
	3	* TI LP8788 MFD - ldo regulator driver
	4	*
	5	* Copyright 2012 Texas Instruments
	6	*
	7	* Author: Milo(Woogyom) Kim <milo.kim@ti.com>
ade7515f KM	8	*/
	9
	10	#include <linux/module.h>
	11	#include <linux/slab.h>
	12	#include <linux/err.h>
	13	#include <linux/platform_device.h>
	14	#include <linux/regulator/driver.h>
2468f0d5	15	#include <linux/gpio/consumer.h>
ade7515f KM	16	#include <linux/mfd/lp8788.h>
	17
	18	/* register address */
	19	#define LP8788_EN_LDO_A 0x0D /* DLDO 1 ~ 8 */
	20	#define LP8788_EN_LDO_B 0x0E /* DLDO 9 ~ 12, ALDO 1 ~ 4 */
	21	#define LP8788_EN_LDO_C 0x0F /* ALDO 5 ~ 10 */
	22	#define LP8788_EN_SEL 0x10
	23	#define LP8788_DLDO1_VOUT 0x2E
	24	#define LP8788_DLDO2_VOUT 0x2F
	25	#define LP8788_DLDO3_VOUT 0x30
	26	#define LP8788_DLDO4_VOUT 0x31
	27	#define LP8788_DLDO5_VOUT 0x32
	28	#define LP8788_DLDO6_VOUT 0x33
	29	#define LP8788_DLDO7_VOUT 0x34
	30	#define LP8788_DLDO8_VOUT 0x35
	31	#define LP8788_DLDO9_VOUT 0x36
	32	#define LP8788_DLDO10_VOUT 0x37
	33	#define LP8788_DLDO11_VOUT 0x38
	34	#define LP8788_DLDO12_VOUT 0x39
	35	#define LP8788_ALDO1_VOUT 0x3A
	36	#define LP8788_ALDO2_VOUT 0x3B
	37	#define LP8788_ALDO3_VOUT 0x3C
	38	#define LP8788_ALDO4_VOUT 0x3D
	39	#define LP8788_ALDO5_VOUT 0x3E
	40	#define LP8788_ALDO6_VOUT 0x3F
	41	#define LP8788_ALDO7_VOUT 0x40
	42	#define LP8788_ALDO8_VOUT 0x41
	43	#define LP8788_ALDO9_VOUT 0x42
	44	#define LP8788_ALDO10_VOUT 0x43
	45	#define LP8788_DLDO1_TIMESTEP 0x44
	46
	47	/* mask/shift bits */
	48	#define LP8788_EN_DLDO1_M BIT(0) /* Addr 0Dh ~ 0Fh */
	49	#define LP8788_EN_DLDO2_M BIT(1)
	50	#define LP8788_EN_DLDO3_M BIT(2)
	51	#define LP8788_EN_DLDO4_M BIT(3)
	52	#define LP8788_EN_DLDO5_M BIT(4)
	53	#define LP8788_EN_DLDO6_M BIT(5)
	54	#define LP8788_EN_DLDO7_M BIT(6)
	55	#define LP8788_EN_DLDO8_M BIT(7)
	56	#define LP8788_EN_DLDO9_M BIT(0)
	57	#define LP8788_EN_DLDO10_M BIT(1)
	58	#define LP8788_EN_DLDO11_M BIT(2)
	59	#define LP8788_EN_DLDO12_M BIT(3)
	60	#define LP8788_EN_ALDO1_M BIT(4)
	61	#define LP8788_EN_ALDO2_M BIT(5)
	62	#define LP8788_EN_ALDO3_M BIT(6)
	63	#define LP8788_EN_ALDO4_M BIT(7)
	64	#define LP8788_EN_ALDO5_M BIT(0)
	65	#define LP8788_EN_ALDO6_M BIT(1)
	66	#define LP8788_EN_ALDO7_M BIT(2)
	67	#define LP8788_EN_ALDO8_M BIT(3)
	68	#define LP8788_EN_ALDO9_M BIT(4)
	69	#define LP8788_EN_ALDO10_M BIT(5)
	70	#define LP8788_EN_SEL_DLDO911_M BIT(0) /* Addr 10h */
	71	#define LP8788_EN_SEL_DLDO7_M BIT(1)
	72	#define LP8788_EN_SEL_ALDO7_M BIT(2)
	73	#define LP8788_EN_SEL_ALDO5_M BIT(3)
	74	#define LP8788_EN_SEL_ALDO234_M BIT(4)
	75	#define LP8788_EN_SEL_ALDO1_M BIT(5)
	76	#define LP8788_VOUT_5BIT_M 0x1F /* Addr 2Eh ~ 43h */
	77	#define LP8788_VOUT_4BIT_M 0x0F
	78	#define LP8788_VOUT_3BIT_M 0x07
	79	#define LP8788_VOUT_1BIT_M 0x01
80	#define LP8788_STARTUP_TIME_M 0xF8 /* Addr 44h ~ 59h */
81	#define LP8788_STARTUP_TIME_S 3
82
83	#define ENABLE_TIME_USEC 32
ade7515f	84
ade7515f KM	85	enum lp8788_ldo_id {
	86	DLDO1,
	87	DLDO2,
	88	DLDO3,
	89	DLDO4,
	90	DLDO5,
	91	DLDO6,
	92	DLDO7,
	93	DLDO8,
	94	DLDO9,
	95	DLDO10,
	96	DLDO11,
	97	DLDO12,
	98	ALDO1,
	99	ALDO2,
	100	ALDO3,
	101	ALDO4,
	102	ALDO5,
	103	ALDO6,
	104	ALDO7,
	105	ALDO8,
	106	ALDO9,
	107	ALDO10,
	108	};
	109
	110	struct lp8788_ldo {
	111	struct lp8788 *lp;
	112	struct regulator_desc *desc;
	113	struct regulator_dev *regulator;
2468f0d5	114	struct gpio_desc *ena_gpiod;
ade7515f KM	115	};
	116
	117	/* DLDO 1, 2, 3, 9 voltage table */
4e92920b	118	static const int lp8788_dldo1239_vtbl[] = {
ade7515f KM	119	1800000, 1900000, 2000000, 2100000, 2200000, 2300000, 2400000, 2500000,
	120	2600000, 2700000, 2800000, 2900000, 3000000, 2850000, 2850000, 2850000,
	121	2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000,
	122	2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000,
	123	};
	124
	125	/* DLDO 4 voltage table */
	126	static const int lp8788_dldo4_vtbl[] = { 1800000, 3000000 };
	127
	128	/* DLDO 5, 7, 8 and ALDO 6 voltage table */
	129	static const int lp8788_dldo578_aldo6_vtbl[] = {
	130	1800000, 1900000, 2000000, 2100000, 2200000, 2300000, 2400000, 2500000,
	131	2600000, 2700000, 2800000, 2900000, 3000000, 3000000, 3000000, 3000000,
	132	};
	133
	134	/* DLDO 6 voltage table */
	135	static const int lp8788_dldo6_vtbl[] = {
	136	3000000, 3100000, 3200000, 3300000, 3400000, 3500000, 3600000, 3600000,
	137	};
	138
	139	/* DLDO 10, 11 voltage table */
	140	static const int lp8788_dldo1011_vtbl[] = {
	141	1100000, 1150000, 1200000, 1250000, 1300000, 1350000, 1400000, 1450000,
	142	1500000, 1500000, 1500000, 1500000, 1500000, 1500000, 1500000, 1500000,
	143	};
	144
	145	/* ALDO 1 voltage table */
	146	static const int lp8788_aldo1_vtbl[] = { 1800000, 2850000 };
	147
	148	/* ALDO 7 voltage table */
	149	static const int lp8788_aldo7_vtbl[] = {
	150	1200000, 1300000, 1400000, 1500000, 1600000, 1700000, 1800000, 1800000,
	151	};
	152
ade7515f KM	153	static int lp8788_ldo_enable_time(struct regulator_dev *rdev)
	154	{
	155	struct lp8788_ldo *ldo = rdev_get_drvdata(rdev);
	156	enum lp8788_ldo_id id = rdev_get_id(rdev);
	157	u8 val, addr = LP8788_DLDO1_TIMESTEP + id;
	158
	159	if (lp8788_read_byte(ldo->lp, addr, &val))
	160	return -EINVAL;
	161
	162	val = (val & LP8788_STARTUP_TIME_M) >> LP8788_STARTUP_TIME_S;
	163
	164	return ENABLE_TIME_USEC * val;
	165	}
	166
95dfead1	167	static const struct regulator_ops lp8788_ldo_voltage_table_ops = {
ade7515f KM	168	.list_voltage = regulator_list_voltage_table,
	169	.set_voltage_sel = regulator_set_voltage_sel_regmap,
	170	.get_voltage_sel = regulator_get_voltage_sel_regmap,
407945fd KM	171	.enable = regulator_enable_regmap,
	172	.disable = regulator_disable_regmap,
	173	.is_enabled = regulator_is_enabled_regmap,
ade7515f KM	174	.enable_time = lp8788_ldo_enable_time,
	175	};
	176
95dfead1	177	static const struct regulator_ops lp8788_ldo_voltage_fixed_ops = {
b5366e5e	178	.list_voltage = regulator_list_voltage_linear,
407945fd KM	179	.enable = regulator_enable_regmap,
	180	.disable = regulator_disable_regmap,
	181	.is_enabled = regulator_is_enabled_regmap,
ade7515f KM	182	.enable_time = lp8788_ldo_enable_time,
	183	};
	184
23295d79	185	static const struct regulator_desc lp8788_dldo_desc[] = {
ade7515f KM	186	{
	187	.name = "dldo1",
	188	.id = DLDO1,
	189	.ops = &lp8788_ldo_voltage_table_ops,
	190	.n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
	191	.volt_table = lp8788_dldo1239_vtbl,
	192	.type = REGULATOR_VOLTAGE,
	193	.owner = THIS_MODULE,
	194	.vsel_reg = LP8788_DLDO1_VOUT,
	195	.vsel_mask = LP8788_VOUT_5BIT_M,
	196	.enable_reg = LP8788_EN_LDO_A,
	197	.enable_mask = LP8788_EN_DLDO1_M,
	198	},
	199	{
	200	.name = "dldo2",
	201	.id = DLDO2,
	202	.ops = &lp8788_ldo_voltage_table_ops,
	203	.n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
	204	.volt_table = lp8788_dldo1239_vtbl,
	205	.type = REGULATOR_VOLTAGE,
	206	.owner = THIS_MODULE,
	207	.vsel_reg = LP8788_DLDO2_VOUT,
	208	.vsel_mask = LP8788_VOUT_5BIT_M,
	209	.enable_reg = LP8788_EN_LDO_A,
	210	.enable_mask = LP8788_EN_DLDO2_M,
	211	},
	212	{
	213	.name = "dldo3",
	214	.id = DLDO3,
	215	.ops = &lp8788_ldo_voltage_table_ops,
	216	.n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
	217	.volt_table = lp8788_dldo1239_vtbl,
	218	.type = REGULATOR_VOLTAGE,
	219	.owner = THIS_MODULE,
	220	.vsel_reg = LP8788_DLDO3_VOUT,
	221	.vsel_mask = LP8788_VOUT_5BIT_M,
	222	.enable_reg = LP8788_EN_LDO_A,
	223	.enable_mask = LP8788_EN_DLDO3_M,
	224	},
	225	{
	226	.name = "dldo4",
	227	.id = DLDO4,
	228	.ops = &lp8788_ldo_voltage_table_ops,
	229	.n_voltages = ARRAY_SIZE(lp8788_dldo4_vtbl),
	230	.volt_table = lp8788_dldo4_vtbl,
	231	.type = REGULATOR_VOLTAGE,
	232	.owner = THIS_MODULE,
	233	.vsel_reg = LP8788_DLDO4_VOUT,
	234	.vsel_mask = LP8788_VOUT_1BIT_M,
	235	.enable_reg = LP8788_EN_LDO_A,
	236	.enable_mask = LP8788_EN_DLDO4_M,
	237	},
	238	{
	239	.name = "dldo5",
	240	.id = DLDO5,
	241	.ops = &lp8788_ldo_voltage_table_ops,
	242	.n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
	243	.volt_table = lp8788_dldo578_aldo6_vtbl,
	244	.type = REGULATOR_VOLTAGE,
	245	.owner = THIS_MODULE,
	246	.vsel_reg = LP8788_DLDO5_VOUT,
	247	.vsel_mask = LP8788_VOUT_4BIT_M,
	248	.enable_reg = LP8788_EN_LDO_A,
	249	.enable_mask = LP8788_EN_DLDO5_M,
250	},
251	{
252	.name = "dldo6",
253	.id = DLDO6,
254	.ops = &lp8788_ldo_voltage_table_ops,
255	.n_voltages = ARRAY_SIZE(lp8788_dldo6_vtbl),
256	.volt_table = lp8788_dldo6_vtbl,
257	.type = REGULATOR_VOLTAGE,
258	.owner = THIS_MODULE,
259	.vsel_reg = LP8788_DLDO6_VOUT,
260	.vsel_mask = LP8788_VOUT_3BIT_M,
261	.enable_reg = LP8788_EN_LDO_A,
262	.enable_mask = LP8788_EN_DLDO6_M,
263	},
264	{
265	.name = "dldo7",
266	.id = DLDO7,
267	.ops = &lp8788_ldo_voltage_table_ops,
268	.n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
269	.volt_table = lp8788_dldo578_aldo6_vtbl,
270	.type = REGULATOR_VOLTAGE,
271	.owner = THIS_MODULE,
272	.vsel_reg = LP8788_DLDO7_VOUT,
273	.vsel_mask = LP8788_VOUT_4BIT_M,
274	.enable_reg = LP8788_EN_LDO_A,
275	.enable_mask = LP8788_EN_DLDO7_M,
276	},
277	{
278	.name = "dldo8",
279	.id = DLDO8,
280	.ops = &lp8788_ldo_voltage_table_ops,
281	.n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
282	.volt_table = lp8788_dldo578_aldo6_vtbl,
283	.type = REGULATOR_VOLTAGE,
284	.owner = THIS_MODULE,
285	.vsel_reg = LP8788_DLDO8_VOUT,
286	.vsel_mask = LP8788_VOUT_4BIT_M,
287	.enable_reg = LP8788_EN_LDO_A,
288	.enable_mask = LP8788_EN_DLDO8_M,
289	},
290	{
291	.name = "dldo9",
292	.id = DLDO9,
293	.ops = &lp8788_ldo_voltage_table_ops,
294	.n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
295	.volt_table = lp8788_dldo1239_vtbl,
296	.type = REGULATOR_VOLTAGE,
297	.owner = THIS_MODULE,
298	.vsel_reg = LP8788_DLDO9_VOUT,
299	.vsel_mask = LP8788_VOUT_5BIT_M,
300	.enable_reg = LP8788_EN_LDO_B,
301	.enable_mask = LP8788_EN_DLDO9_M,
302	},
303	{
304	.name = "dldo10",
305	.id = DLDO10,
306	.ops = &lp8788_ldo_voltage_table_ops,
307	.n_voltages = ARRAY_SIZE(lp8788_dldo1011_vtbl),
308	.volt_table = lp8788_dldo1011_vtbl,
309	.type = REGULATOR_VOLTAGE,
310	.owner = THIS_MODULE,
311	.vsel_reg = LP8788_DLDO10_VOUT,
312	.vsel_mask = LP8788_VOUT_4BIT_M,
313	.enable_reg = LP8788_EN_LDO_B,
314	.enable_mask = LP8788_EN_DLDO10_M,
315	},
316	{
317	.name = "dldo11",
318	.id = DLDO11,
319	.ops = &lp8788_ldo_voltage_table_ops,
320	.n_voltages = ARRAY_SIZE(lp8788_dldo1011_vtbl),
321	.volt_table = lp8788_dldo1011_vtbl,
322	.type = REGULATOR_VOLTAGE,
323	.owner = THIS_MODULE,
324	.vsel_reg = LP8788_DLDO11_VOUT,
325	.vsel_mask = LP8788_VOUT_4BIT_M,
326	.enable_reg = LP8788_EN_LDO_B,
327	.enable_mask = LP8788_EN_DLDO11_M,
328	},
329	{
330	.name = "dldo12",
331	.id = DLDO12,
332	.ops = &lp8788_ldo_voltage_fixed_ops,
74c8cfda	333	.n_voltages = 1,
ade7515f KM	334	.type = REGULATOR_VOLTAGE,
	335	.owner = THIS_MODULE,
	336	.enable_reg = LP8788_EN_LDO_B,
	337	.enable_mask = LP8788_EN_DLDO12_M,
b5366e5e	338	.min_uV = 2500000,
ade7515f KM	339	},
	340	};
	341
23295d79	342	static const struct regulator_desc lp8788_aldo_desc[] = {
ade7515f KM	343	{
	344	.name = "aldo1",
	345	.id = ALDO1,
	346	.ops = &lp8788_ldo_voltage_table_ops,
	347	.n_voltages = ARRAY_SIZE(lp8788_aldo1_vtbl),
	348	.volt_table = lp8788_aldo1_vtbl,
	349	.type = REGULATOR_VOLTAGE,
	350	.owner = THIS_MODULE,
	351	.vsel_reg = LP8788_ALDO1_VOUT,
	352	.vsel_mask = LP8788_VOUT_1BIT_M,
	353	.enable_reg = LP8788_EN_LDO_B,
	354	.enable_mask = LP8788_EN_ALDO1_M,
	355	},
	356	{
	357	.name = "aldo2",
	358	.id = ALDO2,
	359	.ops = &lp8788_ldo_voltage_fixed_ops,
74c8cfda	360	.n_voltages = 1,
ade7515f KM	361	.type = REGULATOR_VOLTAGE,
	362	.owner = THIS_MODULE,
	363	.enable_reg = LP8788_EN_LDO_B,
	364	.enable_mask = LP8788_EN_ALDO2_M,
b5366e5e	365	.min_uV = 2850000,
ade7515f KM	366	},
	367	{
	368	.name = "aldo3",
	369	.id = ALDO3,
	370	.ops = &lp8788_ldo_voltage_fixed_ops,
74c8cfda	371	.n_voltages = 1,
ade7515f KM	372	.type = REGULATOR_VOLTAGE,
	373	.owner = THIS_MODULE,
	374	.enable_reg = LP8788_EN_LDO_B,
	375	.enable_mask = LP8788_EN_ALDO3_M,
b5366e5e	376	.min_uV = 2850000,
ade7515f KM	377	},
	378	{
	379	.name = "aldo4",
	380	.id = ALDO4,
	381	.ops = &lp8788_ldo_voltage_fixed_ops,
74c8cfda	382	.n_voltages = 1,
ade7515f KM	383	.type = REGULATOR_VOLTAGE,
	384	.owner = THIS_MODULE,
	385	.enable_reg = LP8788_EN_LDO_B,
	386	.enable_mask = LP8788_EN_ALDO4_M,
b5366e5e	387	.min_uV = 2850000,
ade7515f KM	388	},
	389	{
	390	.name = "aldo5",
	391	.id = ALDO5,
	392	.ops = &lp8788_ldo_voltage_fixed_ops,
74c8cfda	393	.n_voltages = 1,
ade7515f KM	394	.type = REGULATOR_VOLTAGE,
	395	.owner = THIS_MODULE,
	396	.enable_reg = LP8788_EN_LDO_C,
	397	.enable_mask = LP8788_EN_ALDO5_M,
b5366e5e	398	.min_uV = 2850000,
ade7515f KM	399	},
	400	{
	401	.name = "aldo6",
	402	.id = ALDO6,
	403	.ops = &lp8788_ldo_voltage_table_ops,
	404	.n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
	405	.volt_table = lp8788_dldo578_aldo6_vtbl,
	406	.type = REGULATOR_VOLTAGE,
	407	.owner = THIS_MODULE,
	408	.vsel_reg = LP8788_ALDO6_VOUT,
	409	.vsel_mask = LP8788_VOUT_4BIT_M,
	410	.enable_reg = LP8788_EN_LDO_C,
	411	.enable_mask = LP8788_EN_ALDO6_M,
	412	},
	413	{
	414	.name = "aldo7",
	415	.id = ALDO7,
	416	.ops = &lp8788_ldo_voltage_table_ops,
	417	.n_voltages = ARRAY_SIZE(lp8788_aldo7_vtbl),
	418	.volt_table = lp8788_aldo7_vtbl,
	419	.type = REGULATOR_VOLTAGE,
	420	.owner = THIS_MODULE,
	421	.vsel_reg = LP8788_ALDO7_VOUT,
	422	.vsel_mask = LP8788_VOUT_3BIT_M,
	423	.enable_reg = LP8788_EN_LDO_C,
	424	.enable_mask = LP8788_EN_ALDO7_M,
	425	},
	426	{
	427	.name = "aldo8",
	428	.id = ALDO8,
	429	.ops = &lp8788_ldo_voltage_fixed_ops,
74c8cfda	430	.n_voltages = 1,
ade7515f KM	431	.type = REGULATOR_VOLTAGE,
	432	.owner = THIS_MODULE,
	433	.enable_reg = LP8788_EN_LDO_C,
	434	.enable_mask = LP8788_EN_ALDO8_M,
b5366e5e	435	.min_uV = 2500000,
ade7515f KM	436	},
	437	{
	438	.name = "aldo9",
	439	.id = ALDO9,
	440	.ops = &lp8788_ldo_voltage_fixed_ops,
74c8cfda	441	.n_voltages = 1,
ade7515f KM	442	.type = REGULATOR_VOLTAGE,
	443	.owner = THIS_MODULE,
	444	.enable_reg = LP8788_EN_LDO_C,
	445	.enable_mask = LP8788_EN_ALDO9_M,
b5366e5e	446	.min_uV = 2500000,
ade7515f KM	447	},
	448	{
	449	.name = "aldo10",
	450	.id = ALDO10,
	451	.ops = &lp8788_ldo_voltage_fixed_ops,
74c8cfda	452	.n_voltages = 1,
ade7515f KM	453	.type = REGULATOR_VOLTAGE,
	454	.owner = THIS_MODULE,
	455	.enable_reg = LP8788_EN_LDO_C,
	456	.enable_mask = LP8788_EN_ALDO10_M,
b5366e5e	457	.min_uV = 1100000,
ade7515f KM	458	},
	459	};
	460
f02a3917 KM	461	static int lp8788_config_ldo_enable_mode(struct platform_device *pdev,
f02a3917 KM	462	struct lp8788_ldo *ldo,
ade7515f KM	463	enum lp8788_ldo_id id)
ade7515f KM	464	{
ade7515f	465	struct lp8788 *lp = ldo->lp;
ade7515f KM	466	enum lp8788_ext_ldo_en_id enable_id;
	467	u8 en_mask[] = {
	468	[EN_ALDO1] = LP8788_EN_SEL_ALDO1_M,
	469	[EN_ALDO234] = LP8788_EN_SEL_ALDO234_M,
	470	[EN_ALDO5] = LP8788_EN_SEL_ALDO5_M,
	471	[EN_ALDO7] = LP8788_EN_SEL_ALDO7_M,
	472	[EN_DLDO7] = LP8788_EN_SEL_DLDO7_M,
	473	[EN_DLDO911] = LP8788_EN_SEL_DLDO911_M,
	474	};
ade7515f KM	475
	476	switch (id) {
	477	case DLDO7:
	478	enable_id = EN_DLDO7;
	479	break;
	480	case DLDO9:
	481	case DLDO11:
	482	enable_id = EN_DLDO911;
	483	break;
	484	case ALDO1:
	485	enable_id = EN_ALDO1;
	486	break;
	487	case ALDO2 ... ALDO4:
	488	enable_id = EN_ALDO234;
	489	break;
	490	case ALDO5:
	491	enable_id = EN_ALDO5;
	492	break;
	493	case ALDO7:
	494	enable_id = EN_ALDO7;
	495	break;
	496	default:
	497	return 0;
	498	}
	499
2bb8ede0 LW	500	/*
	501	* Do not use devm* here: the regulator core takes over the
	502	* lifecycle management of the GPIO descriptor.
	503	* FIXME: check default mode for GPIO here: high or low?
	504	*/
	505	ldo->ena_gpiod = gpiod_get_index_optional(&pdev->dev,
63239e4b LW	506	"enable",
	507	enable_id,
	508	GPIOD_OUT_HIGH \|
	509	GPIOD_FLAGS_BIT_NONEXCLUSIVE);
2468f0d5 LW	510	if (IS_ERR(ldo->ena_gpiod))
	511	return PTR_ERR(ldo->ena_gpiod);
	512
	513	/* if no GPIO for ldo pin, then set default enable mode */
	514	if (!ldo->ena_gpiod)
ade7515f KM	515	goto set_default_ldo_enable_mode;
ade7515f KM	516
407945fd	517	return 0;
ade7515f KM	518
ade7515f KM	519	set_default_ldo_enable_mode:
40b5aa8f	520	return lp8788_update_bits(lp, LP8788_EN_SEL, en_mask[enable_id], 0);
ade7515f KM	521	}
ade7515f KM	522
a5023574	523	static int lp8788_dldo_probe(struct platform_device *pdev)
ade7515f KM	524	{
	525	struct lp8788 *lp = dev_get_drvdata(pdev->dev.parent);
	526	int id = pdev->id;
	527	struct lp8788_ldo *ldo;
	528	struct regulator_config cfg = { };
	529	struct regulator_dev *rdev;
	530	int ret;
	531
939e88f0	532	ldo = devm_kzalloc(&pdev->dev, sizeof(struct lp8788_ldo), GFP_KERNEL);
ade7515f KM	533	if (!ldo)
	534	return -ENOMEM;
	535
	536	ldo->lp = lp;
80abd60d	537	ret = lp8788_config_ldo_enable_mode(pdev, ldo, id);
ade7515f KM	538	if (ret)
	539	return ret;
	540
2468f0d5 LW	541	if (ldo->ena_gpiod)
2468f0d5 LW	542	cfg.ena_gpiod = ldo->ena_gpiod;
407945fd	543
939e88f0	544	cfg.dev = pdev->dev.parent;
ade7515f KM	545	cfg.init_data = lp->pdata ? lp->pdata->dldo_data[id] : NULL;
	546	cfg.driver_data = ldo;
	547	cfg.regmap = lp->regmap;
	548
0b7bb090	549	rdev = devm_regulator_register(&pdev->dev, &lp8788_dldo_desc[id], &cfg);
ade7515f KM	550	if (IS_ERR(rdev)) {
ade7515f KM	551	ret = PTR_ERR(rdev);
939e88f0	552	dev_err(&pdev->dev, "DLDO%d regulator register err = %d\n",
ade7515f KM	553	id + 1, ret);
	554	return ret;
	555	}
	556
	557	ldo->regulator = rdev;
	558	platform_set_drvdata(pdev, ldo);
	559
	560	return 0;
	561	}
	562
ade7515f KM	563	static struct platform_driver lp8788_dldo_driver = {
ade7515f KM	564	.probe = lp8788_dldo_probe,
ade7515f KM	565	.driver = {
ade7515f KM	566	.name = LP8788_DEV_DLDO,
ade7515f KM	567	},
	568	};
	569
a5023574	570	static int lp8788_aldo_probe(struct platform_device *pdev)
ade7515f KM	571	{
	572	struct lp8788 *lp = dev_get_drvdata(pdev->dev.parent);
	573	int id = pdev->id;
	574	struct lp8788_ldo *ldo;
	575	struct regulator_config cfg = { };
	576	struct regulator_dev *rdev;
	577	int ret;
	578
939e88f0	579	ldo = devm_kzalloc(&pdev->dev, sizeof(struct lp8788_ldo), GFP_KERNEL);
ade7515f KM	580	if (!ldo)
	581	return -ENOMEM;
	582
	583	ldo->lp = lp;
80abd60d	584	ret = lp8788_config_ldo_enable_mode(pdev, ldo, id + ALDO1);
ade7515f KM	585	if (ret)
	586	return ret;
	587
2468f0d5 LW	588	if (ldo->ena_gpiod)
2468f0d5 LW	589	cfg.ena_gpiod = ldo->ena_gpiod;
407945fd	590
939e88f0	591	cfg.dev = pdev->dev.parent;
ade7515f KM	592	cfg.init_data = lp->pdata ? lp->pdata->aldo_data[id] : NULL;
	593	cfg.driver_data = ldo;
	594	cfg.regmap = lp->regmap;
	595
0b7bb090	596	rdev = devm_regulator_register(&pdev->dev, &lp8788_aldo_desc[id], &cfg);
ade7515f KM	597	if (IS_ERR(rdev)) {
ade7515f KM	598	ret = PTR_ERR(rdev);
939e88f0	599	dev_err(&pdev->dev, "ALDO%d regulator register err = %d\n",
ade7515f KM	600	id + 1, ret);
	601	return ret;
	602	}
	603
	604	ldo->regulator = rdev;
	605	platform_set_drvdata(pdev, ldo);
	606
	607	return 0;
	608	}
	609
ade7515f KM	610	static struct platform_driver lp8788_aldo_driver = {
ade7515f KM	611	.probe = lp8788_aldo_probe,
ade7515f KM	612	.driver = {
ade7515f KM	613	.name = LP8788_DEV_ALDO,
ade7515f KM	614	},
	615	};
	616
7629cef1 TR	617	static struct platform_driver * const drivers[] = {
	618	&lp8788_dldo_driver,
	619	&lp8788_aldo_driver,
	620	};
	621
ade7515f KM	622	static int __init lp8788_ldo_init(void)
ade7515f KM	623	{
7629cef1	624	return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
ade7515f KM	625	}
	626	subsys_initcall(lp8788_ldo_init);
	627
	628	static void __exit lp8788_ldo_exit(void)
	629	{
7629cef1	630	platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
ade7515f KM	631	}
	632	module_exit(lp8788_ldo_exit);
	633
	634	MODULE_DESCRIPTION("TI LP8788 LDO Driver");
	635	MODULE_AUTHOR("Milo Kim");
	636	MODULE_LICENSE("GPL");
	637	MODULE_ALIAS("platform:lp8788-dldo");
	638	MODULE_ALIAS("platform:lp8788-aldo");