[mirror_ubuntu-jammy-kernel.git] / drivers / regulator / ltc3589.c

// SPDX-License-Identifier: GPL-2.0
//
// Linear Technology LTC3589,LTC3589-1 regulator support
//
// Copyright (c) 2014 Philipp Zabel <p.zabel@pengutronix.de>, Pengutronix

#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/of_regulator.h>

#define DRIVER_NAME		"ltc3589"

#define LTC3589_IRQSTAT		0x02
#define LTC3589_SCR1		0x07
#define LTC3589_OVEN		0x10
#define LTC3589_SCR2		0x12
#define LTC3589_PGSTAT		0x13
#define LTC3589_VCCR		0x20
#define LTC3589_CLIRQ		0x21
#define LTC3589_B1DTV1		0x23
#define LTC3589_B1DTV2		0x24
#define LTC3589_VRRCR		0x25
#define LTC3589_B2DTV1		0x26
#define LTC3589_B2DTV2		0x27
#define LTC3589_B3DTV1		0x29
#define LTC3589_B3DTV2		0x2a
#define LTC3589_L2DTV1		0x32
#define LTC3589_L2DTV2		0x33

#define LTC3589_IRQSTAT_PGOOD_TIMEOUT	BIT(3)
#define LTC3589_IRQSTAT_UNDERVOLT_WARN	BIT(4)
#define LTC3589_IRQSTAT_UNDERVOLT_FAULT	BIT(5)
#define LTC3589_IRQSTAT_THERMAL_WARN	BIT(6)
#define LTC3589_IRQSTAT_THERMAL_FAULT	BIT(7)

#define LTC3589_OVEN_SW1		BIT(0)
#define LTC3589_OVEN_SW2		BIT(1)
#define LTC3589_OVEN_SW3		BIT(2)
#define LTC3589_OVEN_BB_OUT		BIT(3)
#define LTC3589_OVEN_LDO2		BIT(4)
#define LTC3589_OVEN_LDO3		BIT(5)
#define LTC3589_OVEN_LDO4		BIT(6)
#define LTC3589_OVEN_SW_CTRL		BIT(7)

#define LTC3589_VCCR_SW1_GO		BIT(0)
#define LTC3589_VCCR_SW2_GO		BIT(2)
#define LTC3589_VCCR_SW3_GO		BIT(4)
#define LTC3589_VCCR_LDO2_GO		BIT(6)

enum ltc3589_variant {
	LTC3589,
	LTC3589_1,
	LTC3589_2,
};

enum ltc3589_reg {
	LTC3589_SW1,
	LTC3589_SW2,
	LTC3589_SW3,
	LTC3589_BB_OUT,
	LTC3589_LDO1,
	LTC3589_LDO2,
	LTC3589_LDO3,
	LTC3589_LDO4,
	LTC3589_NUM_REGULATORS,
};

struct ltc3589 {
	struct regmap *regmap;
	struct device *dev;
	enum ltc3589_variant variant;
	struct regulator_desc regulator_descs[LTC3589_NUM_REGULATORS];
	struct regulator_dev *regulators[LTC3589_NUM_REGULATORS];
};

static const int ltc3589_ldo4[] = {
	2800000, 2500000, 1800000, 3300000,
};

static const int ltc3589_12_ldo4[] = {
	1200000, 1800000, 2500000, 3200000,
};

static int ltc3589_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
{
	struct ltc3589 *ltc3589 = rdev_get_drvdata(rdev);
	int sel, shift;

	if (unlikely(ramp_delay <= 0))
		return -EINVAL;

	/* VRRCR slew rate offsets are the same as VCCR go bit offsets */
	shift = ffs(rdev->desc->apply_bit) - 1;

	/* The slew rate can be set to 0.88, 1.75, 3.5, or 7 mV/uS */
	for (sel = 0; sel < 4; sel++) {
		if ((880 << sel) >= ramp_delay) {
			return regmap_update_bits(ltc3589->regmap,
						  LTC3589_VRRCR,
						  0x3 << shift, sel << shift);
		}
	}
	return -EINVAL;
}

static int ltc3589_set_suspend_voltage(struct regulator_dev *rdev, int uV)
{
	struct ltc3589 *ltc3589 = rdev_get_drvdata(rdev);
	int sel;

	sel = regulator_map_voltage_linear(rdev, uV, uV);
	if (sel < 0)
		return sel;

	/* DTV2 register follows right after the corresponding DTV1 register */
	return regmap_update_bits(ltc3589->regmap, rdev->desc->vsel_reg + 1,
				  rdev->desc->vsel_mask, sel);
}

static int ltc3589_set_suspend_mode(struct regulator_dev *rdev,
				    unsigned int mode)
{
	struct ltc3589 *ltc3589 = rdev_get_drvdata(rdev);
	int mask, bit = 0;

	/* VCCR reference selects are right next to the VCCR go bits */
	mask = rdev->desc->apply_bit << 1;

	if (mode == REGULATOR_MODE_STANDBY)
		bit = mask;	/* Select DTV2 */

	mask |= rdev->desc->apply_bit;
	bit |= rdev->desc->apply_bit;
	return regmap_update_bits(ltc3589->regmap, LTC3589_VCCR, mask, bit);
}

/* SW1, SW2, SW3, LDO2 */
static const struct regulator_ops ltc3589_linear_regulator_ops = {
	.enable = regulator_enable_regmap,
	.disable = regulator_disable_regmap,
	.is_enabled = regulator_is_enabled_regmap,
	.list_voltage = regulator_list_voltage_linear,
	.set_voltage_sel = regulator_set_voltage_sel_regmap,
	.get_voltage_sel = regulator_get_voltage_sel_regmap,
	.set_ramp_delay = ltc3589_set_ramp_delay,
	.set_voltage_time_sel = regulator_set_voltage_time_sel,
	.set_suspend_voltage = ltc3589_set_suspend_voltage,
	.set_suspend_mode = ltc3589_set_suspend_mode,
};

/* BB_OUT, LDO3 */
static const struct regulator_ops ltc3589_fixed_regulator_ops = {
	.enable = regulator_enable_regmap,
	.disable = regulator_disable_regmap,
	.is_enabled = regulator_is_enabled_regmap,
};

/* LDO1 */
static const struct regulator_ops ltc3589_fixed_standby_regulator_ops = {
};

/* LDO4 */
static const struct regulator_ops ltc3589_table_regulator_ops = {
	.enable = regulator_enable_regmap,
	.disable = regulator_disable_regmap,
	.is_enabled = regulator_is_enabled_regmap,
	.list_voltage = regulator_list_voltage_table,
	.set_voltage_sel = regulator_set_voltage_sel_regmap,
	.get_voltage_sel = regulator_get_voltage_sel_regmap,
};

static inline unsigned int ltc3589_scale(unsigned int uV, u32 r1, u32 r2)
{
	uint64_t tmp;

	if (uV == 0)
		return 0;

	tmp = (uint64_t)uV * r1;
	do_div(tmp, r2);
	return uV + (unsigned int)tmp;
}

static int ltc3589_of_parse_cb(struct device_node *np,
			       const struct regulator_desc *desc,
			       struct regulator_config *config)
{
	struct ltc3589 *ltc3589 = config->driver_data;
	struct regulator_desc *rdesc = &ltc3589->regulator_descs[desc->id];
	u32 r[2];
	int ret;

	/* Parse feedback voltage dividers. LDO3 and LDO4 don't have them */
	if (desc->id >= LTC3589_LDO3)
		return 0;

	ret = of_property_read_u32_array(np, "lltc,fb-voltage-divider", r, 2);
	if (ret) {
		dev_err(ltc3589->dev, "Failed to parse voltage divider: %d\n",
			ret);
		return ret;
	}

	if (!r[0] || !r[1])
		return 0;

	rdesc->min_uV = ltc3589_scale(desc->min_uV, r[0], r[1]);
	rdesc->uV_step = ltc3589_scale(desc->uV_step, r[0], r[1]);
	rdesc->fixed_uV = ltc3589_scale(desc->fixed_uV, r[0], r[1]);

	return 0;
}

#define LTC3589_REG(_name, _of_name, _ops, en_bit, dtv1_reg, dtv_mask, go_bit)\
	[LTC3589_ ## _name] = {						\
		.name = #_name,						\
		.of_match = of_match_ptr(#_of_name),			\
		.regulators_node = of_match_ptr("regulators"),		\
		.of_parse_cb = ltc3589_of_parse_cb,			\
		.n_voltages = (dtv_mask) + 1,				\
		.min_uV = (go_bit) ? 362500 : 0,			\
		.uV_step = (go_bit) ? 12500 : 0,			\
		.ramp_delay = (go_bit) ? 1750 : 0,			\
		.fixed_uV = (dtv_mask) ? 0 : 800000,			\
		.ops = &ltc3589_ ## _ops ## _regulator_ops,		\
		.type = REGULATOR_VOLTAGE,				\
		.id = LTC3589_ ## _name,				\
		.owner = THIS_MODULE,					\
		.vsel_reg = (dtv1_reg),					\
		.vsel_mask = (dtv_mask),				\
		.apply_reg = (go_bit) ? LTC3589_VCCR : 0,		\
		.apply_bit = (go_bit),					\
		.enable_reg = (en_bit) ? LTC3589_OVEN : 0,		\
		.enable_mask = (en_bit),				\
	}

#define LTC3589_LINEAR_REG(_name, _of_name, _dtv1)			\
	LTC3589_REG(_name, _of_name, linear, LTC3589_OVEN_ ## _name,	\
		    LTC3589_ ## _dtv1, 0x1f,				\
		    LTC3589_VCCR_ ## _name ## _GO)

#define LTC3589_FIXED_REG(_name, _of_name)				\
	LTC3589_REG(_name, _of_name, fixed, LTC3589_OVEN_ ## _name, 0, 0, 0)

static const struct regulator_desc ltc3589_regulators[] = {
	LTC3589_LINEAR_REG(SW1, sw1, B1DTV1),
	LTC3589_LINEAR_REG(SW2, sw2, B2DTV1),
	LTC3589_LINEAR_REG(SW3, sw3, B3DTV1),
	LTC3589_FIXED_REG(BB_OUT, bb-out),
	LTC3589_REG(LDO1, ldo1, fixed_standby, 0, 0, 0, 0),
	LTC3589_LINEAR_REG(LDO2, ldo2, L2DTV1),
	LTC3589_FIXED_REG(LDO3, ldo3),
	LTC3589_REG(LDO4, ldo4, table, LTC3589_OVEN_LDO4, LTC3589_L2DTV2,
		    0x60, 0),
};

static bool ltc3589_writeable_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case LTC3589_IRQSTAT:
	case LTC3589_SCR1:
	case LTC3589_OVEN:
	case LTC3589_SCR2:
	case LTC3589_VCCR:
	case LTC3589_CLIRQ:
	case LTC3589_B1DTV1:
	case LTC3589_B1DTV2:
	case LTC3589_VRRCR:
	case LTC3589_B2DTV1:
	case LTC3589_B2DTV2:
	case LTC3589_B3DTV1:
	case LTC3589_B3DTV2:
	case LTC3589_L2DTV1:
	case LTC3589_L2DTV2:
		return true;
	}
	return false;
}

static bool ltc3589_readable_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case LTC3589_IRQSTAT:
	case LTC3589_SCR1:
	case LTC3589_OVEN:
	case LTC3589_SCR2:
	case LTC3589_PGSTAT:
	case LTC3589_VCCR:
	case LTC3589_B1DTV1:
	case LTC3589_B1DTV2:
	case LTC3589_VRRCR:
	case LTC3589_B2DTV1:
	case LTC3589_B2DTV2:
	case LTC3589_B3DTV1:
	case LTC3589_B3DTV2:
	case LTC3589_L2DTV1:
	case LTC3589_L2DTV2:
		return true;
	}
	return false;
}

static bool ltc3589_volatile_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case LTC3589_IRQSTAT:
	case LTC3589_PGSTAT:
	case LTC3589_VCCR:
		return true;
	}
	return false;
}

static const struct reg_default ltc3589_reg_defaults[] = {
	{ LTC3589_SCR1,   0x00 },
	{ LTC3589_OVEN,   0x00 },
	{ LTC3589_SCR2,   0x00 },
	{ LTC3589_VCCR,   0x00 },
	{ LTC3589_B1DTV1, 0x19 },
	{ LTC3589_B1DTV2, 0x19 },
	{ LTC3589_VRRCR,  0xff },
	{ LTC3589_B2DTV1, 0x19 },
	{ LTC3589_B2DTV2, 0x19 },
	{ LTC3589_B3DTV1, 0x19 },
	{ LTC3589_B3DTV2, 0x19 },
	{ LTC3589_L2DTV1, 0x19 },
	{ LTC3589_L2DTV2, 0x19 },
};

static const struct regmap_config ltc3589_regmap_config = {
	.reg_bits = 8,
	.val_bits = 8,
	.writeable_reg = ltc3589_writeable_reg,
	.readable_reg = ltc3589_readable_reg,
	.volatile_reg = ltc3589_volatile_reg,
	.max_register = LTC3589_L2DTV2,
	.reg_defaults = ltc3589_reg_defaults,
	.num_reg_defaults = ARRAY_SIZE(ltc3589_reg_defaults),
	.use_single_read = true,
	.use_single_write = true,
	.cache_type = REGCACHE_RBTREE,
};

static irqreturn_t ltc3589_isr(int irq, void *dev_id)
{
	struct ltc3589 *ltc3589 = dev_id;
	unsigned int i, irqstat, event;

	regmap_read(ltc3589->regmap, LTC3589_IRQSTAT, &irqstat);

	if (irqstat & LTC3589_IRQSTAT_THERMAL_WARN) {
		event = REGULATOR_EVENT_OVER_TEMP;
		for (i = 0; i < LTC3589_NUM_REGULATORS; i++) {
		        regulator_lock(ltc3589->regulators[i]);
			regulator_notifier_call_chain(ltc3589->regulators[i],
						      event, NULL);
		        regulator_unlock(ltc3589->regulators[i]);
		}
	}

	if (irqstat & LTC3589_IRQSTAT_UNDERVOLT_WARN) {
		event = REGULATOR_EVENT_UNDER_VOLTAGE;
		for (i = 0; i < LTC3589_NUM_REGULATORS; i++) {
		        regulator_lock(ltc3589->regulators[i]);
			regulator_notifier_call_chain(ltc3589->regulators[i],
						      event, NULL);
		        regulator_unlock(ltc3589->regulators[i]);
		}
	}

	/* Clear warning condition */
	regmap_write(ltc3589->regmap, LTC3589_CLIRQ, 0);

	return IRQ_HANDLED;
}

static int ltc3589_probe(struct i2c_client *client,
			 const struct i2c_device_id *id)
{
	struct device *dev = &client->dev;
	struct regulator_desc *descs;
	struct ltc3589 *ltc3589;
	int i, ret;

	ltc3589 = devm_kzalloc(dev, sizeof(*ltc3589), GFP_KERNEL);
	if (!ltc3589)
		return -ENOMEM;

	i2c_set_clientdata(client, ltc3589);
	if (client->dev.of_node)
		ltc3589->variant = (enum ltc3589_variant)
			of_device_get_match_data(&client->dev);
	else
		ltc3589->variant = id->driver_data;
	ltc3589->dev = dev;

	descs = ltc3589->regulator_descs;
	memcpy(descs, ltc3589_regulators, sizeof(ltc3589_regulators));
	if (ltc3589->variant == LTC3589) {
		descs[LTC3589_LDO3].fixed_uV = 1800000;
		descs[LTC3589_LDO4].volt_table = ltc3589_ldo4;
	} else {
		descs[LTC3589_LDO3].fixed_uV = 2800000;
		descs[LTC3589_LDO4].volt_table = ltc3589_12_ldo4;
	}

	ltc3589->regmap = devm_regmap_init_i2c(client, &ltc3589_regmap_config);
	if (IS_ERR(ltc3589->regmap)) {
		ret = PTR_ERR(ltc3589->regmap);
		dev_err(dev, "failed to initialize regmap: %d\n", ret);
		return ret;
	}

	for (i = 0; i < LTC3589_NUM_REGULATORS; i++) {
		struct regulator_desc *desc = &ltc3589->regulator_descs[i];
		struct regulator_config config = { };

		config.dev = dev;
		config.driver_data = ltc3589;

		ltc3589->regulators[i] = devm_regulator_register(dev, desc,
								 &config);
		if (IS_ERR(ltc3589->regulators[i])) {
			ret = PTR_ERR(ltc3589->regulators[i]);
			dev_err(dev, "failed to register regulator %s: %d\n",
				desc->name, ret);
			return ret;
		}
	}

	if (client->irq) {
		ret = devm_request_threaded_irq(dev, client->irq, NULL,
						ltc3589_isr,
						IRQF_TRIGGER_LOW | IRQF_ONESHOT,
						client->name, ltc3589);
		if (ret) {
			dev_err(dev, "Failed to request IRQ: %d\n", ret);
			return ret;
		}
	}

	return 0;
}

static const struct i2c_device_id ltc3589_i2c_id[] = {
	{ "ltc3589",   LTC3589   },
	{ "ltc3589-1", LTC3589_1 },
	{ "ltc3589-2", LTC3589_2 },
	{ }
};
MODULE_DEVICE_TABLE(i2c, ltc3589_i2c_id);

static const struct of_device_id ltc3589_of_match[] = {
	{
		.compatible = "lltc,ltc3589",
		.data = (void *)LTC3589,
	},
	{
		.compatible = "lltc,ltc3589-1",
		.data = (void *)LTC3589_1,
	},
	{
		.compatible = "lltc,ltc3589-2",
		.data = (void *)LTC3589_2,
	},
	{ },
};
MODULE_DEVICE_TABLE(of, ltc3589_of_match);

static struct i2c_driver ltc3589_driver = {
	.driver = {
		.name = DRIVER_NAME,
		.of_match_table = of_match_ptr(ltc3589_of_match),
	},
	.probe = ltc3589_probe,
	.id_table = ltc3589_i2c_id,
};
module_i2c_driver(ltc3589_driver);

MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
MODULE_DESCRIPTION("Regulator driver for Linear Technology LTC3589(-1,2)");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
b2745697 AL	1	// SPDX-License-Identifier: GPL-2.0
	2	//
	3	// Linear Technology LTC3589,LTC3589-1 regulator support
	4	//
	5	// Copyright (c) 2014 Philipp Zabel <p.zabel@pengutronix.de>, Pengutronix
	6
3eb2c7ec PZ	7	#include <linux/i2c.h>
	8	#include <linux/init.h>
	9	#include <linux/interrupt.h>
	10	#include <linux/module.h>
	11	#include <linux/kernel.h>
	12	#include <linux/of.h>
45a86172	13	#include <linux/of_device.h>
3eb2c7ec PZ	14	#include <linux/regmap.h>
	15	#include <linux/regulator/driver.h>
	16	#include <linux/regulator/of_regulator.h>
	17
	18	#define DRIVER_NAME "ltc3589"
	19
	20	#define LTC3589_IRQSTAT 0x02
	21	#define LTC3589_SCR1 0x07
	22	#define LTC3589_OVEN 0x10
	23	#define LTC3589_SCR2 0x12
	24	#define LTC3589_PGSTAT 0x13
	25	#define LTC3589_VCCR 0x20
	26	#define LTC3589_CLIRQ 0x21
	27	#define LTC3589_B1DTV1 0x23
	28	#define LTC3589_B1DTV2 0x24
	29	#define LTC3589_VRRCR 0x25
	30	#define LTC3589_B2DTV1 0x26
	31	#define LTC3589_B2DTV2 0x27
	32	#define LTC3589_B3DTV1 0x29
	33	#define LTC3589_B3DTV2 0x2a
	34	#define LTC3589_L2DTV1 0x32
	35	#define LTC3589_L2DTV2 0x33
	36
	37	#define LTC3589_IRQSTAT_PGOOD_TIMEOUT BIT(3)
	38	#define LTC3589_IRQSTAT_UNDERVOLT_WARN BIT(4)
	39	#define LTC3589_IRQSTAT_UNDERVOLT_FAULT BIT(5)
	40	#define LTC3589_IRQSTAT_THERMAL_WARN BIT(6)
	41	#define LTC3589_IRQSTAT_THERMAL_FAULT BIT(7)
	42
	43	#define LTC3589_OVEN_SW1 BIT(0)
	44	#define LTC3589_OVEN_SW2 BIT(1)
	45	#define LTC3589_OVEN_SW3 BIT(2)
	46	#define LTC3589_OVEN_BB_OUT BIT(3)
	47	#define LTC3589_OVEN_LDO2 BIT(4)
	48	#define LTC3589_OVEN_LDO3 BIT(5)
	49	#define LTC3589_OVEN_LDO4 BIT(6)
	50	#define LTC3589_OVEN_SW_CTRL BIT(7)
	51
	52	#define LTC3589_VCCR_SW1_GO BIT(0)
	53	#define LTC3589_VCCR_SW2_GO BIT(2)
	54	#define LTC3589_VCCR_SW3_GO BIT(4)
	55	#define LTC3589_VCCR_LDO2_GO BIT(6)
	56
	57	enum ltc3589_variant {
	58	LTC3589,
	59	LTC3589_1,
	60	LTC3589_2,
	61	};
	62
	63	enum ltc3589_reg {
	64	LTC3589_SW1,
	65	LTC3589_SW2,
	66	LTC3589_SW3,
	67	LTC3589_BB_OUT,
	68	LTC3589_LDO1,
	69	LTC3589_LDO2,
	70	LTC3589_LDO3,
	71	LTC3589_LDO4,
	72	LTC3589_NUM_REGULATORS,
	73	};
	74
3eb2c7ec PZ	75	struct ltc3589 {
	76	struct regmap *regmap;
	77	struct device *dev;
	78	enum ltc3589_variant variant;
63c7c296	79	struct regulator_desc regulator_descs[LTC3589_NUM_REGULATORS];
3eb2c7ec PZ	80	struct regulator_dev *regulators[LTC3589_NUM_REGULATORS];
	81	};
	82
	83	static const int ltc3589_ldo4[] = {
	84	2800000, 2500000, 1800000, 3300000,
	85	};
	86
	87	static const int ltc3589_12_ldo4[] = {
	88	1200000, 1800000, 2500000, 3200000,
	89	};
	90
	91	static int ltc3589_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
	92	{
	93	struct ltc3589 *ltc3589 = rdev_get_drvdata(rdev);
	94	int sel, shift;
	95
	96	if (unlikely(ramp_delay <= 0))
	97	return -EINVAL;
	98
	99	/* VRRCR slew rate offsets are the same as VCCR go bit offsets */
	100	shift = ffs(rdev->desc->apply_bit) - 1;
	101
	102	/* The slew rate can be set to 0.88, 1.75, 3.5, or 7 mV/uS */
	103	for (sel = 0; sel < 4; sel++) {
	104	if ((880 << sel) >= ramp_delay) {
	105	return regmap_update_bits(ltc3589->regmap,
	106	LTC3589_VRRCR,
	107	0x3 << shift, sel << shift);
	108	}
	109	}
	110	return -EINVAL;
	111	}
	112
	113	static int ltc3589_set_suspend_voltage(struct regulator_dev *rdev, int uV)
	114	{
	115	struct ltc3589 *ltc3589 = rdev_get_drvdata(rdev);
	116	int sel;
	117
	118	sel = regulator_map_voltage_linear(rdev, uV, uV);
	119	if (sel < 0)
	120	return sel;
	121
	122	/* DTV2 register follows right after the corresponding DTV1 register */
	123	return regmap_update_bits(ltc3589->regmap, rdev->desc->vsel_reg + 1,
	124	rdev->desc->vsel_mask, sel);
	125	}
	126
	127	static int ltc3589_set_suspend_mode(struct regulator_dev *rdev,
	128	unsigned int mode)
	129	{
	130	struct ltc3589 *ltc3589 = rdev_get_drvdata(rdev);
	131	int mask, bit = 0;
	132
	133	/* VCCR reference selects are right next to the VCCR go bits */
	134	mask = rdev->desc->apply_bit << 1;
	135
	136	if (mode == REGULATOR_MODE_STANDBY)
	137	bit = mask; /* Select DTV2 */
	138
	139	mask \|= rdev->desc->apply_bit;
	140	bit \|= rdev->desc->apply_bit;
	141	return regmap_update_bits(ltc3589->regmap, LTC3589_VCCR, mask, bit);
	142	}
	143
3eb2c7ec	144	/* SW1, SW2, SW3, LDO2 */
c093c3a3	145	static const struct regulator_ops ltc3589_linear_regulator_ops = {
3eb2c7ec PZ	146	.enable = regulator_enable_regmap,
	147	.disable = regulator_disable_regmap,
	148	.is_enabled = regulator_is_enabled_regmap,
	149	.list_voltage = regulator_list_voltage_linear,
	150	.set_voltage_sel = regulator_set_voltage_sel_regmap,
	151	.get_voltage_sel = regulator_get_voltage_sel_regmap,
	152	.set_ramp_delay = ltc3589_set_ramp_delay,
	153	.set_voltage_time_sel = regulator_set_voltage_time_sel,
	154	.set_suspend_voltage = ltc3589_set_suspend_voltage,
	155	.set_suspend_mode = ltc3589_set_suspend_mode,
	156	};
	157
	158	/* BB_OUT, LDO3 */
c093c3a3	159	static const struct regulator_ops ltc3589_fixed_regulator_ops = {
3eb2c7ec PZ	160	.enable = regulator_enable_regmap,
	161	.disable = regulator_disable_regmap,
	162	.is_enabled = regulator_is_enabled_regmap,
3eb2c7ec PZ	163	};
	164
	165	/* LDO1 */
c093c3a3	166	static const struct regulator_ops ltc3589_fixed_standby_regulator_ops = {
3eb2c7ec PZ	167	};
	168
	169	/* LDO4 */
c093c3a3	170	static const struct regulator_ops ltc3589_table_regulator_ops = {
3eb2c7ec PZ	171	.enable = regulator_enable_regmap,
	172	.disable = regulator_disable_regmap,
	173	.is_enabled = regulator_is_enabled_regmap,
	174	.list_voltage = regulator_list_voltage_table,
	175	.set_voltage_sel = regulator_set_voltage_sel_regmap,
	176	.get_voltage_sel = regulator_get_voltage_sel_regmap,
	177	};
	178
ce62ba3a AL	179	static inline unsigned int ltc3589_scale(unsigned int uV, u32 r1, u32 r2)
	180	{
	181	uint64_t tmp;
	182
	183	if (uV == 0)
	184	return 0;
	185
	186	tmp = (uint64_t)uV * r1;
	187	do_div(tmp, r2);
	188	return uV + (unsigned int)tmp;
	189	}
	190
	191	static int ltc3589_of_parse_cb(struct device_node *np,
	192	const struct regulator_desc *desc,
	193	struct regulator_config *config)
	194	{
	195	struct ltc3589 *ltc3589 = config->driver_data;
63c7c296	196	struct regulator_desc *rdesc = &ltc3589->regulator_descs[desc->id];
ce62ba3a AL	197	u32 r[2];
	198	int ret;
	199
	200	/* Parse feedback voltage dividers. LDO3 and LDO4 don't have them */
	201	if (desc->id >= LTC3589_LDO3)
	202	return 0;
3eb2c7ec	203
ce62ba3a AL	204	ret = of_property_read_u32_array(np, "lltc,fb-voltage-divider", r, 2);
	205	if (ret) {
	206	dev_err(ltc3589->dev, "Failed to parse voltage divider: %d\n",
	207	ret);
	208	return ret;
	209	}
	210
	211	if (!r[0] \|\| !r[1])
	212	return 0;
	213
63c7c296 AL	214	rdesc->min_uV = ltc3589_scale(desc->min_uV, r[0], r[1]);
	215	rdesc->uV_step = ltc3589_scale(desc->uV_step, r[0], r[1]);
	216	rdesc->fixed_uV = ltc3589_scale(desc->fixed_uV, r[0], r[1]);
ce62ba3a AL	217
	218	return 0;
	219	}
	220
	221	#define LTC3589_REG(_name, _of_name, _ops, en_bit, dtv1_reg, dtv_mask, go_bit)\
3eb2c7ec	222	[LTC3589_ ## _name] = { \
63c7c296 AL	223	.name = #_name, \
	224	.of_match = of_match_ptr(#_of_name), \
	225	.regulators_node = of_match_ptr("regulators"), \
	226	.of_parse_cb = ltc3589_of_parse_cb, \
	227	.n_voltages = (dtv_mask) + 1, \
	228	.min_uV = (go_bit) ? 362500 : 0, \
	229	.uV_step = (go_bit) ? 12500 : 0, \
	230	.ramp_delay = (go_bit) ? 1750 : 0, \
	231	.fixed_uV = (dtv_mask) ? 0 : 800000, \
	232	.ops = &ltc3589_ ## _ops ## _regulator_ops, \
	233	.type = REGULATOR_VOLTAGE, \
	234	.id = LTC3589_ ## _name, \
	235	.owner = THIS_MODULE, \
	236	.vsel_reg = (dtv1_reg), \
	237	.vsel_mask = (dtv_mask), \
	238	.apply_reg = (go_bit) ? LTC3589_VCCR : 0, \
	239	.apply_bit = (go_bit), \
	240	.enable_reg = (en_bit) ? LTC3589_OVEN : 0, \
	241	.enable_mask = (en_bit), \
3eb2c7ec PZ	242	}
3eb2c7ec PZ	243
ce62ba3a AL	244	#define LTC3589_LINEAR_REG(_name, _of_name, _dtv1) \
ce62ba3a AL	245	LTC3589_REG(_name, _of_name, linear, LTC3589_OVEN_ ## _name, \
3eb2c7ec PZ	246	LTC3589_ ## _dtv1, 0x1f, \
	247	LTC3589_VCCR_ ## _name ## _GO)
	248
ce62ba3a AL	249	#define LTC3589_FIXED_REG(_name, _of_name) \
ce62ba3a AL	250	LTC3589_REG(_name, _of_name, fixed, LTC3589_OVEN_ ## _name, 0, 0, 0)
3eb2c7ec	251
63c7c296	252	static const struct regulator_desc ltc3589_regulators[] = {
ce62ba3a AL	253	LTC3589_LINEAR_REG(SW1, sw1, B1DTV1),
	254	LTC3589_LINEAR_REG(SW2, sw2, B2DTV1),
	255	LTC3589_LINEAR_REG(SW3, sw3, B3DTV1),
	256	LTC3589_FIXED_REG(BB_OUT, bb-out),
	257	LTC3589_REG(LDO1, ldo1, fixed_standby, 0, 0, 0, 0),
	258	LTC3589_LINEAR_REG(LDO2, ldo2, L2DTV1),
	259	LTC3589_FIXED_REG(LDO3, ldo3),
	260	LTC3589_REG(LDO4, ldo4, table, LTC3589_OVEN_LDO4, LTC3589_L2DTV2,
	261	0x60, 0),
3eb2c7ec PZ	262	};
3eb2c7ec PZ	263
3eb2c7ec PZ	264	static bool ltc3589_writeable_reg(struct device *dev, unsigned int reg)
	265	{
	266	switch (reg) {
	267	case LTC3589_IRQSTAT:
	268	case LTC3589_SCR1:
	269	case LTC3589_OVEN:
	270	case LTC3589_SCR2:
	271	case LTC3589_VCCR:
	272	case LTC3589_CLIRQ:
	273	case LTC3589_B1DTV1:
	274	case LTC3589_B1DTV2:
	275	case LTC3589_VRRCR:
	276	case LTC3589_B2DTV1:
	277	case LTC3589_B2DTV2:
	278	case LTC3589_B3DTV1:
	279	case LTC3589_B3DTV2:
	280	case LTC3589_L2DTV1:
	281	case LTC3589_L2DTV2:
	282	return true;
	283	}
	284	return false;
	285	}
	286
	287	static bool ltc3589_readable_reg(struct device *dev, unsigned int reg)
	288	{
	289	switch (reg) {
	290	case LTC3589_IRQSTAT:
	291	case LTC3589_SCR1:
	292	case LTC3589_OVEN:
	293	case LTC3589_SCR2:
	294	case LTC3589_PGSTAT:
	295	case LTC3589_VCCR:
	296	case LTC3589_B1DTV1:
	297	case LTC3589_B1DTV2:
	298	case LTC3589_VRRCR:
	299	case LTC3589_B2DTV1:
	300	case LTC3589_B2DTV2:
	301	case LTC3589_B3DTV1:
	302	case LTC3589_B3DTV2:
	303	case LTC3589_L2DTV1:
	304	case LTC3589_L2DTV2:
	305	return true;
	306	}
	307	return false;
	308	}
	309
	310	static bool ltc3589_volatile_reg(struct device *dev, unsigned int reg)
	311	{
	312	switch (reg) {
	313	case LTC3589_IRQSTAT:
	314	case LTC3589_PGSTAT:
c5bb725a	315	case LTC3589_VCCR:
3eb2c7ec PZ	316	return true;
	317	}
	318	return false;
	319	}
	320
ec867726	321	static const struct reg_default ltc3589_reg_defaults[] = {
3eb2c7ec PZ	322	{ LTC3589_SCR1, 0x00 },
	323	{ LTC3589_OVEN, 0x00 },
	324	{ LTC3589_SCR2, 0x00 },
	325	{ LTC3589_VCCR, 0x00 },
	326	{ LTC3589_B1DTV1, 0x19 },
	327	{ LTC3589_B1DTV2, 0x19 },
	328	{ LTC3589_VRRCR, 0xff },
	329	{ LTC3589_B2DTV1, 0x19 },
	330	{ LTC3589_B2DTV2, 0x19 },
	331	{ LTC3589_B3DTV1, 0x19 },
	332	{ LTC3589_B3DTV2, 0x19 },
	333	{ LTC3589_L2DTV1, 0x19 },
	334	{ LTC3589_L2DTV2, 0x19 },
	335	};
	336
	337	static const struct regmap_config ltc3589_regmap_config = {
	338	.reg_bits = 8,
	339	.val_bits = 8,
	340	.writeable_reg = ltc3589_writeable_reg,
	341	.readable_reg = ltc3589_readable_reg,
	342	.volatile_reg = ltc3589_volatile_reg,
	343	.max_register = LTC3589_L2DTV2,
	344	.reg_defaults = ltc3589_reg_defaults,
	345	.num_reg_defaults = ARRAY_SIZE(ltc3589_reg_defaults),
1c96a2f6 DF	346	.use_single_read = true,
1c96a2f6 DF	347	.use_single_write = true,
3eb2c7ec PZ	348	.cache_type = REGCACHE_RBTREE,
	349	};
	350
3eb2c7ec PZ	351	static irqreturn_t ltc3589_isr(int irq, void *dev_id)
	352	{
	353	struct ltc3589 *ltc3589 = dev_id;
	354	unsigned int i, irqstat, event;
	355
	356	regmap_read(ltc3589->regmap, LTC3589_IRQSTAT, &irqstat);
	357
	358	if (irqstat & LTC3589_IRQSTAT_THERMAL_WARN) {
	359	event = REGULATOR_EVENT_OVER_TEMP;
f132da25 ST	360	for (i = 0; i < LTC3589_NUM_REGULATORS; i++) {
f132da25 ST	361	regulator_lock(ltc3589->regulators[i]);
3eb2c7ec PZ	362	regulator_notifier_call_chain(ltc3589->regulators[i],
3eb2c7ec PZ	363	event, NULL);
f132da25 ST	364	regulator_unlock(ltc3589->regulators[i]);
f132da25 ST	365	}
3eb2c7ec PZ	366	}
	367
	368	if (irqstat & LTC3589_IRQSTAT_UNDERVOLT_WARN) {
	369	event = REGULATOR_EVENT_UNDER_VOLTAGE;
f132da25 ST	370	for (i = 0; i < LTC3589_NUM_REGULATORS; i++) {
f132da25 ST	371	regulator_lock(ltc3589->regulators[i]);
3eb2c7ec PZ	372	regulator_notifier_call_chain(ltc3589->regulators[i],
3eb2c7ec PZ	373	event, NULL);
f132da25 ST	374	regulator_unlock(ltc3589->regulators[i]);
f132da25 ST	375	}
3eb2c7ec PZ	376	}
	377
	378	/* Clear warning condition */
	379	regmap_write(ltc3589->regmap, LTC3589_CLIRQ, 0);
	380
	381	return IRQ_HANDLED;
	382	}
	383
3eb2c7ec PZ	384	static int ltc3589_probe(struct i2c_client *client,
	385	const struct i2c_device_id *id)
	386	{
	387	struct device *dev = &client->dev;
63c7c296	388	struct regulator_desc *descs;
3eb2c7ec PZ	389	struct ltc3589 *ltc3589;
	390	int i, ret;
	391
	392	ltc3589 = devm_kzalloc(dev, sizeof(*ltc3589), GFP_KERNEL);
	393	if (!ltc3589)
	394	return -ENOMEM;
	395
	396	i2c_set_clientdata(client, ltc3589);
45a86172 JMC	397	if (client->dev.of_node)
	398	ltc3589->variant = (enum ltc3589_variant)
	399	of_device_get_match_data(&client->dev);
	400	else
	401	ltc3589->variant = id->driver_data;
3eb2c7ec PZ	402	ltc3589->dev = dev;
	403
	404	descs = ltc3589->regulator_descs;
	405	memcpy(descs, ltc3589_regulators, sizeof(ltc3589_regulators));
	406	if (ltc3589->variant == LTC3589) {
63c7c296 AL	407	descs[LTC3589_LDO3].fixed_uV = 1800000;
63c7c296 AL	408	descs[LTC3589_LDO4].volt_table = ltc3589_ldo4;
3eb2c7ec	409	} else {
63c7c296 AL	410	descs[LTC3589_LDO3].fixed_uV = 2800000;
63c7c296 AL	411	descs[LTC3589_LDO4].volt_table = ltc3589_12_ldo4;
3eb2c7ec PZ	412	}
	413
	414	ltc3589->regmap = devm_regmap_init_i2c(client, &ltc3589_regmap_config);
	415	if (IS_ERR(ltc3589->regmap)) {
	416	ret = PTR_ERR(ltc3589->regmap);
	417	dev_err(dev, "failed to initialize regmap: %d\n", ret);
	418	return ret;
	419	}
	420
3eb2c7ec	421	for (i = 0; i < LTC3589_NUM_REGULATORS; i++) {
63c7c296	422	struct regulator_desc *desc = &ltc3589->regulator_descs[i];
3eb2c7ec PZ	423	struct regulator_config config = { };
3eb2c7ec PZ	424
3eb2c7ec	425	config.dev = dev;
3eb2c7ec	426	config.driver_data = ltc3589;
3eb2c7ec PZ	427
	428	ltc3589->regulators[i] = devm_regulator_register(dev, desc,
	429	&config);
	430	if (IS_ERR(ltc3589->regulators[i])) {
	431	ret = PTR_ERR(ltc3589->regulators[i]);
	432	dev_err(dev, "failed to register regulator %s: %d\n",
	433	desc->name, ret);
	434	return ret;
	435	}
	436	}
	437
d4930cf0 BW	438	if (client->irq) {
	439	ret = devm_request_threaded_irq(dev, client->irq, NULL,
	440	ltc3589_isr,
	441	IRQF_TRIGGER_LOW \| IRQF_ONESHOT,
	442	client->name, ltc3589);
	443	if (ret) {
	444	dev_err(dev, "Failed to request IRQ: %d\n", ret);
	445	return ret;
	446	}
3eb2c7ec PZ	447	}
	448
	449	return 0;
	450	}
	451
6d284bb1	452	static const struct i2c_device_id ltc3589_i2c_id[] = {
3eb2c7ec PZ	453	{ "ltc3589", LTC3589 },
	454	{ "ltc3589-1", LTC3589_1 },
	455	{ "ltc3589-2", LTC3589_2 },
	456	{ }
	457	};
	458	MODULE_DEVICE_TABLE(i2c, ltc3589_i2c_id);
	459
45a86172 JMC	460	static const struct of_device_id ltc3589_of_match[] = {
	461	{
	462	.compatible = "lltc,ltc3589",
	463	.data = (void *)LTC3589,
	464	},
	465	{
	466	.compatible = "lltc,ltc3589-1",
	467	.data = (void *)LTC3589_1,
	468	},
	469	{
	470	.compatible = "lltc,ltc3589-2",
	471	.data = (void *)LTC3589_2,
	472	},
	473	{ },
	474	};
	475	MODULE_DEVICE_TABLE(of, ltc3589_of_match);
	476
3eb2c7ec PZ	477	static struct i2c_driver ltc3589_driver = {
	478	.driver = {
	479	.name = DRIVER_NAME,
45a86172	480	.of_match_table = of_match_ptr(ltc3589_of_match),
3eb2c7ec PZ	481	},
	482	.probe = ltc3589_probe,
	483	.id_table = ltc3589_i2c_id,
	484	};
	485	module_i2c_driver(ltc3589_driver);
	486
	487	MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
	488	MODULE_DESCRIPTION("Regulator driver for Linear Technology LTC3589(-1,2)");
	489	MODULE_LICENSE("GPL v2");