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Merge branch 'fix/palmas' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[mirror_ubuntu-artful-kernel.git] / drivers / regulator / palmas-regulator.c
CommitLineData
e5ce4208
GG		 1/*
2 * Driver for Regulator part of Palmas PMIC Chips
3 *
7be859f7 4 * Copyright 2011-2013 Texas Instruments Inc.
e5ce4208
GG		 5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
a7dddf27 7 * Author: Ian Lartey <ian@slimlogic.co.uk>
e5ce4208
GG		 8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/err.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/driver.h>
22#include <linux/regulator/machine.h>
23#include <linux/slab.h>
24#include <linux/regmap.h>
25#include <linux/mfd/palmas.h>
a361cd9f
GG		 26#include <linux/of.h>
27#include <linux/of_platform.h>
28#include <linux/regulator/of_regulator.h>
e5ce4208 29
dbabd624 30static const struct regulator_linear_range smps_low_ranges[] = {
6b7f2d82 31 REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0),
dbabd624
K		 32 REGULATOR_LINEAR_RANGE(500000, 0x1, 0x6, 0),
33 REGULATOR_LINEAR_RANGE(510000, 0x7, 0x79, 10000),
34 REGULATOR_LINEAR_RANGE(1650000, 0x7A, 0x7f, 0),
35};
36
37static const struct regulator_linear_range smps_high_ranges[] = {
6b7f2d82 38 REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0),
dbabd624
K		 39 REGULATOR_LINEAR_RANGE(1000000, 0x1, 0x6, 0),
40 REGULATOR_LINEAR_RANGE(1020000, 0x7, 0x79, 20000),
41 REGULATOR_LINEAR_RANGE(3300000, 0x7A, 0x7f, 0),
42};
43
6839cd6f 44static struct palmas_regs_info palmas_generic_regs_info[] = {
e5ce4208
GG		 45 {
46 .name = "SMPS12",
504382c9 47 .sname = "smps1-in",
e5ce4208
GG		 48 .vsel_addr = PALMAS_SMPS12_VOLTAGE,
49 .ctrl_addr = PALMAS_SMPS12_CTRL,
50 .tstep_addr = PALMAS_SMPS12_TSTEP,
32b6d3f6 51 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
e5ce4208
GG		 52 },
53 {
54 .name = "SMPS123",
504382c9 55 .sname = "smps1-in",
e5ce4208
GG		 56 .vsel_addr = PALMAS_SMPS12_VOLTAGE,
57 .ctrl_addr = PALMAS_SMPS12_CTRL,
58 .tstep_addr = PALMAS_SMPS12_TSTEP,
32b6d3f6 59 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
e5ce4208
GG		 60 },
61 {
62 .name = "SMPS3",
504382c9 63 .sname = "smps3-in",
e5ce4208
GG		 64 .vsel_addr = PALMAS_SMPS3_VOLTAGE,
65 .ctrl_addr = PALMAS_SMPS3_CTRL,
32b6d3f6 66 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS3,
e5ce4208
GG		 67 },
68 {
69 .name = "SMPS45",
504382c9 70 .sname = "smps4-in",
e5ce4208
GG		 71 .vsel_addr = PALMAS_SMPS45_VOLTAGE,
72 .ctrl_addr = PALMAS_SMPS45_CTRL,
73 .tstep_addr = PALMAS_SMPS45_TSTEP,
32b6d3f6 74 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
e5ce4208
GG		 75 },
76 {
77 .name = "SMPS457",
504382c9 78 .sname = "smps4-in",
e5ce4208
GG		 79 .vsel_addr = PALMAS_SMPS45_VOLTAGE,
80 .ctrl_addr = PALMAS_SMPS45_CTRL,
81 .tstep_addr = PALMAS_SMPS45_TSTEP,
32b6d3f6 82 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
e5ce4208
GG		 83 },
84 {
85 .name = "SMPS6",
504382c9 86 .sname = "smps6-in",
e5ce4208
GG		 87 .vsel_addr = PALMAS_SMPS6_VOLTAGE,
88 .ctrl_addr = PALMAS_SMPS6_CTRL,
89 .tstep_addr = PALMAS_SMPS6_TSTEP,
32b6d3f6 90 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS6,
e5ce4208
GG		 91 },
92 {
93 .name = "SMPS7",
504382c9 94 .sname = "smps7-in",
e5ce4208
GG		 95 .vsel_addr = PALMAS_SMPS7_VOLTAGE,
96 .ctrl_addr = PALMAS_SMPS7_CTRL,
32b6d3f6 97 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS7,
e5ce4208
GG		 98 },
99 {
100 .name = "SMPS8",
504382c9 101 .sname = "smps8-in",
e5ce4208
GG		 102 .vsel_addr = PALMAS_SMPS8_VOLTAGE,
103 .ctrl_addr = PALMAS_SMPS8_CTRL,
104 .tstep_addr = PALMAS_SMPS8_TSTEP,
32b6d3f6 105 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS8,
e5ce4208
GG		 106 },
107 {
108 .name = "SMPS9",
504382c9 109 .sname = "smps9-in",
e5ce4208
GG		 110 .vsel_addr = PALMAS_SMPS9_VOLTAGE,
111 .ctrl_addr = PALMAS_SMPS9_CTRL,
32b6d3f6 112 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS9,
e5ce4208
GG		 113 },
114 {
77409d9b 115 .name = "SMPS10_OUT2",
504382c9 116 .sname = "smps10-in",
e31089c6 117 .ctrl_addr = PALMAS_SMPS10_CTRL,
32b6d3f6 118 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
e5ce4208 119 },
77409d9b
KVA		 120 {
121 .name = "SMPS10_OUT1",
122 .sname = "smps10-out2",
123 .ctrl_addr = PALMAS_SMPS10_CTRL,
32b6d3f6 124 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
77409d9b 125 },
e5ce4208
GG		 126 {
127 .name = "LDO1",
504382c9 128 .sname = "ldo1-in",
e5ce4208
GG		 129 .vsel_addr = PALMAS_LDO1_VOLTAGE,
130 .ctrl_addr = PALMAS_LDO1_CTRL,
32b6d3f6 131 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO1,
e5ce4208
GG		 132 },
133 {
134 .name = "LDO2",
504382c9 135 .sname = "ldo2-in",
e5ce4208
GG		 136 .vsel_addr = PALMAS_LDO2_VOLTAGE,
137 .ctrl_addr = PALMAS_LDO2_CTRL,
32b6d3f6 138 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO2,
e5ce4208
GG		 139 },
140 {
141 .name = "LDO3",
504382c9 142 .sname = "ldo3-in",
e5ce4208
GG		 143 .vsel_addr = PALMAS_LDO3_VOLTAGE,
144 .ctrl_addr = PALMAS_LDO3_CTRL,
32b6d3f6 145 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO3,
e5ce4208
GG		 146 },
147 {
148 .name = "LDO4",
504382c9 149 .sname = "ldo4-in",
e5ce4208
GG		 150 .vsel_addr = PALMAS_LDO4_VOLTAGE,
151 .ctrl_addr = PALMAS_LDO4_CTRL,
32b6d3f6 152 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO4,
e5ce4208
GG		 153 },
154 {
155 .name = "LDO5",
504382c9 156 .sname = "ldo5-in",
e5ce4208
GG		 157 .vsel_addr = PALMAS_LDO5_VOLTAGE,
158 .ctrl_addr = PALMAS_LDO5_CTRL,
32b6d3f6 159 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO5,
e5ce4208
GG		 160 },
161 {
162 .name = "LDO6",
504382c9 163 .sname = "ldo6-in",
e5ce4208
GG		 164 .vsel_addr = PALMAS_LDO6_VOLTAGE,
165 .ctrl_addr = PALMAS_LDO6_CTRL,
32b6d3f6 166 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO6,
e5ce4208
GG		 167 },
168 {
169 .name = "LDO7",
504382c9 170 .sname = "ldo7-in",
e5ce4208
GG		 171 .vsel_addr = PALMAS_LDO7_VOLTAGE,
172 .ctrl_addr = PALMAS_LDO7_CTRL,
32b6d3f6 173 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO7,
e5ce4208
GG		 174 },
175 {
176 .name = "LDO8",
504382c9 177 .sname = "ldo8-in",
e5ce4208
GG		 178 .vsel_addr = PALMAS_LDO8_VOLTAGE,
179 .ctrl_addr = PALMAS_LDO8_CTRL,
32b6d3f6 180 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO8,
e5ce4208
GG		 181 },
182 {
183 .name = "LDO9",
504382c9 184 .sname = "ldo9-in",
e5ce4208
GG		 185 .vsel_addr = PALMAS_LDO9_VOLTAGE,
186 .ctrl_addr = PALMAS_LDO9_CTRL,
32b6d3f6 187 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO9,
e5ce4208
GG		 188 },
189 {
190 .name = "LDOLN",
504382c9 191 .sname = "ldoln-in",
e5ce4208
GG		 192 .vsel_addr = PALMAS_LDOLN_VOLTAGE,
193 .ctrl_addr = PALMAS_LDOLN_CTRL,
32b6d3f6 194 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDOLN,
e5ce4208
GG		 195 },
196 {
197 .name = "LDOUSB",
504382c9 198 .sname = "ldousb-in",
e5ce4208
GG		 199 .vsel_addr = PALMAS_LDOUSB_VOLTAGE,
200 .ctrl_addr = PALMAS_LDOUSB_CTRL,
32b6d3f6 201 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDOUSB,
e5ce4208 202 },
aa07f027
LD		 203 {
204 .name = "REGEN1",
205 .ctrl_addr = PALMAS_REGEN1_CTRL,
32b6d3f6 206 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN1,
aa07f027
LD		 207 },
208 {
209 .name = "REGEN2",
210 .ctrl_addr = PALMAS_REGEN2_CTRL,
32b6d3f6 211 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN2,
aa07f027
LD		 212 },
213 {
214 .name = "REGEN3",
215 .ctrl_addr = PALMAS_REGEN3_CTRL,
32b6d3f6 216 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN3,
aa07f027
LD		 217 },
218 {
219 .name = "SYSEN1",
220 .ctrl_addr = PALMAS_SYSEN1_CTRL,
32b6d3f6 221 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SYSEN1,
aa07f027
LD		 222 },
223 {
224 .name = "SYSEN2",
225 .ctrl_addr = PALMAS_SYSEN2_CTRL,
32b6d3f6 226 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SYSEN2,
aa07f027 227 },
e5ce4208
GG		 228};
229
e7cf34ef 230static struct palmas_regs_info tps65917_regs_info[] = {
d6f83370
K		 231 {
232 .name = "SMPS1",
233 .sname = "smps1-in",
234 .vsel_addr = TPS65917_SMPS1_VOLTAGE,
235 .ctrl_addr = TPS65917_SMPS1_CTRL,
236 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS1,
237 },
238 {
239 .name = "SMPS2",
240 .sname = "smps2-in",
241 .vsel_addr = TPS65917_SMPS2_VOLTAGE,
242 .ctrl_addr = TPS65917_SMPS2_CTRL,
243 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS2,
244 },
245 {
246 .name = "SMPS3",
247 .sname = "smps3-in",
248 .vsel_addr = TPS65917_SMPS3_VOLTAGE,
249 .ctrl_addr = TPS65917_SMPS3_CTRL,
250 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS3,
251 },
252 {
253 .name = "SMPS4",
254 .sname = "smps4-in",
255 .vsel_addr = TPS65917_SMPS4_VOLTAGE,
256 .ctrl_addr = TPS65917_SMPS4_CTRL,
257 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS4,
258 },
259 {
260 .name = "SMPS5",
261 .sname = "smps5-in",
262 .vsel_addr = TPS65917_SMPS5_VOLTAGE,
263 .ctrl_addr = TPS65917_SMPS5_CTRL,
264 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS5,
265 },
266 {
267 .name = "LDO1",
268 .sname = "ldo1-in",
269 .vsel_addr = TPS65917_LDO1_VOLTAGE,
270 .ctrl_addr = TPS65917_LDO1_CTRL,
271 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO1,
272 },
273 {
274 .name = "LDO2",
275 .sname = "ldo2-in",
276 .vsel_addr = TPS65917_LDO2_VOLTAGE,
277 .ctrl_addr = TPS65917_LDO2_CTRL,
278 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO2,
279 },
280 {
281 .name = "LDO3",
282 .sname = "ldo3-in",
283 .vsel_addr = TPS65917_LDO3_VOLTAGE,
284 .ctrl_addr = TPS65917_LDO3_CTRL,
285 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO3,
286 },
287 {
288 .name = "LDO4",
289 .sname = "ldo4-in",
290 .vsel_addr = TPS65917_LDO4_VOLTAGE,
291 .ctrl_addr = TPS65917_LDO4_CTRL,
292 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO4,
293 },
294 {
295 .name = "LDO5",
296 .sname = "ldo5-in",
297 .vsel_addr = TPS65917_LDO5_VOLTAGE,
298 .ctrl_addr = TPS65917_LDO5_CTRL,
299 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO5,
300 },
301 {
302 .name = "REGEN1",
303 .ctrl_addr = TPS65917_REGEN1_CTRL,
304 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN1,
305 },
306 {
307 .name = "REGEN2",
308 .ctrl_addr = TPS65917_REGEN2_CTRL,
309 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN2,
310 },
311 {
312 .name = "REGEN3",
313 .ctrl_addr = TPS65917_REGEN3_CTRL,
314 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN3,
315 },
316};
317
cac9e916
K		 318#define EXTERNAL_REQUESTOR(_id, _offset, _pos) \
319 [PALMAS_EXTERNAL_REQSTR_ID_##_id] = { \
320 .id = PALMAS_EXTERNAL_REQSTR_ID_##_id, \
321 .reg_offset = _offset, \
322 .bit_pos = _pos, \
323 }
324
4b09e17b 325static struct palmas_sleep_requestor_info palma_sleep_req_info[] = {
cac9e916
K		 326 EXTERNAL_REQUESTOR(REGEN1, 0, 0),
327 EXTERNAL_REQUESTOR(REGEN2, 0, 1),
328 EXTERNAL_REQUESTOR(SYSEN1, 0, 2),
329 EXTERNAL_REQUESTOR(SYSEN2, 0, 3),
330 EXTERNAL_REQUESTOR(CLK32KG, 0, 4),
331 EXTERNAL_REQUESTOR(CLK32KGAUDIO, 0, 5),
332 EXTERNAL_REQUESTOR(REGEN3, 0, 6),
333 EXTERNAL_REQUESTOR(SMPS12, 1, 0),
334 EXTERNAL_REQUESTOR(SMPS3, 1, 1),
335 EXTERNAL_REQUESTOR(SMPS45, 1, 2),
336 EXTERNAL_REQUESTOR(SMPS6, 1, 3),
337 EXTERNAL_REQUESTOR(SMPS7, 1, 4),
338 EXTERNAL_REQUESTOR(SMPS8, 1, 5),
339 EXTERNAL_REQUESTOR(SMPS9, 1, 6),
340 EXTERNAL_REQUESTOR(SMPS10, 1, 7),
341 EXTERNAL_REQUESTOR(LDO1, 2, 0),
342 EXTERNAL_REQUESTOR(LDO2, 2, 1),
343 EXTERNAL_REQUESTOR(LDO3, 2, 2),
344 EXTERNAL_REQUESTOR(LDO4, 2, 3),
345 EXTERNAL_REQUESTOR(LDO5, 2, 4),
346 EXTERNAL_REQUESTOR(LDO6, 2, 5),
347 EXTERNAL_REQUESTOR(LDO7, 2, 6),
348 EXTERNAL_REQUESTOR(LDO8, 2, 7),
349 EXTERNAL_REQUESTOR(LDO9, 3, 0),
350 EXTERNAL_REQUESTOR(LDOLN, 3, 1),
351 EXTERNAL_REQUESTOR(LDOUSB, 3, 2),
352};
353
d6f83370
K		 354#define EXTERNAL_REQUESTOR_TPS65917(_id, _offset, _pos) \
355 [TPS65917_EXTERNAL_REQSTR_ID_##_id] = { \
356 .id = TPS65917_EXTERNAL_REQSTR_ID_##_id, \
357 .reg_offset = _offset, \
358 .bit_pos = _pos, \
359 }
360
361static struct palmas_sleep_requestor_info tps65917_sleep_req_info[] = {
362 EXTERNAL_REQUESTOR_TPS65917(REGEN1, 0, 0),
363 EXTERNAL_REQUESTOR_TPS65917(REGEN2, 0, 1),
364 EXTERNAL_REQUESTOR_TPS65917(REGEN3, 0, 6),
365 EXTERNAL_REQUESTOR_TPS65917(SMPS1, 1, 0),
366 EXTERNAL_REQUESTOR_TPS65917(SMPS2, 1, 1),
367 EXTERNAL_REQUESTOR_TPS65917(SMPS3, 1, 2),
368 EXTERNAL_REQUESTOR_TPS65917(SMPS4, 1, 3),
369 EXTERNAL_REQUESTOR_TPS65917(SMPS5, 1, 4),
370 EXTERNAL_REQUESTOR_TPS65917(LDO1, 2, 0),
371 EXTERNAL_REQUESTOR_TPS65917(LDO2, 2, 1),
372 EXTERNAL_REQUESTOR_TPS65917(LDO3, 2, 2),
373 EXTERNAL_REQUESTOR_TPS65917(LDO4, 2, 3),
374 EXTERNAL_REQUESTOR_TPS65917(LDO5, 2, 4),
375};
376
28d1e8cd
LD		 377static unsigned int palmas_smps_ramp_delay[4] = {0, 10000, 5000, 2500};
378
e5ce4208
GG		 379#define SMPS_CTRL_MODE_OFF 0x00
380#define SMPS_CTRL_MODE_ON 0x01
381#define SMPS_CTRL_MODE_ECO 0x02
382#define SMPS_CTRL_MODE_PWM 0x03
383
0f45aa84 384#define PALMAS_SMPS_NUM_VOLTAGES 122
e5ce4208
GG		 385#define PALMAS_SMPS10_NUM_VOLTAGES 2
386#define PALMAS_LDO_NUM_VOLTAGES 50
387
388#define SMPS10_VSEL (1<<3)
389#define SMPS10_BOOST_EN (1<<2)
390#define SMPS10_BYPASS_EN (1<<1)
391#define SMPS10_SWITCH_EN (1<<0)
392
393#define REGULATOR_SLAVE 0
394
395static int palmas_smps_read(struct palmas *palmas, unsigned int reg,
396 unsigned int *dest)
397{
398 unsigned int addr;
399
400 addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg);
401
402 return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest);
403}
404
405static int palmas_smps_write(struct palmas *palmas, unsigned int reg,
406 unsigned int value)
407{
408 unsigned int addr;
409
410 addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg);
411
412 return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value);
413}
414
415static int palmas_ldo_read(struct palmas *palmas, unsigned int reg,
416 unsigned int *dest)
417{
418 unsigned int addr;
419
420 addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg);
421
422 return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest);
423}
424
425static int palmas_ldo_write(struct palmas *palmas, unsigned int reg,
426 unsigned int value)
427{
428 unsigned int addr;
429
430 addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg);
431
432 return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value);
433}
434
e5ce4208
GG		 435static int palmas_set_mode_smps(struct regulator_dev *dev, unsigned int mode)
436{
cf910b6b 437 int id = rdev_get_id(dev);
e5ce4208 438 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
cac9e916 439 struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata;
cf910b6b 440 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
e5ce4208 441 unsigned int reg;
51d3a0c9 442 bool rail_enable = true;
e5ce4208 443
cf910b6b 444 palmas_smps_read(pmic->palmas, rinfo->ctrl_addr, &reg);
cac9e916 445
999f0c7c 446 reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
e5ce4208 447
51d3a0c9
LD		 448 if (reg == SMPS_CTRL_MODE_OFF)
449 rail_enable = false;
450
e5ce4208
GG		 451 switch (mode) {
452 case REGULATOR_MODE_NORMAL:
453 reg |= SMPS_CTRL_MODE_ON;
454 break;
455 case REGULATOR_MODE_IDLE:
456 reg |= SMPS_CTRL_MODE_ECO;
457 break;
458 case REGULATOR_MODE_FAST:
459 reg |= SMPS_CTRL_MODE_PWM;
460 break;
461 default:
462 return -EINVAL;
463 }
e5ce4208 464
51d3a0c9
LD		 465 pmic->current_reg_mode[id] = reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
466 if (rail_enable)
cf910b6b 467 palmas_smps_write(pmic->palmas, rinfo->ctrl_addr, reg);
318dbb02
NM		 468
469 /* Switch the enable value to ensure this is used for enable */
470 pmic->desc[id].enable_val = pmic->current_reg_mode[id];
471
e5ce4208
GG		 472 return 0;
473}
474
475static unsigned int palmas_get_mode_smps(struct regulator_dev *dev)
476{
477 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
478 int id = rdev_get_id(dev);
479 unsigned int reg;
480
51d3a0c9 481 reg = pmic->current_reg_mode[id] & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
e5ce4208
GG		 482
483 switch (reg) {
484 case SMPS_CTRL_MODE_ON:
485 return REGULATOR_MODE_NORMAL;
486 case SMPS_CTRL_MODE_ECO:
487 return REGULATOR_MODE_IDLE;
488 case SMPS_CTRL_MODE_PWM:
489 return REGULATOR_MODE_FAST;
490 }
491
492 return 0;
493}
494
28d1e8cd
LD		 495static int palmas_smps_set_ramp_delay(struct regulator_dev *rdev,
496 int ramp_delay)
497{
cf910b6b 498 int id = rdev_get_id(rdev);
28d1e8cd 499 struct palmas_pmic *pmic = rdev_get_drvdata(rdev);
cac9e916 500 struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata;
cf910b6b 501 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
28d1e8cd 502 unsigned int reg = 0;
28d1e8cd
LD		 503 int ret;
504
f22c2bae
AL		 505 /* SMPS3 and SMPS7 do not have tstep_addr setting */
506 switch (id) {
507 case PALMAS_REG_SMPS3:
508 case PALMAS_REG_SMPS7:
509 return 0;
510 }
511
28d1e8cd
LD		 512 if (ramp_delay <= 0)
513 reg = 0;
0ea34b57 514 else if (ramp_delay <= 2500)
28d1e8cd 515 reg = 3;
0ea34b57 516 else if (ramp_delay <= 5000)
28d1e8cd
LD		 517 reg = 2;
518 else
519 reg = 1;
520
cf910b6b 521 ret = palmas_smps_write(pmic->palmas, rinfo->tstep_addr, reg);
28d1e8cd
LD		 522 if (ret < 0) {
523 dev_err(pmic->palmas->dev, "TSTEP write failed: %d\n", ret);
524 return ret;
525 }
526
527 pmic->ramp_delay[id] = palmas_smps_ramp_delay[reg];
528 return ret;
529}
530
e5ce4208 531static struct regulator_ops palmas_ops_smps = {
dbabd624
K		 532 .is_enabled = regulator_is_enabled_regmap,
533 .enable = regulator_enable_regmap,
534 .disable = regulator_disable_regmap,
e5ce4208
GG		 535 .set_mode = palmas_set_mode_smps,
536 .get_mode = palmas_get_mode_smps,
bdc4baac
AL		 537 .get_voltage_sel = regulator_get_voltage_sel_regmap,
538 .set_voltage_sel = regulator_set_voltage_sel_regmap,
dbabd624
K		 539 .list_voltage = regulator_list_voltage_linear_range,
540 .map_voltage = regulator_map_voltage_linear_range,
541 .set_voltage_time_sel = regulator_set_voltage_time_sel,
28d1e8cd 542 .set_ramp_delay = palmas_smps_set_ramp_delay,
e5ce4208
GG		 543};
544
32b6d3f6
LD		 545static struct regulator_ops palmas_ops_ext_control_smps = {
546 .set_mode = palmas_set_mode_smps,
547 .get_mode = palmas_get_mode_smps,
548 .get_voltage_sel = regulator_get_voltage_sel_regmap,
549 .set_voltage_sel = regulator_set_voltage_sel_regmap,
dbabd624
K		 550 .list_voltage = regulator_list_voltage_linear_range,
551 .map_voltage = regulator_map_voltage_linear_range,
552 .set_voltage_time_sel = regulator_set_voltage_time_sel,
32b6d3f6
LD		 553 .set_ramp_delay = palmas_smps_set_ramp_delay,
554};
555
e5ce4208
GG		 556static struct regulator_ops palmas_ops_smps10 = {
557 .is_enabled = regulator_is_enabled_regmap,
558 .enable = regulator_enable_regmap,
559 .disable = regulator_disable_regmap,
560 .get_voltage_sel = regulator_get_voltage_sel_regmap,
561 .set_voltage_sel = regulator_set_voltage_sel_regmap,
8029a006
AL		 562 .list_voltage = regulator_list_voltage_linear,
563 .map_voltage = regulator_map_voltage_linear,
77409d9b
KVA		 564 .set_bypass = regulator_set_bypass_regmap,
565 .get_bypass = regulator_get_bypass_regmap,
e5ce4208
GG		 566};
567
d6f83370
K		 568static struct regulator_ops tps65917_ops_smps = {
569 .is_enabled = regulator_is_enabled_regmap,
570 .enable = regulator_enable_regmap,
571 .disable = regulator_disable_regmap,
572 .set_mode = palmas_set_mode_smps,
573 .get_mode = palmas_get_mode_smps,
574 .get_voltage_sel = regulator_get_voltage_sel_regmap,
575 .set_voltage_sel = regulator_set_voltage_sel_regmap,
576 .list_voltage = regulator_list_voltage_linear_range,
577 .map_voltage = regulator_map_voltage_linear_range,
578 .set_voltage_time_sel = regulator_set_voltage_time_sel,
579};
580
581static struct regulator_ops tps65917_ops_ext_control_smps = {
582 .set_mode = palmas_set_mode_smps,
583 .get_mode = palmas_get_mode_smps,
584 .get_voltage_sel = regulator_get_voltage_sel_regmap,
585 .set_voltage_sel = regulator_set_voltage_sel_regmap,
586 .list_voltage = regulator_list_voltage_linear_range,
587 .map_voltage = regulator_map_voltage_linear_range,
588};
589
e5ce4208
GG		 590static int palmas_is_enabled_ldo(struct regulator_dev *dev)
591{
cf910b6b 592 int id = rdev_get_id(dev);
e5ce4208 593 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
cac9e916 594 struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata;
cf910b6b 595 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
e5ce4208
GG		 596 unsigned int reg;
597
cf910b6b 598 palmas_ldo_read(pmic->palmas, rinfo->ctrl_addr, &reg);
e5ce4208
GG		 599
600 reg &= PALMAS_LDO1_CTRL_STATUS;
601
602 return !!(reg);
603}
604
e5ce4208
GG		 605static struct regulator_ops palmas_ops_ldo = {
606 .is_enabled = palmas_is_enabled_ldo,
607 .enable = regulator_enable_regmap,
608 .disable = regulator_disable_regmap,
4a247a96
AL		 609 .get_voltage_sel = regulator_get_voltage_sel_regmap,
610 .set_voltage_sel = regulator_set_voltage_sel_regmap,
9119ff6a
AL		 611 .list_voltage = regulator_list_voltage_linear,
612 .map_voltage = regulator_map_voltage_linear,
e5ce4208
GG		 613};
614
32b6d3f6
LD		 615static struct regulator_ops palmas_ops_ext_control_ldo = {
616 .get_voltage_sel = regulator_get_voltage_sel_regmap,
617 .set_voltage_sel = regulator_set_voltage_sel_regmap,
618 .list_voltage = regulator_list_voltage_linear,
619 .map_voltage = regulator_map_voltage_linear,
620};
621
aa07f027
LD		 622static struct regulator_ops palmas_ops_extreg = {
623 .is_enabled = regulator_is_enabled_regmap,
624 .enable = regulator_enable_regmap,
625 .disable = regulator_disable_regmap,
626};
627
32b6d3f6
LD		 628static struct regulator_ops palmas_ops_ext_control_extreg = {
629};
630
d6f83370
K		 631static struct regulator_ops tps65917_ops_ldo = {
632 .is_enabled = palmas_is_enabled_ldo,
633 .enable = regulator_enable_regmap,
634 .disable = regulator_disable_regmap,
635 .get_voltage_sel = regulator_get_voltage_sel_regmap,
636 .set_voltage_sel = regulator_set_voltage_sel_regmap,
637 .list_voltage = regulator_list_voltage_linear,
638 .map_voltage = regulator_map_voltage_linear,
639 .set_voltage_time_sel = regulator_set_voltage_time_sel,
640};
641
32b6d3f6
LD		 642static int palmas_regulator_config_external(struct palmas *palmas, int id,
643 struct palmas_reg_init *reg_init)
644{
cf910b6b
NM		 645 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
646 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
32b6d3f6
LD		 647 int ret;
648
cf910b6b
NM		 649 ret = palmas_ext_control_req_config(palmas, rinfo->sleep_id,
650 reg_init->roof_floor, true);
32b6d3f6
LD		 651 if (ret < 0)
652 dev_err(palmas->dev,
653 "Ext control config for regulator %d failed %d\n",
654 id, ret);
655 return ret;
656}
657
e5ce4208
GG		 658/*
659 * setup the hardware based sleep configuration of the SMPS/LDO regulators
660 * from the platform data. This is different to the software based control
661 * supported by the regulator framework as it is controlled by toggling
662 * pins on the PMIC such as PREQ, SYSEN, ...
663 */
664static int palmas_smps_init(struct palmas *palmas, int id,
665 struct palmas_reg_init *reg_init)
666{
667 unsigned int reg;
e5ce4208 668 int ret;
cac9e916 669 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
cf910b6b
NM		 670 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
671 unsigned int addr = rinfo->ctrl_addr;
e5ce4208
GG		 672
673 ret = palmas_smps_read(palmas, addr, &reg);
674 if (ret)
675 return ret;
676
fedd89b1 677 switch (id) {
77409d9b
KVA		 678 case PALMAS_REG_SMPS10_OUT1:
679 case PALMAS_REG_SMPS10_OUT2:
30590d04
LD		 680 reg &= ~PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK;
681 if (reg_init->mode_sleep)
fedd89b1
AL		 682 reg |= reg_init->mode_sleep <<
683 PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT;
fedd89b1
AL		 684 break;
685 default:
e5ce4208
GG		 686 if (reg_init->warm_reset)
687 reg |= PALMAS_SMPS12_CTRL_WR_S;
30590d04
LD		 688 else
689 reg &= ~PALMAS_SMPS12_CTRL_WR_S;
e5ce4208
GG		 690
691 if (reg_init->roof_floor)
692 reg |= PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN;
30590d04
LD		 693 else
694 reg &= ~PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN;
e5ce4208 695
30590d04
LD		 696 reg &= ~PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK;
697 if (reg_init->mode_sleep)
e5ce4208
GG		 698 reg |= reg_init->mode_sleep <<
699 PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT;
e5ce4208 700 }
fedd89b1 701
e5ce4208
GG		 702 ret = palmas_smps_write(palmas, addr, reg);
703 if (ret)
704 return ret;
705
cf910b6b 706 if (rinfo->vsel_addr && reg_init->vsel) {
e5ce4208
GG		 707
708 reg = reg_init->vsel;
709
cf910b6b 710 ret = palmas_smps_write(palmas, rinfo->vsel_addr, reg);
e5ce4208
GG		 711 if (ret)
712 return ret;
713 }
714
32b6d3f6
LD		 715 if (reg_init->roof_floor && (id != PALMAS_REG_SMPS10_OUT1) &&
716 (id != PALMAS_REG_SMPS10_OUT2)) {
717 /* Enable externally controlled regulator */
32b6d3f6
LD		 718 ret = palmas_smps_read(palmas, addr, &reg);
719 if (ret < 0)
720 return ret;
e5ce4208 721
32b6d3f6
LD		 722 if (!(reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK)) {
723 reg |= SMPS_CTRL_MODE_ON;
724 ret = palmas_smps_write(palmas, addr, reg);
725 if (ret < 0)
726 return ret;
727 }
728 return palmas_regulator_config_external(palmas, id, reg_init);
729 }
e5ce4208
GG		 730 return 0;
731}
732
733static int palmas_ldo_init(struct palmas *palmas, int id,
734 struct palmas_reg_init *reg_init)
735{
736 unsigned int reg;
737 unsigned int addr;
738 int ret;
cac9e916 739 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
cf910b6b 740 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
cac9e916 741
cf910b6b 742 addr = rinfo->ctrl_addr;
e5ce4208 743
2735daeb 744 ret = palmas_ldo_read(palmas, addr, &reg);
e5ce4208
GG		 745 if (ret)
746 return ret;
747
748 if (reg_init->warm_reset)
749 reg |= PALMAS_LDO1_CTRL_WR_S;
30590d04
LD		 750 else
751 reg &= ~PALMAS_LDO1_CTRL_WR_S;
e5ce4208
GG		 752
753 if (reg_init->mode_sleep)
754 reg |= PALMAS_LDO1_CTRL_MODE_SLEEP;
30590d04
LD		 755 else
756 reg &= ~PALMAS_LDO1_CTRL_MODE_SLEEP;
e5ce4208 757
2735daeb 758 ret = palmas_ldo_write(palmas, addr, reg);
e5ce4208
GG		 759 if (ret)
760 return ret;
761
32b6d3f6
LD		 762 if (reg_init->roof_floor) {
763 /* Enable externally controlled regulator */
32b6d3f6
LD		 764 ret = palmas_update_bits(palmas, PALMAS_LDO_BASE,
765 addr, PALMAS_LDO1_CTRL_MODE_ACTIVE,
766 PALMAS_LDO1_CTRL_MODE_ACTIVE);
767 if (ret < 0) {
768 dev_err(palmas->dev,
769 "LDO Register 0x%02x update failed %d\n",
770 addr, ret);
771 return ret;
772 }
773 return palmas_regulator_config_external(palmas, id, reg_init);
774 }
e5ce4208
GG		 775 return 0;
776}
777
aa07f027
LD		 778static int palmas_extreg_init(struct palmas *palmas, int id,
779 struct palmas_reg_init *reg_init)
780{
781 unsigned int addr;
782 int ret;
783 unsigned int val = 0;
cac9e916 784 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
cf910b6b 785 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
cac9e916 786
cf910b6b 787 addr = rinfo->ctrl_addr;
aa07f027
LD		 788
789 if (reg_init->mode_sleep)
790 val = PALMAS_REGEN1_CTRL_MODE_SLEEP;
791
792 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
793 addr, PALMAS_REGEN1_CTRL_MODE_SLEEP, val);
794 if (ret < 0) {
795 dev_err(palmas->dev, "Resource reg 0x%02x update failed %d\n",
796 addr, ret);
797 return ret;
798 }
32b6d3f6
LD		 799
800 if (reg_init->roof_floor) {
801 /* Enable externally controlled regulator */
32b6d3f6
LD		 802 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
803 addr, PALMAS_REGEN1_CTRL_MODE_ACTIVE,
804 PALMAS_REGEN1_CTRL_MODE_ACTIVE);
805 if (ret < 0) {
806 dev_err(palmas->dev,
807 "Resource Register 0x%02x update failed %d\n",
808 addr, ret);
809 return ret;
810 }
811 return palmas_regulator_config_external(palmas, id, reg_init);
812 }
aa07f027
LD		 813 return 0;
814}
815
17c11a76
LD		 816static void palmas_enable_ldo8_track(struct palmas *palmas)
817{
818 unsigned int reg;
819 unsigned int addr;
820 int ret;
cac9e916 821 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
cf910b6b 822 struct palmas_regs_info *rinfo;
cac9e916 823
cf910b6b
NM		 824 rinfo = &ddata->palmas_regs_info[PALMAS_REG_LDO8];
825 addr = rinfo->ctrl_addr;
17c11a76
LD		 826
827 ret = palmas_ldo_read(palmas, addr, &reg);
828 if (ret) {
829 dev_err(palmas->dev, "Error in reading ldo8 control reg\n");
830 return;
831 }
832
833 reg |= PALMAS_LDO8_CTRL_LDO_TRACKING_EN;
834 ret = palmas_ldo_write(palmas, addr, reg);
835 if (ret < 0) {
836 dev_err(palmas->dev, "Error in enabling tracking mode\n");
837 return;
838 }
839 /*
840 * When SMPS45 is set to off and LDO8 tracking is enabled, the LDO8
841 * output is defined by the LDO8_VOLTAGE.VSEL register divided by two,
842 * and can be set from 0.45 to 1.65 V.
843 */
cf910b6b 844 addr = rinfo->vsel_addr;
17c11a76
LD		 845 ret = palmas_ldo_read(palmas, addr, &reg);
846 if (ret) {
847 dev_err(palmas->dev, "Error in reading ldo8 voltage reg\n");
848 return;
849 }
850
851 reg = (reg << 1) & PALMAS_LDO8_VOLTAGE_VSEL_MASK;
852 ret = palmas_ldo_write(palmas, addr, reg);
853 if (ret < 0)
854 dev_err(palmas->dev, "Error in setting ldo8 voltage reg\n");
855
856 return;
857}
858
cac9e916
K		 859static int palmas_ldo_registration(struct palmas_pmic *pmic,
860 struct palmas_pmic_driver_data *ddata,
861 struct palmas_pmic_platform_data *pdata,
862 const char *pdev_name,
863 struct regulator_config config)
a361cd9f 864{
cac9e916
K		 865 int id, ret;
866 struct regulator_dev *rdev;
867 struct palmas_reg_init *reg_init;
cf910b6b 868 struct palmas_regs_info *rinfo;
429222d0 869 struct regulator_desc *desc;
a361cd9f 870
cac9e916
K		 871 for (id = ddata->ldo_begin; id < ddata->max_reg; id++) {
872 if (pdata && pdata->reg_init[id])
873 reg_init = pdata->reg_init[id];
874 else
875 reg_init = NULL;
a361cd9f 876
cf910b6b 877 rinfo = &ddata->palmas_regs_info[id];
cac9e916
K		 878 /* Miss out regulators which are not available due
879 * to alternate functions.
880 */
a361cd9f 881
cac9e916 882 /* Register the regulators */
429222d0
NM		 883 desc = &pmic->desc[id];
884 desc->name = rinfo->name;
885 desc->id = id;
886 desc->type = REGULATOR_VOLTAGE;
887 desc->owner = THIS_MODULE;
a361cd9f 888
cac9e916 889 if (id < PALMAS_REG_REGEN1) {
429222d0 890 desc->n_voltages = PALMAS_LDO_NUM_VOLTAGES;
cac9e916 891 if (reg_init && reg_init->roof_floor)
429222d0 892 desc->ops = &palmas_ops_ext_control_ldo;
cac9e916 893 else
429222d0
NM		 894 desc->ops = &palmas_ops_ldo;
895 desc->min_uV = 900000;
896 desc->uV_step = 50000;
897 desc->linear_min_sel = 1;
898 desc->enable_time = 500;
899 desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
900 rinfo->vsel_addr);
901 desc->vsel_mask = PALMAS_LDO1_VOLTAGE_VSEL_MASK;
902 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
903 rinfo->ctrl_addr);
904 desc->enable_mask = PALMAS_LDO1_CTRL_MODE_ACTIVE;
a361cd9f 905
cac9e916
K		 906 /* Check if LDO8 is in tracking mode or not */
907 if (pdata && (id == PALMAS_REG_LDO8) &&
908 pdata->enable_ldo8_tracking) {
909 palmas_enable_ldo8_track(pmic->palmas);
429222d0
NM		 910 desc->min_uV = 450000;
911 desc->uV_step = 25000;
cac9e916 912 }
a361cd9f 913
cac9e916
K		 914 /* LOD6 in vibrator mode will have enable time 2000us */
915 if (pdata && pdata->ldo6_vibrator &&
916 (id == PALMAS_REG_LDO6))
429222d0 917 desc->enable_time = 2000;
cac9e916 918 } else {
429222d0 919 desc->n_voltages = 1;
cac9e916 920 if (reg_init && reg_init->roof_floor)
429222d0 921 desc->ops = &palmas_ops_ext_control_extreg;
cac9e916 922 else
429222d0
NM		 923 desc->ops = &palmas_ops_extreg;
924 desc->enable_reg =
cac9e916 925 PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE,
cf910b6b 926 rinfo->ctrl_addr);
429222d0 927 desc->enable_mask = PALMAS_REGEN1_CTRL_MODE_ACTIVE;
cac9e916 928 }
a361cd9f 929
cac9e916
K		 930 if (pdata)
931 config.init_data = pdata->reg_data[id];
932 else
933 config.init_data = NULL;
32b6d3f6 934
429222d0 935 desc->supply_name = rinfo->sname;
cac9e916 936 config.of_node = ddata->palmas_matches[id].of_node;
a361cd9f 937
429222d0 938 rdev = devm_regulator_register(pmic->dev, desc, &config);
cac9e916
K		 939 if (IS_ERR(rdev)) {
940 dev_err(pmic->dev,
941 "failed to register %s regulator\n",
942 pdev_name);
943 return PTR_ERR(rdev);
944 }
a361cd9f 945
cac9e916
K		 946 /* Save regulator for cleanup */
947 pmic->rdev[id] = rdev;
a361cd9f 948
cac9e916
K		 949 /* Initialise sleep/init values from platform data */
950 if (pdata) {
951 reg_init = pdata->reg_init[id];
952 if (reg_init) {
953 if (id <= ddata->ldo_end)
954 ret = palmas_ldo_init(pmic->palmas, id,
955 reg_init);
956 else
957 ret = palmas_extreg_init(pmic->palmas,
958 id, reg_init);
959 if (ret)
960 return ret;
961 }
962 }
a361cd9f
GG		 963 }
964
cac9e916 965 return 0;
a361cd9f
GG		 966}
967
d6f83370
K		 968static int tps65917_ldo_registration(struct palmas_pmic *pmic,
969 struct palmas_pmic_driver_data *ddata,
970 struct palmas_pmic_platform_data *pdata,
971 const char *pdev_name,
972 struct regulator_config config)
973{
974 int id, ret;
975 struct regulator_dev *rdev;
976 struct palmas_reg_init *reg_init;
cf910b6b 977 struct palmas_regs_info *rinfo;
429222d0 978 struct regulator_desc *desc;
d6f83370
K		 979
980 for (id = ddata->ldo_begin; id < ddata->max_reg; id++) {
981 if (pdata && pdata->reg_init[id])
982 reg_init = pdata->reg_init[id];
983 else
984 reg_init = NULL;
985
986 /* Miss out regulators which are not available due
987 * to alternate functions.
988 */
cf910b6b 989 rinfo = &ddata->palmas_regs_info[id];
d6f83370
K		 990
991 /* Register the regulators */
429222d0
NM		 992 desc = &pmic->desc[id];
993 desc->name = rinfo->name;
994 desc->id = id;
995 desc->type = REGULATOR_VOLTAGE;
996 desc->owner = THIS_MODULE;
d6f83370
K		 997
998 if (id < TPS65917_REG_REGEN1) {
429222d0 999 desc->n_voltages = PALMAS_LDO_NUM_VOLTAGES;
d6f83370 1000 if (reg_init && reg_init->roof_floor)
429222d0 1001 desc->ops = &palmas_ops_ext_control_ldo;
d6f83370 1002 else
429222d0
NM		 1003 desc->ops = &tps65917_ops_ldo;
1004 desc->min_uV = 900000;
1005 desc->uV_step = 50000;
1006 desc->linear_min_sel = 1;
1007 desc->enable_time = 500;
1008 desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
1009 rinfo->vsel_addr);
1010 desc->vsel_mask = PALMAS_LDO1_VOLTAGE_VSEL_MASK;
1011 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
1012 rinfo->ctrl_addr);
1013 desc->enable_mask = PALMAS_LDO1_CTRL_MODE_ACTIVE;
d6f83370
K		 1014 /*
1015 * To be confirmed. Discussion on going with PMIC Team.
1016 * It is of the order of ~60mV/uS.
1017 */
429222d0 1018 desc->ramp_delay = 2500;
d6f83370 1019 } else {
429222d0 1020 desc->n_voltages = 1;
d6f83370 1021 if (reg_init && reg_init->roof_floor)
429222d0 1022 desc->ops = &palmas_ops_ext_control_extreg;
d6f83370 1023 else
429222d0
NM		 1024 desc->ops = &palmas_ops_extreg;
1025 desc->enable_reg =
d6f83370 1026 PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE,
cf910b6b 1027 rinfo->ctrl_addr);
429222d0 1028 desc->enable_mask = PALMAS_REGEN1_CTRL_MODE_ACTIVE;
d6f83370
K		 1029 }
1030
1031 if (pdata)
1032 config.init_data = pdata->reg_data[id];
1033 else
1034 config.init_data = NULL;
1035
429222d0 1036 desc->supply_name = rinfo->sname;
d6f83370
K		 1037 config.of_node = ddata->palmas_matches[id].of_node;
1038
429222d0 1039 rdev = devm_regulator_register(pmic->dev, desc, &config);
d6f83370
K		 1040 if (IS_ERR(rdev)) {
1041 dev_err(pmic->dev,
1042 "failed to register %s regulator\n",
1043 pdev_name);
1044 return PTR_ERR(rdev);
1045 }
1046
1047 /* Save regulator for cleanup */
1048 pmic->rdev[id] = rdev;
1049
1050 /* Initialise sleep/init values from platform data */
1051 if (pdata) {
1052 reg_init = pdata->reg_init[id];
1053 if (reg_init) {
1054 if (id < TPS65917_REG_REGEN1)
1055 ret = palmas_ldo_init(pmic->palmas,
1056 id, reg_init);
1057 else
1058 ret = palmas_extreg_init(pmic->palmas,
1059 id, reg_init);
1060 if (ret)
1061 return ret;
1062 }
1063 }
1064 }
1065
1066 return 0;
1067}
1068
cac9e916
K		 1069static int palmas_smps_registration(struct palmas_pmic *pmic,
1070 struct palmas_pmic_driver_data *ddata,
1071 struct palmas_pmic_platform_data *pdata,
1072 const char *pdev_name,
1073 struct regulator_config config)
e5ce4208 1074{
cac9e916
K		 1075 int id, ret;
1076 unsigned int addr, reg;
e5ce4208 1077 struct regulator_dev *rdev;
e5ce4208 1078 struct palmas_reg_init *reg_init;
cf910b6b 1079 struct palmas_regs_info *rinfo;
429222d0 1080 struct regulator_desc *desc;
e5ce4208 1081
cac9e916 1082 for (id = ddata->smps_start; id <= ddata->smps_end; id++) {
28d1e8cd 1083 bool ramp_delay_support = false;
e5ce4208
GG		 1084
1085 /*
1086 * Miss out regulators which are not available due
1087 * to slaving configurations.
1088 */
1089 switch (id) {
1090 case PALMAS_REG_SMPS12:
1091 case PALMAS_REG_SMPS3:
1092 if (pmic->smps123)
1093 continue;
28d1e8cd
LD		 1094 if (id == PALMAS_REG_SMPS12)
1095 ramp_delay_support = true;
e5ce4208
GG		 1096 break;
1097 case PALMAS_REG_SMPS123:
1098 if (!pmic->smps123)
1099 continue;
28d1e8cd 1100 ramp_delay_support = true;
e5ce4208
GG		 1101 break;
1102 case PALMAS_REG_SMPS45:
1103 case PALMAS_REG_SMPS7:
1104 if (pmic->smps457)
1105 continue;
28d1e8cd
LD		 1106 if (id == PALMAS_REG_SMPS45)
1107 ramp_delay_support = true;
e5ce4208
GG		 1108 break;
1109 case PALMAS_REG_SMPS457:
1110 if (!pmic->smps457)
1111 continue;
28d1e8cd
LD		 1112 ramp_delay_support = true;
1113 break;
77409d9b
KVA		 1114 case PALMAS_REG_SMPS10_OUT1:
1115 case PALMAS_REG_SMPS10_OUT2:
cac9e916 1116 if (!PALMAS_PMIC_HAS(pmic->palmas, SMPS10_BOOST))
1ffb0be3 1117 continue;
28d1e8cd 1118 }
cf910b6b 1119 rinfo = &ddata->palmas_regs_info[id];
429222d0 1120 desc = &pmic->desc[id];
28d1e8cd 1121
3f4d6364 1122 if ((id == PALMAS_REG_SMPS6) || (id == PALMAS_REG_SMPS8))
28d1e8cd
LD		 1123 ramp_delay_support = true;
1124
1125 if (ramp_delay_support) {
cf910b6b 1126 addr = rinfo->tstep_addr;
28d1e8cd
LD		 1127 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1128 if (ret < 0) {
cac9e916 1129 dev_err(pmic->dev,
28d1e8cd 1130 "reading TSTEP reg failed: %d\n", ret);
51c86b3e 1131 return ret;
28d1e8cd 1132 }
429222d0
NM		 1133 desc->ramp_delay = palmas_smps_ramp_delay[reg & 0x3];
1134 pmic->ramp_delay[id] = desc->ramp_delay;
e5ce4208
GG		 1135 }
1136
bdc4baac
AL		 1137 /* Initialise sleep/init values from platform data */
1138 if (pdata && pdata->reg_init[id]) {
1139 reg_init = pdata->reg_init[id];
cac9e916 1140 ret = palmas_smps_init(pmic->palmas, id, reg_init);
bdc4baac 1141 if (ret)
51c86b3e 1142 return ret;
32b6d3f6
LD		 1143 } else {
1144 reg_init = NULL;
bdc4baac
AL		 1145 }
1146
e5ce4208 1147 /* Register the regulators */
429222d0
NM		 1148 desc->name = rinfo->name;
1149 desc->id = id;
e5ce4208 1150
fedd89b1 1151 switch (id) {
77409d9b
KVA		 1152 case PALMAS_REG_SMPS10_OUT1:
1153 case PALMAS_REG_SMPS10_OUT2:
429222d0
NM		 1154 desc->n_voltages = PALMAS_SMPS10_NUM_VOLTAGES;
1155 desc->ops = &palmas_ops_smps10;
1156 desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1157 PALMAS_SMPS10_CTRL);
1158 desc->vsel_mask = SMPS10_VSEL;
1159 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1160 PALMAS_SMPS10_CTRL);
77409d9b 1161 if (id == PALMAS_REG_SMPS10_OUT1)
429222d0 1162 desc->enable_mask = SMPS10_SWITCH_EN;
77409d9b 1163 else
429222d0
NM		 1164 desc->enable_mask = SMPS10_BOOST_EN;
1165 desc->bypass_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1166 PALMAS_SMPS10_CTRL);
1167 desc->bypass_mask = SMPS10_BYPASS_EN;
1168 desc->min_uV = 3750000;
1169 desc->uV_step = 1250000;
fedd89b1
AL		 1170 break;
1171 default:
bdc4baac
AL		 1172 /*
1173 * Read and store the RANGE bit for later use
1174 * This must be done before regulator is probed,
51d3a0c9
LD		 1175 * otherwise we error in probe with unsupportable
1176 * ranges. Read the current smps mode for later use.
bdc4baac 1177 */
cf910b6b 1178 addr = rinfo->vsel_addr;
429222d0 1179 desc->n_linear_ranges = 3;
e5ce4208
GG		 1180
1181 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1182 if (ret)
51c86b3e 1183 return ret;
e5ce4208
GG		 1184 if (reg & PALMAS_SMPS12_VOLTAGE_RANGE)
1185 pmic->range[id] = 1;
dbabd624 1186 if (pmic->range[id])
429222d0 1187 desc->linear_ranges = smps_high_ranges;
dbabd624 1188 else
429222d0 1189 desc->linear_ranges = smps_low_ranges;
bdc4baac 1190
32b6d3f6 1191 if (reg_init && reg_init->roof_floor)
429222d0 1192 desc->ops = &palmas_ops_ext_control_smps;
32b6d3f6 1193 else
429222d0
NM		 1194 desc->ops = &palmas_ops_smps;
1195 desc->n_voltages = PALMAS_SMPS_NUM_VOLTAGES;
1196 desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1197 rinfo->vsel_addr);
1198 desc->vsel_mask = PALMAS_SMPS12_VOLTAGE_VSEL_MASK;
51d3a0c9
LD		 1199
1200 /* Read the smps mode for later use. */
cf910b6b 1201 addr = rinfo->ctrl_addr;
51d3a0c9
LD		 1202 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1203 if (ret)
51c86b3e 1204 return ret;
51d3a0c9
LD		 1205 pmic->current_reg_mode[id] = reg &
1206 PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
318dbb02 1207
429222d0
NM		 1208 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1209 rinfo->ctrl_addr);
1210 desc->enable_mask = PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
318dbb02 1211 /* set_mode overrides this value */
429222d0 1212 desc->enable_val = SMPS_CTRL_MODE_ON;
e5ce4208
GG		 1213 }
1214
429222d0
NM		 1215 desc->type = REGULATOR_VOLTAGE;
1216 desc->owner = THIS_MODULE;
bdc4baac 1217
a361cd9f 1218 if (pdata)
e5ce4208
GG		 1219 config.init_data = pdata->reg_data[id];
1220 else
1221 config.init_data = NULL;
1222
429222d0 1223 desc->supply_name = rinfo->sname;
cac9e916 1224 config.of_node = ddata->palmas_matches[id].of_node;
a361cd9f 1225
429222d0 1226 rdev = devm_regulator_register(pmic->dev, desc, &config);
e5ce4208 1227 if (IS_ERR(rdev)) {
cac9e916 1228 dev_err(pmic->dev,
e5ce4208 1229 "failed to register %s regulator\n",
cac9e916 1230 pdev_name);
51c86b3e 1231 return PTR_ERR(rdev);
e5ce4208
GG		 1232 }
1233
1234 /* Save regulator for cleanup */
1235 pmic->rdev[id] = rdev;
1236 }
1237
cac9e916
K		 1238 return 0;
1239}
e5ce4208 1240
d6f83370
K		 1241static int tps65917_smps_registration(struct palmas_pmic *pmic,
1242 struct palmas_pmic_driver_data *ddata,
1243 struct palmas_pmic_platform_data *pdata,
1244 const char *pdev_name,
1245 struct regulator_config config)
1246{
1247 int id, ret;
1248 unsigned int addr, reg;
1249 struct regulator_dev *rdev;
1250 struct palmas_reg_init *reg_init;
cf910b6b 1251 struct palmas_regs_info *rinfo;
429222d0 1252 struct regulator_desc *desc;
d6f83370
K		 1253
1254 for (id = ddata->smps_start; id <= ddata->smps_end; id++) {
1255 /*
1256 * Miss out regulators which are not available due
1257 * to slaving configurations.
1258 */
429222d0
NM		 1259 desc = &pmic->desc[id];
1260 desc->n_linear_ranges = 3;
d6f83370
K		 1261 if ((id == TPS65917_REG_SMPS2) && pmic->smps12)
1262 continue;
1263
1264 /* Initialise sleep/init values from platform data */
1265 if (pdata && pdata->reg_init[id]) {
1266 reg_init = pdata->reg_init[id];
1267 ret = palmas_smps_init(pmic->palmas, id, reg_init);
1268 if (ret)
1269 return ret;
1270 } else {
1271 reg_init = NULL;
1272 }
cf910b6b 1273 rinfo = &ddata->palmas_regs_info[id];
d6f83370
K		 1274
1275 /* Register the regulators */
429222d0
NM		 1276 desc->name = rinfo->name;
1277 desc->id = id;
d6f83370
K		 1278
1279 /*
1280 * Read and store the RANGE bit for later use
1281 * This must be done before regulator is probed,
1282 * otherwise we error in probe with unsupportable
1283 * ranges. Read the current smps mode for later use.
1284 */
cf910b6b 1285 addr = rinfo->vsel_addr;
d6f83370
K		 1286
1287 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1288 if (ret)
1289 return ret;
1290 if (reg & TPS65917_SMPS1_VOLTAGE_RANGE)
1291 pmic->range[id] = 1;
1292
1293 if (pmic->range[id])
429222d0
NM		 1294 desc->linear_ranges = smps_high_ranges;
1295 else
1296 desc->linear_ranges = smps_low_ranges;
d6f83370
K		 1297
1298 if (reg_init && reg_init->roof_floor)
429222d0 1299 desc->ops = &tps65917_ops_ext_control_smps;
d6f83370 1300 else
429222d0
NM		 1301 desc->ops = &tps65917_ops_smps;
1302 desc->n_voltages = PALMAS_SMPS_NUM_VOLTAGES;
1303 desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1304 rinfo->vsel_addr);
1305 desc->vsel_mask = PALMAS_SMPS12_VOLTAGE_VSEL_MASK;
1306 desc->ramp_delay = 2500;
d6f83370
K		 1307
1308 /* Read the smps mode for later use. */
cf910b6b 1309 addr = rinfo->ctrl_addr;
d6f83370
K		 1310 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1311 if (ret)
1312 return ret;
1313 pmic->current_reg_mode[id] = reg &
1314 PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
b632815e
NM		 1315 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1316 rinfo->ctrl_addr);
1317 desc->enable_mask = PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
1318 /* set_mode overrides this value */
1319 desc->enable_val = SMPS_CTRL_MODE_ON;
d6f83370 1320
429222d0
NM		 1321 desc->type = REGULATOR_VOLTAGE;
1322 desc->owner = THIS_MODULE;
d6f83370
K		 1323
1324 if (pdata)
1325 config.init_data = pdata->reg_data[id];
1326 else
1327 config.init_data = NULL;
1328
429222d0 1329 desc->supply_name = rinfo->sname;
d6f83370
K		 1330 config.of_node = ddata->palmas_matches[id].of_node;
1331
429222d0 1332 rdev = devm_regulator_register(pmic->dev, desc, &config);
d6f83370
K		 1333 if (IS_ERR(rdev)) {
1334 dev_err(pmic->dev,
1335 "failed to register %s regulator\n",
1336 pdev_name);
1337 return PTR_ERR(rdev);
1338 }
1339
1340 /* Save regulator for cleanup */
1341 pmic->rdev[id] = rdev;
1342 }
1343
1344 return 0;
1345}
1346
cac9e916
K		 1347static struct of_regulator_match palmas_matches[] = {
1348 { .name = "smps12", },
1349 { .name = "smps123", },
1350 { .name = "smps3", },
1351 { .name = "smps45", },
1352 { .name = "smps457", },
1353 { .name = "smps6", },
1354 { .name = "smps7", },
1355 { .name = "smps8", },
1356 { .name = "smps9", },
1357 { .name = "smps10_out2", },
1358 { .name = "smps10_out1", },
1359 { .name = "ldo1", },
1360 { .name = "ldo2", },
1361 { .name = "ldo3", },
1362 { .name = "ldo4", },
1363 { .name = "ldo5", },
1364 { .name = "ldo6", },
1365 { .name = "ldo7", },
1366 { .name = "ldo8", },
1367 { .name = "ldo9", },
1368 { .name = "ldoln", },
1369 { .name = "ldousb", },
1370 { .name = "regen1", },
1371 { .name = "regen2", },
1372 { .name = "regen3", },
1373 { .name = "sysen1", },
1374 { .name = "sysen2", },
1375};
e5ce4208 1376
d6f83370
K		 1377static struct of_regulator_match tps65917_matches[] = {
1378 { .name = "smps1", },
1379 { .name = "smps2", },
1380 { .name = "smps3", },
1381 { .name = "smps4", },
1382 { .name = "smps5", },
1383 { .name = "ldo1", },
1384 { .name = "ldo2", },
1385 { .name = "ldo3", },
1386 { .name = "ldo4", },
1387 { .name = "ldo5", },
1388 { .name = "regen1", },
1389 { .name = "regen2", },
1390 { .name = "regen3", },
1391 { .name = "sysen1", },
1392 { .name = "sysen2", },
1393};
1394
4b09e17b 1395static struct palmas_pmic_driver_data palmas_ddata = {
cac9e916
K		 1396 .smps_start = PALMAS_REG_SMPS12,
1397 .smps_end = PALMAS_REG_SMPS10_OUT1,
1398 .ldo_begin = PALMAS_REG_LDO1,
1399 .ldo_end = PALMAS_REG_LDOUSB,
1400 .max_reg = PALMAS_NUM_REGS,
6839cd6f 1401 .palmas_regs_info = palmas_generic_regs_info,
cac9e916
K		 1402 .palmas_matches = palmas_matches,
1403 .sleep_req_info = palma_sleep_req_info,
1404 .smps_register = palmas_smps_registration,
1405 .ldo_register = palmas_ldo_registration,
1406};
aa07f027 1407
4b09e17b 1408static struct palmas_pmic_driver_data tps65917_ddata = {
d6f83370
K		 1409 .smps_start = TPS65917_REG_SMPS1,
1410 .smps_end = TPS65917_REG_SMPS5,
1411 .ldo_begin = TPS65917_REG_LDO1,
1412 .ldo_end = TPS65917_REG_LDO5,
1413 .max_reg = TPS65917_NUM_REGS,
1414 .palmas_regs_info = tps65917_regs_info,
1415 .palmas_matches = tps65917_matches,
1416 .sleep_req_info = tps65917_sleep_req_info,
1417 .smps_register = tps65917_smps_registration,
1418 .ldo_register = tps65917_ldo_registration,
1419};
1420
cac9e916
K		 1421static void palmas_dt_to_pdata(struct device *dev,
1422 struct device_node *node,
1423 struct palmas_pmic_platform_data *pdata,
1424 struct palmas_pmic_driver_data *ddata)
1425{
1426 struct device_node *regulators;
1427 u32 prop;
1428 int idx, ret;
17c11a76 1429
cac9e916
K		 1430 regulators = of_get_child_by_name(node, "regulators");
1431 if (!regulators) {
1432 dev_info(dev, "regulator node not found\n");
1433 return;
1434 }
087d30e3 1435
cac9e916
K		 1436 ret = of_regulator_match(dev, regulators, ddata->palmas_matches,
1437 ddata->max_reg);
1438 of_node_put(regulators);
1439 if (ret < 0) {
1440 dev_err(dev, "Error parsing regulator init data: %d\n", ret);
1441 return;
1442 }
e5ce4208 1443
cac9e916
K		 1444 for (idx = 0; idx < ddata->max_reg; idx++) {
1445 if (!ddata->palmas_matches[idx].init_data ||
1446 !ddata->palmas_matches[idx].of_node)
1447 continue;
e5ce4208 1448
cac9e916 1449 pdata->reg_data[idx] = ddata->palmas_matches[idx].init_data;
a361cd9f 1450
cac9e916
K		 1451 pdata->reg_init[idx] = devm_kzalloc(dev,
1452 sizeof(struct palmas_reg_init), GFP_KERNEL);
e5ce4208 1453
cac9e916
K		 1454 pdata->reg_init[idx]->warm_reset =
1455 of_property_read_bool(ddata->palmas_matches[idx].of_node,
1456 "ti,warm-reset");
e5ce4208 1457
cac9e916
K		 1458 ret = of_property_read_u32(ddata->palmas_matches[idx].of_node,
1459 "ti,roof-floor", &prop);
1460 /* EINVAL: Property not found */
1461 if (ret != -EINVAL) {
1462 int econtrol;
1463
1464 /* use default value, when no value is specified */
1465 econtrol = PALMAS_EXT_CONTROL_NSLEEP;
1466 if (!ret) {
1467 switch (prop) {
1468 case 1:
1469 econtrol = PALMAS_EXT_CONTROL_ENABLE1;
1470 break;
1471 case 2:
1472 econtrol = PALMAS_EXT_CONTROL_ENABLE2;
1473 break;
1474 case 3:
1475 econtrol = PALMAS_EXT_CONTROL_NSLEEP;
1476 break;
1477 default:
1478 WARN_ON(1);
1479 dev_warn(dev,
1480 "%s: Invalid roof-floor option: %u\n",
1481 palmas_matches[idx].name, prop);
1482 break;
1483 }
e5ce4208 1484 }
cac9e916 1485 pdata->reg_init[idx]->roof_floor = econtrol;
e5ce4208 1486 }
e5ce4208 1487
cac9e916
K		 1488 ret = of_property_read_u32(ddata->palmas_matches[idx].of_node,
1489 "ti,mode-sleep", &prop);
1490 if (!ret)
1491 pdata->reg_init[idx]->mode_sleep = prop;
17c11a76 1492
cac9e916
K		 1493 ret = of_property_read_bool(ddata->palmas_matches[idx].of_node,
1494 "ti,smps-range");
1495 if (ret)
1496 pdata->reg_init[idx]->vsel =
1497 PALMAS_SMPS12_VOLTAGE_RANGE;
1498
1499 if (idx == PALMAS_REG_LDO8)
1500 pdata->enable_ldo8_tracking = of_property_read_bool(
1501 ddata->palmas_matches[idx].of_node,
1502 "ti,enable-ldo8-tracking");
1503 }
1504
1505 pdata->ldo6_vibrator = of_property_read_bool(node, "ti,ldo6-vibrator");
e5ce4208
GG		 1506}
1507
cdbf6f0e 1508static const struct of_device_id of_palmas_match_tbl[] = {
cac9e916
K		 1509 {
1510 .compatible = "ti,palmas-pmic",
1511 .data = &palmas_ddata,
1512 },
1513 {
1514 .compatible = "ti,twl6035-pmic",
1515 .data = &palmas_ddata,
1516 },
1517 {
1518 .compatible = "ti,twl6036-pmic",
1519 .data = &palmas_ddata,
1520 },
1521 {
1522 .compatible = "ti,twl6037-pmic",
1523 .data = &palmas_ddata,
1524 },
1525 {
1526 .compatible = "ti,tps65913-pmic",
1527 .data = &palmas_ddata,
1528 },
1529 {
1530 .compatible = "ti,tps65914-pmic",
1531 .data = &palmas_ddata,
1532 },
1533 {
1534 .compatible = "ti,tps80036-pmic",
1535 .data = &palmas_ddata,
1536 },
1537 {
1538 .compatible = "ti,tps659038-pmic",
1539 .data = &palmas_ddata,
d6f83370
K		 1540 },
1541 {
1542 .compatible = "ti,tps65917-pmic",
1543 .data = &tps65917_ddata,
cac9e916 1544 },
a361cd9f
GG		 1545 { /* end */ }
1546};
1547
cac9e916
K		 1548static int palmas_regulators_probe(struct platform_device *pdev)
1549{
1550 struct palmas *palmas = dev_get_drvdata(pdev->dev.parent);
1551 struct palmas_pmic_platform_data *pdata = dev_get_platdata(&pdev->dev);
1552 struct device_node *node = pdev->dev.of_node;
1553 struct palmas_pmic_driver_data *driver_data;
1554 struct regulator_config config = { };
1555 struct palmas_pmic *pmic;
1556 const char *pdev_name;
1557 const struct of_device_id *match;
1558 int ret = 0;
1559 unsigned int reg;
1560
1561 match = of_match_device(of_match_ptr(of_palmas_match_tbl), &pdev->dev);
1562
1563 if (!match)
1564 return -ENODATA;
1565
1566 driver_data = (struct palmas_pmic_driver_data *)match->data;
1567 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1568 if (!pdata)
1569 return -ENOMEM;
1570
1571 pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
1572 if (!pmic)
1573 return -ENOMEM;
1574
e03826d5
K		 1575 if (of_device_is_compatible(node, "ti,tps659038-pmic"))
1576 palmas_generic_regs_info[PALMAS_REG_REGEN2].ctrl_addr =
1577 TPS659038_REGEN2_CTRL;
1578
cac9e916
K		 1579 pmic->dev = &pdev->dev;
1580 pmic->palmas = palmas;
1581 palmas->pmic = pmic;
1582 platform_set_drvdata(pdev, pmic);
1583 pmic->palmas->pmic_ddata = driver_data;
1584
1585 palmas_dt_to_pdata(&pdev->dev, node, pdata, driver_data);
1586
1587 ret = palmas_smps_read(palmas, PALMAS_SMPS_CTRL, &reg);
1588 if (ret)
1589 return ret;
1590
1591 if (reg & PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN)
1592 pmic->smps123 = 1;
1593
1594 if (reg & PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN)
1595 pmic->smps457 = 1;
1596
1597 config.regmap = palmas->regmap[REGULATOR_SLAVE];
1598 config.dev = &pdev->dev;
1599 config.driver_data = pmic;
1600 pdev_name = pdev->name;
1601
1602 ret = driver_data->smps_register(pmic, driver_data, pdata, pdev_name,
1603 config);
1604 if (ret)
1605 return ret;
1606
1607 ret = driver_data->ldo_register(pmic, driver_data, pdata, pdev_name,
1608 config);
1609
1610 return ret;
1611}
1612
e5ce4208
GG		 1613static struct platform_driver palmas_driver = {
1614 .driver = {
1615 .name = "palmas-pmic",
a361cd9f 1616 .of_match_table = of_palmas_match_tbl,
e5ce4208 1617 },
bbcf50b1 1618 .probe = palmas_regulators_probe,
e5ce4208
GG		 1619};
1620
1621static int __init palmas_init(void)
1622{
1623 return platform_driver_register(&palmas_driver);
1624}
1625subsys_initcall(palmas_init);
1626
1627static void __exit palmas_exit(void)
1628{
1629 platform_driver_unregister(&palmas_driver);
1630}
1631module_exit(palmas_exit);
1632
1633MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
1634MODULE_DESCRIPTION("Palmas voltage regulator driver");
1635MODULE_LICENSE("GPL");
1636MODULE_ALIAS("platform:palmas-pmic");
a361cd9f 1637MODULE_DEVICE_TABLE(of, of_palmas_match_tbl);
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