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[mirror_ubuntu-jammy-kernel.git] / drivers / regulator / palmas-regulator.c
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e5ce4208
GG		 1/*
2 * Driver for Regulator part of Palmas PMIC Chips
3 *
7be859f7 4 * Copyright 2011-2013 Texas Instruments Inc.
e5ce4208
GG		 5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
a7dddf27 7 * Author: Ian Lartey <ian@slimlogic.co.uk>
e5ce4208
GG		 8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/err.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/driver.h>
22#include <linux/regulator/machine.h>
23#include <linux/slab.h>
24#include <linux/regmap.h>
25#include <linux/mfd/palmas.h>
a361cd9f
GG		 26#include <linux/of.h>
27#include <linux/of_platform.h>
28#include <linux/regulator/of_regulator.h>
e5ce4208 29
dbabd624 30static const struct regulator_linear_range smps_low_ranges[] = {
6b7f2d82 31 REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0),
dbabd624
K		 32 REGULATOR_LINEAR_RANGE(500000, 0x1, 0x6, 0),
33 REGULATOR_LINEAR_RANGE(510000, 0x7, 0x79, 10000),
34 REGULATOR_LINEAR_RANGE(1650000, 0x7A, 0x7f, 0),
35};
36
37static const struct regulator_linear_range smps_high_ranges[] = {
6b7f2d82 38 REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0),
dbabd624
K		 39 REGULATOR_LINEAR_RANGE(1000000, 0x1, 0x6, 0),
40 REGULATOR_LINEAR_RANGE(1020000, 0x7, 0x79, 20000),
41 REGULATOR_LINEAR_RANGE(3300000, 0x7A, 0x7f, 0),
42};
43
6839cd6f 44static struct palmas_regs_info palmas_generic_regs_info[] = {
e5ce4208
GG		 45 {
46 .name = "SMPS12",
504382c9 47 .sname = "smps1-in",
e5ce4208
GG		 48 .vsel_addr = PALMAS_SMPS12_VOLTAGE,
49 .ctrl_addr = PALMAS_SMPS12_CTRL,
50 .tstep_addr = PALMAS_SMPS12_TSTEP,
32b6d3f6 51 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
e5ce4208
GG		 52 },
53 {
54 .name = "SMPS123",
504382c9 55 .sname = "smps1-in",
e5ce4208
GG		 56 .vsel_addr = PALMAS_SMPS12_VOLTAGE,
57 .ctrl_addr = PALMAS_SMPS12_CTRL,
58 .tstep_addr = PALMAS_SMPS12_TSTEP,
32b6d3f6 59 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
e5ce4208
GG		 60 },
61 {
62 .name = "SMPS3",
504382c9 63 .sname = "smps3-in",
e5ce4208
GG		 64 .vsel_addr = PALMAS_SMPS3_VOLTAGE,
65 .ctrl_addr = PALMAS_SMPS3_CTRL,
32b6d3f6 66 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS3,
e5ce4208
GG		 67 },
68 {
69 .name = "SMPS45",
504382c9 70 .sname = "smps4-in",
e5ce4208
GG		 71 .vsel_addr = PALMAS_SMPS45_VOLTAGE,
72 .ctrl_addr = PALMAS_SMPS45_CTRL,
73 .tstep_addr = PALMAS_SMPS45_TSTEP,
32b6d3f6 74 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
e5ce4208
GG		 75 },
76 {
77 .name = "SMPS457",
504382c9 78 .sname = "smps4-in",
e5ce4208
GG		 79 .vsel_addr = PALMAS_SMPS45_VOLTAGE,
80 .ctrl_addr = PALMAS_SMPS45_CTRL,
81 .tstep_addr = PALMAS_SMPS45_TSTEP,
32b6d3f6 82 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
e5ce4208
GG		 83 },
84 {
85 .name = "SMPS6",
504382c9 86 .sname = "smps6-in",
e5ce4208
GG		 87 .vsel_addr = PALMAS_SMPS6_VOLTAGE,
88 .ctrl_addr = PALMAS_SMPS6_CTRL,
89 .tstep_addr = PALMAS_SMPS6_TSTEP,
32b6d3f6 90 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS6,
e5ce4208
GG		 91 },
92 {
93 .name = "SMPS7",
504382c9 94 .sname = "smps7-in",
e5ce4208
GG		 95 .vsel_addr = PALMAS_SMPS7_VOLTAGE,
96 .ctrl_addr = PALMAS_SMPS7_CTRL,
32b6d3f6 97 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS7,
e5ce4208
GG		 98 },
99 {
100 .name = "SMPS8",
504382c9 101 .sname = "smps8-in",
e5ce4208
GG		 102 .vsel_addr = PALMAS_SMPS8_VOLTAGE,
103 .ctrl_addr = PALMAS_SMPS8_CTRL,
104 .tstep_addr = PALMAS_SMPS8_TSTEP,
32b6d3f6 105 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS8,
e5ce4208
GG		 106 },
107 {
108 .name = "SMPS9",
504382c9 109 .sname = "smps9-in",
e5ce4208
GG		 110 .vsel_addr = PALMAS_SMPS9_VOLTAGE,
111 .ctrl_addr = PALMAS_SMPS9_CTRL,
32b6d3f6 112 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS9,
e5ce4208
GG		 113 },
114 {
77409d9b 115 .name = "SMPS10_OUT2",
504382c9 116 .sname = "smps10-in",
e31089c6 117 .ctrl_addr = PALMAS_SMPS10_CTRL,
32b6d3f6 118 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
e5ce4208 119 },
77409d9b
KVA		 120 {
121 .name = "SMPS10_OUT1",
122 .sname = "smps10-out2",
123 .ctrl_addr = PALMAS_SMPS10_CTRL,
32b6d3f6 124 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
77409d9b 125 },
e5ce4208
GG		 126 {
127 .name = "LDO1",
504382c9 128 .sname = "ldo1-in",
e5ce4208
GG		 129 .vsel_addr = PALMAS_LDO1_VOLTAGE,
130 .ctrl_addr = PALMAS_LDO1_CTRL,
32b6d3f6 131 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO1,
e5ce4208
GG		 132 },
133 {
134 .name = "LDO2",
504382c9 135 .sname = "ldo2-in",
e5ce4208
GG		 136 .vsel_addr = PALMAS_LDO2_VOLTAGE,
137 .ctrl_addr = PALMAS_LDO2_CTRL,
32b6d3f6 138 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO2,
e5ce4208
GG		 139 },
140 {
141 .name = "LDO3",
504382c9 142 .sname = "ldo3-in",
e5ce4208
GG		 143 .vsel_addr = PALMAS_LDO3_VOLTAGE,
144 .ctrl_addr = PALMAS_LDO3_CTRL,
32b6d3f6 145 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO3,
e5ce4208
GG		 146 },
147 {
148 .name = "LDO4",
504382c9 149 .sname = "ldo4-in",
e5ce4208
GG		 150 .vsel_addr = PALMAS_LDO4_VOLTAGE,
151 .ctrl_addr = PALMAS_LDO4_CTRL,
32b6d3f6 152 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO4,
e5ce4208
GG		 153 },
154 {
155 .name = "LDO5",
504382c9 156 .sname = "ldo5-in",
e5ce4208
GG		 157 .vsel_addr = PALMAS_LDO5_VOLTAGE,
158 .ctrl_addr = PALMAS_LDO5_CTRL,
32b6d3f6 159 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO5,
e5ce4208
GG		 160 },
161 {
162 .name = "LDO6",
504382c9 163 .sname = "ldo6-in",
e5ce4208
GG		 164 .vsel_addr = PALMAS_LDO6_VOLTAGE,
165 .ctrl_addr = PALMAS_LDO6_CTRL,
32b6d3f6 166 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO6,
e5ce4208
GG		 167 },
168 {
169 .name = "LDO7",
504382c9 170 .sname = "ldo7-in",
e5ce4208
GG		 171 .vsel_addr = PALMAS_LDO7_VOLTAGE,
172 .ctrl_addr = PALMAS_LDO7_CTRL,
32b6d3f6 173 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO7,
e5ce4208
GG		 174 },
175 {
176 .name = "LDO8",
504382c9 177 .sname = "ldo8-in",
e5ce4208
GG		 178 .vsel_addr = PALMAS_LDO8_VOLTAGE,
179 .ctrl_addr = PALMAS_LDO8_CTRL,
32b6d3f6 180 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO8,
e5ce4208
GG		 181 },
182 {
183 .name = "LDO9",
504382c9 184 .sname = "ldo9-in",
e5ce4208
GG		 185 .vsel_addr = PALMAS_LDO9_VOLTAGE,
186 .ctrl_addr = PALMAS_LDO9_CTRL,
32b6d3f6 187 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO9,
e5ce4208
GG		 188 },
189 {
190 .name = "LDOLN",
504382c9 191 .sname = "ldoln-in",
e5ce4208
GG		 192 .vsel_addr = PALMAS_LDOLN_VOLTAGE,
193 .ctrl_addr = PALMAS_LDOLN_CTRL,
32b6d3f6 194 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDOLN,
e5ce4208
GG		 195 },
196 {
197 .name = "LDOUSB",
504382c9 198 .sname = "ldousb-in",
e5ce4208
GG		 199 .vsel_addr = PALMAS_LDOUSB_VOLTAGE,
200 .ctrl_addr = PALMAS_LDOUSB_CTRL,
32b6d3f6 201 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDOUSB,
e5ce4208 202 },
aa07f027
LD		 203 {
204 .name = "REGEN1",
205 .ctrl_addr = PALMAS_REGEN1_CTRL,
32b6d3f6 206 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN1,
aa07f027
LD		 207 },
208 {
209 .name = "REGEN2",
210 .ctrl_addr = PALMAS_REGEN2_CTRL,
32b6d3f6 211 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN2,
aa07f027
LD		 212 },
213 {
214 .name = "REGEN3",
215 .ctrl_addr = PALMAS_REGEN3_CTRL,
32b6d3f6 216 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN3,
aa07f027
LD		 217 },
218 {
219 .name = "SYSEN1",
220 .ctrl_addr = PALMAS_SYSEN1_CTRL,
32b6d3f6 221 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SYSEN1,
aa07f027
LD		 222 },
223 {
224 .name = "SYSEN2",
225 .ctrl_addr = PALMAS_SYSEN2_CTRL,
32b6d3f6 226 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SYSEN2,
aa07f027 227 },
e5ce4208
GG		 228};
229
e7cf34ef 230static struct palmas_regs_info tps65917_regs_info[] = {
d6f83370
K		 231 {
232 .name = "SMPS1",
233 .sname = "smps1-in",
234 .vsel_addr = TPS65917_SMPS1_VOLTAGE,
235 .ctrl_addr = TPS65917_SMPS1_CTRL,
236 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS1,
237 },
238 {
239 .name = "SMPS2",
240 .sname = "smps2-in",
241 .vsel_addr = TPS65917_SMPS2_VOLTAGE,
242 .ctrl_addr = TPS65917_SMPS2_CTRL,
243 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS2,
244 },
245 {
246 .name = "SMPS3",
247 .sname = "smps3-in",
248 .vsel_addr = TPS65917_SMPS3_VOLTAGE,
249 .ctrl_addr = TPS65917_SMPS3_CTRL,
250 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS3,
251 },
252 {
253 .name = "SMPS4",
254 .sname = "smps4-in",
255 .vsel_addr = TPS65917_SMPS4_VOLTAGE,
256 .ctrl_addr = TPS65917_SMPS4_CTRL,
257 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS4,
258 },
259 {
260 .name = "SMPS5",
261 .sname = "smps5-in",
262 .vsel_addr = TPS65917_SMPS5_VOLTAGE,
263 .ctrl_addr = TPS65917_SMPS5_CTRL,
264 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS5,
265 },
be035303
K		 266 {
267 .name = "SMPS12",
268 .sname = "smps1-in",
269 .vsel_addr = TPS65917_SMPS1_VOLTAGE,
270 .ctrl_addr = TPS65917_SMPS1_CTRL,
271 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS12,
272 },
d6f83370
K		 273 {
274 .name = "LDO1",
275 .sname = "ldo1-in",
276 .vsel_addr = TPS65917_LDO1_VOLTAGE,
277 .ctrl_addr = TPS65917_LDO1_CTRL,
278 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO1,
279 },
280 {
281 .name = "LDO2",
282 .sname = "ldo2-in",
283 .vsel_addr = TPS65917_LDO2_VOLTAGE,
284 .ctrl_addr = TPS65917_LDO2_CTRL,
285 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO2,
286 },
287 {
288 .name = "LDO3",
289 .sname = "ldo3-in",
290 .vsel_addr = TPS65917_LDO3_VOLTAGE,
291 .ctrl_addr = TPS65917_LDO3_CTRL,
292 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO3,
293 },
294 {
295 .name = "LDO4",
296 .sname = "ldo4-in",
297 .vsel_addr = TPS65917_LDO4_VOLTAGE,
298 .ctrl_addr = TPS65917_LDO4_CTRL,
299 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO4,
300 },
301 {
302 .name = "LDO5",
303 .sname = "ldo5-in",
304 .vsel_addr = TPS65917_LDO5_VOLTAGE,
305 .ctrl_addr = TPS65917_LDO5_CTRL,
306 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO5,
307 },
308 {
309 .name = "REGEN1",
310 .ctrl_addr = TPS65917_REGEN1_CTRL,
311 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN1,
312 },
313 {
314 .name = "REGEN2",
315 .ctrl_addr = TPS65917_REGEN2_CTRL,
316 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN2,
317 },
318 {
319 .name = "REGEN3",
320 .ctrl_addr = TPS65917_REGEN3_CTRL,
321 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN3,
322 },
323};
324
cac9e916
K		 325#define EXTERNAL_REQUESTOR(_id, _offset, _pos) \
326 [PALMAS_EXTERNAL_REQSTR_ID_##_id] = { \
327 .id = PALMAS_EXTERNAL_REQSTR_ID_##_id, \
328 .reg_offset = _offset, \
329 .bit_pos = _pos, \
330 }
331
4b09e17b 332static struct palmas_sleep_requestor_info palma_sleep_req_info[] = {
cac9e916
K		 333 EXTERNAL_REQUESTOR(REGEN1, 0, 0),
334 EXTERNAL_REQUESTOR(REGEN2, 0, 1),
335 EXTERNAL_REQUESTOR(SYSEN1, 0, 2),
336 EXTERNAL_REQUESTOR(SYSEN2, 0, 3),
337 EXTERNAL_REQUESTOR(CLK32KG, 0, 4),
338 EXTERNAL_REQUESTOR(CLK32KGAUDIO, 0, 5),
339 EXTERNAL_REQUESTOR(REGEN3, 0, 6),
340 EXTERNAL_REQUESTOR(SMPS12, 1, 0),
341 EXTERNAL_REQUESTOR(SMPS3, 1, 1),
342 EXTERNAL_REQUESTOR(SMPS45, 1, 2),
343 EXTERNAL_REQUESTOR(SMPS6, 1, 3),
344 EXTERNAL_REQUESTOR(SMPS7, 1, 4),
345 EXTERNAL_REQUESTOR(SMPS8, 1, 5),
346 EXTERNAL_REQUESTOR(SMPS9, 1, 6),
347 EXTERNAL_REQUESTOR(SMPS10, 1, 7),
348 EXTERNAL_REQUESTOR(LDO1, 2, 0),
349 EXTERNAL_REQUESTOR(LDO2, 2, 1),
350 EXTERNAL_REQUESTOR(LDO3, 2, 2),
351 EXTERNAL_REQUESTOR(LDO4, 2, 3),
352 EXTERNAL_REQUESTOR(LDO5, 2, 4),
353 EXTERNAL_REQUESTOR(LDO6, 2, 5),
354 EXTERNAL_REQUESTOR(LDO7, 2, 6),
355 EXTERNAL_REQUESTOR(LDO8, 2, 7),
356 EXTERNAL_REQUESTOR(LDO9, 3, 0),
357 EXTERNAL_REQUESTOR(LDOLN, 3, 1),
358 EXTERNAL_REQUESTOR(LDOUSB, 3, 2),
359};
360
d6f83370
K		 361#define EXTERNAL_REQUESTOR_TPS65917(_id, _offset, _pos) \
362 [TPS65917_EXTERNAL_REQSTR_ID_##_id] = { \
363 .id = TPS65917_EXTERNAL_REQSTR_ID_##_id, \
364 .reg_offset = _offset, \
365 .bit_pos = _pos, \
366 }
367
368static struct palmas_sleep_requestor_info tps65917_sleep_req_info[] = {
369 EXTERNAL_REQUESTOR_TPS65917(REGEN1, 0, 0),
370 EXTERNAL_REQUESTOR_TPS65917(REGEN2, 0, 1),
371 EXTERNAL_REQUESTOR_TPS65917(REGEN3, 0, 6),
372 EXTERNAL_REQUESTOR_TPS65917(SMPS1, 1, 0),
373 EXTERNAL_REQUESTOR_TPS65917(SMPS2, 1, 1),
374 EXTERNAL_REQUESTOR_TPS65917(SMPS3, 1, 2),
375 EXTERNAL_REQUESTOR_TPS65917(SMPS4, 1, 3),
376 EXTERNAL_REQUESTOR_TPS65917(SMPS5, 1, 4),
be035303 377 EXTERNAL_REQUESTOR_TPS65917(SMPS12, 1, 5),
d6f83370
K		 378 EXTERNAL_REQUESTOR_TPS65917(LDO1, 2, 0),
379 EXTERNAL_REQUESTOR_TPS65917(LDO2, 2, 1),
380 EXTERNAL_REQUESTOR_TPS65917(LDO3, 2, 2),
381 EXTERNAL_REQUESTOR_TPS65917(LDO4, 2, 3),
382 EXTERNAL_REQUESTOR_TPS65917(LDO5, 2, 4),
383};
384
ad542a52 385static const unsigned int palmas_smps_ramp_delay[4] = {0, 10000, 5000, 2500};
28d1e8cd 386
e5ce4208
GG		 387#define SMPS_CTRL_MODE_OFF 0x00
388#define SMPS_CTRL_MODE_ON 0x01
389#define SMPS_CTRL_MODE_ECO 0x02
390#define SMPS_CTRL_MODE_PWM 0x03
391
0f45aa84 392#define PALMAS_SMPS_NUM_VOLTAGES 122
e5ce4208
GG		 393#define PALMAS_SMPS10_NUM_VOLTAGES 2
394#define PALMAS_LDO_NUM_VOLTAGES 50
395
396#define SMPS10_VSEL (1<<3)
397#define SMPS10_BOOST_EN (1<<2)
398#define SMPS10_BYPASS_EN (1<<1)
399#define SMPS10_SWITCH_EN (1<<0)
400
401#define REGULATOR_SLAVE 0
402
403static int palmas_smps_read(struct palmas *palmas, unsigned int reg,
404 unsigned int *dest)
405{
406 unsigned int addr;
407
408 addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg);
409
410 return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest);
411}
412
413static int palmas_smps_write(struct palmas *palmas, unsigned int reg,
414 unsigned int value)
415{
416 unsigned int addr;
417
418 addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg);
419
420 return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value);
421}
422
423static int palmas_ldo_read(struct palmas *palmas, unsigned int reg,
424 unsigned int *dest)
425{
426 unsigned int addr;
427
428 addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg);
429
430 return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest);
431}
432
433static int palmas_ldo_write(struct palmas *palmas, unsigned int reg,
434 unsigned int value)
435{
436 unsigned int addr;
437
438 addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg);
439
440 return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value);
441}
442
e5ce4208
GG		 443static int palmas_set_mode_smps(struct regulator_dev *dev, unsigned int mode)
444{
cf910b6b 445 int id = rdev_get_id(dev);
966e927b 446 int ret;
e5ce4208 447 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
cac9e916 448 struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata;
cf910b6b 449 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
e5ce4208 450 unsigned int reg;
51d3a0c9 451 bool rail_enable = true;
e5ce4208 452
966e927b
KL		 453 ret = palmas_smps_read(pmic->palmas, rinfo->ctrl_addr, &reg);
454 if (ret)
455 return ret;
cac9e916 456
999f0c7c 457 reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
e5ce4208 458
51d3a0c9
LD		 459 if (reg == SMPS_CTRL_MODE_OFF)
460 rail_enable = false;
461
e5ce4208
GG		 462 switch (mode) {
463 case REGULATOR_MODE_NORMAL:
464 reg |= SMPS_CTRL_MODE_ON;
465 break;
466 case REGULATOR_MODE_IDLE:
467 reg |= SMPS_CTRL_MODE_ECO;
468 break;
469 case REGULATOR_MODE_FAST:
470 reg |= SMPS_CTRL_MODE_PWM;
471 break;
472 default:
473 return -EINVAL;
474 }
e5ce4208 475
51d3a0c9
LD		 476 pmic->current_reg_mode[id] = reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
477 if (rail_enable)
cf910b6b 478 palmas_smps_write(pmic->palmas, rinfo->ctrl_addr, reg);
318dbb02
NM		 479
480 /* Switch the enable value to ensure this is used for enable */
481 pmic->desc[id].enable_val = pmic->current_reg_mode[id];
482
e5ce4208
GG		 483 return 0;
484}
485
486static unsigned int palmas_get_mode_smps(struct regulator_dev *dev)
487{
488 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
489 int id = rdev_get_id(dev);
490 unsigned int reg;
491
51d3a0c9 492 reg = pmic->current_reg_mode[id] & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
e5ce4208
GG		 493
494 switch (reg) {
495 case SMPS_CTRL_MODE_ON:
496 return REGULATOR_MODE_NORMAL;
497 case SMPS_CTRL_MODE_ECO:
498 return REGULATOR_MODE_IDLE;
499 case SMPS_CTRL_MODE_PWM:
500 return REGULATOR_MODE_FAST;
501 }
502
503 return 0;
504}
505
28d1e8cd
LD		 506static int palmas_smps_set_ramp_delay(struct regulator_dev *rdev,
507 int ramp_delay)
508{
cf910b6b 509 int id = rdev_get_id(rdev);
28d1e8cd 510 struct palmas_pmic *pmic = rdev_get_drvdata(rdev);
cac9e916 511 struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata;
cf910b6b 512 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
28d1e8cd 513 unsigned int reg = 0;
28d1e8cd
LD		 514 int ret;
515
f22c2bae
AL		 516 /* SMPS3 and SMPS7 do not have tstep_addr setting */
517 switch (id) {
518 case PALMAS_REG_SMPS3:
519 case PALMAS_REG_SMPS7:
520 return 0;
521 }
522
28d1e8cd
LD		 523 if (ramp_delay <= 0)
524 reg = 0;
0ea34b57 525 else if (ramp_delay <= 2500)
28d1e8cd 526 reg = 3;
0ea34b57 527 else if (ramp_delay <= 5000)
28d1e8cd
LD		 528 reg = 2;
529 else
530 reg = 1;
531
cf910b6b 532 ret = palmas_smps_write(pmic->palmas, rinfo->tstep_addr, reg);
28d1e8cd
LD		 533 if (ret < 0) {
534 dev_err(pmic->palmas->dev, "TSTEP write failed: %d\n", ret);
535 return ret;
536 }
537
538 pmic->ramp_delay[id] = palmas_smps_ramp_delay[reg];
539 return ret;
540}
541
0e5a7680 542static const struct regulator_ops palmas_ops_smps = {
dbabd624
K		 543 .is_enabled = regulator_is_enabled_regmap,
544 .enable = regulator_enable_regmap,
545 .disable = regulator_disable_regmap,
e5ce4208
GG		 546 .set_mode = palmas_set_mode_smps,
547 .get_mode = palmas_get_mode_smps,
bdc4baac
AL		 548 .get_voltage_sel = regulator_get_voltage_sel_regmap,
549 .set_voltage_sel = regulator_set_voltage_sel_regmap,
dbabd624
K		 550 .list_voltage = regulator_list_voltage_linear_range,
551 .map_voltage = regulator_map_voltage_linear_range,
552 .set_voltage_time_sel = regulator_set_voltage_time_sel,
28d1e8cd 553 .set_ramp_delay = palmas_smps_set_ramp_delay,
e5ce4208
GG		 554};
555
0e5a7680 556static const struct regulator_ops palmas_ops_ext_control_smps = {
32b6d3f6
LD		 557 .set_mode = palmas_set_mode_smps,
558 .get_mode = palmas_get_mode_smps,
559 .get_voltage_sel = regulator_get_voltage_sel_regmap,
560 .set_voltage_sel = regulator_set_voltage_sel_regmap,
dbabd624
K		 561 .list_voltage = regulator_list_voltage_linear_range,
562 .map_voltage = regulator_map_voltage_linear_range,
563 .set_voltage_time_sel = regulator_set_voltage_time_sel,
32b6d3f6
LD		 564 .set_ramp_delay = palmas_smps_set_ramp_delay,
565};
566
0e5a7680 567static const struct regulator_ops palmas_ops_smps10 = {
e5ce4208
GG		 568 .is_enabled = regulator_is_enabled_regmap,
569 .enable = regulator_enable_regmap,
570 .disable = regulator_disable_regmap,
571 .get_voltage_sel = regulator_get_voltage_sel_regmap,
572 .set_voltage_sel = regulator_set_voltage_sel_regmap,
8029a006
AL		 573 .list_voltage = regulator_list_voltage_linear,
574 .map_voltage = regulator_map_voltage_linear,
77409d9b
KVA		 575 .set_bypass = regulator_set_bypass_regmap,
576 .get_bypass = regulator_get_bypass_regmap,
e5ce4208
GG		 577};
578
0e5a7680 579static const struct regulator_ops tps65917_ops_smps = {
d6f83370
K		 580 .is_enabled = regulator_is_enabled_regmap,
581 .enable = regulator_enable_regmap,
582 .disable = regulator_disable_regmap,
583 .set_mode = palmas_set_mode_smps,
584 .get_mode = palmas_get_mode_smps,
585 .get_voltage_sel = regulator_get_voltage_sel_regmap,
586 .set_voltage_sel = regulator_set_voltage_sel_regmap,
587 .list_voltage = regulator_list_voltage_linear_range,
588 .map_voltage = regulator_map_voltage_linear_range,
589 .set_voltage_time_sel = regulator_set_voltage_time_sel,
590};
591
0e5a7680 592static const struct regulator_ops tps65917_ops_ext_control_smps = {
d6f83370
K		 593 .set_mode = palmas_set_mode_smps,
594 .get_mode = palmas_get_mode_smps,
595 .get_voltage_sel = regulator_get_voltage_sel_regmap,
596 .set_voltage_sel = regulator_set_voltage_sel_regmap,
597 .list_voltage = regulator_list_voltage_linear_range,
598 .map_voltage = regulator_map_voltage_linear_range,
599};
600
e5ce4208
GG		 601static int palmas_is_enabled_ldo(struct regulator_dev *dev)
602{
cf910b6b 603 int id = rdev_get_id(dev);
e5ce4208 604 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
cac9e916 605 struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata;
cf910b6b 606 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
e5ce4208
GG		 607 unsigned int reg;
608
cf910b6b 609 palmas_ldo_read(pmic->palmas, rinfo->ctrl_addr, &reg);
e5ce4208
GG		 610
611 reg &= PALMAS_LDO1_CTRL_STATUS;
612
613 return !!(reg);
614}
615
0e5a7680 616static const struct regulator_ops palmas_ops_ldo = {
e5ce4208
GG		 617 .is_enabled = palmas_is_enabled_ldo,
618 .enable = regulator_enable_regmap,
619 .disable = regulator_disable_regmap,
4a247a96
AL		 620 .get_voltage_sel = regulator_get_voltage_sel_regmap,
621 .set_voltage_sel = regulator_set_voltage_sel_regmap,
9119ff6a
AL		 622 .list_voltage = regulator_list_voltage_linear,
623 .map_voltage = regulator_map_voltage_linear,
e5ce4208
GG		 624};
625
0e5a7680 626static const struct regulator_ops palmas_ops_ldo9 = {
b554e145
K		 627 .is_enabled = palmas_is_enabled_ldo,
628 .enable = regulator_enable_regmap,
629 .disable = regulator_disable_regmap,
630 .get_voltage_sel = regulator_get_voltage_sel_regmap,
631 .set_voltage_sel = regulator_set_voltage_sel_regmap,
632 .list_voltage = regulator_list_voltage_linear,
633 .map_voltage = regulator_map_voltage_linear,
634 .set_bypass = regulator_set_bypass_regmap,
635 .get_bypass = regulator_get_bypass_regmap,
636};
637
0e5a7680 638static const struct regulator_ops palmas_ops_ext_control_ldo = {
32b6d3f6
LD		 639 .get_voltage_sel = regulator_get_voltage_sel_regmap,
640 .set_voltage_sel = regulator_set_voltage_sel_regmap,
641 .list_voltage = regulator_list_voltage_linear,
642 .map_voltage = regulator_map_voltage_linear,
643};
644
0e5a7680 645static const struct regulator_ops palmas_ops_extreg = {
aa07f027
LD		 646 .is_enabled = regulator_is_enabled_regmap,
647 .enable = regulator_enable_regmap,
648 .disable = regulator_disable_regmap,
649};
650
0e5a7680 651static const struct regulator_ops palmas_ops_ext_control_extreg = {
32b6d3f6
LD		 652};
653
0e5a7680 654static const struct regulator_ops tps65917_ops_ldo = {
d6f83370
K		 655 .is_enabled = palmas_is_enabled_ldo,
656 .enable = regulator_enable_regmap,
657 .disable = regulator_disable_regmap,
658 .get_voltage_sel = regulator_get_voltage_sel_regmap,
659 .set_voltage_sel = regulator_set_voltage_sel_regmap,
660 .list_voltage = regulator_list_voltage_linear,
661 .map_voltage = regulator_map_voltage_linear,
662 .set_voltage_time_sel = regulator_set_voltage_time_sel,
663};
664
0e5a7680 665static const struct regulator_ops tps65917_ops_ldo_1_2 = {
b554e145
K		 666 .is_enabled = palmas_is_enabled_ldo,
667 .enable = regulator_enable_regmap,
668 .disable = regulator_disable_regmap,
669 .get_voltage_sel = regulator_get_voltage_sel_regmap,
670 .set_voltage_sel = regulator_set_voltage_sel_regmap,
671 .list_voltage = regulator_list_voltage_linear,
672 .map_voltage = regulator_map_voltage_linear,
673 .set_voltage_time_sel = regulator_set_voltage_time_sel,
674 .set_bypass = regulator_set_bypass_regmap,
675 .get_bypass = regulator_get_bypass_regmap,
676};
677
32b6d3f6
LD		 678static int palmas_regulator_config_external(struct palmas *palmas, int id,
679 struct palmas_reg_init *reg_init)
680{
cf910b6b
NM		 681 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
682 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
32b6d3f6
LD		 683 int ret;
684
cf910b6b
NM		 685 ret = palmas_ext_control_req_config(palmas, rinfo->sleep_id,
686 reg_init->roof_floor, true);
32b6d3f6
LD		 687 if (ret < 0)
688 dev_err(palmas->dev,
689 "Ext control config for regulator %d failed %d\n",
690 id, ret);
691 return ret;
692}
693
e5ce4208
GG		 694/*
695 * setup the hardware based sleep configuration of the SMPS/LDO regulators
696 * from the platform data. This is different to the software based control
697 * supported by the regulator framework as it is controlled by toggling
698 * pins on the PMIC such as PREQ, SYSEN, ...
699 */
700static int palmas_smps_init(struct palmas *palmas, int id,
701 struct palmas_reg_init *reg_init)
702{
703 unsigned int reg;
e5ce4208 704 int ret;
cac9e916 705 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
cf910b6b
NM		 706 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
707 unsigned int addr = rinfo->ctrl_addr;
e5ce4208
GG		 708
709 ret = palmas_smps_read(palmas, addr, &reg);
710 if (ret)
711 return ret;
712
fedd89b1 713 switch (id) {
77409d9b
KVA		 714 case PALMAS_REG_SMPS10_OUT1:
715 case PALMAS_REG_SMPS10_OUT2:
30590d04
LD		 716 reg &= ~PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK;
717 if (reg_init->mode_sleep)
fedd89b1
AL		 718 reg |= reg_init->mode_sleep <<
719 PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT;
fedd89b1
AL		 720 break;
721 default:
e5ce4208
GG		 722 if (reg_init->warm_reset)
723 reg |= PALMAS_SMPS12_CTRL_WR_S;
30590d04
LD		 724 else
725 reg &= ~PALMAS_SMPS12_CTRL_WR_S;
e5ce4208
GG		 726
727 if (reg_init->roof_floor)
728 reg |= PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN;
30590d04
LD		 729 else
730 reg &= ~PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN;
e5ce4208 731
30590d04
LD		 732 reg &= ~PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK;
733 if (reg_init->mode_sleep)
e5ce4208
GG		 734 reg |= reg_init->mode_sleep <<
735 PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT;
e5ce4208 736 }
fedd89b1 737
e5ce4208
GG		 738 ret = palmas_smps_write(palmas, addr, reg);
739 if (ret)
740 return ret;
741
cf910b6b 742 if (rinfo->vsel_addr && reg_init->vsel) {
e5ce4208
GG		 743
744 reg = reg_init->vsel;
745
cf910b6b 746 ret = palmas_smps_write(palmas, rinfo->vsel_addr, reg);
e5ce4208
GG		 747 if (ret)
748 return ret;
749 }
750
32b6d3f6
LD		 751 if (reg_init->roof_floor && (id != PALMAS_REG_SMPS10_OUT1) &&
752 (id != PALMAS_REG_SMPS10_OUT2)) {
753 /* Enable externally controlled regulator */
32b6d3f6
LD		 754 ret = palmas_smps_read(palmas, addr, &reg);
755 if (ret < 0)
756 return ret;
e5ce4208 757
32b6d3f6
LD		 758 if (!(reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK)) {
759 reg |= SMPS_CTRL_MODE_ON;
760 ret = palmas_smps_write(palmas, addr, reg);
761 if (ret < 0)
762 return ret;
763 }
764 return palmas_regulator_config_external(palmas, id, reg_init);
765 }
e5ce4208
GG		 766 return 0;
767}
768
769static int palmas_ldo_init(struct palmas *palmas, int id,
770 struct palmas_reg_init *reg_init)
771{
772 unsigned int reg;
773 unsigned int addr;
774 int ret;
cac9e916 775 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
cf910b6b 776 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
cac9e916 777
cf910b6b 778 addr = rinfo->ctrl_addr;
e5ce4208 779
2735daeb 780 ret = palmas_ldo_read(palmas, addr, &reg);
e5ce4208
GG		 781 if (ret)
782 return ret;
783
784 if (reg_init->warm_reset)
785 reg |= PALMAS_LDO1_CTRL_WR_S;
30590d04
LD		 786 else
787 reg &= ~PALMAS_LDO1_CTRL_WR_S;
e5ce4208
GG		 788
789 if (reg_init->mode_sleep)
790 reg |= PALMAS_LDO1_CTRL_MODE_SLEEP;
30590d04
LD		 791 else
792 reg &= ~PALMAS_LDO1_CTRL_MODE_SLEEP;
e5ce4208 793
2735daeb 794 ret = palmas_ldo_write(palmas, addr, reg);
e5ce4208
GG		 795 if (ret)
796 return ret;
797
32b6d3f6
LD		 798 if (reg_init->roof_floor) {
799 /* Enable externally controlled regulator */
32b6d3f6
LD		 800 ret = palmas_update_bits(palmas, PALMAS_LDO_BASE,
801 addr, PALMAS_LDO1_CTRL_MODE_ACTIVE,
802 PALMAS_LDO1_CTRL_MODE_ACTIVE);
803 if (ret < 0) {
804 dev_err(palmas->dev,
805 "LDO Register 0x%02x update failed %d\n",
806 addr, ret);
807 return ret;
808 }
809 return palmas_regulator_config_external(palmas, id, reg_init);
810 }
e5ce4208
GG		 811 return 0;
812}
813
aa07f027
LD		 814static int palmas_extreg_init(struct palmas *palmas, int id,
815 struct palmas_reg_init *reg_init)
816{
817 unsigned int addr;
818 int ret;
819 unsigned int val = 0;
cac9e916 820 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
cf910b6b 821 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
cac9e916 822
cf910b6b 823 addr = rinfo->ctrl_addr;
aa07f027
LD		 824
825 if (reg_init->mode_sleep)
826 val = PALMAS_REGEN1_CTRL_MODE_SLEEP;
827
828 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
829 addr, PALMAS_REGEN1_CTRL_MODE_SLEEP, val);
830 if (ret < 0) {
831 dev_err(palmas->dev, "Resource reg 0x%02x update failed %d\n",
832 addr, ret);
833 return ret;
834 }
32b6d3f6
LD		 835
836 if (reg_init->roof_floor) {
837 /* Enable externally controlled regulator */
32b6d3f6
LD		 838 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
839 addr, PALMAS_REGEN1_CTRL_MODE_ACTIVE,
840 PALMAS_REGEN1_CTRL_MODE_ACTIVE);
841 if (ret < 0) {
842 dev_err(palmas->dev,
843 "Resource Register 0x%02x update failed %d\n",
844 addr, ret);
845 return ret;
846 }
847 return palmas_regulator_config_external(palmas, id, reg_init);
848 }
aa07f027
LD		 849 return 0;
850}
851
17c11a76
LD		 852static void palmas_enable_ldo8_track(struct palmas *palmas)
853{
854 unsigned int reg;
855 unsigned int addr;
856 int ret;
cac9e916 857 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
cf910b6b 858 struct palmas_regs_info *rinfo;
cac9e916 859
cf910b6b
NM		 860 rinfo = &ddata->palmas_regs_info[PALMAS_REG_LDO8];
861 addr = rinfo->ctrl_addr;
17c11a76
LD		 862
863 ret = palmas_ldo_read(palmas, addr, &reg);
864 if (ret) {
865 dev_err(palmas->dev, "Error in reading ldo8 control reg\n");
866 return;
867 }
868
869 reg |= PALMAS_LDO8_CTRL_LDO_TRACKING_EN;
870 ret = palmas_ldo_write(palmas, addr, reg);
871 if (ret < 0) {
872 dev_err(palmas->dev, "Error in enabling tracking mode\n");
873 return;
874 }
875 /*
876 * When SMPS45 is set to off and LDO8 tracking is enabled, the LDO8
877 * output is defined by the LDO8_VOLTAGE.VSEL register divided by two,
878 * and can be set from 0.45 to 1.65 V.
879 */
cf910b6b 880 addr = rinfo->vsel_addr;
17c11a76
LD		 881 ret = palmas_ldo_read(palmas, addr, &reg);
882 if (ret) {
883 dev_err(palmas->dev, "Error in reading ldo8 voltage reg\n");
884 return;
885 }
886
887 reg = (reg << 1) & PALMAS_LDO8_VOLTAGE_VSEL_MASK;
888 ret = palmas_ldo_write(palmas, addr, reg);
889 if (ret < 0)
890 dev_err(palmas->dev, "Error in setting ldo8 voltage reg\n");
891
892 return;
893}
894
cac9e916
K		 895static int palmas_ldo_registration(struct palmas_pmic *pmic,
896 struct palmas_pmic_driver_data *ddata,
897 struct palmas_pmic_platform_data *pdata,
898 const char *pdev_name,
899 struct regulator_config config)
a361cd9f 900{
cac9e916
K		 901 int id, ret;
902 struct regulator_dev *rdev;
903 struct palmas_reg_init *reg_init;
cf910b6b 904 struct palmas_regs_info *rinfo;
429222d0 905 struct regulator_desc *desc;
a361cd9f 906
cac9e916
K		 907 for (id = ddata->ldo_begin; id < ddata->max_reg; id++) {
908 if (pdata && pdata->reg_init[id])
909 reg_init = pdata->reg_init[id];
910 else
911 reg_init = NULL;
a361cd9f 912
cf910b6b 913 rinfo = &ddata->palmas_regs_info[id];
cac9e916
K		 914 /* Miss out regulators which are not available due
915 * to alternate functions.
916 */
a361cd9f 917
cac9e916 918 /* Register the regulators */
429222d0
NM		 919 desc = &pmic->desc[id];
920 desc->name = rinfo->name;
921 desc->id = id;
922 desc->type = REGULATOR_VOLTAGE;
923 desc->owner = THIS_MODULE;
a361cd9f 924
cac9e916 925 if (id < PALMAS_REG_REGEN1) {
429222d0 926 desc->n_voltages = PALMAS_LDO_NUM_VOLTAGES;
cac9e916 927 if (reg_init && reg_init->roof_floor)
429222d0 928 desc->ops = &palmas_ops_ext_control_ldo;
cac9e916 929 else
429222d0
NM		 930 desc->ops = &palmas_ops_ldo;
931 desc->min_uV = 900000;
932 desc->uV_step = 50000;
933 desc->linear_min_sel = 1;
934 desc->enable_time = 500;
935 desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
936 rinfo->vsel_addr);
937 desc->vsel_mask = PALMAS_LDO1_VOLTAGE_VSEL_MASK;
938 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
939 rinfo->ctrl_addr);
940 desc->enable_mask = PALMAS_LDO1_CTRL_MODE_ACTIVE;
a361cd9f 941
cac9e916
K		 942 /* Check if LDO8 is in tracking mode or not */
943 if (pdata && (id == PALMAS_REG_LDO8) &&
944 pdata->enable_ldo8_tracking) {
945 palmas_enable_ldo8_track(pmic->palmas);
429222d0
NM		 946 desc->min_uV = 450000;
947 desc->uV_step = 25000;
cac9e916 948 }
a361cd9f 949
cac9e916
K		 950 /* LOD6 in vibrator mode will have enable time 2000us */
951 if (pdata && pdata->ldo6_vibrator &&
952 (id == PALMAS_REG_LDO6))
429222d0 953 desc->enable_time = 2000;
b554e145
K		 954
955 if (id == PALMAS_REG_LDO9) {
956 desc->ops = &palmas_ops_ldo9;
957 desc->bypass_reg = desc->enable_reg;
e0341f17
NM		 958 desc->bypass_val_on =
959 PALMAS_LDO9_CTRL_LDO_BYPASS_EN;
b554e145
K		 960 desc->bypass_mask =
961 PALMAS_LDO9_CTRL_LDO_BYPASS_EN;
962 }
cac9e916 963 } else {
e999c728
K		 964 if (!ddata->has_regen3 && id == PALMAS_REG_REGEN3)
965 continue;
966
429222d0 967 desc->n_voltages = 1;
cac9e916 968 if (reg_init && reg_init->roof_floor)
429222d0 969 desc->ops = &palmas_ops_ext_control_extreg;
cac9e916 970 else
429222d0
NM		 971 desc->ops = &palmas_ops_extreg;
972 desc->enable_reg =
cac9e916 973 PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE,
cf910b6b 974 rinfo->ctrl_addr);
429222d0 975 desc->enable_mask = PALMAS_REGEN1_CTRL_MODE_ACTIVE;
cac9e916 976 }
a361cd9f 977
cac9e916
K		 978 if (pdata)
979 config.init_data = pdata->reg_data[id];
980 else
981 config.init_data = NULL;
32b6d3f6 982
429222d0 983 desc->supply_name = rinfo->sname;
cac9e916 984 config.of_node = ddata->palmas_matches[id].of_node;
a361cd9f 985
429222d0 986 rdev = devm_regulator_register(pmic->dev, desc, &config);
cac9e916
K		 987 if (IS_ERR(rdev)) {
988 dev_err(pmic->dev,
989 "failed to register %s regulator\n",
990 pdev_name);
991 return PTR_ERR(rdev);
992 }
a361cd9f 993
cac9e916
K		 994 /* Initialise sleep/init values from platform data */
995 if (pdata) {
996 reg_init = pdata->reg_init[id];
997 if (reg_init) {
998 if (id <= ddata->ldo_end)
999 ret = palmas_ldo_init(pmic->palmas, id,
1000 reg_init);
1001 else
1002 ret = palmas_extreg_init(pmic->palmas,
1003 id, reg_init);
1004 if (ret)
1005 return ret;
1006 }
1007 }
a361cd9f
GG		 1008 }
1009
cac9e916 1010 return 0;
a361cd9f
GG		 1011}
1012
d6f83370
K		 1013static int tps65917_ldo_registration(struct palmas_pmic *pmic,
1014 struct palmas_pmic_driver_data *ddata,
1015 struct palmas_pmic_platform_data *pdata,
1016 const char *pdev_name,
1017 struct regulator_config config)
1018{
1019 int id, ret;
1020 struct regulator_dev *rdev;
1021 struct palmas_reg_init *reg_init;
cf910b6b 1022 struct palmas_regs_info *rinfo;
429222d0 1023 struct regulator_desc *desc;
d6f83370
K		 1024
1025 for (id = ddata->ldo_begin; id < ddata->max_reg; id++) {
1026 if (pdata && pdata->reg_init[id])
1027 reg_init = pdata->reg_init[id];
1028 else
1029 reg_init = NULL;
1030
1031 /* Miss out regulators which are not available due
1032 * to alternate functions.
1033 */
cf910b6b 1034 rinfo = &ddata->palmas_regs_info[id];
d6f83370
K		 1035
1036 /* Register the regulators */
429222d0
NM		 1037 desc = &pmic->desc[id];
1038 desc->name = rinfo->name;
1039 desc->id = id;
1040 desc->type = REGULATOR_VOLTAGE;
1041 desc->owner = THIS_MODULE;
d6f83370
K		 1042
1043 if (id < TPS65917_REG_REGEN1) {
429222d0 1044 desc->n_voltages = PALMAS_LDO_NUM_VOLTAGES;
d6f83370 1045 if (reg_init && reg_init->roof_floor)
429222d0 1046 desc->ops = &palmas_ops_ext_control_ldo;
d6f83370 1047 else
429222d0
NM		 1048 desc->ops = &tps65917_ops_ldo;
1049 desc->min_uV = 900000;
1050 desc->uV_step = 50000;
1051 desc->linear_min_sel = 1;
1052 desc->enable_time = 500;
1053 desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
1054 rinfo->vsel_addr);
1055 desc->vsel_mask = PALMAS_LDO1_VOLTAGE_VSEL_MASK;
1056 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
1057 rinfo->ctrl_addr);
1058 desc->enable_mask = PALMAS_LDO1_CTRL_MODE_ACTIVE;
d6f83370
K		 1059 /*
1060 * To be confirmed. Discussion on going with PMIC Team.
1061 * It is of the order of ~60mV/uS.
1062 */
429222d0 1063 desc->ramp_delay = 2500;
b554e145
K		 1064 if (id == TPS65917_REG_LDO1 ||
1065 id == TPS65917_REG_LDO2) {
1066 desc->ops = &tps65917_ops_ldo_1_2;
1067 desc->bypass_reg = desc->enable_reg;
e0341f17
NM		 1068 desc->bypass_val_on =
1069 TPS65917_LDO1_CTRL_BYPASS_EN;
b554e145
K		 1070 desc->bypass_mask =
1071 TPS65917_LDO1_CTRL_BYPASS_EN;
1072 }
d6f83370 1073 } else {
429222d0 1074 desc->n_voltages = 1;
d6f83370 1075 if (reg_init && reg_init->roof_floor)
429222d0 1076 desc->ops = &palmas_ops_ext_control_extreg;
d6f83370 1077 else
429222d0
NM		 1078 desc->ops = &palmas_ops_extreg;
1079 desc->enable_reg =
d6f83370 1080 PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE,
cf910b6b 1081 rinfo->ctrl_addr);
429222d0 1082 desc->enable_mask = PALMAS_REGEN1_CTRL_MODE_ACTIVE;
d6f83370
K		 1083 }
1084
1085 if (pdata)
1086 config.init_data = pdata->reg_data[id];
1087 else
1088 config.init_data = NULL;
1089
429222d0 1090 desc->supply_name = rinfo->sname;
d6f83370
K		 1091 config.of_node = ddata->palmas_matches[id].of_node;
1092
429222d0 1093 rdev = devm_regulator_register(pmic->dev, desc, &config);
d6f83370
K		 1094 if (IS_ERR(rdev)) {
1095 dev_err(pmic->dev,
1096 "failed to register %s regulator\n",
1097 pdev_name);
1098 return PTR_ERR(rdev);
1099 }
1100
d6f83370
K		 1101 /* Initialise sleep/init values from platform data */
1102 if (pdata) {
1103 reg_init = pdata->reg_init[id];
1104 if (reg_init) {
1105 if (id < TPS65917_REG_REGEN1)
1106 ret = palmas_ldo_init(pmic->palmas,
1107 id, reg_init);
1108 else
1109 ret = palmas_extreg_init(pmic->palmas,
1110 id, reg_init);
1111 if (ret)
1112 return ret;
1113 }
1114 }
1115 }
1116
1117 return 0;
1118}
1119
cac9e916
K		 1120static int palmas_smps_registration(struct palmas_pmic *pmic,
1121 struct palmas_pmic_driver_data *ddata,
1122 struct palmas_pmic_platform_data *pdata,
1123 const char *pdev_name,
1124 struct regulator_config config)
e5ce4208 1125{
cac9e916
K		 1126 int id, ret;
1127 unsigned int addr, reg;
e5ce4208 1128 struct regulator_dev *rdev;
e5ce4208 1129 struct palmas_reg_init *reg_init;
cf910b6b 1130 struct palmas_regs_info *rinfo;
429222d0 1131 struct regulator_desc *desc;
e5ce4208 1132
cac9e916 1133 for (id = ddata->smps_start; id <= ddata->smps_end; id++) {
28d1e8cd 1134 bool ramp_delay_support = false;
e5ce4208
GG		 1135
1136 /*
1137 * Miss out regulators which are not available due
1138 * to slaving configurations.
1139 */
1140 switch (id) {
1141 case PALMAS_REG_SMPS12:
1142 case PALMAS_REG_SMPS3:
1143 if (pmic->smps123)
1144 continue;
28d1e8cd
LD		 1145 if (id == PALMAS_REG_SMPS12)
1146 ramp_delay_support = true;
e5ce4208
GG		 1147 break;
1148 case PALMAS_REG_SMPS123:
1149 if (!pmic->smps123)
1150 continue;
28d1e8cd 1151 ramp_delay_support = true;
e5ce4208
GG		 1152 break;
1153 case PALMAS_REG_SMPS45:
1154 case PALMAS_REG_SMPS7:
1155 if (pmic->smps457)
1156 continue;
28d1e8cd
LD		 1157 if (id == PALMAS_REG_SMPS45)
1158 ramp_delay_support = true;
e5ce4208
GG		 1159 break;
1160 case PALMAS_REG_SMPS457:
1161 if (!pmic->smps457)
1162 continue;
28d1e8cd
LD		 1163 ramp_delay_support = true;
1164 break;
77409d9b
KVA		 1165 case PALMAS_REG_SMPS10_OUT1:
1166 case PALMAS_REG_SMPS10_OUT2:
cac9e916 1167 if (!PALMAS_PMIC_HAS(pmic->palmas, SMPS10_BOOST))
1ffb0be3 1168 continue;
28d1e8cd 1169 }
cf910b6b 1170 rinfo = &ddata->palmas_regs_info[id];
429222d0 1171 desc = &pmic->desc[id];
28d1e8cd 1172
3f4d6364 1173 if ((id == PALMAS_REG_SMPS6) || (id == PALMAS_REG_SMPS8))
28d1e8cd
LD		 1174 ramp_delay_support = true;
1175
1176 if (ramp_delay_support) {
cf910b6b 1177 addr = rinfo->tstep_addr;
28d1e8cd
LD		 1178 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1179 if (ret < 0) {
cac9e916 1180 dev_err(pmic->dev,
28d1e8cd 1181 "reading TSTEP reg failed: %d\n", ret);
51c86b3e 1182 return ret;
28d1e8cd 1183 }
429222d0
NM		 1184 desc->ramp_delay = palmas_smps_ramp_delay[reg & 0x3];
1185 pmic->ramp_delay[id] = desc->ramp_delay;
e5ce4208
GG		 1186 }
1187
bdc4baac
AL		 1188 /* Initialise sleep/init values from platform data */
1189 if (pdata && pdata->reg_init[id]) {
1190 reg_init = pdata->reg_init[id];
cac9e916 1191 ret = palmas_smps_init(pmic->palmas, id, reg_init);
bdc4baac 1192 if (ret)
51c86b3e 1193 return ret;
32b6d3f6
LD		 1194 } else {
1195 reg_init = NULL;
bdc4baac
AL		 1196 }
1197
e5ce4208 1198 /* Register the regulators */
429222d0
NM		 1199 desc->name = rinfo->name;
1200 desc->id = id;
e5ce4208 1201
fedd89b1 1202 switch (id) {
77409d9b
KVA		 1203 case PALMAS_REG_SMPS10_OUT1:
1204 case PALMAS_REG_SMPS10_OUT2:
429222d0
NM		 1205 desc->n_voltages = PALMAS_SMPS10_NUM_VOLTAGES;
1206 desc->ops = &palmas_ops_smps10;
1207 desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1208 PALMAS_SMPS10_CTRL);
1209 desc->vsel_mask = SMPS10_VSEL;
1210 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1211 PALMAS_SMPS10_CTRL);
77409d9b 1212 if (id == PALMAS_REG_SMPS10_OUT1)
429222d0 1213 desc->enable_mask = SMPS10_SWITCH_EN;
77409d9b 1214 else
429222d0
NM		 1215 desc->enable_mask = SMPS10_BOOST_EN;
1216 desc->bypass_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1217 PALMAS_SMPS10_CTRL);
e0341f17 1218 desc->bypass_val_on = SMPS10_BYPASS_EN;
429222d0
NM		 1219 desc->bypass_mask = SMPS10_BYPASS_EN;
1220 desc->min_uV = 3750000;
1221 desc->uV_step = 1250000;
fedd89b1
AL		 1222 break;
1223 default:
bdc4baac
AL		 1224 /*
1225 * Read and store the RANGE bit for later use
1226 * This must be done before regulator is probed,
51d3a0c9
LD		 1227 * otherwise we error in probe with unsupportable
1228 * ranges. Read the current smps mode for later use.
bdc4baac 1229 */
cf910b6b 1230 addr = rinfo->vsel_addr;
429222d0 1231 desc->n_linear_ranges = 3;
e5ce4208
GG		 1232
1233 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1234 if (ret)
51c86b3e 1235 return ret;
e5ce4208
GG		 1236 if (reg & PALMAS_SMPS12_VOLTAGE_RANGE)
1237 pmic->range[id] = 1;
dbabd624 1238 if (pmic->range[id])
429222d0 1239 desc->linear_ranges = smps_high_ranges;
dbabd624 1240 else
429222d0 1241 desc->linear_ranges = smps_low_ranges;
bdc4baac 1242
32b6d3f6 1243 if (reg_init && reg_init->roof_floor)
429222d0 1244 desc->ops = &palmas_ops_ext_control_smps;
32b6d3f6 1245 else
429222d0
NM		 1246 desc->ops = &palmas_ops_smps;
1247 desc->n_voltages = PALMAS_SMPS_NUM_VOLTAGES;
1248 desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1249 rinfo->vsel_addr);
1250 desc->vsel_mask = PALMAS_SMPS12_VOLTAGE_VSEL_MASK;
51d3a0c9
LD		 1251
1252 /* Read the smps mode for later use. */
cf910b6b 1253 addr = rinfo->ctrl_addr;
51d3a0c9
LD		 1254 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1255 if (ret)
51c86b3e 1256 return ret;
51d3a0c9
LD		 1257 pmic->current_reg_mode[id] = reg &
1258 PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
318dbb02 1259
429222d0
NM		 1260 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1261 rinfo->ctrl_addr);
1262 desc->enable_mask = PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
318dbb02 1263 /* set_mode overrides this value */
429222d0 1264 desc->enable_val = SMPS_CTRL_MODE_ON;
e5ce4208
GG		 1265 }
1266
429222d0
NM		 1267 desc->type = REGULATOR_VOLTAGE;
1268 desc->owner = THIS_MODULE;
bdc4baac 1269
a361cd9f 1270 if (pdata)
e5ce4208
GG		 1271 config.init_data = pdata->reg_data[id];
1272 else
1273 config.init_data = NULL;
1274
429222d0 1275 desc->supply_name = rinfo->sname;
cac9e916 1276 config.of_node = ddata->palmas_matches[id].of_node;
a361cd9f 1277
429222d0 1278 rdev = devm_regulator_register(pmic->dev, desc, &config);
e5ce4208 1279 if (IS_ERR(rdev)) {
cac9e916 1280 dev_err(pmic->dev,
e5ce4208 1281 "failed to register %s regulator\n",
cac9e916 1282 pdev_name);
51c86b3e 1283 return PTR_ERR(rdev);
e5ce4208 1284 }
e5ce4208
GG		 1285 }
1286
cac9e916
K		 1287 return 0;
1288}
e5ce4208 1289
d6f83370
K		 1290static int tps65917_smps_registration(struct palmas_pmic *pmic,
1291 struct palmas_pmic_driver_data *ddata,
1292 struct palmas_pmic_platform_data *pdata,
1293 const char *pdev_name,
1294 struct regulator_config config)
1295{
1296 int id, ret;
1297 unsigned int addr, reg;
1298 struct regulator_dev *rdev;
1299 struct palmas_reg_init *reg_init;
cf910b6b 1300 struct palmas_regs_info *rinfo;
429222d0 1301 struct regulator_desc *desc;
d6f83370
K		 1302
1303 for (id = ddata->smps_start; id <= ddata->smps_end; id++) {
1304 /*
1305 * Miss out regulators which are not available due
1306 * to slaving configurations.
1307 */
429222d0
NM		 1308 desc = &pmic->desc[id];
1309 desc->n_linear_ranges = 3;
be035303
K		 1310 if ((id == TPS65917_REG_SMPS2 || id == TPS65917_REG_SMPS1) &&
1311 pmic->smps12)
d6f83370
K		 1312 continue;
1313
1314 /* Initialise sleep/init values from platform data */
1315 if (pdata && pdata->reg_init[id]) {
1316 reg_init = pdata->reg_init[id];
1317 ret = palmas_smps_init(pmic->palmas, id, reg_init);
1318 if (ret)
1319 return ret;
1320 } else {
1321 reg_init = NULL;
1322 }
cf910b6b 1323 rinfo = &ddata->palmas_regs_info[id];
d6f83370
K		 1324
1325 /* Register the regulators */
429222d0
NM		 1326 desc->name = rinfo->name;
1327 desc->id = id;
d6f83370
K		 1328
1329 /*
1330 * Read and store the RANGE bit for later use
1331 * This must be done before regulator is probed,
1332 * otherwise we error in probe with unsupportable
1333 * ranges. Read the current smps mode for later use.
1334 */
cf910b6b 1335 addr = rinfo->vsel_addr;
d6f83370
K		 1336
1337 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1338 if (ret)
1339 return ret;
1340 if (reg & TPS65917_SMPS1_VOLTAGE_RANGE)
1341 pmic->range[id] = 1;
1342
1343 if (pmic->range[id])
429222d0
NM		 1344 desc->linear_ranges = smps_high_ranges;
1345 else
1346 desc->linear_ranges = smps_low_ranges;
d6f83370
K		 1347
1348 if (reg_init && reg_init->roof_floor)
429222d0 1349 desc->ops = &tps65917_ops_ext_control_smps;
d6f83370 1350 else
429222d0
NM		 1351 desc->ops = &tps65917_ops_smps;
1352 desc->n_voltages = PALMAS_SMPS_NUM_VOLTAGES;
1353 desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1354 rinfo->vsel_addr);
1355 desc->vsel_mask = PALMAS_SMPS12_VOLTAGE_VSEL_MASK;
1356 desc->ramp_delay = 2500;
d6f83370
K		 1357
1358 /* Read the smps mode for later use. */
cf910b6b 1359 addr = rinfo->ctrl_addr;
d6f83370
K		 1360 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1361 if (ret)
1362 return ret;
1363 pmic->current_reg_mode[id] = reg &
1364 PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
b632815e
NM		 1365 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1366 rinfo->ctrl_addr);
1367 desc->enable_mask = PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
1368 /* set_mode overrides this value */
1369 desc->enable_val = SMPS_CTRL_MODE_ON;
d6f83370 1370
429222d0
NM		 1371 desc->type = REGULATOR_VOLTAGE;
1372 desc->owner = THIS_MODULE;
d6f83370
K		 1373
1374 if (pdata)
1375 config.init_data = pdata->reg_data[id];
1376 else
1377 config.init_data = NULL;
1378
429222d0 1379 desc->supply_name = rinfo->sname;
d6f83370
K		 1380 config.of_node = ddata->palmas_matches[id].of_node;
1381
429222d0 1382 rdev = devm_regulator_register(pmic->dev, desc, &config);
d6f83370
K		 1383 if (IS_ERR(rdev)) {
1384 dev_err(pmic->dev,
1385 "failed to register %s regulator\n",
1386 pdev_name);
1387 return PTR_ERR(rdev);
1388 }
d6f83370
K		 1389 }
1390
1391 return 0;
1392}
1393
cac9e916
K		 1394static struct of_regulator_match palmas_matches[] = {
1395 { .name = "smps12", },
1396 { .name = "smps123", },
1397 { .name = "smps3", },
1398 { .name = "smps45", },
1399 { .name = "smps457", },
1400 { .name = "smps6", },
1401 { .name = "smps7", },
1402 { .name = "smps8", },
1403 { .name = "smps9", },
1404 { .name = "smps10_out2", },
1405 { .name = "smps10_out1", },
1406 { .name = "ldo1", },
1407 { .name = "ldo2", },
1408 { .name = "ldo3", },
1409 { .name = "ldo4", },
1410 { .name = "ldo5", },
1411 { .name = "ldo6", },
1412 { .name = "ldo7", },
1413 { .name = "ldo8", },
1414 { .name = "ldo9", },
1415 { .name = "ldoln", },
1416 { .name = "ldousb", },
1417 { .name = "regen1", },
1418 { .name = "regen2", },
1419 { .name = "regen3", },
1420 { .name = "sysen1", },
1421 { .name = "sysen2", },
1422};
e5ce4208 1423
d6f83370
K		 1424static struct of_regulator_match tps65917_matches[] = {
1425 { .name = "smps1", },
1426 { .name = "smps2", },
1427 { .name = "smps3", },
1428 { .name = "smps4", },
1429 { .name = "smps5", },
be035303 1430 { .name = "smps12",},
d6f83370
K		 1431 { .name = "ldo1", },
1432 { .name = "ldo2", },
1433 { .name = "ldo3", },
1434 { .name = "ldo4", },
1435 { .name = "ldo5", },
1436 { .name = "regen1", },
1437 { .name = "regen2", },
1438 { .name = "regen3", },
1439 { .name = "sysen1", },
1440 { .name = "sysen2", },
1441};
1442
4b09e17b 1443static struct palmas_pmic_driver_data palmas_ddata = {
cac9e916
K		 1444 .smps_start = PALMAS_REG_SMPS12,
1445 .smps_end = PALMAS_REG_SMPS10_OUT1,
1446 .ldo_begin = PALMAS_REG_LDO1,
1447 .ldo_end = PALMAS_REG_LDOUSB,
1448 .max_reg = PALMAS_NUM_REGS,
e999c728 1449 .has_regen3 = true,
6839cd6f 1450 .palmas_regs_info = palmas_generic_regs_info,
cac9e916
K		 1451 .palmas_matches = palmas_matches,
1452 .sleep_req_info = palma_sleep_req_info,
1453 .smps_register = palmas_smps_registration,
1454 .ldo_register = palmas_ldo_registration,
1455};
aa07f027 1456
4b09e17b 1457static struct palmas_pmic_driver_data tps65917_ddata = {
d6f83370 1458 .smps_start = TPS65917_REG_SMPS1,
be035303 1459 .smps_end = TPS65917_REG_SMPS12,
d6f83370
K		 1460 .ldo_begin = TPS65917_REG_LDO1,
1461 .ldo_end = TPS65917_REG_LDO5,
1462 .max_reg = TPS65917_NUM_REGS,
e999c728 1463 .has_regen3 = true,
d6f83370
K		 1464 .palmas_regs_info = tps65917_regs_info,
1465 .palmas_matches = tps65917_matches,
1466 .sleep_req_info = tps65917_sleep_req_info,
1467 .smps_register = tps65917_smps_registration,
1468 .ldo_register = tps65917_ldo_registration,
1469};
1470
7f091e53
NM		 1471static int palmas_dt_to_pdata(struct device *dev,
1472 struct device_node *node,
1473 struct palmas_pmic_platform_data *pdata,
1474 struct palmas_pmic_driver_data *ddata)
cac9e916
K		 1475{
1476 struct device_node *regulators;
1477 u32 prop;
1478 int idx, ret;
17c11a76 1479
cac9e916
K		 1480 regulators = of_get_child_by_name(node, "regulators");
1481 if (!regulators) {
1482 dev_info(dev, "regulator node not found\n");
7f091e53 1483 return 0;
cac9e916 1484 }
087d30e3 1485
cac9e916
K		 1486 ret = of_regulator_match(dev, regulators, ddata->palmas_matches,
1487 ddata->max_reg);
1488 of_node_put(regulators);
1489 if (ret < 0) {
1490 dev_err(dev, "Error parsing regulator init data: %d\n", ret);
7f091e53 1491 return 0;
cac9e916 1492 }
e5ce4208 1493
cac9e916 1494 for (idx = 0; idx < ddata->max_reg; idx++) {
96e4f523 1495 struct of_regulator_match *match;
1b42443d 1496 struct palmas_reg_init *rinit;
6c7d614f 1497 struct device_node *np;
036d193d
NM		 1498
1499 match = &ddata->palmas_matches[idx];
6c7d614f 1500 np = match->of_node;
036d193d 1501
6c7d614f 1502 if (!match->init_data || !np)
cac9e916 1503 continue;
e5ce4208 1504
1b42443d 1505 rinit = devm_kzalloc(dev, sizeof(*rinit), GFP_KERNEL);
7f091e53
NM		 1506 if (!rinit)
1507 return -ENOMEM;
1508
036d193d 1509 pdata->reg_data[idx] = match->init_data;
1b42443d 1510 pdata->reg_init[idx] = rinit;
a361cd9f 1511
6c7d614f
NM		 1512 rinit->warm_reset = of_property_read_bool(np, "ti,warm-reset");
1513 ret = of_property_read_u32(np, "ti,roof-floor", &prop);
cac9e916
K		 1514 /* EINVAL: Property not found */
1515 if (ret != -EINVAL) {
1516 int econtrol;
1517
1518 /* use default value, when no value is specified */
1519 econtrol = PALMAS_EXT_CONTROL_NSLEEP;
1520 if (!ret) {
1521 switch (prop) {
1522 case 1:
1523 econtrol = PALMAS_EXT_CONTROL_ENABLE1;
1524 break;
1525 case 2:
1526 econtrol = PALMAS_EXT_CONTROL_ENABLE2;
1527 break;
1528 case 3:
1529 econtrol = PALMAS_EXT_CONTROL_NSLEEP;
1530 break;
1531 default:
1532 WARN_ON(1);
1533 dev_warn(dev,
1534 "%s: Invalid roof-floor option: %u\n",
036d193d 1535 match->name, prop);
cac9e916
K		 1536 break;
1537 }
e5ce4208 1538 }
1b42443d 1539 rinit->roof_floor = econtrol;
e5ce4208 1540 }
e5ce4208 1541
6c7d614f 1542 ret = of_property_read_u32(np, "ti,mode-sleep", &prop);
cac9e916 1543 if (!ret)
1b42443d 1544 rinit->mode_sleep = prop;
17c11a76 1545
6c7d614f 1546 ret = of_property_read_bool(np, "ti,smps-range");
cac9e916 1547 if (ret)
1b42443d 1548 rinit->vsel = PALMAS_SMPS12_VOLTAGE_RANGE;
cac9e916
K		 1549
1550 if (idx == PALMAS_REG_LDO8)
1551 pdata->enable_ldo8_tracking = of_property_read_bool(
6c7d614f 1552 np, "ti,enable-ldo8-tracking");
cac9e916
K		 1553 }
1554
1555 pdata->ldo6_vibrator = of_property_read_bool(node, "ti,ldo6-vibrator");
7f091e53
NM		 1556
1557 return 0;
e5ce4208
GG		 1558}
1559
cdbf6f0e 1560static const struct of_device_id of_palmas_match_tbl[] = {
cac9e916
K		 1561 {
1562 .compatible = "ti,palmas-pmic",
1563 .data = &palmas_ddata,
1564 },
1565 {
1566 .compatible = "ti,twl6035-pmic",
1567 .data = &palmas_ddata,
1568 },
1569 {
1570 .compatible = "ti,twl6036-pmic",
1571 .data = &palmas_ddata,
1572 },
1573 {
1574 .compatible = "ti,twl6037-pmic",
1575 .data = &palmas_ddata,
1576 },
1577 {
1578 .compatible = "ti,tps65913-pmic",
1579 .data = &palmas_ddata,
1580 },
1581 {
1582 .compatible = "ti,tps65914-pmic",
1583 .data = &palmas_ddata,
1584 },
1585 {
1586 .compatible = "ti,tps80036-pmic",
1587 .data = &palmas_ddata,
1588 },
1589 {
1590 .compatible = "ti,tps659038-pmic",
1591 .data = &palmas_ddata,
d6f83370
K		 1592 },
1593 {
1594 .compatible = "ti,tps65917-pmic",
1595 .data = &tps65917_ddata,
cac9e916 1596 },
a361cd9f
GG		 1597 { /* end */ }
1598};
1599
cac9e916
K		 1600static int palmas_regulators_probe(struct platform_device *pdev)
1601{
1602 struct palmas *palmas = dev_get_drvdata(pdev->dev.parent);
1603 struct palmas_pmic_platform_data *pdata = dev_get_platdata(&pdev->dev);
1604 struct device_node *node = pdev->dev.of_node;
1605 struct palmas_pmic_driver_data *driver_data;
1606 struct regulator_config config = { };
1607 struct palmas_pmic *pmic;
1608 const char *pdev_name;
1609 const struct of_device_id *match;
1610 int ret = 0;
1611 unsigned int reg;
1612
1613 match = of_match_device(of_match_ptr(of_palmas_match_tbl), &pdev->dev);
1614
1615 if (!match)
1616 return -ENODATA;
1617
1618 driver_data = (struct palmas_pmic_driver_data *)match->data;
1619 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1620 if (!pdata)
1621 return -ENOMEM;
1622
1623 pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
1624 if (!pmic)
1625 return -ENOMEM;
1626
e999c728 1627 if (of_device_is_compatible(node, "ti,tps659038-pmic")) {
e03826d5
K		 1628 palmas_generic_regs_info[PALMAS_REG_REGEN2].ctrl_addr =
1629 TPS659038_REGEN2_CTRL;
e999c728
K		 1630 palmas_ddata.has_regen3 = false;
1631 }
e03826d5 1632
cac9e916
K		 1633 pmic->dev = &pdev->dev;
1634 pmic->palmas = palmas;
1635 palmas->pmic = pmic;
1636 platform_set_drvdata(pdev, pmic);
1637 pmic->palmas->pmic_ddata = driver_data;
1638
7f091e53
NM		 1639 ret = palmas_dt_to_pdata(&pdev->dev, node, pdata, driver_data);
1640 if (ret)
1641 return ret;
cac9e916
K		 1642
1643 ret = palmas_smps_read(palmas, PALMAS_SMPS_CTRL, &reg);
1644 if (ret)
1645 return ret;
1646
be035303 1647 if (reg & PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN) {
cac9e916 1648 pmic->smps123 = 1;
be035303
K		 1649 pmic->smps12 = 1;
1650 }
cac9e916
K		 1651
1652 if (reg & PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN)
1653 pmic->smps457 = 1;
1654
1655 config.regmap = palmas->regmap[REGULATOR_SLAVE];
1656 config.dev = &pdev->dev;
1657 config.driver_data = pmic;
1658 pdev_name = pdev->name;
1659
1660 ret = driver_data->smps_register(pmic, driver_data, pdata, pdev_name,
1661 config);
1662 if (ret)
1663 return ret;
1664
1665 ret = driver_data->ldo_register(pmic, driver_data, pdata, pdev_name,
1666 config);
1667
1668 return ret;
1669}
1670
e5ce4208
GG		 1671static struct platform_driver palmas_driver = {
1672 .driver = {
1673 .name = "palmas-pmic",
a361cd9f 1674 .of_match_table = of_palmas_match_tbl,
e5ce4208 1675 },
bbcf50b1 1676 .probe = palmas_regulators_probe,
e5ce4208
GG		 1677};
1678
1679static int __init palmas_init(void)
1680{
1681 return platform_driver_register(&palmas_driver);
1682}
1683subsys_initcall(palmas_init);
1684
1685static void __exit palmas_exit(void)
1686{
1687 platform_driver_unregister(&palmas_driver);
1688}
1689module_exit(palmas_exit);
1690
1691MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
1692MODULE_DESCRIPTION("Palmas voltage regulator driver");
1693MODULE_LICENSE("GPL");
1694MODULE_ALIAS("platform:palmas-pmic");
a361cd9f 1695MODULE_DEVICE_TABLE(of, of_palmas_match_tbl);
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