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4f3fb287 KK |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | // | |
3 | // Copyright (c) 2011 Samsung Electronics Co., Ltd | |
4 | // http://www.samsung.com | |
9767ec7f | 5 | |
9767ec7f | 6 | #include <linux/err.h> |
26aec009 | 7 | #include <linux/of_gpio.h> |
9ae5cc75 | 8 | #include <linux/gpio/consumer.h> |
9767ec7f SK |
9 | #include <linux/module.h> |
10 | #include <linux/platform_device.h> | |
11 | #include <linux/regulator/driver.h> | |
12 | #include <linux/regulator/machine.h> | |
54227bcf SK |
13 | #include <linux/mfd/samsung/core.h> |
14 | #include <linux/mfd/samsung/s5m8767.h> | |
26aec009 | 15 | #include <linux/regulator/of_regulator.h> |
d13733f4 | 16 | #include <linux/regmap.h> |
26aec009 ADK |
17 | |
18 | #define S5M8767_OPMODE_NORMAL_MODE 0x1 | |
9767ec7f SK |
19 | |
20 | struct s5m8767_info { | |
21 | struct device *dev; | |
63063bfb | 22 | struct sec_pmic_dev *iodev; |
9767ec7f | 23 | int num_regulators; |
63063bfb | 24 | struct sec_opmode_data *opmode; |
9767ec7f SK |
25 | |
26 | int ramp_delay; | |
27 | bool buck2_ramp; | |
28 | bool buck3_ramp; | |
29 | bool buck4_ramp; | |
30 | ||
31 | bool buck2_gpiodvs; | |
32 | bool buck3_gpiodvs; | |
33 | bool buck4_gpiodvs; | |
34 | u8 buck2_vol[8]; | |
35 | u8 buck3_vol[8]; | |
36 | u8 buck4_vol[8]; | |
37 | int buck_gpios[3]; | |
c848bc85 | 38 | int buck_ds[3]; |
9767ec7f SK |
39 | int buck_gpioindex; |
40 | }; | |
41 | ||
63063bfb | 42 | struct sec_voltage_desc { |
9767ec7f SK |
43 | int max; |
44 | int min; | |
45 | int step; | |
46 | }; | |
47 | ||
63063bfb | 48 | static const struct sec_voltage_desc buck_voltage_val1 = { |
9767ec7f SK |
49 | .max = 2225000, |
50 | .min = 650000, | |
51 | .step = 6250, | |
52 | }; | |
53 | ||
63063bfb | 54 | static const struct sec_voltage_desc buck_voltage_val2 = { |
9767ec7f SK |
55 | .max = 1600000, |
56 | .min = 600000, | |
57 | .step = 6250, | |
58 | }; | |
59 | ||
63063bfb | 60 | static const struct sec_voltage_desc buck_voltage_val3 = { |
9767ec7f SK |
61 | .max = 3000000, |
62 | .min = 750000, | |
63 | .step = 12500, | |
64 | }; | |
65 | ||
63063bfb | 66 | static const struct sec_voltage_desc ldo_voltage_val1 = { |
9767ec7f SK |
67 | .max = 3950000, |
68 | .min = 800000, | |
69 | .step = 50000, | |
70 | }; | |
71 | ||
63063bfb | 72 | static const struct sec_voltage_desc ldo_voltage_val2 = { |
9767ec7f SK |
73 | .max = 2375000, |
74 | .min = 800000, | |
75 | .step = 25000, | |
76 | }; | |
77 | ||
63063bfb | 78 | static const struct sec_voltage_desc *reg_voltage_map[] = { |
9767ec7f SK |
79 | [S5M8767_LDO1] = &ldo_voltage_val2, |
80 | [S5M8767_LDO2] = &ldo_voltage_val2, | |
81 | [S5M8767_LDO3] = &ldo_voltage_val1, | |
82 | [S5M8767_LDO4] = &ldo_voltage_val1, | |
83 | [S5M8767_LDO5] = &ldo_voltage_val1, | |
84 | [S5M8767_LDO6] = &ldo_voltage_val2, | |
85 | [S5M8767_LDO7] = &ldo_voltage_val2, | |
86 | [S5M8767_LDO8] = &ldo_voltage_val2, | |
87 | [S5M8767_LDO9] = &ldo_voltage_val1, | |
88 | [S5M8767_LDO10] = &ldo_voltage_val1, | |
89 | [S5M8767_LDO11] = &ldo_voltage_val1, | |
90 | [S5M8767_LDO12] = &ldo_voltage_val1, | |
91 | [S5M8767_LDO13] = &ldo_voltage_val1, | |
92 | [S5M8767_LDO14] = &ldo_voltage_val1, | |
93 | [S5M8767_LDO15] = &ldo_voltage_val2, | |
94 | [S5M8767_LDO16] = &ldo_voltage_val1, | |
95 | [S5M8767_LDO17] = &ldo_voltage_val1, | |
96 | [S5M8767_LDO18] = &ldo_voltage_val1, | |
97 | [S5M8767_LDO19] = &ldo_voltage_val1, | |
98 | [S5M8767_LDO20] = &ldo_voltage_val1, | |
99 | [S5M8767_LDO21] = &ldo_voltage_val1, | |
100 | [S5M8767_LDO22] = &ldo_voltage_val1, | |
101 | [S5M8767_LDO23] = &ldo_voltage_val1, | |
102 | [S5M8767_LDO24] = &ldo_voltage_val1, | |
103 | [S5M8767_LDO25] = &ldo_voltage_val1, | |
104 | [S5M8767_LDO26] = &ldo_voltage_val1, | |
105 | [S5M8767_LDO27] = &ldo_voltage_val1, | |
106 | [S5M8767_LDO28] = &ldo_voltage_val1, | |
107 | [S5M8767_BUCK1] = &buck_voltage_val1, | |
108 | [S5M8767_BUCK2] = &buck_voltage_val2, | |
109 | [S5M8767_BUCK3] = &buck_voltage_val2, | |
110 | [S5M8767_BUCK4] = &buck_voltage_val2, | |
111 | [S5M8767_BUCK5] = &buck_voltage_val1, | |
112 | [S5M8767_BUCK6] = &buck_voltage_val1, | |
463616ea KK |
113 | [S5M8767_BUCK7] = &buck_voltage_val3, |
114 | [S5M8767_BUCK8] = &buck_voltage_val3, | |
9767ec7f SK |
115 | [S5M8767_BUCK9] = &buck_voltage_val3, |
116 | }; | |
117 | ||
21687b16 | 118 | static const unsigned int s5m8767_opmode_reg[][4] = { |
7e44bb83 SK |
119 | /* {OFF, ON, LOWPOWER, SUSPEND} */ |
120 | /* LDO1 ... LDO28 */ | |
121 | {0x0, 0x3, 0x2, 0x1}, /* LDO1 */ | |
122 | {0x0, 0x3, 0x2, 0x1}, | |
123 | {0x0, 0x3, 0x2, 0x1}, | |
124 | {0x0, 0x0, 0x0, 0x0}, | |
125 | {0x0, 0x3, 0x2, 0x1}, /* LDO5 */ | |
126 | {0x0, 0x3, 0x2, 0x1}, | |
127 | {0x0, 0x3, 0x2, 0x1}, | |
128 | {0x0, 0x3, 0x2, 0x1}, | |
129 | {0x0, 0x3, 0x2, 0x1}, | |
130 | {0x0, 0x3, 0x2, 0x1}, /* LDO10 */ | |
131 | {0x0, 0x3, 0x2, 0x1}, | |
132 | {0x0, 0x3, 0x2, 0x1}, | |
133 | {0x0, 0x3, 0x2, 0x1}, | |
134 | {0x0, 0x3, 0x2, 0x1}, | |
135 | {0x0, 0x3, 0x2, 0x1}, /* LDO15 */ | |
136 | {0x0, 0x3, 0x2, 0x1}, | |
137 | {0x0, 0x3, 0x2, 0x1}, | |
138 | {0x0, 0x0, 0x0, 0x0}, | |
139 | {0x0, 0x3, 0x2, 0x1}, | |
140 | {0x0, 0x3, 0x2, 0x1}, /* LDO20 */ | |
141 | {0x0, 0x3, 0x2, 0x1}, | |
142 | {0x0, 0x3, 0x2, 0x1}, | |
143 | {0x0, 0x0, 0x0, 0x0}, | |
144 | {0x0, 0x3, 0x2, 0x1}, | |
145 | {0x0, 0x3, 0x2, 0x1}, /* LDO25 */ | |
146 | {0x0, 0x3, 0x2, 0x1}, | |
147 | {0x0, 0x3, 0x2, 0x1}, | |
148 | {0x0, 0x3, 0x2, 0x1}, /* LDO28 */ | |
149 | ||
150 | /* BUCK1 ... BUCK9 */ | |
151 | {0x0, 0x3, 0x1, 0x1}, /* BUCK1 */ | |
152 | {0x0, 0x3, 0x1, 0x1}, | |
153 | {0x0, 0x3, 0x1, 0x1}, | |
154 | {0x0, 0x3, 0x1, 0x1}, | |
155 | {0x0, 0x3, 0x2, 0x1}, /* BUCK5 */ | |
156 | {0x0, 0x3, 0x1, 0x1}, | |
157 | {0x0, 0x3, 0x1, 0x1}, | |
158 | {0x0, 0x3, 0x1, 0x1}, | |
159 | {0x0, 0x3, 0x1, 0x1}, /* BUCK9 */ | |
160 | }; | |
161 | ||
9c4c6055 AL |
162 | static int s5m8767_get_register(struct s5m8767_info *s5m8767, int reg_id, |
163 | int *reg, int *enable_ctrl) | |
9767ec7f | 164 | { |
9c4c6055 | 165 | int i; |
7e44bb83 | 166 | unsigned int mode; |
9767ec7f SK |
167 | |
168 | switch (reg_id) { | |
169 | case S5M8767_LDO1 ... S5M8767_LDO2: | |
170 | *reg = S5M8767_REG_LDO1CTRL + (reg_id - S5M8767_LDO1); | |
171 | break; | |
172 | case S5M8767_LDO3 ... S5M8767_LDO28: | |
173 | *reg = S5M8767_REG_LDO3CTRL + (reg_id - S5M8767_LDO3); | |
174 | break; | |
175 | case S5M8767_BUCK1: | |
176 | *reg = S5M8767_REG_BUCK1CTRL1; | |
177 | break; | |
178 | case S5M8767_BUCK2 ... S5M8767_BUCK4: | |
179 | *reg = S5M8767_REG_BUCK2CTRL + (reg_id - S5M8767_BUCK2) * 9; | |
180 | break; | |
181 | case S5M8767_BUCK5: | |
182 | *reg = S5M8767_REG_BUCK5CTRL1; | |
183 | break; | |
184 | case S5M8767_BUCK6 ... S5M8767_BUCK9: | |
185 | *reg = S5M8767_REG_BUCK6CTRL1 + (reg_id - S5M8767_BUCK6) * 2; | |
186 | break; | |
187 | default: | |
188 | return -EINVAL; | |
189 | } | |
190 | ||
9bb096ff ADK |
191 | for (i = 0; i < s5m8767->num_regulators; i++) { |
192 | if (s5m8767->opmode[i].id == reg_id) { | |
193 | mode = s5m8767->opmode[i].mode; | |
194 | break; | |
195 | } | |
196 | } | |
197 | ||
e07ff943 AB |
198 | if (i >= s5m8767->num_regulators) |
199 | return -EINVAL; | |
200 | ||
201 | *enable_ctrl = s5m8767_opmode_reg[reg_id][mode] << S5M8767_ENCTRL_SHIFT; | |
9bb096ff | 202 | |
9767ec7f SK |
203 | return 0; |
204 | } | |
205 | ||
31a932e1 | 206 | static int s5m8767_get_vsel_reg(int reg_id, struct s5m8767_info *s5m8767) |
9767ec7f | 207 | { |
9767ec7f SK |
208 | int reg; |
209 | ||
210 | switch (reg_id) { | |
211 | case S5M8767_LDO1 ... S5M8767_LDO2: | |
212 | reg = S5M8767_REG_LDO1CTRL + (reg_id - S5M8767_LDO1); | |
213 | break; | |
214 | case S5M8767_LDO3 ... S5M8767_LDO28: | |
215 | reg = S5M8767_REG_LDO3CTRL + (reg_id - S5M8767_LDO3); | |
216 | break; | |
217 | case S5M8767_BUCK1: | |
218 | reg = S5M8767_REG_BUCK1CTRL2; | |
219 | break; | |
220 | case S5M8767_BUCK2: | |
da130ab2 | 221 | reg = S5M8767_REG_BUCK2DVS1; |
0a41685f AL |
222 | if (s5m8767->buck2_gpiodvs) |
223 | reg += s5m8767->buck_gpioindex; | |
9767ec7f SK |
224 | break; |
225 | case S5M8767_BUCK3: | |
da130ab2 | 226 | reg = S5M8767_REG_BUCK3DVS1; |
0a41685f AL |
227 | if (s5m8767->buck3_gpiodvs) |
228 | reg += s5m8767->buck_gpioindex; | |
9767ec7f SK |
229 | break; |
230 | case S5M8767_BUCK4: | |
da130ab2 | 231 | reg = S5M8767_REG_BUCK4DVS1; |
0a41685f AL |
232 | if (s5m8767->buck4_gpiodvs) |
233 | reg += s5m8767->buck_gpioindex; | |
9767ec7f SK |
234 | break; |
235 | case S5M8767_BUCK5: | |
236 | reg = S5M8767_REG_BUCK5CTRL2; | |
237 | break; | |
238 | case S5M8767_BUCK6 ... S5M8767_BUCK9: | |
239 | reg = S5M8767_REG_BUCK6CTRL2 + (reg_id - S5M8767_BUCK6) * 2; | |
240 | break; | |
241 | default: | |
242 | return -EINVAL; | |
243 | } | |
244 | ||
31a932e1 | 245 | return reg; |
9767ec7f SK |
246 | } |
247 | ||
854f73ec AL |
248 | static int s5m8767_convert_voltage_to_sel(const struct sec_voltage_desc *desc, |
249 | int min_vol) | |
9767ec7f | 250 | { |
5b5e977c | 251 | int selector = 0; |
9767ec7f SK |
252 | |
253 | if (desc == NULL) | |
254 | return -EINVAL; | |
255 | ||
854f73ec | 256 | if (min_vol > desc->max) |
9767ec7f SK |
257 | return -EINVAL; |
258 | ||
94e85a3c AL |
259 | if (min_vol < desc->min) |
260 | min_vol = desc->min; | |
261 | ||
262 | selector = DIV_ROUND_UP(min_vol - desc->min, desc->step); | |
9767ec7f | 263 | |
854f73ec | 264 | if (desc->min + desc->step * selector > desc->max) |
9767ec7f SK |
265 | return -EINVAL; |
266 | ||
5b5e977c | 267 | return selector; |
9767ec7f SK |
268 | } |
269 | ||
df2643cf | 270 | static inline int s5m8767_set_high(struct s5m8767_info *s5m8767) |
321d2aba AL |
271 | { |
272 | int temp_index = s5m8767->buck_gpioindex; | |
273 | ||
274 | gpio_set_value(s5m8767->buck_gpios[0], (temp_index >> 2) & 0x1); | |
275 | gpio_set_value(s5m8767->buck_gpios[1], (temp_index >> 1) & 0x1); | |
276 | gpio_set_value(s5m8767->buck_gpios[2], temp_index & 0x1); | |
df2643cf SK |
277 | |
278 | return 0; | |
321d2aba AL |
279 | } |
280 | ||
df2643cf | 281 | static inline int s5m8767_set_low(struct s5m8767_info *s5m8767) |
321d2aba AL |
282 | { |
283 | int temp_index = s5m8767->buck_gpioindex; | |
284 | ||
285 | gpio_set_value(s5m8767->buck_gpios[2], temp_index & 0x1); | |
286 | gpio_set_value(s5m8767->buck_gpios[1], (temp_index >> 1) & 0x1); | |
287 | gpio_set_value(s5m8767->buck_gpios[0], (temp_index >> 2) & 0x1); | |
df2643cf SK |
288 | |
289 | return 0; | |
321d2aba AL |
290 | } |
291 | ||
df2643cf SK |
292 | static int s5m8767_set_voltage_sel(struct regulator_dev *rdev, |
293 | unsigned selector) | |
9767ec7f SK |
294 | { |
295 | struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev); | |
20a14b84 | 296 | int reg_id = rdev_get_id(rdev); |
31a932e1 | 297 | int old_index, index = 0; |
321d2aba | 298 | u8 *buck234_vol = NULL; |
9767ec7f SK |
299 | |
300 | switch (reg_id) { | |
301 | case S5M8767_LDO1 ... S5M8767_LDO28: | |
9767ec7f SK |
302 | break; |
303 | case S5M8767_BUCK1 ... S5M8767_BUCK6: | |
321d2aba AL |
304 | if (reg_id == S5M8767_BUCK2 && s5m8767->buck2_gpiodvs) |
305 | buck234_vol = &s5m8767->buck2_vol[0]; | |
306 | else if (reg_id == S5M8767_BUCK3 && s5m8767->buck3_gpiodvs) | |
307 | buck234_vol = &s5m8767->buck3_vol[0]; | |
308 | else if (reg_id == S5M8767_BUCK4 && s5m8767->buck4_gpiodvs) | |
309 | buck234_vol = &s5m8767->buck4_vol[0]; | |
9767ec7f SK |
310 | break; |
311 | case S5M8767_BUCK7 ... S5M8767_BUCK8: | |
312 | return -EINVAL; | |
313 | case S5M8767_BUCK9: | |
9767ec7f SK |
314 | break; |
315 | default: | |
316 | return -EINVAL; | |
317 | } | |
318 | ||
321d2aba AL |
319 | /* buck234_vol != NULL means to control buck234 voltage via DVS GPIO */ |
320 | if (buck234_vol) { | |
df2643cf | 321 | while (*buck234_vol != selector) { |
321d2aba AL |
322 | buck234_vol++; |
323 | index++; | |
324 | } | |
325 | old_index = s5m8767->buck_gpioindex; | |
326 | s5m8767->buck_gpioindex = index; | |
327 | ||
328 | if (index > old_index) | |
df2643cf | 329 | return s5m8767_set_high(s5m8767); |
321d2aba | 330 | else |
df2643cf | 331 | return s5m8767_set_low(s5m8767); |
321d2aba | 332 | } else { |
31a932e1 | 333 | return regulator_set_voltage_sel_regmap(rdev, selector); |
321d2aba | 334 | } |
9767ec7f SK |
335 | } |
336 | ||
9767ec7f SK |
337 | static int s5m8767_set_voltage_time_sel(struct regulator_dev *rdev, |
338 | unsigned int old_sel, | |
339 | unsigned int new_sel) | |
340 | { | |
341 | struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev); | |
9767ec7f | 342 | |
9d88fc0b | 343 | if ((old_sel < new_sel) && s5m8767->ramp_delay) |
bf1fc259 | 344 | return DIV_ROUND_UP(rdev->desc->uV_step * (new_sel - old_sel), |
0f8b9c77 | 345 | s5m8767->ramp_delay * 1000); |
89e0f0e4 | 346 | return 0; |
9767ec7f SK |
347 | } |
348 | ||
8a05eb19 | 349 | static const struct regulator_ops s5m8767_ops = { |
e2eb169b | 350 | .list_voltage = regulator_list_voltage_linear, |
9c4c6055 AL |
351 | .is_enabled = regulator_is_enabled_regmap, |
352 | .enable = regulator_enable_regmap, | |
353 | .disable = regulator_disable_regmap, | |
31a932e1 | 354 | .get_voltage_sel = regulator_get_voltage_sel_regmap, |
df2643cf | 355 | .set_voltage_sel = s5m8767_set_voltage_sel, |
9767ec7f SK |
356 | .set_voltage_time_sel = s5m8767_set_voltage_time_sel, |
357 | }; | |
358 | ||
8a05eb19 | 359 | static const struct regulator_ops s5m8767_buck78_ops = { |
463616ea | 360 | .list_voltage = regulator_list_voltage_linear, |
9c4c6055 AL |
361 | .is_enabled = regulator_is_enabled_regmap, |
362 | .enable = regulator_enable_regmap, | |
363 | .disable = regulator_disable_regmap, | |
463616ea KK |
364 | .get_voltage_sel = regulator_get_voltage_sel_regmap, |
365 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
e2eb169b AL |
366 | }; |
367 | ||
65896e73 AL |
368 | #define s5m8767_regulator_desc(_name) { \ |
369 | .name = #_name, \ | |
370 | .id = S5M8767_##_name, \ | |
371 | .ops = &s5m8767_ops, \ | |
9767ec7f SK |
372 | .type = REGULATOR_VOLTAGE, \ |
373 | .owner = THIS_MODULE, \ | |
374 | } | |
375 | ||
e2eb169b AL |
376 | #define s5m8767_regulator_buck78_desc(_name) { \ |
377 | .name = #_name, \ | |
378 | .id = S5M8767_##_name, \ | |
379 | .ops = &s5m8767_buck78_ops, \ | |
380 | .type = REGULATOR_VOLTAGE, \ | |
381 | .owner = THIS_MODULE, \ | |
382 | } | |
383 | ||
9767ec7f | 384 | static struct regulator_desc regulators[] = { |
65896e73 AL |
385 | s5m8767_regulator_desc(LDO1), |
386 | s5m8767_regulator_desc(LDO2), | |
387 | s5m8767_regulator_desc(LDO3), | |
388 | s5m8767_regulator_desc(LDO4), | |
389 | s5m8767_regulator_desc(LDO5), | |
390 | s5m8767_regulator_desc(LDO6), | |
391 | s5m8767_regulator_desc(LDO7), | |
392 | s5m8767_regulator_desc(LDO8), | |
393 | s5m8767_regulator_desc(LDO9), | |
394 | s5m8767_regulator_desc(LDO10), | |
395 | s5m8767_regulator_desc(LDO11), | |
396 | s5m8767_regulator_desc(LDO12), | |
397 | s5m8767_regulator_desc(LDO13), | |
398 | s5m8767_regulator_desc(LDO14), | |
399 | s5m8767_regulator_desc(LDO15), | |
400 | s5m8767_regulator_desc(LDO16), | |
401 | s5m8767_regulator_desc(LDO17), | |
402 | s5m8767_regulator_desc(LDO18), | |
403 | s5m8767_regulator_desc(LDO19), | |
404 | s5m8767_regulator_desc(LDO20), | |
405 | s5m8767_regulator_desc(LDO21), | |
406 | s5m8767_regulator_desc(LDO22), | |
407 | s5m8767_regulator_desc(LDO23), | |
408 | s5m8767_regulator_desc(LDO24), | |
409 | s5m8767_regulator_desc(LDO25), | |
410 | s5m8767_regulator_desc(LDO26), | |
411 | s5m8767_regulator_desc(LDO27), | |
412 | s5m8767_regulator_desc(LDO28), | |
413 | s5m8767_regulator_desc(BUCK1), | |
414 | s5m8767_regulator_desc(BUCK2), | |
415 | s5m8767_regulator_desc(BUCK3), | |
416 | s5m8767_regulator_desc(BUCK4), | |
417 | s5m8767_regulator_desc(BUCK5), | |
418 | s5m8767_regulator_desc(BUCK6), | |
e2eb169b AL |
419 | s5m8767_regulator_buck78_desc(BUCK7), |
420 | s5m8767_regulator_buck78_desc(BUCK8), | |
65896e73 | 421 | s5m8767_regulator_desc(BUCK9), |
9767ec7f SK |
422 | }; |
423 | ||
ee1e0994 KK |
424 | /* |
425 | * Enable GPIO control over BUCK9 in regulator_config for that regulator. | |
426 | */ | |
427 | static void s5m8767_regulator_config_ext_control(struct s5m8767_info *s5m8767, | |
428 | struct sec_regulator_data *rdata, | |
429 | struct regulator_config *config) | |
430 | { | |
431 | int i, mode = 0; | |
432 | ||
433 | if (rdata->id != S5M8767_BUCK9) | |
434 | return; | |
435 | ||
436 | /* Check if opmode for regulator matches S5M8767_ENCTRL_USE_GPIO */ | |
437 | for (i = 0; i < s5m8767->num_regulators; i++) { | |
438 | const struct sec_opmode_data *opmode = &s5m8767->opmode[i]; | |
439 | if (opmode->id == rdata->id) { | |
440 | mode = s5m8767_opmode_reg[rdata->id][opmode->mode]; | |
441 | break; | |
442 | } | |
443 | } | |
444 | if (mode != S5M8767_ENCTRL_USE_GPIO) { | |
445 | dev_warn(s5m8767->dev, | |
0c9721a5 RH |
446 | "ext-control for %pOFn: mismatched op_mode (%x), ignoring\n", |
447 | rdata->reg_node, mode); | |
ee1e0994 KK |
448 | return; |
449 | } | |
450 | ||
9ae5cc75 | 451 | if (!rdata->ext_control_gpiod) { |
ee1e0994 | 452 | dev_warn(s5m8767->dev, |
0c9721a5 RH |
453 | "ext-control for %pOFn: GPIO not valid, ignoring\n", |
454 | rdata->reg_node); | |
ee1e0994 KK |
455 | return; |
456 | } | |
457 | ||
9ae5cc75 | 458 | config->ena_gpiod = rdata->ext_control_gpiod; |
ee1e0994 KK |
459 | } |
460 | ||
461 | /* | |
462 | * Turn on GPIO control over BUCK9. | |
463 | */ | |
464 | static int s5m8767_enable_ext_control(struct s5m8767_info *s5m8767, | |
465 | struct regulator_dev *rdev) | |
466 | { | |
9c4c6055 | 467 | int id = rdev_get_id(rdev); |
ee1e0994 KK |
468 | int ret, reg, enable_ctrl; |
469 | ||
9c4c6055 | 470 | if (id != S5M8767_BUCK9) |
ee1e0994 KK |
471 | return -EINVAL; |
472 | ||
9c4c6055 | 473 | ret = s5m8767_get_register(s5m8767, id, ®, &enable_ctrl); |
ee1e0994 KK |
474 | if (ret) |
475 | return ret; | |
476 | ||
477 | return regmap_update_bits(s5m8767->iodev->regmap_pmic, | |
478 | reg, S5M8767_ENCTRL_MASK, | |
479 | S5M8767_ENCTRL_USE_GPIO << S5M8767_ENCTRL_SHIFT); | |
480 | } | |
481 | ||
482 | ||
26aec009 ADK |
483 | #ifdef CONFIG_OF |
484 | static int s5m8767_pmic_dt_parse_dvs_gpio(struct sec_pmic_dev *iodev, | |
485 | struct sec_platform_data *pdata, | |
486 | struct device_node *pmic_np) | |
487 | { | |
488 | int i, gpio; | |
489 | ||
490 | for (i = 0; i < 3; i++) { | |
491 | gpio = of_get_named_gpio(pmic_np, | |
492 | "s5m8767,pmic-buck-dvs-gpios", i); | |
493 | if (!gpio_is_valid(gpio)) { | |
494 | dev_err(iodev->dev, "invalid gpio[%d]: %d\n", i, gpio); | |
495 | return -EINVAL; | |
496 | } | |
497 | pdata->buck_gpios[i] = gpio; | |
498 | } | |
499 | return 0; | |
500 | } | |
501 | ||
502 | static int s5m8767_pmic_dt_parse_ds_gpio(struct sec_pmic_dev *iodev, | |
503 | struct sec_platform_data *pdata, | |
504 | struct device_node *pmic_np) | |
505 | { | |
506 | int i, gpio; | |
507 | ||
508 | for (i = 0; i < 3; i++) { | |
509 | gpio = of_get_named_gpio(pmic_np, | |
510 | "s5m8767,pmic-buck-ds-gpios", i); | |
511 | if (!gpio_is_valid(gpio)) { | |
512 | dev_err(iodev->dev, "invalid gpio[%d]: %d\n", i, gpio); | |
513 | return -EINVAL; | |
514 | } | |
515 | pdata->buck_ds[i] = gpio; | |
516 | } | |
517 | return 0; | |
518 | } | |
519 | ||
cbb0ed49 | 520 | static int s5m8767_pmic_dt_parse_pdata(struct platform_device *pdev, |
26aec009 ADK |
521 | struct sec_platform_data *pdata) |
522 | { | |
cbb0ed49 | 523 | struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent); |
26aec009 ADK |
524 | struct device_node *pmic_np, *regulators_np, *reg_np; |
525 | struct sec_regulator_data *rdata; | |
526 | struct sec_opmode_data *rmode; | |
04f9f068 | 527 | unsigned int i, dvs_voltage_nr = 8, ret; |
26aec009 ADK |
528 | |
529 | pmic_np = iodev->dev->of_node; | |
530 | if (!pmic_np) { | |
531 | dev_err(iodev->dev, "could not find pmic sub-node\n"); | |
532 | return -ENODEV; | |
533 | } | |
534 | ||
4e52c03d | 535 | regulators_np = of_get_child_by_name(pmic_np, "regulators"); |
26aec009 ADK |
536 | if (!regulators_np) { |
537 | dev_err(iodev->dev, "could not find regulators sub-node\n"); | |
538 | return -EINVAL; | |
539 | } | |
540 | ||
541 | /* count the number of regulators to be supported in pmic */ | |
1f91b6f6 | 542 | pdata->num_regulators = of_get_child_count(regulators_np); |
26aec009 | 543 | |
a86854d0 KC |
544 | rdata = devm_kcalloc(&pdev->dev, |
545 | pdata->num_regulators, sizeof(*rdata), | |
546 | GFP_KERNEL); | |
a5872bd3 KK |
547 | if (!rdata) { |
548 | of_node_put(regulators_np); | |
26aec009 | 549 | return -ENOMEM; |
a5872bd3 | 550 | } |
26aec009 | 551 | |
a86854d0 KC |
552 | rmode = devm_kcalloc(&pdev->dev, |
553 | pdata->num_regulators, sizeof(*rmode), | |
554 | GFP_KERNEL); | |
a5872bd3 KK |
555 | if (!rmode) { |
556 | of_node_put(regulators_np); | |
26aec009 | 557 | return -ENOMEM; |
a5872bd3 | 558 | } |
26aec009 ADK |
559 | |
560 | pdata->regulators = rdata; | |
561 | pdata->opmode = rmode; | |
562 | for_each_child_of_node(regulators_np, reg_np) { | |
563 | for (i = 0; i < ARRAY_SIZE(regulators); i++) | |
c32569e3 | 564 | if (of_node_name_eq(reg_np, regulators[i].name)) |
26aec009 ADK |
565 | break; |
566 | ||
567 | if (i == ARRAY_SIZE(regulators)) { | |
568 | dev_warn(iodev->dev, | |
0c9721a5 RH |
569 | "don't know how to configure regulator %pOFn\n", |
570 | reg_np); | |
26aec009 ADK |
571 | continue; |
572 | } | |
573 | ||
5be0e549 | 574 | rdata->ext_control_gpiod = devm_fwnode_gpiod_get( |
63239e4b | 575 | &pdev->dev, |
5be0e549 DT |
576 | of_fwnode_handle(reg_np), |
577 | "s5m8767,pmic-ext-control", | |
63239e4b LW |
578 | GPIOD_OUT_HIGH | GPIOD_FLAGS_BIT_NONEXCLUSIVE, |
579 | "s5m8767"); | |
dea6dd2b | 580 | if (PTR_ERR(rdata->ext_control_gpiod) == -ENOENT) { |
025bf377 | 581 | rdata->ext_control_gpiod = NULL; |
dea6dd2b PB |
582 | } else if (IS_ERR(rdata->ext_control_gpiod)) { |
583 | of_node_put(reg_np); | |
584 | of_node_put(regulators_np); | |
9ae5cc75 | 585 | return PTR_ERR(rdata->ext_control_gpiod); |
dea6dd2b | 586 | } |
ee1e0994 | 587 | |
26aec009 ADK |
588 | rdata->id = i; |
589 | rdata->initdata = of_get_regulator_init_data( | |
072e78b1 JMC |
590 | &pdev->dev, reg_np, |
591 | ®ulators[i]); | |
26aec009 ADK |
592 | rdata->reg_node = reg_np; |
593 | rdata++; | |
594 | rmode->id = i; | |
595 | if (of_property_read_u32(reg_np, "op_mode", | |
596 | &rmode->mode)) { | |
597 | dev_warn(iodev->dev, | |
f3c7f7b6 | 598 | "no op_mode property at %pOF\n", |
7799167b | 599 | reg_np); |
26aec009 ADK |
600 | |
601 | rmode->mode = S5M8767_OPMODE_NORMAL_MODE; | |
602 | } | |
603 | rmode++; | |
604 | } | |
605 | ||
b7db01f3 SK |
606 | of_node_put(regulators_np); |
607 | ||
04f9f068 | 608 | if (of_get_property(pmic_np, "s5m8767,pmic-buck2-uses-gpio-dvs", NULL)) { |
26aec009 ADK |
609 | pdata->buck2_gpiodvs = true; |
610 | ||
04f9f068 CC |
611 | if (of_property_read_u32_array(pmic_np, |
612 | "s5m8767,pmic-buck2-dvs-voltage", | |
613 | pdata->buck2_voltage, dvs_voltage_nr)) { | |
614 | dev_err(iodev->dev, "buck2 voltages not specified\n"); | |
615 | return -EINVAL; | |
616 | } | |
617 | } | |
618 | ||
619 | if (of_get_property(pmic_np, "s5m8767,pmic-buck3-uses-gpio-dvs", NULL)) { | |
26aec009 ADK |
620 | pdata->buck3_gpiodvs = true; |
621 | ||
04f9f068 CC |
622 | if (of_property_read_u32_array(pmic_np, |
623 | "s5m8767,pmic-buck3-dvs-voltage", | |
624 | pdata->buck3_voltage, dvs_voltage_nr)) { | |
625 | dev_err(iodev->dev, "buck3 voltages not specified\n"); | |
626 | return -EINVAL; | |
627 | } | |
628 | } | |
629 | ||
630 | if (of_get_property(pmic_np, "s5m8767,pmic-buck4-uses-gpio-dvs", NULL)) { | |
26aec009 ADK |
631 | pdata->buck4_gpiodvs = true; |
632 | ||
04f9f068 CC |
633 | if (of_property_read_u32_array(pmic_np, |
634 | "s5m8767,pmic-buck4-dvs-voltage", | |
635 | pdata->buck4_voltage, dvs_voltage_nr)) { | |
636 | dev_err(iodev->dev, "buck4 voltages not specified\n"); | |
637 | return -EINVAL; | |
638 | } | |
639 | } | |
640 | ||
26aec009 ADK |
641 | if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs || |
642 | pdata->buck4_gpiodvs) { | |
643 | ret = s5m8767_pmic_dt_parse_dvs_gpio(iodev, pdata, pmic_np); | |
644 | if (ret) | |
645 | return -EINVAL; | |
646 | ||
647 | if (of_property_read_u32(pmic_np, | |
648 | "s5m8767,pmic-buck-default-dvs-idx", | |
649 | &pdata->buck_default_idx)) { | |
650 | pdata->buck_default_idx = 0; | |
651 | } else { | |
652 | if (pdata->buck_default_idx >= 8) { | |
653 | pdata->buck_default_idx = 0; | |
654 | dev_info(iodev->dev, | |
655 | "invalid value for default dvs index, use 0\n"); | |
656 | } | |
657 | } | |
26aec009 ADK |
658 | } |
659 | ||
660 | ret = s5m8767_pmic_dt_parse_ds_gpio(iodev, pdata, pmic_np); | |
661 | if (ret) | |
662 | return -EINVAL; | |
663 | ||
033054e8 CC |
664 | if (of_get_property(pmic_np, "s5m8767,pmic-buck2-ramp-enable", NULL)) |
665 | pdata->buck2_ramp_enable = true; | |
26aec009 | 666 | |
033054e8 CC |
667 | if (of_get_property(pmic_np, "s5m8767,pmic-buck3-ramp-enable", NULL)) |
668 | pdata->buck3_ramp_enable = true; | |
26aec009 | 669 | |
033054e8 CC |
670 | if (of_get_property(pmic_np, "s5m8767,pmic-buck4-ramp-enable", NULL)) |
671 | pdata->buck4_ramp_enable = true; | |
672 | ||
673 | if (pdata->buck2_ramp_enable || pdata->buck3_ramp_enable | |
674 | || pdata->buck4_ramp_enable) { | |
675 | if (of_property_read_u32(pmic_np, "s5m8767,pmic-buck-ramp-delay", | |
676 | &pdata->buck_ramp_delay)) | |
677 | pdata->buck_ramp_delay = 0; | |
26aec009 ADK |
678 | } |
679 | ||
680 | return 0; | |
681 | } | |
682 | #else | |
cbb0ed49 | 683 | static int s5m8767_pmic_dt_parse_pdata(struct platform_device *pdev, |
26aec009 ADK |
684 | struct sec_platform_data *pdata) |
685 | { | |
686 | return 0; | |
687 | } | |
688 | #endif /* CONFIG_OF */ | |
689 | ||
a5023574 | 690 | static int s5m8767_pmic_probe(struct platform_device *pdev) |
9767ec7f | 691 | { |
63063bfb | 692 | struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent); |
26aec009 | 693 | struct sec_platform_data *pdata = iodev->pdata; |
c172708d | 694 | struct regulator_config config = { }; |
9767ec7f | 695 | struct s5m8767_info *s5m8767; |
0a3ade7e | 696 | int i, ret, buck_init; |
9767ec7f | 697 | |
e81d7bc8 AL |
698 | if (!pdata) { |
699 | dev_err(pdev->dev.parent, "Platform data not supplied\n"); | |
700 | return -ENODEV; | |
701 | } | |
702 | ||
26aec009 | 703 | if (iodev->dev->of_node) { |
cbb0ed49 | 704 | ret = s5m8767_pmic_dt_parse_pdata(pdev, pdata); |
26aec009 ADK |
705 | if (ret) |
706 | return ret; | |
707 | } | |
708 | ||
6c4efe24 AL |
709 | if (pdata->buck2_gpiodvs) { |
710 | if (pdata->buck3_gpiodvs || pdata->buck4_gpiodvs) { | |
711 | dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n"); | |
712 | return -EINVAL; | |
713 | } | |
714 | } | |
715 | ||
716 | if (pdata->buck3_gpiodvs) { | |
717 | if (pdata->buck2_gpiodvs || pdata->buck4_gpiodvs) { | |
718 | dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n"); | |
719 | return -EINVAL; | |
720 | } | |
721 | } | |
722 | ||
723 | if (pdata->buck4_gpiodvs) { | |
724 | if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs) { | |
725 | dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n"); | |
726 | return -EINVAL; | |
727 | } | |
728 | } | |
729 | ||
9767ec7f SK |
730 | s5m8767 = devm_kzalloc(&pdev->dev, sizeof(struct s5m8767_info), |
731 | GFP_KERNEL); | |
732 | if (!s5m8767) | |
733 | return -ENOMEM; | |
734 | ||
9767ec7f SK |
735 | s5m8767->dev = &pdev->dev; |
736 | s5m8767->iodev = iodev; | |
9bb096ff | 737 | s5m8767->num_regulators = pdata->num_regulators; |
9767ec7f | 738 | platform_set_drvdata(pdev, s5m8767); |
9767ec7f SK |
739 | |
740 | s5m8767->buck_gpioindex = pdata->buck_default_idx; | |
741 | s5m8767->buck2_gpiodvs = pdata->buck2_gpiodvs; | |
742 | s5m8767->buck3_gpiodvs = pdata->buck3_gpiodvs; | |
743 | s5m8767->buck4_gpiodvs = pdata->buck4_gpiodvs; | |
744 | s5m8767->buck_gpios[0] = pdata->buck_gpios[0]; | |
745 | s5m8767->buck_gpios[1] = pdata->buck_gpios[1]; | |
746 | s5m8767->buck_gpios[2] = pdata->buck_gpios[2]; | |
c848bc85 SK |
747 | s5m8767->buck_ds[0] = pdata->buck_ds[0]; |
748 | s5m8767->buck_ds[1] = pdata->buck_ds[1]; | |
749 | s5m8767->buck_ds[2] = pdata->buck_ds[2]; | |
750 | ||
9767ec7f SK |
751 | s5m8767->ramp_delay = pdata->buck_ramp_delay; |
752 | s5m8767->buck2_ramp = pdata->buck2_ramp_enable; | |
753 | s5m8767->buck3_ramp = pdata->buck3_ramp_enable; | |
754 | s5m8767->buck4_ramp = pdata->buck4_ramp_enable; | |
7e44bb83 | 755 | s5m8767->opmode = pdata->opmode; |
9767ec7f | 756 | |
c848bc85 | 757 | buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2, |
854f73ec | 758 | pdata->buck2_init); |
c848bc85 | 759 | |
d13733f4 KK |
760 | regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK2DVS2, |
761 | buck_init); | |
c848bc85 SK |
762 | |
763 | buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2, | |
854f73ec | 764 | pdata->buck3_init); |
c848bc85 | 765 | |
d13733f4 KK |
766 | regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK3DVS2, |
767 | buck_init); | |
c848bc85 SK |
768 | |
769 | buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2, | |
854f73ec | 770 | pdata->buck4_init); |
c848bc85 | 771 | |
d13733f4 KK |
772 | regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK4DVS2, |
773 | buck_init); | |
c848bc85 | 774 | |
9767ec7f SK |
775 | for (i = 0; i < 8; i++) { |
776 | if (s5m8767->buck2_gpiodvs) { | |
777 | s5m8767->buck2_vol[i] = | |
5b5e977c | 778 | s5m8767_convert_voltage_to_sel( |
9767ec7f | 779 | &buck_voltage_val2, |
854f73ec | 780 | pdata->buck2_voltage[i]); |
9767ec7f SK |
781 | } |
782 | ||
783 | if (s5m8767->buck3_gpiodvs) { | |
784 | s5m8767->buck3_vol[i] = | |
5b5e977c | 785 | s5m8767_convert_voltage_to_sel( |
9767ec7f | 786 | &buck_voltage_val2, |
854f73ec | 787 | pdata->buck3_voltage[i]); |
9767ec7f SK |
788 | } |
789 | ||
790 | if (s5m8767->buck4_gpiodvs) { | |
791 | s5m8767->buck4_vol[i] = | |
5b5e977c | 792 | s5m8767_convert_voltage_to_sel( |
9767ec7f | 793 | &buck_voltage_val2, |
854f73ec | 794 | pdata->buck4_voltage[i]); |
9767ec7f SK |
795 | } |
796 | } | |
797 | ||
76c854d1 ADK |
798 | if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs || |
799 | pdata->buck4_gpiodvs) { | |
800 | ||
801 | if (!gpio_is_valid(pdata->buck_gpios[0]) || | |
802 | !gpio_is_valid(pdata->buck_gpios[1]) || | |
803 | !gpio_is_valid(pdata->buck_gpios[2])) { | |
804 | dev_err(&pdev->dev, "GPIO NOT VALID\n"); | |
805 | return -EINVAL; | |
806 | } | |
807 | ||
5febb3c9 AL |
808 | ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[0], |
809 | "S5M8767 SET1"); | |
810 | if (ret) | |
811 | return ret; | |
812 | ||
813 | ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[1], | |
814 | "S5M8767 SET2"); | |
815 | if (ret) | |
816 | return ret; | |
817 | ||
818 | ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[2], | |
819 | "S5M8767 SET3"); | |
820 | if (ret) | |
821 | return ret; | |
822 | ||
c848bc85 SK |
823 | /* SET1 GPIO */ |
824 | gpio_direction_output(pdata->buck_gpios[0], | |
825 | (s5m8767->buck_gpioindex >> 2) & 0x1); | |
826 | /* SET2 GPIO */ | |
827 | gpio_direction_output(pdata->buck_gpios[1], | |
828 | (s5m8767->buck_gpioindex >> 1) & 0x1); | |
829 | /* SET3 GPIO */ | |
830 | gpio_direction_output(pdata->buck_gpios[2], | |
831 | (s5m8767->buck_gpioindex >> 0) & 0x1); | |
9767ec7f SK |
832 | } |
833 | ||
5febb3c9 AL |
834 | ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[0], "S5M8767 DS2"); |
835 | if (ret) | |
836 | return ret; | |
c848bc85 | 837 | |
5febb3c9 AL |
838 | ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[1], "S5M8767 DS3"); |
839 | if (ret) | |
840 | return ret; | |
c848bc85 | 841 | |
5febb3c9 AL |
842 | ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[2], "S5M8767 DS4"); |
843 | if (ret) | |
844 | return ret; | |
c848bc85 SK |
845 | |
846 | /* DS2 GPIO */ | |
847 | gpio_direction_output(pdata->buck_ds[0], 0x0); | |
848 | /* DS3 GPIO */ | |
849 | gpio_direction_output(pdata->buck_ds[1], 0x0); | |
850 | /* DS4 GPIO */ | |
851 | gpio_direction_output(pdata->buck_ds[2], 0x0); | |
852 | ||
853 | if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs || | |
854 | pdata->buck4_gpiodvs) { | |
d13733f4 KK |
855 | regmap_update_bits(s5m8767->iodev->regmap_pmic, |
856 | S5M8767_REG_BUCK2CTRL, 1 << 1, | |
857 | (pdata->buck2_gpiodvs) ? (1 << 1) : (0 << 1)); | |
858 | regmap_update_bits(s5m8767->iodev->regmap_pmic, | |
859 | S5M8767_REG_BUCK3CTRL, 1 << 1, | |
860 | (pdata->buck3_gpiodvs) ? (1 << 1) : (0 << 1)); | |
861 | regmap_update_bits(s5m8767->iodev->regmap_pmic, | |
862 | S5M8767_REG_BUCK4CTRL, 1 << 1, | |
863 | (pdata->buck4_gpiodvs) ? (1 << 1) : (0 << 1)); | |
c848bc85 | 864 | } |
9767ec7f SK |
865 | |
866 | /* Initialize GPIO DVS registers */ | |
867 | for (i = 0; i < 8; i++) { | |
868 | if (s5m8767->buck2_gpiodvs) { | |
d13733f4 KK |
869 | regmap_write(s5m8767->iodev->regmap_pmic, |
870 | S5M8767_REG_BUCK2DVS1 + i, | |
871 | s5m8767->buck2_vol[i]); | |
9767ec7f SK |
872 | } |
873 | ||
874 | if (s5m8767->buck3_gpiodvs) { | |
d13733f4 KK |
875 | regmap_write(s5m8767->iodev->regmap_pmic, |
876 | S5M8767_REG_BUCK3DVS1 + i, | |
877 | s5m8767->buck3_vol[i]); | |
9767ec7f SK |
878 | } |
879 | ||
880 | if (s5m8767->buck4_gpiodvs) { | |
d13733f4 KK |
881 | regmap_write(s5m8767->iodev->regmap_pmic, |
882 | S5M8767_REG_BUCK4DVS1 + i, | |
883 | s5m8767->buck4_vol[i]); | |
9767ec7f SK |
884 | } |
885 | } | |
9767ec7f SK |
886 | |
887 | if (s5m8767->buck2_ramp) | |
d13733f4 KK |
888 | regmap_update_bits(s5m8767->iodev->regmap_pmic, |
889 | S5M8767_REG_DVSRAMP, 0x08, 0x08); | |
9767ec7f SK |
890 | |
891 | if (s5m8767->buck3_ramp) | |
d13733f4 KK |
892 | regmap_update_bits(s5m8767->iodev->regmap_pmic, |
893 | S5M8767_REG_DVSRAMP, 0x04, 0x04); | |
9767ec7f SK |
894 | |
895 | if (s5m8767->buck4_ramp) | |
d13733f4 KK |
896 | regmap_update_bits(s5m8767->iodev->regmap_pmic, |
897 | S5M8767_REG_DVSRAMP, 0x02, 0x02); | |
9767ec7f SK |
898 | |
899 | if (s5m8767->buck2_ramp || s5m8767->buck3_ramp | |
900 | || s5m8767->buck4_ramp) { | |
f37ff6b6 | 901 | unsigned int val; |
9767ec7f | 902 | switch (s5m8767->ramp_delay) { |
1af142c6 | 903 | case 5: |
f37ff6b6 | 904 | val = S5M8767_DVS_BUCK_RAMP_5; |
1af142c6 SK |
905 | break; |
906 | case 10: | |
f37ff6b6 | 907 | val = S5M8767_DVS_BUCK_RAMP_10; |
047ec220 | 908 | break; |
9767ec7f | 909 | case 25: |
f37ff6b6 | 910 | val = S5M8767_DVS_BUCK_RAMP_25; |
047ec220 | 911 | break; |
9767ec7f | 912 | case 50: |
f37ff6b6 | 913 | val = S5M8767_DVS_BUCK_RAMP_50; |
047ec220 | 914 | break; |
9767ec7f | 915 | case 100: |
f37ff6b6 | 916 | val = S5M8767_DVS_BUCK_RAMP_100; |
047ec220 | 917 | break; |
9767ec7f | 918 | default: |
f37ff6b6 | 919 | val = S5M8767_DVS_BUCK_RAMP_10; |
9767ec7f | 920 | } |
d13733f4 KK |
921 | regmap_update_bits(s5m8767->iodev->regmap_pmic, |
922 | S5M8767_REG_DVSRAMP, | |
923 | S5M8767_DVS_BUCK_RAMP_MASK, | |
924 | val << S5M8767_DVS_BUCK_RAMP_SHIFT); | |
9767ec7f SK |
925 | } |
926 | ||
927 | for (i = 0; i < pdata->num_regulators; i++) { | |
63063bfb | 928 | const struct sec_voltage_desc *desc; |
9767ec7f | 929 | int id = pdata->regulators[i].id; |
9c4c6055 | 930 | int enable_reg, enable_val; |
e80fb721 | 931 | struct regulator_dev *rdev; |
9767ec7f SK |
932 | |
933 | desc = reg_voltage_map[id]; | |
e2eb169b | 934 | if (desc) { |
9767ec7f SK |
935 | regulators[id].n_voltages = |
936 | (desc->max - desc->min) / desc->step + 1; | |
e2eb169b AL |
937 | regulators[id].min_uV = desc->min; |
938 | regulators[id].uV_step = desc->step; | |
31a932e1 AL |
939 | regulators[id].vsel_reg = |
940 | s5m8767_get_vsel_reg(id, s5m8767); | |
941 | if (id < S5M8767_BUCK1) | |
942 | regulators[id].vsel_mask = 0x3f; | |
943 | else | |
944 | regulators[id].vsel_mask = 0xff; | |
9c4c6055 | 945 | |
e07ff943 | 946 | ret = s5m8767_get_register(s5m8767, id, &enable_reg, |
9c4c6055 | 947 | &enable_val); |
e07ff943 AB |
948 | if (ret) { |
949 | dev_err(s5m8767->dev, "error reading registers\n"); | |
950 | return ret; | |
951 | } | |
9c4c6055 AL |
952 | regulators[id].enable_reg = enable_reg; |
953 | regulators[id].enable_mask = S5M8767_ENCTRL_MASK; | |
954 | regulators[id].enable_val = enable_val; | |
e2eb169b | 955 | } |
9767ec7f | 956 | |
c172708d MB |
957 | config.dev = s5m8767->dev; |
958 | config.init_data = pdata->regulators[i].initdata; | |
959 | config.driver_data = s5m8767; | |
3e1e4a5f | 960 | config.regmap = iodev->regmap_pmic; |
26aec009 | 961 | config.of_node = pdata->regulators[i].reg_node; |
9ae5cc75 | 962 | config.ena_gpiod = NULL; |
1f5163fc LW |
963 | if (pdata->regulators[i].ext_control_gpiod) { |
964 | /* Assigns config.ena_gpiod */ | |
ee1e0994 KK |
965 | s5m8767_regulator_config_ext_control(s5m8767, |
966 | &pdata->regulators[i], &config); | |
c172708d | 967 | |
1f5163fc LW |
968 | /* |
969 | * Hand the GPIO descriptor management over to the | |
970 | * regulator core, remove it from devres management. | |
971 | */ | |
972 | devm_gpiod_unhinge(s5m8767->dev, config.ena_gpiod); | |
973 | } | |
e80fb721 | 974 | rdev = devm_regulator_register(&pdev->dev, ®ulators[id], |
f0db475d | 975 | &config); |
e80fb721 KK |
976 | if (IS_ERR(rdev)) { |
977 | ret = PTR_ERR(rdev); | |
9767ec7f SK |
978 | dev_err(s5m8767->dev, "regulator init failed for %d\n", |
979 | id); | |
f0db475d | 980 | return ret; |
9767ec7f | 981 | } |
ee1e0994 | 982 | |
9ae5cc75 | 983 | if (pdata->regulators[i].ext_control_gpiod) { |
e80fb721 | 984 | ret = s5m8767_enable_ext_control(s5m8767, rdev); |
ee1e0994 KK |
985 | if (ret < 0) { |
986 | dev_err(s5m8767->dev, | |
987 | "failed to enable gpio control over %s: %d\n", | |
e80fb721 | 988 | rdev->desc->name, ret); |
ee1e0994 KK |
989 | return ret; |
990 | } | |
991 | } | |
9767ec7f SK |
992 | } |
993 | ||
9767ec7f SK |
994 | return 0; |
995 | } | |
996 | ||
997 | static const struct platform_device_id s5m8767_pmic_id[] = { | |
998 | { "s5m8767-pmic", 0}, | |
999 | { }, | |
1000 | }; | |
1001 | MODULE_DEVICE_TABLE(platform, s5m8767_pmic_id); | |
1002 | ||
1003 | static struct platform_driver s5m8767_pmic_driver = { | |
1004 | .driver = { | |
1005 | .name = "s5m8767-pmic", | |
9767ec7f SK |
1006 | }, |
1007 | .probe = s5m8767_pmic_probe, | |
9767ec7f SK |
1008 | .id_table = s5m8767_pmic_id, |
1009 | }; | |
8d23b0b8 | 1010 | module_platform_driver(s5m8767_pmic_driver); |
9767ec7f SK |
1011 | |
1012 | /* Module information */ | |
1013 | MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>"); | |
fc2b10d1 | 1014 | MODULE_DESCRIPTION("Samsung S5M8767 Regulator Driver"); |
9767ec7f | 1015 | MODULE_LICENSE("GPL"); |