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rtc: s5m: enable IRQ wake during suspend
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1/*
2 * s5m8767.c
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14#include <linux/bug.h>
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15#include <linux/err.h>
16#include <linux/gpio.h>
26aec009 17#include <linux/of_gpio.h>
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18#include <linux/slab.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/driver.h>
22#include <linux/regulator/machine.h>
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23#include <linux/mfd/samsung/core.h>
24#include <linux/mfd/samsung/s5m8767.h>
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25#include <linux/regulator/of_regulator.h>
26
27#define S5M8767_OPMODE_NORMAL_MODE 0x1
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28
29struct s5m8767_info {
30 struct device *dev;
63063bfb 31 struct sec_pmic_dev *iodev;
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32 int num_regulators;
33 struct regulator_dev **rdev;
63063bfb 34 struct sec_opmode_data *opmode;
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35
36 int ramp_delay;
37 bool buck2_ramp;
38 bool buck3_ramp;
39 bool buck4_ramp;
40
41 bool buck2_gpiodvs;
42 bool buck3_gpiodvs;
43 bool buck4_gpiodvs;
44 u8 buck2_vol[8];
45 u8 buck3_vol[8];
46 u8 buck4_vol[8];
47 int buck_gpios[3];
c848bc85 48 int buck_ds[3];
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49 int buck_gpioindex;
50};
51
63063bfb 52struct sec_voltage_desc {
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53 int max;
54 int min;
55 int step;
56};
57
63063bfb 58static const struct sec_voltage_desc buck_voltage_val1 = {
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59 .max = 2225000,
60 .min = 650000,
61 .step = 6250,
62};
63
63063bfb 64static const struct sec_voltage_desc buck_voltage_val2 = {
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65 .max = 1600000,
66 .min = 600000,
67 .step = 6250,
68};
69
63063bfb 70static const struct sec_voltage_desc buck_voltage_val3 = {
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71 .max = 3000000,
72 .min = 750000,
73 .step = 12500,
74};
75
63063bfb 76static const struct sec_voltage_desc ldo_voltage_val1 = {
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77 .max = 3950000,
78 .min = 800000,
79 .step = 50000,
80};
81
63063bfb 82static const struct sec_voltage_desc ldo_voltage_val2 = {
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83 .max = 2375000,
84 .min = 800000,
85 .step = 25000,
86};
87
63063bfb 88static const struct sec_voltage_desc *reg_voltage_map[] = {
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89 [S5M8767_LDO1] = &ldo_voltage_val2,
90 [S5M8767_LDO2] = &ldo_voltage_val2,
91 [S5M8767_LDO3] = &ldo_voltage_val1,
92 [S5M8767_LDO4] = &ldo_voltage_val1,
93 [S5M8767_LDO5] = &ldo_voltage_val1,
94 [S5M8767_LDO6] = &ldo_voltage_val2,
95 [S5M8767_LDO7] = &ldo_voltage_val2,
96 [S5M8767_LDO8] = &ldo_voltage_val2,
97 [S5M8767_LDO9] = &ldo_voltage_val1,
98 [S5M8767_LDO10] = &ldo_voltage_val1,
99 [S5M8767_LDO11] = &ldo_voltage_val1,
100 [S5M8767_LDO12] = &ldo_voltage_val1,
101 [S5M8767_LDO13] = &ldo_voltage_val1,
102 [S5M8767_LDO14] = &ldo_voltage_val1,
103 [S5M8767_LDO15] = &ldo_voltage_val2,
104 [S5M8767_LDO16] = &ldo_voltage_val1,
105 [S5M8767_LDO17] = &ldo_voltage_val1,
106 [S5M8767_LDO18] = &ldo_voltage_val1,
107 [S5M8767_LDO19] = &ldo_voltage_val1,
108 [S5M8767_LDO20] = &ldo_voltage_val1,
109 [S5M8767_LDO21] = &ldo_voltage_val1,
110 [S5M8767_LDO22] = &ldo_voltage_val1,
111 [S5M8767_LDO23] = &ldo_voltage_val1,
112 [S5M8767_LDO24] = &ldo_voltage_val1,
113 [S5M8767_LDO25] = &ldo_voltage_val1,
114 [S5M8767_LDO26] = &ldo_voltage_val1,
115 [S5M8767_LDO27] = &ldo_voltage_val1,
116 [S5M8767_LDO28] = &ldo_voltage_val1,
117 [S5M8767_BUCK1] = &buck_voltage_val1,
118 [S5M8767_BUCK2] = &buck_voltage_val2,
119 [S5M8767_BUCK3] = &buck_voltage_val2,
120 [S5M8767_BUCK4] = &buck_voltage_val2,
121 [S5M8767_BUCK5] = &buck_voltage_val1,
122 [S5M8767_BUCK6] = &buck_voltage_val1,
123 [S5M8767_BUCK7] = NULL,
124 [S5M8767_BUCK8] = NULL,
125 [S5M8767_BUCK9] = &buck_voltage_val3,
126};
127
5ceba7ba 128static unsigned int s5m8767_opmode_reg[][4] = {
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129 /* {OFF, ON, LOWPOWER, SUSPEND} */
130 /* LDO1 ... LDO28 */
131 {0x0, 0x3, 0x2, 0x1}, /* LDO1 */
132 {0x0, 0x3, 0x2, 0x1},
133 {0x0, 0x3, 0x2, 0x1},
134 {0x0, 0x0, 0x0, 0x0},
135 {0x0, 0x3, 0x2, 0x1}, /* LDO5 */
136 {0x0, 0x3, 0x2, 0x1},
137 {0x0, 0x3, 0x2, 0x1},
138 {0x0, 0x3, 0x2, 0x1},
139 {0x0, 0x3, 0x2, 0x1},
140 {0x0, 0x3, 0x2, 0x1}, /* LDO10 */
141 {0x0, 0x3, 0x2, 0x1},
142 {0x0, 0x3, 0x2, 0x1},
143 {0x0, 0x3, 0x2, 0x1},
144 {0x0, 0x3, 0x2, 0x1},
145 {0x0, 0x3, 0x2, 0x1}, /* LDO15 */
146 {0x0, 0x3, 0x2, 0x1},
147 {0x0, 0x3, 0x2, 0x1},
148 {0x0, 0x0, 0x0, 0x0},
149 {0x0, 0x3, 0x2, 0x1},
150 {0x0, 0x3, 0x2, 0x1}, /* LDO20 */
151 {0x0, 0x3, 0x2, 0x1},
152 {0x0, 0x3, 0x2, 0x1},
153 {0x0, 0x0, 0x0, 0x0},
154 {0x0, 0x3, 0x2, 0x1},
155 {0x0, 0x3, 0x2, 0x1}, /* LDO25 */
156 {0x0, 0x3, 0x2, 0x1},
157 {0x0, 0x3, 0x2, 0x1},
158 {0x0, 0x3, 0x2, 0x1}, /* LDO28 */
159
160 /* BUCK1 ... BUCK9 */
161 {0x0, 0x3, 0x1, 0x1}, /* BUCK1 */
162 {0x0, 0x3, 0x1, 0x1},
163 {0x0, 0x3, 0x1, 0x1},
164 {0x0, 0x3, 0x1, 0x1},
165 {0x0, 0x3, 0x2, 0x1}, /* BUCK5 */
166 {0x0, 0x3, 0x1, 0x1},
167 {0x0, 0x3, 0x1, 0x1},
168 {0x0, 0x3, 0x1, 0x1},
169 {0x0, 0x3, 0x1, 0x1}, /* BUCK9 */
170};
171
172static int s5m8767_get_register(struct regulator_dev *rdev, int *reg,
173 int *enable_ctrl)
9767ec7f 174{
9bb096ff 175 int i, reg_id = rdev_get_id(rdev);
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176 unsigned int mode;
177 struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
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178
179 switch (reg_id) {
180 case S5M8767_LDO1 ... S5M8767_LDO2:
181 *reg = S5M8767_REG_LDO1CTRL + (reg_id - S5M8767_LDO1);
182 break;
183 case S5M8767_LDO3 ... S5M8767_LDO28:
184 *reg = S5M8767_REG_LDO3CTRL + (reg_id - S5M8767_LDO3);
185 break;
186 case S5M8767_BUCK1:
187 *reg = S5M8767_REG_BUCK1CTRL1;
188 break;
189 case S5M8767_BUCK2 ... S5M8767_BUCK4:
190 *reg = S5M8767_REG_BUCK2CTRL + (reg_id - S5M8767_BUCK2) * 9;
191 break;
192 case S5M8767_BUCK5:
193 *reg = S5M8767_REG_BUCK5CTRL1;
194 break;
195 case S5M8767_BUCK6 ... S5M8767_BUCK9:
196 *reg = S5M8767_REG_BUCK6CTRL1 + (reg_id - S5M8767_BUCK6) * 2;
197 break;
198 default:
199 return -EINVAL;
200 }
201
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ADK
202 for (i = 0; i < s5m8767->num_regulators; i++) {
203 if (s5m8767->opmode[i].id == reg_id) {
204 mode = s5m8767->opmode[i].mode;
205 break;
206 }
207 }
208
209 if (i < s5m8767->num_regulators)
210 *enable_ctrl =
211 s5m8767_opmode_reg[reg_id][mode] << S5M8767_ENCTRL_SHIFT;
212
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213 return 0;
214}
215
216static int s5m8767_reg_is_enabled(struct regulator_dev *rdev)
217{
218 struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
219 int ret, reg;
7e44bb83 220 int mask = 0xc0, enable_ctrl;
3ef30398 221 unsigned int val;
9767ec7f 222
7e44bb83 223 ret = s5m8767_get_register(rdev, &reg, &enable_ctrl);
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224 if (ret == -EINVAL)
225 return 1;
226 else if (ret)
227 return ret;
228
63063bfb 229 ret = sec_reg_read(s5m8767->iodev, reg, &val);
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230 if (ret)
231 return ret;
232
7e44bb83 233 return (val & mask) == enable_ctrl;
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234}
235
236static int s5m8767_reg_enable(struct regulator_dev *rdev)
237{
238 struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
239 int ret, reg;
7e44bb83 240 int mask = 0xc0, enable_ctrl;
9767ec7f 241
7e44bb83 242 ret = s5m8767_get_register(rdev, &reg, &enable_ctrl);
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243 if (ret)
244 return ret;
245
63063bfb 246 return sec_reg_update(s5m8767->iodev, reg, enable_ctrl, mask);
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247}
248
249static int s5m8767_reg_disable(struct regulator_dev *rdev)
250{
251 struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
252 int ret, reg;
7e44bb83 253 int mask = 0xc0, enable_ctrl;
9767ec7f 254
7e44bb83 255 ret = s5m8767_get_register(rdev, &reg, &enable_ctrl);
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256 if (ret)
257 return ret;
258
63063bfb 259 return sec_reg_update(s5m8767->iodev, reg, ~mask, mask);
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260}
261
31a932e1 262static int s5m8767_get_vsel_reg(int reg_id, struct s5m8767_info *s5m8767)
9767ec7f 263{
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264 int reg;
265
266 switch (reg_id) {
267 case S5M8767_LDO1 ... S5M8767_LDO2:
268 reg = S5M8767_REG_LDO1CTRL + (reg_id - S5M8767_LDO1);
269 break;
270 case S5M8767_LDO3 ... S5M8767_LDO28:
271 reg = S5M8767_REG_LDO3CTRL + (reg_id - S5M8767_LDO3);
272 break;
273 case S5M8767_BUCK1:
274 reg = S5M8767_REG_BUCK1CTRL2;
275 break;
276 case S5M8767_BUCK2:
da130ab2 277 reg = S5M8767_REG_BUCK2DVS1;
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278 if (s5m8767->buck2_gpiodvs)
279 reg += s5m8767->buck_gpioindex;
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280 break;
281 case S5M8767_BUCK3:
da130ab2 282 reg = S5M8767_REG_BUCK3DVS1;
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283 if (s5m8767->buck3_gpiodvs)
284 reg += s5m8767->buck_gpioindex;
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285 break;
286 case S5M8767_BUCK4:
da130ab2 287 reg = S5M8767_REG_BUCK4DVS1;
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288 if (s5m8767->buck4_gpiodvs)
289 reg += s5m8767->buck_gpioindex;
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290 break;
291 case S5M8767_BUCK5:
292 reg = S5M8767_REG_BUCK5CTRL2;
293 break;
294 case S5M8767_BUCK6 ... S5M8767_BUCK9:
295 reg = S5M8767_REG_BUCK6CTRL2 + (reg_id - S5M8767_BUCK6) * 2;
296 break;
297 default:
298 return -EINVAL;
299 }
300
31a932e1 301 return reg;
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302}
303
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304static int s5m8767_convert_voltage_to_sel(const struct sec_voltage_desc *desc,
305 int min_vol)
9767ec7f 306{
5b5e977c 307 int selector = 0;
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308
309 if (desc == NULL)
310 return -EINVAL;
311
854f73ec 312 if (min_vol > desc->max)
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313 return -EINVAL;
314
94e85a3c
AL
315 if (min_vol < desc->min)
316 min_vol = desc->min;
317
318 selector = DIV_ROUND_UP(min_vol - desc->min, desc->step);
9767ec7f 319
854f73ec 320 if (desc->min + desc->step * selector > desc->max)
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321 return -EINVAL;
322
5b5e977c 323 return selector;
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324}
325
df2643cf 326static inline int s5m8767_set_high(struct s5m8767_info *s5m8767)
321d2aba
AL
327{
328 int temp_index = s5m8767->buck_gpioindex;
329
330 gpio_set_value(s5m8767->buck_gpios[0], (temp_index >> 2) & 0x1);
331 gpio_set_value(s5m8767->buck_gpios[1], (temp_index >> 1) & 0x1);
332 gpio_set_value(s5m8767->buck_gpios[2], temp_index & 0x1);
df2643cf
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333
334 return 0;
321d2aba
AL
335}
336
df2643cf 337static inline int s5m8767_set_low(struct s5m8767_info *s5m8767)
321d2aba
AL
338{
339 int temp_index = s5m8767->buck_gpioindex;
340
341 gpio_set_value(s5m8767->buck_gpios[2], temp_index & 0x1);
342 gpio_set_value(s5m8767->buck_gpios[1], (temp_index >> 1) & 0x1);
343 gpio_set_value(s5m8767->buck_gpios[0], (temp_index >> 2) & 0x1);
df2643cf
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344
345 return 0;
321d2aba
AL
346}
347
df2643cf
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348static int s5m8767_set_voltage_sel(struct regulator_dev *rdev,
349 unsigned selector)
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350{
351 struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
20a14b84 352 int reg_id = rdev_get_id(rdev);
31a932e1 353 int old_index, index = 0;
321d2aba 354 u8 *buck234_vol = NULL;
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355
356 switch (reg_id) {
357 case S5M8767_LDO1 ... S5M8767_LDO28:
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358 break;
359 case S5M8767_BUCK1 ... S5M8767_BUCK6:
321d2aba
AL
360 if (reg_id == S5M8767_BUCK2 && s5m8767->buck2_gpiodvs)
361 buck234_vol = &s5m8767->buck2_vol[0];
362 else if (reg_id == S5M8767_BUCK3 && s5m8767->buck3_gpiodvs)
363 buck234_vol = &s5m8767->buck3_vol[0];
364 else if (reg_id == S5M8767_BUCK4 && s5m8767->buck4_gpiodvs)
365 buck234_vol = &s5m8767->buck4_vol[0];
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366 break;
367 case S5M8767_BUCK7 ... S5M8767_BUCK8:
368 return -EINVAL;
369 case S5M8767_BUCK9:
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370 break;
371 default:
372 return -EINVAL;
373 }
374
321d2aba
AL
375 /* buck234_vol != NULL means to control buck234 voltage via DVS GPIO */
376 if (buck234_vol) {
df2643cf 377 while (*buck234_vol != selector) {
321d2aba
AL
378 buck234_vol++;
379 index++;
380 }
381 old_index = s5m8767->buck_gpioindex;
382 s5m8767->buck_gpioindex = index;
383
384 if (index > old_index)
df2643cf 385 return s5m8767_set_high(s5m8767);
321d2aba 386 else
df2643cf 387 return s5m8767_set_low(s5m8767);
321d2aba 388 } else {
31a932e1 389 return regulator_set_voltage_sel_regmap(rdev, selector);
321d2aba 390 }
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391}
392
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393static int s5m8767_set_voltage_time_sel(struct regulator_dev *rdev,
394 unsigned int old_sel,
395 unsigned int new_sel)
396{
397 struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
63063bfb 398 const struct sec_voltage_desc *desc;
20a14b84 399 int reg_id = rdev_get_id(rdev);
9767ec7f 400
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401 desc = reg_voltage_map[reg_id];
402
9d88fc0b 403 if ((old_sel < new_sel) && s5m8767->ramp_delay)
89e0f0e4 404 return DIV_ROUND_UP(desc->step * (new_sel - old_sel),
0f8b9c77 405 s5m8767->ramp_delay * 1000);
89e0f0e4 406 return 0;
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407}
408
d35aad0c 409static struct regulator_ops s5m8767_ops = {
e2eb169b 410 .list_voltage = regulator_list_voltage_linear,
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411 .is_enabled = s5m8767_reg_is_enabled,
412 .enable = s5m8767_reg_enable,
413 .disable = s5m8767_reg_disable,
31a932e1 414 .get_voltage_sel = regulator_get_voltage_sel_regmap,
df2643cf 415 .set_voltage_sel = s5m8767_set_voltage_sel,
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416 .set_voltage_time_sel = s5m8767_set_voltage_time_sel,
417};
418
e2eb169b
AL
419static struct regulator_ops s5m8767_buck78_ops = {
420 .is_enabled = s5m8767_reg_is_enabled,
421 .enable = s5m8767_reg_enable,
422 .disable = s5m8767_reg_disable,
423};
424
65896e73
AL
425#define s5m8767_regulator_desc(_name) { \
426 .name = #_name, \
427 .id = S5M8767_##_name, \
428 .ops = &s5m8767_ops, \
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429 .type = REGULATOR_VOLTAGE, \
430 .owner = THIS_MODULE, \
431}
432
e2eb169b
AL
433#define s5m8767_regulator_buck78_desc(_name) { \
434 .name = #_name, \
435 .id = S5M8767_##_name, \
436 .ops = &s5m8767_buck78_ops, \
437 .type = REGULATOR_VOLTAGE, \
438 .owner = THIS_MODULE, \
439}
440
9767ec7f 441static struct regulator_desc regulators[] = {
65896e73
AL
442 s5m8767_regulator_desc(LDO1),
443 s5m8767_regulator_desc(LDO2),
444 s5m8767_regulator_desc(LDO3),
445 s5m8767_regulator_desc(LDO4),
446 s5m8767_regulator_desc(LDO5),
447 s5m8767_regulator_desc(LDO6),
448 s5m8767_regulator_desc(LDO7),
449 s5m8767_regulator_desc(LDO8),
450 s5m8767_regulator_desc(LDO9),
451 s5m8767_regulator_desc(LDO10),
452 s5m8767_regulator_desc(LDO11),
453 s5m8767_regulator_desc(LDO12),
454 s5m8767_regulator_desc(LDO13),
455 s5m8767_regulator_desc(LDO14),
456 s5m8767_regulator_desc(LDO15),
457 s5m8767_regulator_desc(LDO16),
458 s5m8767_regulator_desc(LDO17),
459 s5m8767_regulator_desc(LDO18),
460 s5m8767_regulator_desc(LDO19),
461 s5m8767_regulator_desc(LDO20),
462 s5m8767_regulator_desc(LDO21),
463 s5m8767_regulator_desc(LDO22),
464 s5m8767_regulator_desc(LDO23),
465 s5m8767_regulator_desc(LDO24),
466 s5m8767_regulator_desc(LDO25),
467 s5m8767_regulator_desc(LDO26),
468 s5m8767_regulator_desc(LDO27),
469 s5m8767_regulator_desc(LDO28),
470 s5m8767_regulator_desc(BUCK1),
471 s5m8767_regulator_desc(BUCK2),
472 s5m8767_regulator_desc(BUCK3),
473 s5m8767_regulator_desc(BUCK4),
474 s5m8767_regulator_desc(BUCK5),
475 s5m8767_regulator_desc(BUCK6),
e2eb169b
AL
476 s5m8767_regulator_buck78_desc(BUCK7),
477 s5m8767_regulator_buck78_desc(BUCK8),
65896e73 478 s5m8767_regulator_desc(BUCK9),
9767ec7f
SK
479};
480
26aec009
ADK
481#ifdef CONFIG_OF
482static int s5m8767_pmic_dt_parse_dvs_gpio(struct sec_pmic_dev *iodev,
483 struct sec_platform_data *pdata,
484 struct device_node *pmic_np)
485{
486 int i, gpio;
487
488 for (i = 0; i < 3; i++) {
489 gpio = of_get_named_gpio(pmic_np,
490 "s5m8767,pmic-buck-dvs-gpios", i);
491 if (!gpio_is_valid(gpio)) {
492 dev_err(iodev->dev, "invalid gpio[%d]: %d\n", i, gpio);
493 return -EINVAL;
494 }
495 pdata->buck_gpios[i] = gpio;
496 }
497 return 0;
498}
499
500static int s5m8767_pmic_dt_parse_ds_gpio(struct sec_pmic_dev *iodev,
501 struct sec_platform_data *pdata,
502 struct device_node *pmic_np)
503{
504 int i, gpio;
505
506 for (i = 0; i < 3; i++) {
507 gpio = of_get_named_gpio(pmic_np,
508 "s5m8767,pmic-buck-ds-gpios", i);
509 if (!gpio_is_valid(gpio)) {
510 dev_err(iodev->dev, "invalid gpio[%d]: %d\n", i, gpio);
511 return -EINVAL;
512 }
513 pdata->buck_ds[i] = gpio;
514 }
515 return 0;
516}
517
cbb0ed49 518static int s5m8767_pmic_dt_parse_pdata(struct platform_device *pdev,
26aec009
ADK
519 struct sec_platform_data *pdata)
520{
cbb0ed49 521 struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
26aec009
ADK
522 struct device_node *pmic_np, *regulators_np, *reg_np;
523 struct sec_regulator_data *rdata;
524 struct sec_opmode_data *rmode;
04f9f068 525 unsigned int i, dvs_voltage_nr = 8, ret;
26aec009
ADK
526
527 pmic_np = iodev->dev->of_node;
528 if (!pmic_np) {
529 dev_err(iodev->dev, "could not find pmic sub-node\n");
530 return -ENODEV;
531 }
532
533 regulators_np = of_find_node_by_name(pmic_np, "regulators");
534 if (!regulators_np) {
535 dev_err(iodev->dev, "could not find regulators sub-node\n");
536 return -EINVAL;
537 }
538
539 /* count the number of regulators to be supported in pmic */
1f91b6f6 540 pdata->num_regulators = of_get_child_count(regulators_np);
26aec009 541
cbb0ed49 542 rdata = devm_kzalloc(&pdev->dev, sizeof(*rdata) *
26aec009
ADK
543 pdata->num_regulators, GFP_KERNEL);
544 if (!rdata) {
545 dev_err(iodev->dev,
546 "could not allocate memory for regulator data\n");
547 return -ENOMEM;
548 }
549
cbb0ed49 550 rmode = devm_kzalloc(&pdev->dev, sizeof(*rmode) *
26aec009 551 pdata->num_regulators, GFP_KERNEL);
720a9717 552 if (!rmode) {
26aec009
ADK
553 dev_err(iodev->dev,
554 "could not allocate memory for regulator mode\n");
555 return -ENOMEM;
556 }
557
558 pdata->regulators = rdata;
559 pdata->opmode = rmode;
560 for_each_child_of_node(regulators_np, reg_np) {
561 for (i = 0; i < ARRAY_SIZE(regulators); i++)
562 if (!of_node_cmp(reg_np->name, regulators[i].name))
563 break;
564
565 if (i == ARRAY_SIZE(regulators)) {
566 dev_warn(iodev->dev,
567 "don't know how to configure regulator %s\n",
568 reg_np->name);
569 continue;
570 }
571
572 rdata->id = i;
573 rdata->initdata = of_get_regulator_init_data(
cbb0ed49 574 &pdev->dev, reg_np);
26aec009
ADK
575 rdata->reg_node = reg_np;
576 rdata++;
577 rmode->id = i;
578 if (of_property_read_u32(reg_np, "op_mode",
579 &rmode->mode)) {
580 dev_warn(iodev->dev,
581 "no op_mode property property at %s\n",
582 reg_np->full_name);
583
584 rmode->mode = S5M8767_OPMODE_NORMAL_MODE;
585 }
586 rmode++;
587 }
588
04f9f068 589 if (of_get_property(pmic_np, "s5m8767,pmic-buck2-uses-gpio-dvs", NULL)) {
26aec009
ADK
590 pdata->buck2_gpiodvs = true;
591
04f9f068
CC
592 if (of_property_read_u32_array(pmic_np,
593 "s5m8767,pmic-buck2-dvs-voltage",
594 pdata->buck2_voltage, dvs_voltage_nr)) {
595 dev_err(iodev->dev, "buck2 voltages not specified\n");
596 return -EINVAL;
597 }
598 }
599
600 if (of_get_property(pmic_np, "s5m8767,pmic-buck3-uses-gpio-dvs", NULL)) {
26aec009
ADK
601 pdata->buck3_gpiodvs = true;
602
04f9f068
CC
603 if (of_property_read_u32_array(pmic_np,
604 "s5m8767,pmic-buck3-dvs-voltage",
605 pdata->buck3_voltage, dvs_voltage_nr)) {
606 dev_err(iodev->dev, "buck3 voltages not specified\n");
607 return -EINVAL;
608 }
609 }
610
611 if (of_get_property(pmic_np, "s5m8767,pmic-buck4-uses-gpio-dvs", NULL)) {
26aec009
ADK
612 pdata->buck4_gpiodvs = true;
613
04f9f068
CC
614 if (of_property_read_u32_array(pmic_np,
615 "s5m8767,pmic-buck4-dvs-voltage",
616 pdata->buck4_voltage, dvs_voltage_nr)) {
617 dev_err(iodev->dev, "buck4 voltages not specified\n");
618 return -EINVAL;
619 }
620 }
621
26aec009
ADK
622 if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs ||
623 pdata->buck4_gpiodvs) {
624 ret = s5m8767_pmic_dt_parse_dvs_gpio(iodev, pdata, pmic_np);
625 if (ret)
626 return -EINVAL;
627
628 if (of_property_read_u32(pmic_np,
629 "s5m8767,pmic-buck-default-dvs-idx",
630 &pdata->buck_default_idx)) {
631 pdata->buck_default_idx = 0;
632 } else {
633 if (pdata->buck_default_idx >= 8) {
634 pdata->buck_default_idx = 0;
635 dev_info(iodev->dev,
636 "invalid value for default dvs index, use 0\n");
637 }
638 }
26aec009
ADK
639 }
640
641 ret = s5m8767_pmic_dt_parse_ds_gpio(iodev, pdata, pmic_np);
642 if (ret)
643 return -EINVAL;
644
033054e8
CC
645 if (of_get_property(pmic_np, "s5m8767,pmic-buck2-ramp-enable", NULL))
646 pdata->buck2_ramp_enable = true;
26aec009 647
033054e8
CC
648 if (of_get_property(pmic_np, "s5m8767,pmic-buck3-ramp-enable", NULL))
649 pdata->buck3_ramp_enable = true;
26aec009 650
033054e8
CC
651 if (of_get_property(pmic_np, "s5m8767,pmic-buck4-ramp-enable", NULL))
652 pdata->buck4_ramp_enable = true;
653
654 if (pdata->buck2_ramp_enable || pdata->buck3_ramp_enable
655 || pdata->buck4_ramp_enable) {
656 if (of_property_read_u32(pmic_np, "s5m8767,pmic-buck-ramp-delay",
657 &pdata->buck_ramp_delay))
658 pdata->buck_ramp_delay = 0;
26aec009
ADK
659 }
660
661 return 0;
662}
663#else
cbb0ed49 664static int s5m8767_pmic_dt_parse_pdata(struct platform_device *pdev,
26aec009
ADK
665 struct sec_platform_data *pdata)
666{
667 return 0;
668}
669#endif /* CONFIG_OF */
670
a5023574 671static int s5m8767_pmic_probe(struct platform_device *pdev)
9767ec7f 672{
63063bfb 673 struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
26aec009 674 struct sec_platform_data *pdata = iodev->pdata;
c172708d 675 struct regulator_config config = { };
9767ec7f
SK
676 struct regulator_dev **rdev;
677 struct s5m8767_info *s5m8767;
c848bc85 678 int i, ret, size, buck_init;
9767ec7f 679
e81d7bc8
AL
680 if (!pdata) {
681 dev_err(pdev->dev.parent, "Platform data not supplied\n");
682 return -ENODEV;
683 }
684
26aec009 685 if (iodev->dev->of_node) {
cbb0ed49 686 ret = s5m8767_pmic_dt_parse_pdata(pdev, pdata);
26aec009
ADK
687 if (ret)
688 return ret;
689 }
690
6c4efe24
AL
691 if (pdata->buck2_gpiodvs) {
692 if (pdata->buck3_gpiodvs || pdata->buck4_gpiodvs) {
693 dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n");
694 return -EINVAL;
695 }
696 }
697
698 if (pdata->buck3_gpiodvs) {
699 if (pdata->buck2_gpiodvs || pdata->buck4_gpiodvs) {
700 dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n");
701 return -EINVAL;
702 }
703 }
704
705 if (pdata->buck4_gpiodvs) {
706 if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs) {
707 dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n");
708 return -EINVAL;
709 }
710 }
711
9767ec7f
SK
712 s5m8767 = devm_kzalloc(&pdev->dev, sizeof(struct s5m8767_info),
713 GFP_KERNEL);
714 if (!s5m8767)
715 return -ENOMEM;
716
717 size = sizeof(struct regulator_dev *) * (S5M8767_REG_MAX - 2);
718 s5m8767->rdev = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
719 if (!s5m8767->rdev)
720 return -ENOMEM;
721
722 rdev = s5m8767->rdev;
723 s5m8767->dev = &pdev->dev;
724 s5m8767->iodev = iodev;
9bb096ff 725 s5m8767->num_regulators = pdata->num_regulators;
9767ec7f 726 platform_set_drvdata(pdev, s5m8767);
9767ec7f
SK
727
728 s5m8767->buck_gpioindex = pdata->buck_default_idx;
729 s5m8767->buck2_gpiodvs = pdata->buck2_gpiodvs;
730 s5m8767->buck3_gpiodvs = pdata->buck3_gpiodvs;
731 s5m8767->buck4_gpiodvs = pdata->buck4_gpiodvs;
732 s5m8767->buck_gpios[0] = pdata->buck_gpios[0];
733 s5m8767->buck_gpios[1] = pdata->buck_gpios[1];
734 s5m8767->buck_gpios[2] = pdata->buck_gpios[2];
c848bc85
SK
735 s5m8767->buck_ds[0] = pdata->buck_ds[0];
736 s5m8767->buck_ds[1] = pdata->buck_ds[1];
737 s5m8767->buck_ds[2] = pdata->buck_ds[2];
738
9767ec7f
SK
739 s5m8767->ramp_delay = pdata->buck_ramp_delay;
740 s5m8767->buck2_ramp = pdata->buck2_ramp_enable;
741 s5m8767->buck3_ramp = pdata->buck3_ramp_enable;
742 s5m8767->buck4_ramp = pdata->buck4_ramp_enable;
7e44bb83 743 s5m8767->opmode = pdata->opmode;
9767ec7f 744
c848bc85 745 buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2,
854f73ec 746 pdata->buck2_init);
c848bc85 747
938e05bf 748 sec_reg_write(s5m8767->iodev, S5M8767_REG_BUCK2DVS2, buck_init);
c848bc85
SK
749
750 buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2,
854f73ec 751 pdata->buck3_init);
c848bc85 752
938e05bf 753 sec_reg_write(s5m8767->iodev, S5M8767_REG_BUCK3DVS2, buck_init);
c848bc85
SK
754
755 buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2,
854f73ec 756 pdata->buck4_init);
c848bc85 757
938e05bf 758 sec_reg_write(s5m8767->iodev, S5M8767_REG_BUCK4DVS2, buck_init);
c848bc85 759
9767ec7f
SK
760 for (i = 0; i < 8; i++) {
761 if (s5m8767->buck2_gpiodvs) {
762 s5m8767->buck2_vol[i] =
5b5e977c 763 s5m8767_convert_voltage_to_sel(
9767ec7f 764 &buck_voltage_val2,
854f73ec 765 pdata->buck2_voltage[i]);
9767ec7f
SK
766 }
767
768 if (s5m8767->buck3_gpiodvs) {
769 s5m8767->buck3_vol[i] =
5b5e977c 770 s5m8767_convert_voltage_to_sel(
9767ec7f 771 &buck_voltage_val2,
854f73ec 772 pdata->buck3_voltage[i]);
9767ec7f
SK
773 }
774
775 if (s5m8767->buck4_gpiodvs) {
776 s5m8767->buck4_vol[i] =
5b5e977c 777 s5m8767_convert_voltage_to_sel(
9767ec7f 778 &buck_voltage_val2,
854f73ec 779 pdata->buck4_voltage[i]);
9767ec7f
SK
780 }
781 }
782
76c854d1
ADK
783 if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs ||
784 pdata->buck4_gpiodvs) {
785
786 if (!gpio_is_valid(pdata->buck_gpios[0]) ||
787 !gpio_is_valid(pdata->buck_gpios[1]) ||
788 !gpio_is_valid(pdata->buck_gpios[2])) {
789 dev_err(&pdev->dev, "GPIO NOT VALID\n");
790 return -EINVAL;
791 }
792
5febb3c9
AL
793 ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[0],
794 "S5M8767 SET1");
795 if (ret)
796 return ret;
797
798 ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[1],
799 "S5M8767 SET2");
800 if (ret)
801 return ret;
802
803 ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[2],
804 "S5M8767 SET3");
805 if (ret)
806 return ret;
807
c848bc85
SK
808 /* SET1 GPIO */
809 gpio_direction_output(pdata->buck_gpios[0],
810 (s5m8767->buck_gpioindex >> 2) & 0x1);
811 /* SET2 GPIO */
812 gpio_direction_output(pdata->buck_gpios[1],
813 (s5m8767->buck_gpioindex >> 1) & 0x1);
814 /* SET3 GPIO */
815 gpio_direction_output(pdata->buck_gpios[2],
816 (s5m8767->buck_gpioindex >> 0) & 0x1);
9767ec7f
SK
817 }
818
5febb3c9
AL
819 ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[0], "S5M8767 DS2");
820 if (ret)
821 return ret;
c848bc85 822
5febb3c9
AL
823 ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[1], "S5M8767 DS3");
824 if (ret)
825 return ret;
c848bc85 826
5febb3c9
AL
827 ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[2], "S5M8767 DS4");
828 if (ret)
829 return ret;
c848bc85
SK
830
831 /* DS2 GPIO */
832 gpio_direction_output(pdata->buck_ds[0], 0x0);
833 /* DS3 GPIO */
834 gpio_direction_output(pdata->buck_ds[1], 0x0);
835 /* DS4 GPIO */
836 gpio_direction_output(pdata->buck_ds[2], 0x0);
837
838 if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs ||
839 pdata->buck4_gpiodvs) {
3e701cdf 840 sec_reg_update(s5m8767->iodev, S5M8767_REG_BUCK2CTRL,
c848bc85
SK
841 (pdata->buck2_gpiodvs) ? (1 << 1) : (0 << 1),
842 1 << 1);
3e701cdf 843 sec_reg_update(s5m8767->iodev, S5M8767_REG_BUCK3CTRL,
c848bc85
SK
844 (pdata->buck3_gpiodvs) ? (1 << 1) : (0 << 1),
845 1 << 1);
3e701cdf 846 sec_reg_update(s5m8767->iodev, S5M8767_REG_BUCK4CTRL,
c848bc85
SK
847 (pdata->buck4_gpiodvs) ? (1 << 1) : (0 << 1),
848 1 << 1);
849 }
9767ec7f
SK
850
851 /* Initialize GPIO DVS registers */
852 for (i = 0; i < 8; i++) {
853 if (s5m8767->buck2_gpiodvs) {
63063bfb 854 sec_reg_write(s5m8767->iodev, S5M8767_REG_BUCK2DVS1 + i,
9767ec7f
SK
855 s5m8767->buck2_vol[i]);
856 }
857
858 if (s5m8767->buck3_gpiodvs) {
63063bfb 859 sec_reg_write(s5m8767->iodev, S5M8767_REG_BUCK3DVS1 + i,
9767ec7f
SK
860 s5m8767->buck3_vol[i]);
861 }
862
863 if (s5m8767->buck4_gpiodvs) {
63063bfb 864 sec_reg_write(s5m8767->iodev, S5M8767_REG_BUCK4DVS1 + i,
9767ec7f
SK
865 s5m8767->buck4_vol[i]);
866 }
867 }
9767ec7f
SK
868
869 if (s5m8767->buck2_ramp)
63063bfb 870 sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP, 0x08, 0x08);
9767ec7f
SK
871
872 if (s5m8767->buck3_ramp)
63063bfb 873 sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP, 0x04, 0x04);
9767ec7f
SK
874
875 if (s5m8767->buck4_ramp)
63063bfb 876 sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP, 0x02, 0x02);
9767ec7f
SK
877
878 if (s5m8767->buck2_ramp || s5m8767->buck3_ramp
879 || s5m8767->buck4_ramp) {
880 switch (s5m8767->ramp_delay) {
1af142c6 881 case 5:
63063bfb 882 sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP,
1af142c6
SK
883 0x40, 0xf0);
884 break;
885 case 10:
3e701cdf 886 sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP,
1af142c6 887 0x90, 0xf0);
047ec220 888 break;
9767ec7f 889 case 25:
63063bfb 890 sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP,
9767ec7f 891 0xd0, 0xf0);
047ec220 892 break;
9767ec7f 893 case 50:
63063bfb 894 sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP,
9767ec7f 895 0xe0, 0xf0);
047ec220 896 break;
9767ec7f 897 case 100:
63063bfb 898 sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP,
9767ec7f 899 0xf0, 0xf0);
047ec220 900 break;
9767ec7f 901 default:
63063bfb 902 sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP,
9767ec7f
SK
903 0x90, 0xf0);
904 }
905 }
906
907 for (i = 0; i < pdata->num_regulators; i++) {
63063bfb 908 const struct sec_voltage_desc *desc;
9767ec7f
SK
909 int id = pdata->regulators[i].id;
910
911 desc = reg_voltage_map[id];
e2eb169b 912 if (desc) {
9767ec7f
SK
913 regulators[id].n_voltages =
914 (desc->max - desc->min) / desc->step + 1;
e2eb169b
AL
915 regulators[id].min_uV = desc->min;
916 regulators[id].uV_step = desc->step;
31a932e1
AL
917 regulators[id].vsel_reg =
918 s5m8767_get_vsel_reg(id, s5m8767);
919 if (id < S5M8767_BUCK1)
920 regulators[id].vsel_mask = 0x3f;
921 else
922 regulators[id].vsel_mask = 0xff;
e2eb169b 923 }
9767ec7f 924
c172708d
MB
925 config.dev = s5m8767->dev;
926 config.init_data = pdata->regulators[i].initdata;
927 config.driver_data = s5m8767;
31a932e1 928 config.regmap = iodev->regmap;
26aec009 929 config.of_node = pdata->regulators[i].reg_node;
c172708d 930
f0db475d
MB
931 rdev[i] = devm_regulator_register(&pdev->dev, &regulators[id],
932 &config);
9767ec7f
SK
933 if (IS_ERR(rdev[i])) {
934 ret = PTR_ERR(rdev[i]);
935 dev_err(s5m8767->dev, "regulator init failed for %d\n",
936 id);
f0db475d 937 return ret;
9767ec7f
SK
938 }
939 }
940
9767ec7f
SK
941 return 0;
942}
943
944static const struct platform_device_id s5m8767_pmic_id[] = {
945 { "s5m8767-pmic", 0},
946 { },
947};
948MODULE_DEVICE_TABLE(platform, s5m8767_pmic_id);
949
950static struct platform_driver s5m8767_pmic_driver = {
951 .driver = {
952 .name = "s5m8767-pmic",
953 .owner = THIS_MODULE,
954 },
955 .probe = s5m8767_pmic_probe,
9767ec7f
SK
956 .id_table = s5m8767_pmic_id,
957};
958
959static int __init s5m8767_pmic_init(void)
960{
961 return platform_driver_register(&s5m8767_pmic_driver);
962}
963subsys_initcall(s5m8767_pmic_init);
964
965static void __exit s5m8767_pmic_exit(void)
966{
967 platform_driver_unregister(&s5m8767_pmic_driver);
968}
969module_exit(s5m8767_pmic_exit);
970
971/* Module information */
972MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>");
973MODULE_DESCRIPTION("SAMSUNG S5M8767 Regulator Driver");
974MODULE_LICENSE("GPL");