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9767ec7f SK |
1 | /* |
2 | * s5m8767.c | |
3 | * | |
4 | * Copyright (c) 2011 Samsung Electronics Co., Ltd | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | * | |
12 | */ | |
13 | ||
14 | #include <linux/bug.h> | |
9767ec7f SK |
15 | #include <linux/err.h> |
16 | #include <linux/gpio.h> | |
26aec009 | 17 | #include <linux/of_gpio.h> |
9767ec7f SK |
18 | #include <linux/slab.h> |
19 | #include <linux/module.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/regulator/driver.h> | |
22 | #include <linux/regulator/machine.h> | |
54227bcf SK |
23 | #include <linux/mfd/samsung/core.h> |
24 | #include <linux/mfd/samsung/s5m8767.h> | |
26aec009 ADK |
25 | #include <linux/regulator/of_regulator.h> |
26 | ||
27 | #define S5M8767_OPMODE_NORMAL_MODE 0x1 | |
9767ec7f SK |
28 | |
29 | struct s5m8767_info { | |
30 | struct device *dev; | |
63063bfb | 31 | struct sec_pmic_dev *iodev; |
9767ec7f SK |
32 | int num_regulators; |
33 | struct regulator_dev **rdev; | |
63063bfb | 34 | struct sec_opmode_data *opmode; |
9767ec7f SK |
35 | |
36 | int ramp_delay; | |
37 | bool buck2_ramp; | |
38 | bool buck3_ramp; | |
39 | bool buck4_ramp; | |
40 | ||
41 | bool buck2_gpiodvs; | |
42 | bool buck3_gpiodvs; | |
43 | bool buck4_gpiodvs; | |
44 | u8 buck2_vol[8]; | |
45 | u8 buck3_vol[8]; | |
46 | u8 buck4_vol[8]; | |
47 | int buck_gpios[3]; | |
c848bc85 | 48 | int buck_ds[3]; |
9767ec7f SK |
49 | int buck_gpioindex; |
50 | }; | |
51 | ||
63063bfb | 52 | struct sec_voltage_desc { |
9767ec7f SK |
53 | int max; |
54 | int min; | |
55 | int step; | |
56 | }; | |
57 | ||
63063bfb | 58 | static const struct sec_voltage_desc buck_voltage_val1 = { |
9767ec7f SK |
59 | .max = 2225000, |
60 | .min = 650000, | |
61 | .step = 6250, | |
62 | }; | |
63 | ||
63063bfb | 64 | static const struct sec_voltage_desc buck_voltage_val2 = { |
9767ec7f SK |
65 | .max = 1600000, |
66 | .min = 600000, | |
67 | .step = 6250, | |
68 | }; | |
69 | ||
63063bfb | 70 | static const struct sec_voltage_desc buck_voltage_val3 = { |
9767ec7f SK |
71 | .max = 3000000, |
72 | .min = 750000, | |
73 | .step = 12500, | |
74 | }; | |
75 | ||
63063bfb | 76 | static const struct sec_voltage_desc ldo_voltage_val1 = { |
9767ec7f SK |
77 | .max = 3950000, |
78 | .min = 800000, | |
79 | .step = 50000, | |
80 | }; | |
81 | ||
63063bfb | 82 | static const struct sec_voltage_desc ldo_voltage_val2 = { |
9767ec7f SK |
83 | .max = 2375000, |
84 | .min = 800000, | |
85 | .step = 25000, | |
86 | }; | |
87 | ||
63063bfb | 88 | static const struct sec_voltage_desc *reg_voltage_map[] = { |
9767ec7f SK |
89 | [S5M8767_LDO1] = &ldo_voltage_val2, |
90 | [S5M8767_LDO2] = &ldo_voltage_val2, | |
91 | [S5M8767_LDO3] = &ldo_voltage_val1, | |
92 | [S5M8767_LDO4] = &ldo_voltage_val1, | |
93 | [S5M8767_LDO5] = &ldo_voltage_val1, | |
94 | [S5M8767_LDO6] = &ldo_voltage_val2, | |
95 | [S5M8767_LDO7] = &ldo_voltage_val2, | |
96 | [S5M8767_LDO8] = &ldo_voltage_val2, | |
97 | [S5M8767_LDO9] = &ldo_voltage_val1, | |
98 | [S5M8767_LDO10] = &ldo_voltage_val1, | |
99 | [S5M8767_LDO11] = &ldo_voltage_val1, | |
100 | [S5M8767_LDO12] = &ldo_voltage_val1, | |
101 | [S5M8767_LDO13] = &ldo_voltage_val1, | |
102 | [S5M8767_LDO14] = &ldo_voltage_val1, | |
103 | [S5M8767_LDO15] = &ldo_voltage_val2, | |
104 | [S5M8767_LDO16] = &ldo_voltage_val1, | |
105 | [S5M8767_LDO17] = &ldo_voltage_val1, | |
106 | [S5M8767_LDO18] = &ldo_voltage_val1, | |
107 | [S5M8767_LDO19] = &ldo_voltage_val1, | |
108 | [S5M8767_LDO20] = &ldo_voltage_val1, | |
109 | [S5M8767_LDO21] = &ldo_voltage_val1, | |
110 | [S5M8767_LDO22] = &ldo_voltage_val1, | |
111 | [S5M8767_LDO23] = &ldo_voltage_val1, | |
112 | [S5M8767_LDO24] = &ldo_voltage_val1, | |
113 | [S5M8767_LDO25] = &ldo_voltage_val1, | |
114 | [S5M8767_LDO26] = &ldo_voltage_val1, | |
115 | [S5M8767_LDO27] = &ldo_voltage_val1, | |
116 | [S5M8767_LDO28] = &ldo_voltage_val1, | |
117 | [S5M8767_BUCK1] = &buck_voltage_val1, | |
118 | [S5M8767_BUCK2] = &buck_voltage_val2, | |
119 | [S5M8767_BUCK3] = &buck_voltage_val2, | |
120 | [S5M8767_BUCK4] = &buck_voltage_val2, | |
121 | [S5M8767_BUCK5] = &buck_voltage_val1, | |
122 | [S5M8767_BUCK6] = &buck_voltage_val1, | |
463616ea KK |
123 | [S5M8767_BUCK7] = &buck_voltage_val3, |
124 | [S5M8767_BUCK8] = &buck_voltage_val3, | |
9767ec7f SK |
125 | [S5M8767_BUCK9] = &buck_voltage_val3, |
126 | }; | |
127 | ||
5ceba7ba | 128 | static unsigned int s5m8767_opmode_reg[][4] = { |
7e44bb83 SK |
129 | /* {OFF, ON, LOWPOWER, SUSPEND} */ |
130 | /* LDO1 ... LDO28 */ | |
131 | {0x0, 0x3, 0x2, 0x1}, /* LDO1 */ | |
132 | {0x0, 0x3, 0x2, 0x1}, | |
133 | {0x0, 0x3, 0x2, 0x1}, | |
134 | {0x0, 0x0, 0x0, 0x0}, | |
135 | {0x0, 0x3, 0x2, 0x1}, /* LDO5 */ | |
136 | {0x0, 0x3, 0x2, 0x1}, | |
137 | {0x0, 0x3, 0x2, 0x1}, | |
138 | {0x0, 0x3, 0x2, 0x1}, | |
139 | {0x0, 0x3, 0x2, 0x1}, | |
140 | {0x0, 0x3, 0x2, 0x1}, /* LDO10 */ | |
141 | {0x0, 0x3, 0x2, 0x1}, | |
142 | {0x0, 0x3, 0x2, 0x1}, | |
143 | {0x0, 0x3, 0x2, 0x1}, | |
144 | {0x0, 0x3, 0x2, 0x1}, | |
145 | {0x0, 0x3, 0x2, 0x1}, /* LDO15 */ | |
146 | {0x0, 0x3, 0x2, 0x1}, | |
147 | {0x0, 0x3, 0x2, 0x1}, | |
148 | {0x0, 0x0, 0x0, 0x0}, | |
149 | {0x0, 0x3, 0x2, 0x1}, | |
150 | {0x0, 0x3, 0x2, 0x1}, /* LDO20 */ | |
151 | {0x0, 0x3, 0x2, 0x1}, | |
152 | {0x0, 0x3, 0x2, 0x1}, | |
153 | {0x0, 0x0, 0x0, 0x0}, | |
154 | {0x0, 0x3, 0x2, 0x1}, | |
155 | {0x0, 0x3, 0x2, 0x1}, /* LDO25 */ | |
156 | {0x0, 0x3, 0x2, 0x1}, | |
157 | {0x0, 0x3, 0x2, 0x1}, | |
158 | {0x0, 0x3, 0x2, 0x1}, /* LDO28 */ | |
159 | ||
160 | /* BUCK1 ... BUCK9 */ | |
161 | {0x0, 0x3, 0x1, 0x1}, /* BUCK1 */ | |
162 | {0x0, 0x3, 0x1, 0x1}, | |
163 | {0x0, 0x3, 0x1, 0x1}, | |
164 | {0x0, 0x3, 0x1, 0x1}, | |
165 | {0x0, 0x3, 0x2, 0x1}, /* BUCK5 */ | |
166 | {0x0, 0x3, 0x1, 0x1}, | |
167 | {0x0, 0x3, 0x1, 0x1}, | |
168 | {0x0, 0x3, 0x1, 0x1}, | |
169 | {0x0, 0x3, 0x1, 0x1}, /* BUCK9 */ | |
170 | }; | |
171 | ||
172 | static int s5m8767_get_register(struct regulator_dev *rdev, int *reg, | |
173 | int *enable_ctrl) | |
9767ec7f | 174 | { |
9bb096ff | 175 | int i, reg_id = rdev_get_id(rdev); |
7e44bb83 SK |
176 | unsigned int mode; |
177 | struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev); | |
9767ec7f SK |
178 | |
179 | switch (reg_id) { | |
180 | case S5M8767_LDO1 ... S5M8767_LDO2: | |
181 | *reg = S5M8767_REG_LDO1CTRL + (reg_id - S5M8767_LDO1); | |
182 | break; | |
183 | case S5M8767_LDO3 ... S5M8767_LDO28: | |
184 | *reg = S5M8767_REG_LDO3CTRL + (reg_id - S5M8767_LDO3); | |
185 | break; | |
186 | case S5M8767_BUCK1: | |
187 | *reg = S5M8767_REG_BUCK1CTRL1; | |
188 | break; | |
189 | case S5M8767_BUCK2 ... S5M8767_BUCK4: | |
190 | *reg = S5M8767_REG_BUCK2CTRL + (reg_id - S5M8767_BUCK2) * 9; | |
191 | break; | |
192 | case S5M8767_BUCK5: | |
193 | *reg = S5M8767_REG_BUCK5CTRL1; | |
194 | break; | |
195 | case S5M8767_BUCK6 ... S5M8767_BUCK9: | |
196 | *reg = S5M8767_REG_BUCK6CTRL1 + (reg_id - S5M8767_BUCK6) * 2; | |
197 | break; | |
198 | default: | |
199 | return -EINVAL; | |
200 | } | |
201 | ||
9bb096ff ADK |
202 | for (i = 0; i < s5m8767->num_regulators; i++) { |
203 | if (s5m8767->opmode[i].id == reg_id) { | |
204 | mode = s5m8767->opmode[i].mode; | |
205 | break; | |
206 | } | |
207 | } | |
208 | ||
209 | if (i < s5m8767->num_regulators) | |
210 | *enable_ctrl = | |
211 | s5m8767_opmode_reg[reg_id][mode] << S5M8767_ENCTRL_SHIFT; | |
212 | ||
9767ec7f SK |
213 | return 0; |
214 | } | |
215 | ||
216 | static int s5m8767_reg_is_enabled(struct regulator_dev *rdev) | |
217 | { | |
218 | struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev); | |
219 | int ret, reg; | |
79b53d19 | 220 | int enable_ctrl; |
3ef30398 | 221 | unsigned int val; |
9767ec7f | 222 | |
7e44bb83 | 223 | ret = s5m8767_get_register(rdev, ®, &enable_ctrl); |
9767ec7f SK |
224 | if (ret == -EINVAL) |
225 | return 1; | |
226 | else if (ret) | |
227 | return ret; | |
228 | ||
63063bfb | 229 | ret = sec_reg_read(s5m8767->iodev, reg, &val); |
9767ec7f SK |
230 | if (ret) |
231 | return ret; | |
232 | ||
79b53d19 | 233 | return (val & S5M8767_ENCTRL_MASK) == enable_ctrl; |
9767ec7f SK |
234 | } |
235 | ||
236 | static int s5m8767_reg_enable(struct regulator_dev *rdev) | |
237 | { | |
238 | struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev); | |
239 | int ret, reg; | |
79b53d19 | 240 | int enable_ctrl; |
9767ec7f | 241 | |
7e44bb83 | 242 | ret = s5m8767_get_register(rdev, ®, &enable_ctrl); |
9767ec7f SK |
243 | if (ret) |
244 | return ret; | |
245 | ||
79b53d19 KK |
246 | return sec_reg_update(s5m8767->iodev, reg, enable_ctrl, |
247 | S5M8767_ENCTRL_MASK); | |
9767ec7f SK |
248 | } |
249 | ||
250 | static int s5m8767_reg_disable(struct regulator_dev *rdev) | |
251 | { | |
252 | struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev); | |
253 | int ret, reg; | |
79b53d19 | 254 | int mask = S5M8767_ENCTRL_MASK, enable_ctrl; |
9767ec7f | 255 | |
7e44bb83 | 256 | ret = s5m8767_get_register(rdev, ®, &enable_ctrl); |
9767ec7f SK |
257 | if (ret) |
258 | return ret; | |
259 | ||
63063bfb | 260 | return sec_reg_update(s5m8767->iodev, reg, ~mask, mask); |
9767ec7f SK |
261 | } |
262 | ||
31a932e1 | 263 | static int s5m8767_get_vsel_reg(int reg_id, struct s5m8767_info *s5m8767) |
9767ec7f | 264 | { |
9767ec7f SK |
265 | int reg; |
266 | ||
267 | switch (reg_id) { | |
268 | case S5M8767_LDO1 ... S5M8767_LDO2: | |
269 | reg = S5M8767_REG_LDO1CTRL + (reg_id - S5M8767_LDO1); | |
270 | break; | |
271 | case S5M8767_LDO3 ... S5M8767_LDO28: | |
272 | reg = S5M8767_REG_LDO3CTRL + (reg_id - S5M8767_LDO3); | |
273 | break; | |
274 | case S5M8767_BUCK1: | |
275 | reg = S5M8767_REG_BUCK1CTRL2; | |
276 | break; | |
277 | case S5M8767_BUCK2: | |
da130ab2 | 278 | reg = S5M8767_REG_BUCK2DVS1; |
0a41685f AL |
279 | if (s5m8767->buck2_gpiodvs) |
280 | reg += s5m8767->buck_gpioindex; | |
9767ec7f SK |
281 | break; |
282 | case S5M8767_BUCK3: | |
da130ab2 | 283 | reg = S5M8767_REG_BUCK3DVS1; |
0a41685f AL |
284 | if (s5m8767->buck3_gpiodvs) |
285 | reg += s5m8767->buck_gpioindex; | |
9767ec7f SK |
286 | break; |
287 | case S5M8767_BUCK4: | |
da130ab2 | 288 | reg = S5M8767_REG_BUCK4DVS1; |
0a41685f AL |
289 | if (s5m8767->buck4_gpiodvs) |
290 | reg += s5m8767->buck_gpioindex; | |
9767ec7f SK |
291 | break; |
292 | case S5M8767_BUCK5: | |
293 | reg = S5M8767_REG_BUCK5CTRL2; | |
294 | break; | |
295 | case S5M8767_BUCK6 ... S5M8767_BUCK9: | |
296 | reg = S5M8767_REG_BUCK6CTRL2 + (reg_id - S5M8767_BUCK6) * 2; | |
297 | break; | |
298 | default: | |
299 | return -EINVAL; | |
300 | } | |
301 | ||
31a932e1 | 302 | return reg; |
9767ec7f SK |
303 | } |
304 | ||
854f73ec AL |
305 | static int s5m8767_convert_voltage_to_sel(const struct sec_voltage_desc *desc, |
306 | int min_vol) | |
9767ec7f | 307 | { |
5b5e977c | 308 | int selector = 0; |
9767ec7f SK |
309 | |
310 | if (desc == NULL) | |
311 | return -EINVAL; | |
312 | ||
854f73ec | 313 | if (min_vol > desc->max) |
9767ec7f SK |
314 | return -EINVAL; |
315 | ||
94e85a3c AL |
316 | if (min_vol < desc->min) |
317 | min_vol = desc->min; | |
318 | ||
319 | selector = DIV_ROUND_UP(min_vol - desc->min, desc->step); | |
9767ec7f | 320 | |
854f73ec | 321 | if (desc->min + desc->step * selector > desc->max) |
9767ec7f SK |
322 | return -EINVAL; |
323 | ||
5b5e977c | 324 | return selector; |
9767ec7f SK |
325 | } |
326 | ||
df2643cf | 327 | static inline int s5m8767_set_high(struct s5m8767_info *s5m8767) |
321d2aba AL |
328 | { |
329 | int temp_index = s5m8767->buck_gpioindex; | |
330 | ||
331 | gpio_set_value(s5m8767->buck_gpios[0], (temp_index >> 2) & 0x1); | |
332 | gpio_set_value(s5m8767->buck_gpios[1], (temp_index >> 1) & 0x1); | |
333 | gpio_set_value(s5m8767->buck_gpios[2], temp_index & 0x1); | |
df2643cf SK |
334 | |
335 | return 0; | |
321d2aba AL |
336 | } |
337 | ||
df2643cf | 338 | static inline int s5m8767_set_low(struct s5m8767_info *s5m8767) |
321d2aba AL |
339 | { |
340 | int temp_index = s5m8767->buck_gpioindex; | |
341 | ||
342 | gpio_set_value(s5m8767->buck_gpios[2], temp_index & 0x1); | |
343 | gpio_set_value(s5m8767->buck_gpios[1], (temp_index >> 1) & 0x1); | |
344 | gpio_set_value(s5m8767->buck_gpios[0], (temp_index >> 2) & 0x1); | |
df2643cf SK |
345 | |
346 | return 0; | |
321d2aba AL |
347 | } |
348 | ||
df2643cf SK |
349 | static int s5m8767_set_voltage_sel(struct regulator_dev *rdev, |
350 | unsigned selector) | |
9767ec7f SK |
351 | { |
352 | struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev); | |
20a14b84 | 353 | int reg_id = rdev_get_id(rdev); |
31a932e1 | 354 | int old_index, index = 0; |
321d2aba | 355 | u8 *buck234_vol = NULL; |
9767ec7f SK |
356 | |
357 | switch (reg_id) { | |
358 | case S5M8767_LDO1 ... S5M8767_LDO28: | |
9767ec7f SK |
359 | break; |
360 | case S5M8767_BUCK1 ... S5M8767_BUCK6: | |
321d2aba AL |
361 | if (reg_id == S5M8767_BUCK2 && s5m8767->buck2_gpiodvs) |
362 | buck234_vol = &s5m8767->buck2_vol[0]; | |
363 | else if (reg_id == S5M8767_BUCK3 && s5m8767->buck3_gpiodvs) | |
364 | buck234_vol = &s5m8767->buck3_vol[0]; | |
365 | else if (reg_id == S5M8767_BUCK4 && s5m8767->buck4_gpiodvs) | |
366 | buck234_vol = &s5m8767->buck4_vol[0]; | |
9767ec7f SK |
367 | break; |
368 | case S5M8767_BUCK7 ... S5M8767_BUCK8: | |
369 | return -EINVAL; | |
370 | case S5M8767_BUCK9: | |
9767ec7f SK |
371 | break; |
372 | default: | |
373 | return -EINVAL; | |
374 | } | |
375 | ||
321d2aba AL |
376 | /* buck234_vol != NULL means to control buck234 voltage via DVS GPIO */ |
377 | if (buck234_vol) { | |
df2643cf | 378 | while (*buck234_vol != selector) { |
321d2aba AL |
379 | buck234_vol++; |
380 | index++; | |
381 | } | |
382 | old_index = s5m8767->buck_gpioindex; | |
383 | s5m8767->buck_gpioindex = index; | |
384 | ||
385 | if (index > old_index) | |
df2643cf | 386 | return s5m8767_set_high(s5m8767); |
321d2aba | 387 | else |
df2643cf | 388 | return s5m8767_set_low(s5m8767); |
321d2aba | 389 | } else { |
31a932e1 | 390 | return regulator_set_voltage_sel_regmap(rdev, selector); |
321d2aba | 391 | } |
9767ec7f SK |
392 | } |
393 | ||
9767ec7f SK |
394 | static int s5m8767_set_voltage_time_sel(struct regulator_dev *rdev, |
395 | unsigned int old_sel, | |
396 | unsigned int new_sel) | |
397 | { | |
398 | struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev); | |
63063bfb | 399 | const struct sec_voltage_desc *desc; |
20a14b84 | 400 | int reg_id = rdev_get_id(rdev); |
9767ec7f | 401 | |
9767ec7f SK |
402 | desc = reg_voltage_map[reg_id]; |
403 | ||
9d88fc0b | 404 | if ((old_sel < new_sel) && s5m8767->ramp_delay) |
89e0f0e4 | 405 | return DIV_ROUND_UP(desc->step * (new_sel - old_sel), |
0f8b9c77 | 406 | s5m8767->ramp_delay * 1000); |
89e0f0e4 | 407 | return 0; |
9767ec7f SK |
408 | } |
409 | ||
d35aad0c | 410 | static struct regulator_ops s5m8767_ops = { |
e2eb169b | 411 | .list_voltage = regulator_list_voltage_linear, |
9767ec7f SK |
412 | .is_enabled = s5m8767_reg_is_enabled, |
413 | .enable = s5m8767_reg_enable, | |
414 | .disable = s5m8767_reg_disable, | |
31a932e1 | 415 | .get_voltage_sel = regulator_get_voltage_sel_regmap, |
df2643cf | 416 | .set_voltage_sel = s5m8767_set_voltage_sel, |
9767ec7f SK |
417 | .set_voltage_time_sel = s5m8767_set_voltage_time_sel, |
418 | }; | |
419 | ||
e2eb169b | 420 | static struct regulator_ops s5m8767_buck78_ops = { |
463616ea | 421 | .list_voltage = regulator_list_voltage_linear, |
e2eb169b AL |
422 | .is_enabled = s5m8767_reg_is_enabled, |
423 | .enable = s5m8767_reg_enable, | |
424 | .disable = s5m8767_reg_disable, | |
463616ea KK |
425 | .get_voltage_sel = regulator_get_voltage_sel_regmap, |
426 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
e2eb169b AL |
427 | }; |
428 | ||
65896e73 AL |
429 | #define s5m8767_regulator_desc(_name) { \ |
430 | .name = #_name, \ | |
431 | .id = S5M8767_##_name, \ | |
432 | .ops = &s5m8767_ops, \ | |
9767ec7f SK |
433 | .type = REGULATOR_VOLTAGE, \ |
434 | .owner = THIS_MODULE, \ | |
435 | } | |
436 | ||
e2eb169b AL |
437 | #define s5m8767_regulator_buck78_desc(_name) { \ |
438 | .name = #_name, \ | |
439 | .id = S5M8767_##_name, \ | |
440 | .ops = &s5m8767_buck78_ops, \ | |
441 | .type = REGULATOR_VOLTAGE, \ | |
442 | .owner = THIS_MODULE, \ | |
443 | } | |
444 | ||
9767ec7f | 445 | static struct regulator_desc regulators[] = { |
65896e73 AL |
446 | s5m8767_regulator_desc(LDO1), |
447 | s5m8767_regulator_desc(LDO2), | |
448 | s5m8767_regulator_desc(LDO3), | |
449 | s5m8767_regulator_desc(LDO4), | |
450 | s5m8767_regulator_desc(LDO5), | |
451 | s5m8767_regulator_desc(LDO6), | |
452 | s5m8767_regulator_desc(LDO7), | |
453 | s5m8767_regulator_desc(LDO8), | |
454 | s5m8767_regulator_desc(LDO9), | |
455 | s5m8767_regulator_desc(LDO10), | |
456 | s5m8767_regulator_desc(LDO11), | |
457 | s5m8767_regulator_desc(LDO12), | |
458 | s5m8767_regulator_desc(LDO13), | |
459 | s5m8767_regulator_desc(LDO14), | |
460 | s5m8767_regulator_desc(LDO15), | |
461 | s5m8767_regulator_desc(LDO16), | |
462 | s5m8767_regulator_desc(LDO17), | |
463 | s5m8767_regulator_desc(LDO18), | |
464 | s5m8767_regulator_desc(LDO19), | |
465 | s5m8767_regulator_desc(LDO20), | |
466 | s5m8767_regulator_desc(LDO21), | |
467 | s5m8767_regulator_desc(LDO22), | |
468 | s5m8767_regulator_desc(LDO23), | |
469 | s5m8767_regulator_desc(LDO24), | |
470 | s5m8767_regulator_desc(LDO25), | |
471 | s5m8767_regulator_desc(LDO26), | |
472 | s5m8767_regulator_desc(LDO27), | |
473 | s5m8767_regulator_desc(LDO28), | |
474 | s5m8767_regulator_desc(BUCK1), | |
475 | s5m8767_regulator_desc(BUCK2), | |
476 | s5m8767_regulator_desc(BUCK3), | |
477 | s5m8767_regulator_desc(BUCK4), | |
478 | s5m8767_regulator_desc(BUCK5), | |
479 | s5m8767_regulator_desc(BUCK6), | |
e2eb169b AL |
480 | s5m8767_regulator_buck78_desc(BUCK7), |
481 | s5m8767_regulator_buck78_desc(BUCK8), | |
65896e73 | 482 | s5m8767_regulator_desc(BUCK9), |
9767ec7f SK |
483 | }; |
484 | ||
26aec009 ADK |
485 | #ifdef CONFIG_OF |
486 | static int s5m8767_pmic_dt_parse_dvs_gpio(struct sec_pmic_dev *iodev, | |
487 | struct sec_platform_data *pdata, | |
488 | struct device_node *pmic_np) | |
489 | { | |
490 | int i, gpio; | |
491 | ||
492 | for (i = 0; i < 3; i++) { | |
493 | gpio = of_get_named_gpio(pmic_np, | |
494 | "s5m8767,pmic-buck-dvs-gpios", i); | |
495 | if (!gpio_is_valid(gpio)) { | |
496 | dev_err(iodev->dev, "invalid gpio[%d]: %d\n", i, gpio); | |
497 | return -EINVAL; | |
498 | } | |
499 | pdata->buck_gpios[i] = gpio; | |
500 | } | |
501 | return 0; | |
502 | } | |
503 | ||
504 | static int s5m8767_pmic_dt_parse_ds_gpio(struct sec_pmic_dev *iodev, | |
505 | struct sec_platform_data *pdata, | |
506 | struct device_node *pmic_np) | |
507 | { | |
508 | int i, gpio; | |
509 | ||
510 | for (i = 0; i < 3; i++) { | |
511 | gpio = of_get_named_gpio(pmic_np, | |
512 | "s5m8767,pmic-buck-ds-gpios", i); | |
513 | if (!gpio_is_valid(gpio)) { | |
514 | dev_err(iodev->dev, "invalid gpio[%d]: %d\n", i, gpio); | |
515 | return -EINVAL; | |
516 | } | |
517 | pdata->buck_ds[i] = gpio; | |
518 | } | |
519 | return 0; | |
520 | } | |
521 | ||
cbb0ed49 | 522 | static int s5m8767_pmic_dt_parse_pdata(struct platform_device *pdev, |
26aec009 ADK |
523 | struct sec_platform_data *pdata) |
524 | { | |
cbb0ed49 | 525 | struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent); |
26aec009 ADK |
526 | struct device_node *pmic_np, *regulators_np, *reg_np; |
527 | struct sec_regulator_data *rdata; | |
528 | struct sec_opmode_data *rmode; | |
04f9f068 | 529 | unsigned int i, dvs_voltage_nr = 8, ret; |
26aec009 ADK |
530 | |
531 | pmic_np = iodev->dev->of_node; | |
532 | if (!pmic_np) { | |
533 | dev_err(iodev->dev, "could not find pmic sub-node\n"); | |
534 | return -ENODEV; | |
535 | } | |
536 | ||
537 | regulators_np = of_find_node_by_name(pmic_np, "regulators"); | |
538 | if (!regulators_np) { | |
539 | dev_err(iodev->dev, "could not find regulators sub-node\n"); | |
540 | return -EINVAL; | |
541 | } | |
542 | ||
543 | /* count the number of regulators to be supported in pmic */ | |
1f91b6f6 | 544 | pdata->num_regulators = of_get_child_count(regulators_np); |
26aec009 | 545 | |
cbb0ed49 | 546 | rdata = devm_kzalloc(&pdev->dev, sizeof(*rdata) * |
26aec009 ADK |
547 | pdata->num_regulators, GFP_KERNEL); |
548 | if (!rdata) { | |
549 | dev_err(iodev->dev, | |
550 | "could not allocate memory for regulator data\n"); | |
551 | return -ENOMEM; | |
552 | } | |
553 | ||
cbb0ed49 | 554 | rmode = devm_kzalloc(&pdev->dev, sizeof(*rmode) * |
26aec009 | 555 | pdata->num_regulators, GFP_KERNEL); |
720a9717 | 556 | if (!rmode) { |
26aec009 ADK |
557 | dev_err(iodev->dev, |
558 | "could not allocate memory for regulator mode\n"); | |
559 | return -ENOMEM; | |
560 | } | |
561 | ||
562 | pdata->regulators = rdata; | |
563 | pdata->opmode = rmode; | |
564 | for_each_child_of_node(regulators_np, reg_np) { | |
565 | for (i = 0; i < ARRAY_SIZE(regulators); i++) | |
566 | if (!of_node_cmp(reg_np->name, regulators[i].name)) | |
567 | break; | |
568 | ||
569 | if (i == ARRAY_SIZE(regulators)) { | |
570 | dev_warn(iodev->dev, | |
571 | "don't know how to configure regulator %s\n", | |
572 | reg_np->name); | |
573 | continue; | |
574 | } | |
575 | ||
576 | rdata->id = i; | |
577 | rdata->initdata = of_get_regulator_init_data( | |
cbb0ed49 | 578 | &pdev->dev, reg_np); |
26aec009 ADK |
579 | rdata->reg_node = reg_np; |
580 | rdata++; | |
581 | rmode->id = i; | |
582 | if (of_property_read_u32(reg_np, "op_mode", | |
583 | &rmode->mode)) { | |
584 | dev_warn(iodev->dev, | |
585 | "no op_mode property property at %s\n", | |
586 | reg_np->full_name); | |
587 | ||
588 | rmode->mode = S5M8767_OPMODE_NORMAL_MODE; | |
589 | } | |
590 | rmode++; | |
591 | } | |
592 | ||
04f9f068 | 593 | if (of_get_property(pmic_np, "s5m8767,pmic-buck2-uses-gpio-dvs", NULL)) { |
26aec009 ADK |
594 | pdata->buck2_gpiodvs = true; |
595 | ||
04f9f068 CC |
596 | if (of_property_read_u32_array(pmic_np, |
597 | "s5m8767,pmic-buck2-dvs-voltage", | |
598 | pdata->buck2_voltage, dvs_voltage_nr)) { | |
599 | dev_err(iodev->dev, "buck2 voltages not specified\n"); | |
600 | return -EINVAL; | |
601 | } | |
602 | } | |
603 | ||
604 | if (of_get_property(pmic_np, "s5m8767,pmic-buck3-uses-gpio-dvs", NULL)) { | |
26aec009 ADK |
605 | pdata->buck3_gpiodvs = true; |
606 | ||
04f9f068 CC |
607 | if (of_property_read_u32_array(pmic_np, |
608 | "s5m8767,pmic-buck3-dvs-voltage", | |
609 | pdata->buck3_voltage, dvs_voltage_nr)) { | |
610 | dev_err(iodev->dev, "buck3 voltages not specified\n"); | |
611 | return -EINVAL; | |
612 | } | |
613 | } | |
614 | ||
615 | if (of_get_property(pmic_np, "s5m8767,pmic-buck4-uses-gpio-dvs", NULL)) { | |
26aec009 ADK |
616 | pdata->buck4_gpiodvs = true; |
617 | ||
04f9f068 CC |
618 | if (of_property_read_u32_array(pmic_np, |
619 | "s5m8767,pmic-buck4-dvs-voltage", | |
620 | pdata->buck4_voltage, dvs_voltage_nr)) { | |
621 | dev_err(iodev->dev, "buck4 voltages not specified\n"); | |
622 | return -EINVAL; | |
623 | } | |
624 | } | |
625 | ||
26aec009 ADK |
626 | if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs || |
627 | pdata->buck4_gpiodvs) { | |
628 | ret = s5m8767_pmic_dt_parse_dvs_gpio(iodev, pdata, pmic_np); | |
629 | if (ret) | |
630 | return -EINVAL; | |
631 | ||
632 | if (of_property_read_u32(pmic_np, | |
633 | "s5m8767,pmic-buck-default-dvs-idx", | |
634 | &pdata->buck_default_idx)) { | |
635 | pdata->buck_default_idx = 0; | |
636 | } else { | |
637 | if (pdata->buck_default_idx >= 8) { | |
638 | pdata->buck_default_idx = 0; | |
639 | dev_info(iodev->dev, | |
640 | "invalid value for default dvs index, use 0\n"); | |
641 | } | |
642 | } | |
26aec009 ADK |
643 | } |
644 | ||
645 | ret = s5m8767_pmic_dt_parse_ds_gpio(iodev, pdata, pmic_np); | |
646 | if (ret) | |
647 | return -EINVAL; | |
648 | ||
033054e8 CC |
649 | if (of_get_property(pmic_np, "s5m8767,pmic-buck2-ramp-enable", NULL)) |
650 | pdata->buck2_ramp_enable = true; | |
26aec009 | 651 | |
033054e8 CC |
652 | if (of_get_property(pmic_np, "s5m8767,pmic-buck3-ramp-enable", NULL)) |
653 | pdata->buck3_ramp_enable = true; | |
26aec009 | 654 | |
033054e8 CC |
655 | if (of_get_property(pmic_np, "s5m8767,pmic-buck4-ramp-enable", NULL)) |
656 | pdata->buck4_ramp_enable = true; | |
657 | ||
658 | if (pdata->buck2_ramp_enable || pdata->buck3_ramp_enable | |
659 | || pdata->buck4_ramp_enable) { | |
660 | if (of_property_read_u32(pmic_np, "s5m8767,pmic-buck-ramp-delay", | |
661 | &pdata->buck_ramp_delay)) | |
662 | pdata->buck_ramp_delay = 0; | |
26aec009 ADK |
663 | } |
664 | ||
665 | return 0; | |
666 | } | |
667 | #else | |
cbb0ed49 | 668 | static int s5m8767_pmic_dt_parse_pdata(struct platform_device *pdev, |
26aec009 ADK |
669 | struct sec_platform_data *pdata) |
670 | { | |
671 | return 0; | |
672 | } | |
673 | #endif /* CONFIG_OF */ | |
674 | ||
a5023574 | 675 | static int s5m8767_pmic_probe(struct platform_device *pdev) |
9767ec7f | 676 | { |
63063bfb | 677 | struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent); |
26aec009 | 678 | struct sec_platform_data *pdata = iodev->pdata; |
c172708d | 679 | struct regulator_config config = { }; |
9767ec7f SK |
680 | struct regulator_dev **rdev; |
681 | struct s5m8767_info *s5m8767; | |
c848bc85 | 682 | int i, ret, size, buck_init; |
9767ec7f | 683 | |
e81d7bc8 AL |
684 | if (!pdata) { |
685 | dev_err(pdev->dev.parent, "Platform data not supplied\n"); | |
686 | return -ENODEV; | |
687 | } | |
688 | ||
26aec009 | 689 | if (iodev->dev->of_node) { |
cbb0ed49 | 690 | ret = s5m8767_pmic_dt_parse_pdata(pdev, pdata); |
26aec009 ADK |
691 | if (ret) |
692 | return ret; | |
693 | } | |
694 | ||
6c4efe24 AL |
695 | if (pdata->buck2_gpiodvs) { |
696 | if (pdata->buck3_gpiodvs || pdata->buck4_gpiodvs) { | |
697 | dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n"); | |
698 | return -EINVAL; | |
699 | } | |
700 | } | |
701 | ||
702 | if (pdata->buck3_gpiodvs) { | |
703 | if (pdata->buck2_gpiodvs || pdata->buck4_gpiodvs) { | |
704 | dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n"); | |
705 | return -EINVAL; | |
706 | } | |
707 | } | |
708 | ||
709 | if (pdata->buck4_gpiodvs) { | |
710 | if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs) { | |
711 | dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n"); | |
712 | return -EINVAL; | |
713 | } | |
714 | } | |
715 | ||
9767ec7f SK |
716 | s5m8767 = devm_kzalloc(&pdev->dev, sizeof(struct s5m8767_info), |
717 | GFP_KERNEL); | |
718 | if (!s5m8767) | |
719 | return -ENOMEM; | |
720 | ||
721 | size = sizeof(struct regulator_dev *) * (S5M8767_REG_MAX - 2); | |
722 | s5m8767->rdev = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); | |
723 | if (!s5m8767->rdev) | |
724 | return -ENOMEM; | |
725 | ||
726 | rdev = s5m8767->rdev; | |
727 | s5m8767->dev = &pdev->dev; | |
728 | s5m8767->iodev = iodev; | |
9bb096ff | 729 | s5m8767->num_regulators = pdata->num_regulators; |
9767ec7f | 730 | platform_set_drvdata(pdev, s5m8767); |
9767ec7f SK |
731 | |
732 | s5m8767->buck_gpioindex = pdata->buck_default_idx; | |
733 | s5m8767->buck2_gpiodvs = pdata->buck2_gpiodvs; | |
734 | s5m8767->buck3_gpiodvs = pdata->buck3_gpiodvs; | |
735 | s5m8767->buck4_gpiodvs = pdata->buck4_gpiodvs; | |
736 | s5m8767->buck_gpios[0] = pdata->buck_gpios[0]; | |
737 | s5m8767->buck_gpios[1] = pdata->buck_gpios[1]; | |
738 | s5m8767->buck_gpios[2] = pdata->buck_gpios[2]; | |
c848bc85 SK |
739 | s5m8767->buck_ds[0] = pdata->buck_ds[0]; |
740 | s5m8767->buck_ds[1] = pdata->buck_ds[1]; | |
741 | s5m8767->buck_ds[2] = pdata->buck_ds[2]; | |
742 | ||
9767ec7f SK |
743 | s5m8767->ramp_delay = pdata->buck_ramp_delay; |
744 | s5m8767->buck2_ramp = pdata->buck2_ramp_enable; | |
745 | s5m8767->buck3_ramp = pdata->buck3_ramp_enable; | |
746 | s5m8767->buck4_ramp = pdata->buck4_ramp_enable; | |
7e44bb83 | 747 | s5m8767->opmode = pdata->opmode; |
9767ec7f | 748 | |
c848bc85 | 749 | buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2, |
854f73ec | 750 | pdata->buck2_init); |
c848bc85 | 751 | |
938e05bf | 752 | sec_reg_write(s5m8767->iodev, S5M8767_REG_BUCK2DVS2, buck_init); |
c848bc85 SK |
753 | |
754 | buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2, | |
854f73ec | 755 | pdata->buck3_init); |
c848bc85 | 756 | |
938e05bf | 757 | sec_reg_write(s5m8767->iodev, S5M8767_REG_BUCK3DVS2, buck_init); |
c848bc85 SK |
758 | |
759 | buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2, | |
854f73ec | 760 | pdata->buck4_init); |
c848bc85 | 761 | |
938e05bf | 762 | sec_reg_write(s5m8767->iodev, S5M8767_REG_BUCK4DVS2, buck_init); |
c848bc85 | 763 | |
9767ec7f SK |
764 | for (i = 0; i < 8; i++) { |
765 | if (s5m8767->buck2_gpiodvs) { | |
766 | s5m8767->buck2_vol[i] = | |
5b5e977c | 767 | s5m8767_convert_voltage_to_sel( |
9767ec7f | 768 | &buck_voltage_val2, |
854f73ec | 769 | pdata->buck2_voltage[i]); |
9767ec7f SK |
770 | } |
771 | ||
772 | if (s5m8767->buck3_gpiodvs) { | |
773 | s5m8767->buck3_vol[i] = | |
5b5e977c | 774 | s5m8767_convert_voltage_to_sel( |
9767ec7f | 775 | &buck_voltage_val2, |
854f73ec | 776 | pdata->buck3_voltage[i]); |
9767ec7f SK |
777 | } |
778 | ||
779 | if (s5m8767->buck4_gpiodvs) { | |
780 | s5m8767->buck4_vol[i] = | |
5b5e977c | 781 | s5m8767_convert_voltage_to_sel( |
9767ec7f | 782 | &buck_voltage_val2, |
854f73ec | 783 | pdata->buck4_voltage[i]); |
9767ec7f SK |
784 | } |
785 | } | |
786 | ||
76c854d1 ADK |
787 | if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs || |
788 | pdata->buck4_gpiodvs) { | |
789 | ||
790 | if (!gpio_is_valid(pdata->buck_gpios[0]) || | |
791 | !gpio_is_valid(pdata->buck_gpios[1]) || | |
792 | !gpio_is_valid(pdata->buck_gpios[2])) { | |
793 | dev_err(&pdev->dev, "GPIO NOT VALID\n"); | |
794 | return -EINVAL; | |
795 | } | |
796 | ||
5febb3c9 AL |
797 | ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[0], |
798 | "S5M8767 SET1"); | |
799 | if (ret) | |
800 | return ret; | |
801 | ||
802 | ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[1], | |
803 | "S5M8767 SET2"); | |
804 | if (ret) | |
805 | return ret; | |
806 | ||
807 | ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[2], | |
808 | "S5M8767 SET3"); | |
809 | if (ret) | |
810 | return ret; | |
811 | ||
c848bc85 SK |
812 | /* SET1 GPIO */ |
813 | gpio_direction_output(pdata->buck_gpios[0], | |
814 | (s5m8767->buck_gpioindex >> 2) & 0x1); | |
815 | /* SET2 GPIO */ | |
816 | gpio_direction_output(pdata->buck_gpios[1], | |
817 | (s5m8767->buck_gpioindex >> 1) & 0x1); | |
818 | /* SET3 GPIO */ | |
819 | gpio_direction_output(pdata->buck_gpios[2], | |
820 | (s5m8767->buck_gpioindex >> 0) & 0x1); | |
9767ec7f SK |
821 | } |
822 | ||
5febb3c9 AL |
823 | ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[0], "S5M8767 DS2"); |
824 | if (ret) | |
825 | return ret; | |
c848bc85 | 826 | |
5febb3c9 AL |
827 | ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[1], "S5M8767 DS3"); |
828 | if (ret) | |
829 | return ret; | |
c848bc85 | 830 | |
5febb3c9 AL |
831 | ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[2], "S5M8767 DS4"); |
832 | if (ret) | |
833 | return ret; | |
c848bc85 SK |
834 | |
835 | /* DS2 GPIO */ | |
836 | gpio_direction_output(pdata->buck_ds[0], 0x0); | |
837 | /* DS3 GPIO */ | |
838 | gpio_direction_output(pdata->buck_ds[1], 0x0); | |
839 | /* DS4 GPIO */ | |
840 | gpio_direction_output(pdata->buck_ds[2], 0x0); | |
841 | ||
842 | if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs || | |
843 | pdata->buck4_gpiodvs) { | |
3e701cdf | 844 | sec_reg_update(s5m8767->iodev, S5M8767_REG_BUCK2CTRL, |
c848bc85 SK |
845 | (pdata->buck2_gpiodvs) ? (1 << 1) : (0 << 1), |
846 | 1 << 1); | |
3e701cdf | 847 | sec_reg_update(s5m8767->iodev, S5M8767_REG_BUCK3CTRL, |
c848bc85 SK |
848 | (pdata->buck3_gpiodvs) ? (1 << 1) : (0 << 1), |
849 | 1 << 1); | |
3e701cdf | 850 | sec_reg_update(s5m8767->iodev, S5M8767_REG_BUCK4CTRL, |
c848bc85 SK |
851 | (pdata->buck4_gpiodvs) ? (1 << 1) : (0 << 1), |
852 | 1 << 1); | |
853 | } | |
9767ec7f SK |
854 | |
855 | /* Initialize GPIO DVS registers */ | |
856 | for (i = 0; i < 8; i++) { | |
857 | if (s5m8767->buck2_gpiodvs) { | |
63063bfb | 858 | sec_reg_write(s5m8767->iodev, S5M8767_REG_BUCK2DVS1 + i, |
9767ec7f SK |
859 | s5m8767->buck2_vol[i]); |
860 | } | |
861 | ||
862 | if (s5m8767->buck3_gpiodvs) { | |
63063bfb | 863 | sec_reg_write(s5m8767->iodev, S5M8767_REG_BUCK3DVS1 + i, |
9767ec7f SK |
864 | s5m8767->buck3_vol[i]); |
865 | } | |
866 | ||
867 | if (s5m8767->buck4_gpiodvs) { | |
63063bfb | 868 | sec_reg_write(s5m8767->iodev, S5M8767_REG_BUCK4DVS1 + i, |
9767ec7f SK |
869 | s5m8767->buck4_vol[i]); |
870 | } | |
871 | } | |
9767ec7f SK |
872 | |
873 | if (s5m8767->buck2_ramp) | |
63063bfb | 874 | sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP, 0x08, 0x08); |
9767ec7f SK |
875 | |
876 | if (s5m8767->buck3_ramp) | |
63063bfb | 877 | sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP, 0x04, 0x04); |
9767ec7f SK |
878 | |
879 | if (s5m8767->buck4_ramp) | |
63063bfb | 880 | sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP, 0x02, 0x02); |
9767ec7f SK |
881 | |
882 | if (s5m8767->buck2_ramp || s5m8767->buck3_ramp | |
883 | || s5m8767->buck4_ramp) { | |
f37ff6b6 | 884 | unsigned int val; |
9767ec7f | 885 | switch (s5m8767->ramp_delay) { |
1af142c6 | 886 | case 5: |
f37ff6b6 | 887 | val = S5M8767_DVS_BUCK_RAMP_5; |
1af142c6 SK |
888 | break; |
889 | case 10: | |
f37ff6b6 | 890 | val = S5M8767_DVS_BUCK_RAMP_10; |
047ec220 | 891 | break; |
9767ec7f | 892 | case 25: |
f37ff6b6 | 893 | val = S5M8767_DVS_BUCK_RAMP_25; |
047ec220 | 894 | break; |
9767ec7f | 895 | case 50: |
f37ff6b6 | 896 | val = S5M8767_DVS_BUCK_RAMP_50; |
047ec220 | 897 | break; |
9767ec7f | 898 | case 100: |
f37ff6b6 | 899 | val = S5M8767_DVS_BUCK_RAMP_100; |
047ec220 | 900 | break; |
9767ec7f | 901 | default: |
f37ff6b6 | 902 | val = S5M8767_DVS_BUCK_RAMP_10; |
9767ec7f | 903 | } |
f37ff6b6 KK |
904 | sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP, |
905 | val << S5M8767_DVS_BUCK_RAMP_SHIFT, | |
906 | S5M8767_DVS_BUCK_RAMP_MASK); | |
9767ec7f SK |
907 | } |
908 | ||
909 | for (i = 0; i < pdata->num_regulators; i++) { | |
63063bfb | 910 | const struct sec_voltage_desc *desc; |
9767ec7f SK |
911 | int id = pdata->regulators[i].id; |
912 | ||
913 | desc = reg_voltage_map[id]; | |
e2eb169b | 914 | if (desc) { |
9767ec7f SK |
915 | regulators[id].n_voltages = |
916 | (desc->max - desc->min) / desc->step + 1; | |
e2eb169b AL |
917 | regulators[id].min_uV = desc->min; |
918 | regulators[id].uV_step = desc->step; | |
31a932e1 AL |
919 | regulators[id].vsel_reg = |
920 | s5m8767_get_vsel_reg(id, s5m8767); | |
921 | if (id < S5M8767_BUCK1) | |
922 | regulators[id].vsel_mask = 0x3f; | |
923 | else | |
924 | regulators[id].vsel_mask = 0xff; | |
e2eb169b | 925 | } |
9767ec7f | 926 | |
c172708d MB |
927 | config.dev = s5m8767->dev; |
928 | config.init_data = pdata->regulators[i].initdata; | |
929 | config.driver_data = s5m8767; | |
31a932e1 | 930 | config.regmap = iodev->regmap; |
26aec009 | 931 | config.of_node = pdata->regulators[i].reg_node; |
c172708d | 932 | |
f0db475d MB |
933 | rdev[i] = devm_regulator_register(&pdev->dev, ®ulators[id], |
934 | &config); | |
9767ec7f SK |
935 | if (IS_ERR(rdev[i])) { |
936 | ret = PTR_ERR(rdev[i]); | |
937 | dev_err(s5m8767->dev, "regulator init failed for %d\n", | |
938 | id); | |
f0db475d | 939 | return ret; |
9767ec7f SK |
940 | } |
941 | } | |
942 | ||
9767ec7f SK |
943 | return 0; |
944 | } | |
945 | ||
946 | static const struct platform_device_id s5m8767_pmic_id[] = { | |
947 | { "s5m8767-pmic", 0}, | |
948 | { }, | |
949 | }; | |
950 | MODULE_DEVICE_TABLE(platform, s5m8767_pmic_id); | |
951 | ||
952 | static struct platform_driver s5m8767_pmic_driver = { | |
953 | .driver = { | |
954 | .name = "s5m8767-pmic", | |
955 | .owner = THIS_MODULE, | |
956 | }, | |
957 | .probe = s5m8767_pmic_probe, | |
9767ec7f SK |
958 | .id_table = s5m8767_pmic_id, |
959 | }; | |
960 | ||
961 | static int __init s5m8767_pmic_init(void) | |
962 | { | |
963 | return platform_driver_register(&s5m8767_pmic_driver); | |
964 | } | |
965 | subsys_initcall(s5m8767_pmic_init); | |
966 | ||
967 | static void __exit s5m8767_pmic_exit(void) | |
968 | { | |
969 | platform_driver_unregister(&s5m8767_pmic_driver); | |
970 | } | |
971 | module_exit(s5m8767_pmic_exit); | |
972 | ||
973 | /* Module information */ | |
974 | MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>"); | |
975 | MODULE_DESCRIPTION("SAMSUNG S5M8767 Regulator Driver"); | |
976 | MODULE_LICENSE("GPL"); |