[mirror_ubuntu-hirsute-kernel.git] / drivers / regulator / stm32-pwr.c

// SPDX-License-Identifier: GPL-2.0
// Copyright (C) STMicroelectronics 2019
// Authors: Gabriel Fernandez <gabriel.fernandez@st.com>
//          Pascal Paillet <p.paillet@st.com>.

#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/of_regulator.h>

/*
 * Registers description
 */
#define REG_PWR_CR3 0x0C

#define USB_3_3_EN BIT(24)
#define USB_3_3_RDY BIT(26)
#define REG_1_8_EN BIT(28)
#define REG_1_8_RDY BIT(29)
#define REG_1_1_EN BIT(30)
#define REG_1_1_RDY BIT(31)

/* list of supported regulators */
enum {
	PWR_REG11,
	PWR_REG18,
	PWR_USB33,
	STM32PWR_REG_NUM_REGS
};

static u32 ready_mask_table[STM32PWR_REG_NUM_REGS] = {
	[PWR_REG11] = REG_1_1_RDY,
	[PWR_REG18] = REG_1_8_RDY,
	[PWR_USB33] = USB_3_3_RDY,
};

struct stm32_pwr_reg {
	void __iomem *base;
	u32 ready_mask;
};

static int stm32_pwr_reg_is_ready(struct regulator_dev *rdev)
{
	struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
	u32 val;

	val = readl_relaxed(priv->base + REG_PWR_CR3);

	return (val & priv->ready_mask);
}

static int stm32_pwr_reg_is_enabled(struct regulator_dev *rdev)
{
	struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
	u32 val;

	val = readl_relaxed(priv->base + REG_PWR_CR3);

	return (val & rdev->desc->enable_mask);
}

static int stm32_pwr_reg_enable(struct regulator_dev *rdev)
{
	struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
	int ret;
	u32 val;

	val = readl_relaxed(priv->base + REG_PWR_CR3);
	val |= rdev->desc->enable_mask;
	writel_relaxed(val, priv->base + REG_PWR_CR3);

	/* use an arbitrary timeout of 20ms */
	ret = readx_poll_timeout(stm32_pwr_reg_is_ready, rdev, val, val,
				 100, 20 * 1000);
	if (ret)
		dev_err(&rdev->dev, "regulator enable timed out!\n");

	return ret;
}

static int stm32_pwr_reg_disable(struct regulator_dev *rdev)
{
	struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
	int ret;
	u32 val;

	val = readl_relaxed(priv->base + REG_PWR_CR3);
	val &= ~rdev->desc->enable_mask;
	writel_relaxed(val, priv->base + REG_PWR_CR3);

	/* use an arbitrary timeout of 20ms */
	ret = readx_poll_timeout(stm32_pwr_reg_is_ready, rdev, val, !val,
				 100, 20 * 1000);
	if (ret)
		dev_err(&rdev->dev, "regulator disable timed out!\n");

	return ret;
}

static const struct regulator_ops stm32_pwr_reg_ops = {
	.enable		= stm32_pwr_reg_enable,
	.disable	= stm32_pwr_reg_disable,
	.is_enabled	= stm32_pwr_reg_is_enabled,
};

#define PWR_REG(_id, _name, _volt, _en, _supply) \
	[_id] = { \
		.id = _id, \
		.name = _name, \
		.of_match = of_match_ptr(_name), \
		.n_voltages = 1, \
		.type = REGULATOR_VOLTAGE, \
		.fixed_uV = _volt, \
		.ops = &stm32_pwr_reg_ops, \
		.enable_mask = _en, \
		.owner = THIS_MODULE, \
		.supply_name = _supply, \
	} \

static const struct regulator_desc stm32_pwr_desc[] = {
	PWR_REG(PWR_REG11, "reg11", 1100000, REG_1_1_EN, "vdd"),
	PWR_REG(PWR_REG18, "reg18", 1800000, REG_1_8_EN, "vdd"),
	PWR_REG(PWR_USB33, "usb33", 3300000, USB_3_3_EN, "vdd_3v3_usbfs"),
};

static int stm32_pwr_regulator_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct stm32_pwr_reg *priv;
	void __iomem *base;
	struct regulator_dev *rdev;
	struct regulator_config config = { };
	int i, ret = 0;

	base = of_iomap(np, 0);
	if (!base) {
		dev_err(&pdev->dev, "Unable to map IO memory\n");
		return -ENOMEM;
	}

	config.dev = &pdev->dev;

	for (i = 0; i < STM32PWR_REG_NUM_REGS; i++) {
		priv = devm_kzalloc(&pdev->dev, sizeof(struct stm32_pwr_reg),
				    GFP_KERNEL);
		if (!priv)
			return -ENOMEM;
		priv->base = base;
		priv->ready_mask = ready_mask_table[i];
		config.driver_data = priv;

		rdev = devm_regulator_register(&pdev->dev,
					       &stm32_pwr_desc[i],
					       &config);
		if (IS_ERR(rdev)) {
			ret = PTR_ERR(rdev);
			dev_err(&pdev->dev,
				"Failed to register regulator: %d\n", ret);
			break;
		}
	}
	return ret;
}

static const struct of_device_id stm32_pwr_of_match[] = {
	{ .compatible = "st,stm32mp1,pwr-reg", },
	{},
};
MODULE_DEVICE_TABLE(of, stm32_pwr_of_match);

static struct platform_driver stm32_pwr_driver = {
	.probe = stm32_pwr_regulator_probe,
	.driver = {
		.name  = "stm32-pwr-regulator",
		.of_match_table = of_match_ptr(stm32_pwr_of_match),
	},
};
module_platform_driver(stm32_pwr_driver);

MODULE_DESCRIPTION("STM32MP1 PWR voltage regulator driver");
MODULE_AUTHOR("Pascal Paillet <p.paillet@st.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
6cdae817 PPL	1	// SPDX-License-Identifier: GPL-2.0
	2	// Copyright (C) STMicroelectronics 2019
	3	// Authors: Gabriel Fernandez <gabriel.fernandez@st.com>
	4	// Pascal Paillet <p.paillet@st.com>.
	5
	6	#include <linux/io.h>
	7	#include <linux/iopoll.h>
	8	#include <linux/module.h>
	9	#include <linux/of_address.h>
	10	#include <linux/of_device.h>
	11	#include <linux/platform_device.h>
	12	#include <linux/regulator/driver.h>
	13	#include <linux/regulator/of_regulator.h>
	14
	15	/*
	16	* Registers description
	17	*/
	18	#define REG_PWR_CR3 0x0C
	19
	20	#define USB_3_3_EN BIT(24)
	21	#define USB_3_3_RDY BIT(26)
	22	#define REG_1_8_EN BIT(28)
	23	#define REG_1_8_RDY BIT(29)
	24	#define REG_1_1_EN BIT(30)
	25	#define REG_1_1_RDY BIT(31)
	26
	27	/* list of supported regulators */
	28	enum {
	29	PWR_REG11,
	30	PWR_REG18,
	31	PWR_USB33,
	32	STM32PWR_REG_NUM_REGS
	33	};
	34
82f26185	35	static u32 ready_mask_table[STM32PWR_REG_NUM_REGS] = {
6cdae817 PPL	36	[PWR_REG11] = REG_1_1_RDY,
	37	[PWR_REG18] = REG_1_8_RDY,
	38	[PWR_USB33] = USB_3_3_RDY,
	39	};
	40
	41	struct stm32_pwr_reg {
	42	void __iomem *base;
6cdae817 PPL	43	u32 ready_mask;
	44	};
	45
82f26185	46	static int stm32_pwr_reg_is_ready(struct regulator_dev *rdev)
6cdae817 PPL	47	{
	48	struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
	49	u32 val;
	50
	51	val = readl_relaxed(priv->base + REG_PWR_CR3);
	52
	53	return (val & priv->ready_mask);
	54	}
	55
82f26185	56	static int stm32_pwr_reg_is_enabled(struct regulator_dev *rdev)
6cdae817 PPL	57	{
	58	struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
	59	u32 val;
	60
	61	val = readl_relaxed(priv->base + REG_PWR_CR3);
	62
7bcbdbe0	63	return (val & rdev->desc->enable_mask);
6cdae817 PPL	64	}
	65
	66	static int stm32_pwr_reg_enable(struct regulator_dev *rdev)
	67	{
	68	struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
	69	int ret;
	70	u32 val;
	71
	72	val = readl_relaxed(priv->base + REG_PWR_CR3);
7bcbdbe0	73	val \|= rdev->desc->enable_mask;
6cdae817 PPL	74	writel_relaxed(val, priv->base + REG_PWR_CR3);
	75
	76	/* use an arbitrary timeout of 20ms */
	77	ret = readx_poll_timeout(stm32_pwr_reg_is_ready, rdev, val, val,
	78	100, 20 * 1000);
	79	if (ret)
	80	dev_err(&rdev->dev, "regulator enable timed out!\n");
	81
	82	return ret;
	83	}
	84
	85	static int stm32_pwr_reg_disable(struct regulator_dev *rdev)
	86	{
	87	struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
	88	int ret;
	89	u32 val;
	90
	91	val = readl_relaxed(priv->base + REG_PWR_CR3);
7bcbdbe0	92	val &= ~rdev->desc->enable_mask;
6cdae817 PPL	93	writel_relaxed(val, priv->base + REG_PWR_CR3);
	94
	95	/* use an arbitrary timeout of 20ms */
	96	ret = readx_poll_timeout(stm32_pwr_reg_is_ready, rdev, val, !val,
	97	100, 20 * 1000);
	98	if (ret)
	99	dev_err(&rdev->dev, "regulator disable timed out!\n");
	100
	101	return ret;
	102	}
	103
	104	static const struct regulator_ops stm32_pwr_reg_ops = {
6cdae817 PPL	105	.enable = stm32_pwr_reg_enable,
	106	.disable = stm32_pwr_reg_disable,
	107	.is_enabled = stm32_pwr_reg_is_enabled,
	108	};
	109
	110	#define PWR_REG(_id, _name, _volt, _en, _supply) \
	111	[_id] = { \
	112	.id = _id, \
	113	.name = _name, \
	114	.of_match = of_match_ptr(_name), \
	115	.n_voltages = 1, \
	116	.type = REGULATOR_VOLTAGE, \
6cdae817 PPL	117	.fixed_uV = _volt, \
	118	.ops = &stm32_pwr_reg_ops, \
	119	.enable_mask = _en, \
	120	.owner = THIS_MODULE, \
	121	.supply_name = _supply, \
	122	} \
	123
	124	static const struct regulator_desc stm32_pwr_desc[] = {
	125	PWR_REG(PWR_REG11, "reg11", 1100000, REG_1_1_EN, "vdd"),
	126	PWR_REG(PWR_REG18, "reg18", 1800000, REG_1_8_EN, "vdd"),
	127	PWR_REG(PWR_USB33, "usb33", 3300000, USB_3_3_EN, "vdd_3v3_usbfs"),
	128	};
	129
	130	static int stm32_pwr_regulator_probe(struct platform_device *pdev)
	131	{
	132	struct device_node *np = pdev->dev.of_node;
	133	struct stm32_pwr_reg *priv;
	134	void __iomem *base;
	135	struct regulator_dev *rdev;
	136	struct regulator_config config = { };
	137	int i, ret = 0;
	138
	139	base = of_iomap(np, 0);
dc62f951	140	if (!base) {
6cdae817	141	dev_err(&pdev->dev, "Unable to map IO memory\n");
dc62f951	142	return -ENOMEM;
6cdae817 PPL	143	}
	144
	145	config.dev = &pdev->dev;
	146
	147	for (i = 0; i < STM32PWR_REG_NUM_REGS; i++) {
	148	priv = devm_kzalloc(&pdev->dev, sizeof(struct stm32_pwr_reg),
	149	GFP_KERNEL);
	150	if (!priv)
	151	return -ENOMEM;
	152	priv->base = base;
6cdae817 PPL	153	priv->ready_mask = ready_mask_table[i];
	154	config.driver_data = priv;
	155
	156	rdev = devm_regulator_register(&pdev->dev,
	157	&stm32_pwr_desc[i],
	158	&config);
	159	if (IS_ERR(rdev)) {
	160	ret = PTR_ERR(rdev);
	161	dev_err(&pdev->dev,
	162	"Failed to register regulator: %d\n", ret);
	163	break;
	164	}
	165	}
	166	return ret;
	167	}
	168
	169	static const struct of_device_id stm32_pwr_of_match[] = {
	170	{ .compatible = "st,stm32mp1,pwr-reg", },
	171	{},
	172	};
	173	MODULE_DEVICE_TABLE(of, stm32_pwr_of_match);
	174
	175	static struct platform_driver stm32_pwr_driver = {
	176	.probe = stm32_pwr_regulator_probe,
	177	.driver = {
	178	.name = "stm32-pwr-regulator",
	179	.of_match_table = of_match_ptr(stm32_pwr_of_match),
	180	},
	181	};
	182	module_platform_driver(stm32_pwr_driver);
	183
	184	MODULE_DESCRIPTION("STM32MP1 PWR voltage regulator driver");
	185	MODULE_AUTHOR("Pascal Paillet <p.paillet@st.com>");
	186	MODULE_LICENSE("GPL v2");