]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - drivers/regulator/tps65910-regulator.c
Merge tag 'omap-for-v5.8/dt-missed-signed' of git://git.kernel.org/pub/scm/linux...
[mirror_ubuntu-hirsute-kernel.git] / drivers / regulator / tps65910-regulator.c
CommitLineData
2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
518fb721
GG
2/*
3 * tps65910.c -- TI tps65910
4 *
5 * Copyright 2010 Texas Instruments Inc.
6 *
7 * Author: Graeme Gregory <gg@slimlogic.co.uk>
8 * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
518fb721
GG
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/err.h>
d16da513 15#include <linux/of.h>
518fb721
GG
16#include <linux/platform_device.h>
17#include <linux/regulator/driver.h>
18#include <linux/regulator/machine.h>
518fb721
GG
19#include <linux/slab.h>
20#include <linux/gpio.h>
21#include <linux/mfd/tps65910.h>
6790178f 22#include <linux/regulator/of_regulator.h>
518fb721 23
518fb721 24#define TPS65910_SUPPLY_STATE_ENABLED 0x1
1e0c66f4
LD
25#define EXT_SLEEP_CONTROL (TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 | \
26 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 | \
f30b0716
LD
27 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 | \
28 TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP)
518fb721 29
d9fe28f9
AL
30/* supported VIO voltages in microvolts */
31static const unsigned int VIO_VSEL_table[] = {
32 1500000, 1800000, 2500000, 3300000,
518fb721
GG
33};
34
a320e3c3
JEC
35/* VSEL tables for TPS65910 specific LDOs and dcdc's */
36
a9a5659a
AC
37/* supported VRTC voltages in microvolts */
38static const unsigned int VRTC_VSEL_table[] = {
39 1800000,
40};
41
d9fe28f9
AL
42/* supported VDD3 voltages in microvolts */
43static const unsigned int VDD3_VSEL_table[] = {
44 5000000,
518fb721
GG
45};
46
d9fe28f9
AL
47/* supported VDIG1 voltages in microvolts */
48static const unsigned int VDIG1_VSEL_table[] = {
49 1200000, 1500000, 1800000, 2700000,
518fb721
GG
50};
51
d9fe28f9
AL
52/* supported VDIG2 voltages in microvolts */
53static const unsigned int VDIG2_VSEL_table[] = {
54 1000000, 1100000, 1200000, 1800000,
518fb721
GG
55};
56
d9fe28f9
AL
57/* supported VPLL voltages in microvolts */
58static const unsigned int VPLL_VSEL_table[] = {
59 1000000, 1100000, 1800000, 2500000,
518fb721
GG
60};
61
d9fe28f9
AL
62/* supported VDAC voltages in microvolts */
63static const unsigned int VDAC_VSEL_table[] = {
64 1800000, 2600000, 2800000, 2850000,
518fb721
GG
65};
66
d9fe28f9
AL
67/* supported VAUX1 voltages in microvolts */
68static const unsigned int VAUX1_VSEL_table[] = {
69 1800000, 2500000, 2800000, 2850000,
518fb721
GG
70};
71
d9fe28f9
AL
72/* supported VAUX2 voltages in microvolts */
73static const unsigned int VAUX2_VSEL_table[] = {
74 1800000, 2800000, 2900000, 3300000,
518fb721
GG
75};
76
d9fe28f9
AL
77/* supported VAUX33 voltages in microvolts */
78static const unsigned int VAUX33_VSEL_table[] = {
79 1800000, 2000000, 2800000, 3300000,
518fb721
GG
80};
81
d9fe28f9
AL
82/* supported VMMC voltages in microvolts */
83static const unsigned int VMMC_VSEL_table[] = {
84 1800000, 2800000, 3000000, 3300000,
518fb721
GG
85};
86
03746dcb
MP
87/* supported BBCH voltages in microvolts */
88static const unsigned int VBB_VSEL_table[] = {
89 3000000, 2520000, 3150000, 5000000,
90};
91
518fb721
GG
92struct tps_info {
93 const char *name;
19228a6a 94 const char *vin_name;
7d38a3cb 95 u8 n_voltages;
d9fe28f9 96 const unsigned int *voltage_table;
0651eed5 97 int enable_time_us;
518fb721
GG
98};
99
100static struct tps_info tps65910_regs[] = {
101 {
33a6943d 102 .name = "vrtc",
19228a6a 103 .vin_name = "vcc7",
a9a5659a
AC
104 .n_voltages = ARRAY_SIZE(VRTC_VSEL_table),
105 .voltage_table = VRTC_VSEL_table,
0651eed5 106 .enable_time_us = 2200,
518fb721
GG
107 },
108 {
33a6943d 109 .name = "vio",
19228a6a 110 .vin_name = "vccio",
7d38a3cb
LD
111 .n_voltages = ARRAY_SIZE(VIO_VSEL_table),
112 .voltage_table = VIO_VSEL_table,
0651eed5 113 .enable_time_us = 350,
518fb721
GG
114 },
115 {
33a6943d 116 .name = "vdd1",
19228a6a 117 .vin_name = "vcc1",
0651eed5 118 .enable_time_us = 350,
518fb721
GG
119 },
120 {
33a6943d 121 .name = "vdd2",
19228a6a 122 .vin_name = "vcc2",
0651eed5 123 .enable_time_us = 350,
518fb721
GG
124 },
125 {
33a6943d 126 .name = "vdd3",
7d38a3cb
LD
127 .n_voltages = ARRAY_SIZE(VDD3_VSEL_table),
128 .voltage_table = VDD3_VSEL_table,
0651eed5 129 .enable_time_us = 200,
518fb721
GG
130 },
131 {
33a6943d 132 .name = "vdig1",
19228a6a 133 .vin_name = "vcc6",
7d38a3cb
LD
134 .n_voltages = ARRAY_SIZE(VDIG1_VSEL_table),
135 .voltage_table = VDIG1_VSEL_table,
0651eed5 136 .enable_time_us = 100,
518fb721
GG
137 },
138 {
33a6943d 139 .name = "vdig2",
19228a6a 140 .vin_name = "vcc6",
7d38a3cb
LD
141 .n_voltages = ARRAY_SIZE(VDIG2_VSEL_table),
142 .voltage_table = VDIG2_VSEL_table,
0651eed5 143 .enable_time_us = 100,
518fb721
GG
144 },
145 {
33a6943d 146 .name = "vpll",
19228a6a 147 .vin_name = "vcc5",
7d38a3cb
LD
148 .n_voltages = ARRAY_SIZE(VPLL_VSEL_table),
149 .voltage_table = VPLL_VSEL_table,
0651eed5 150 .enable_time_us = 100,
518fb721
GG
151 },
152 {
33a6943d 153 .name = "vdac",
19228a6a 154 .vin_name = "vcc5",
7d38a3cb
LD
155 .n_voltages = ARRAY_SIZE(VDAC_VSEL_table),
156 .voltage_table = VDAC_VSEL_table,
0651eed5 157 .enable_time_us = 100,
518fb721
GG
158 },
159 {
33a6943d 160 .name = "vaux1",
19228a6a 161 .vin_name = "vcc4",
7d38a3cb
LD
162 .n_voltages = ARRAY_SIZE(VAUX1_VSEL_table),
163 .voltage_table = VAUX1_VSEL_table,
0651eed5 164 .enable_time_us = 100,
518fb721
GG
165 },
166 {
33a6943d 167 .name = "vaux2",
19228a6a 168 .vin_name = "vcc4",
7d38a3cb
LD
169 .n_voltages = ARRAY_SIZE(VAUX2_VSEL_table),
170 .voltage_table = VAUX2_VSEL_table,
0651eed5 171 .enable_time_us = 100,
518fb721
GG
172 },
173 {
33a6943d 174 .name = "vaux33",
19228a6a 175 .vin_name = "vcc3",
7d38a3cb
LD
176 .n_voltages = ARRAY_SIZE(VAUX33_VSEL_table),
177 .voltage_table = VAUX33_VSEL_table,
0651eed5 178 .enable_time_us = 100,
518fb721
GG
179 },
180 {
33a6943d 181 .name = "vmmc",
19228a6a 182 .vin_name = "vcc3",
7d38a3cb
LD
183 .n_voltages = ARRAY_SIZE(VMMC_VSEL_table),
184 .voltage_table = VMMC_VSEL_table,
0651eed5 185 .enable_time_us = 100,
518fb721 186 },
03746dcb
MP
187 {
188 .name = "vbb",
189 .vin_name = "vcc7",
190 .n_voltages = ARRAY_SIZE(VBB_VSEL_table),
191 .voltage_table = VBB_VSEL_table,
192 },
518fb721
GG
193};
194
a320e3c3 195static struct tps_info tps65911_regs[] = {
c2f8efd7 196 {
33a6943d 197 .name = "vrtc",
19228a6a 198 .vin_name = "vcc7",
0651eed5 199 .enable_time_us = 2200,
c2f8efd7 200 },
a320e3c3 201 {
33a6943d 202 .name = "vio",
19228a6a 203 .vin_name = "vccio",
7d38a3cb
LD
204 .n_voltages = ARRAY_SIZE(VIO_VSEL_table),
205 .voltage_table = VIO_VSEL_table,
0651eed5 206 .enable_time_us = 350,
a320e3c3
JEC
207 },
208 {
33a6943d 209 .name = "vdd1",
19228a6a 210 .vin_name = "vcc1",
7be53188 211 .n_voltages = 0x4C,
0651eed5 212 .enable_time_us = 350,
a320e3c3
JEC
213 },
214 {
33a6943d 215 .name = "vdd2",
19228a6a 216 .vin_name = "vcc2",
7be53188 217 .n_voltages = 0x4C,
0651eed5 218 .enable_time_us = 350,
a320e3c3
JEC
219 },
220 {
33a6943d 221 .name = "vddctrl",
7be53188 222 .n_voltages = 0x44,
0651eed5 223 .enable_time_us = 900,
a320e3c3
JEC
224 },
225 {
33a6943d 226 .name = "ldo1",
19228a6a 227 .vin_name = "vcc6",
7be53188 228 .n_voltages = 0x33,
0651eed5 229 .enable_time_us = 420,
a320e3c3
JEC
230 },
231 {
33a6943d 232 .name = "ldo2",
19228a6a 233 .vin_name = "vcc6",
7be53188 234 .n_voltages = 0x33,
0651eed5 235 .enable_time_us = 420,
a320e3c3
JEC
236 },
237 {
33a6943d 238 .name = "ldo3",
19228a6a 239 .vin_name = "vcc5",
7be53188 240 .n_voltages = 0x1A,
0651eed5 241 .enable_time_us = 230,
a320e3c3
JEC
242 },
243 {
33a6943d 244 .name = "ldo4",
19228a6a 245 .vin_name = "vcc5",
7be53188 246 .n_voltages = 0x33,
0651eed5 247 .enable_time_us = 230,
a320e3c3
JEC
248 },
249 {
33a6943d 250 .name = "ldo5",
19228a6a 251 .vin_name = "vcc4",
7be53188 252 .n_voltages = 0x1A,
0651eed5 253 .enable_time_us = 230,
a320e3c3
JEC
254 },
255 {
33a6943d 256 .name = "ldo6",
19228a6a 257 .vin_name = "vcc3",
7be53188 258 .n_voltages = 0x1A,
0651eed5 259 .enable_time_us = 230,
a320e3c3
JEC
260 },
261 {
33a6943d 262 .name = "ldo7",
19228a6a 263 .vin_name = "vcc3",
7be53188 264 .n_voltages = 0x1A,
0651eed5 265 .enable_time_us = 230,
a320e3c3
JEC
266 },
267 {
33a6943d 268 .name = "ldo8",
19228a6a 269 .vin_name = "vcc3",
7be53188 270 .n_voltages = 0x1A,
0651eed5 271 .enable_time_us = 230,
a320e3c3
JEC
272 },
273};
274
1e0c66f4
LD
275#define EXT_CONTROL_REG_BITS(id, regs_offs, bits) (((regs_offs) << 8) | (bits))
276static unsigned int tps65910_ext_sleep_control[] = {
277 0,
278 EXT_CONTROL_REG_BITS(VIO, 1, 0),
279 EXT_CONTROL_REG_BITS(VDD1, 1, 1),
280 EXT_CONTROL_REG_BITS(VDD2, 1, 2),
281 EXT_CONTROL_REG_BITS(VDD3, 1, 3),
282 EXT_CONTROL_REG_BITS(VDIG1, 0, 1),
283 EXT_CONTROL_REG_BITS(VDIG2, 0, 2),
284 EXT_CONTROL_REG_BITS(VPLL, 0, 6),
285 EXT_CONTROL_REG_BITS(VDAC, 0, 7),
286 EXT_CONTROL_REG_BITS(VAUX1, 0, 3),
287 EXT_CONTROL_REG_BITS(VAUX2, 0, 4),
288 EXT_CONTROL_REG_BITS(VAUX33, 0, 5),
289 EXT_CONTROL_REG_BITS(VMMC, 0, 0),
290};
291
292static unsigned int tps65911_ext_sleep_control[] = {
293 0,
294 EXT_CONTROL_REG_BITS(VIO, 1, 0),
295 EXT_CONTROL_REG_BITS(VDD1, 1, 1),
296 EXT_CONTROL_REG_BITS(VDD2, 1, 2),
297 EXT_CONTROL_REG_BITS(VDDCTRL, 1, 3),
298 EXT_CONTROL_REG_BITS(LDO1, 0, 1),
299 EXT_CONTROL_REG_BITS(LDO2, 0, 2),
300 EXT_CONTROL_REG_BITS(LDO3, 0, 7),
301 EXT_CONTROL_REG_BITS(LDO4, 0, 6),
302 EXT_CONTROL_REG_BITS(LDO5, 0, 3),
303 EXT_CONTROL_REG_BITS(LDO6, 0, 0),
304 EXT_CONTROL_REG_BITS(LDO7, 0, 5),
305 EXT_CONTROL_REG_BITS(LDO8, 0, 4),
306};
307
518fb721 308struct tps65910_reg {
39aa9b6e 309 struct regulator_desc *desc;
518fb721 310 struct tps65910 *mfd;
39aa9b6e
AL
311 struct regulator_dev **rdev;
312 struct tps_info **info;
39aa9b6e 313 int num_regulators;
518fb721 314 int mode;
a320e3c3 315 int (*get_ctrl_reg)(int);
1e0c66f4
LD
316 unsigned int *ext_sleep_control;
317 unsigned int board_ext_control[TPS65910_NUM_REGS];
518fb721
GG
318};
319
518fb721
GG
320static int tps65910_get_ctrl_register(int id)
321{
322 switch (id) {
323 case TPS65910_REG_VRTC:
324 return TPS65910_VRTC;
325 case TPS65910_REG_VIO:
326 return TPS65910_VIO;
327 case TPS65910_REG_VDD1:
328 return TPS65910_VDD1;
329 case TPS65910_REG_VDD2:
330 return TPS65910_VDD2;
331 case TPS65910_REG_VDD3:
332 return TPS65910_VDD3;
333 case TPS65910_REG_VDIG1:
334 return TPS65910_VDIG1;
335 case TPS65910_REG_VDIG2:
336 return TPS65910_VDIG2;
337 case TPS65910_REG_VPLL:
338 return TPS65910_VPLL;
339 case TPS65910_REG_VDAC:
340 return TPS65910_VDAC;
341 case TPS65910_REG_VAUX1:
342 return TPS65910_VAUX1;
343 case TPS65910_REG_VAUX2:
344 return TPS65910_VAUX2;
345 case TPS65910_REG_VAUX33:
346 return TPS65910_VAUX33;
347 case TPS65910_REG_VMMC:
348 return TPS65910_VMMC;
03746dcb
MP
349 case TPS65910_REG_VBB:
350 return TPS65910_BBCH;
518fb721
GG
351 default:
352 return -EINVAL;
353 }
354}
355
a320e3c3
JEC
356static int tps65911_get_ctrl_register(int id)
357{
358 switch (id) {
359 case TPS65910_REG_VRTC:
360 return TPS65910_VRTC;
361 case TPS65910_REG_VIO:
362 return TPS65910_VIO;
363 case TPS65910_REG_VDD1:
364 return TPS65910_VDD1;
365 case TPS65910_REG_VDD2:
366 return TPS65910_VDD2;
367 case TPS65911_REG_VDDCTRL:
368 return TPS65911_VDDCTRL;
369 case TPS65911_REG_LDO1:
370 return TPS65911_LDO1;
371 case TPS65911_REG_LDO2:
372 return TPS65911_LDO2;
373 case TPS65911_REG_LDO3:
374 return TPS65911_LDO3;
375 case TPS65911_REG_LDO4:
376 return TPS65911_LDO4;
377 case TPS65911_REG_LDO5:
378 return TPS65911_LDO5;
379 case TPS65911_REG_LDO6:
380 return TPS65911_LDO6;
381 case TPS65911_REG_LDO7:
382 return TPS65911_LDO7;
383 case TPS65911_REG_LDO8:
384 return TPS65911_LDO8;
385 default:
386 return -EINVAL;
387 }
388}
389
518fb721
GG
390static int tps65910_set_mode(struct regulator_dev *dev, unsigned int mode)
391{
392 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
393 struct tps65910 *mfd = pmic->mfd;
394 int reg, value, id = rdev_get_id(dev);
a320e3c3
JEC
395
396 reg = pmic->get_ctrl_reg(id);
518fb721
GG
397 if (reg < 0)
398 return reg;
399
400 switch (mode) {
401 case REGULATOR_MODE_NORMAL:
faa95fde
AL
402 return tps65910_reg_update_bits(pmic->mfd, reg,
403 LDO_ST_MODE_BIT | LDO_ST_ON_BIT,
404 LDO_ST_ON_BIT);
518fb721
GG
405 case REGULATOR_MODE_IDLE:
406 value = LDO_ST_ON_BIT | LDO_ST_MODE_BIT;
3f7e8275 407 return tps65910_reg_set_bits(mfd, reg, value);
518fb721 408 case REGULATOR_MODE_STANDBY:
3f7e8275 409 return tps65910_reg_clear_bits(mfd, reg, LDO_ST_ON_BIT);
518fb721
GG
410 }
411
412 return -EINVAL;
413}
414
415static unsigned int tps65910_get_mode(struct regulator_dev *dev)
416{
417 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
faa95fde 418 int ret, reg, value, id = rdev_get_id(dev);
518fb721 419
a320e3c3 420 reg = pmic->get_ctrl_reg(id);
518fb721
GG
421 if (reg < 0)
422 return reg;
423
faa95fde
AL
424 ret = tps65910_reg_read(pmic->mfd, reg, &value);
425 if (ret < 0)
426 return ret;
518fb721 427
58599393 428 if (!(value & LDO_ST_ON_BIT))
518fb721
GG
429 return REGULATOR_MODE_STANDBY;
430 else if (value & LDO_ST_MODE_BIT)
431 return REGULATOR_MODE_IDLE;
432 else
433 return REGULATOR_MODE_NORMAL;
434}
435
18039e0f 436static int tps65910_get_voltage_dcdc_sel(struct regulator_dev *dev)
518fb721
GG
437{
438 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
faa95fde 439 int ret, id = rdev_get_id(dev);
a320e3c3 440 int opvsel = 0, srvsel = 0, vselmax = 0, mult = 0, sr = 0;
518fb721
GG
441
442 switch (id) {
443 case TPS65910_REG_VDD1:
faa95fde
AL
444 ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD1_OP, &opvsel);
445 if (ret < 0)
446 return ret;
447 ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD1, &mult);
448 if (ret < 0)
449 return ret;
518fb721 450 mult = (mult & VDD1_VGAIN_SEL_MASK) >> VDD1_VGAIN_SEL_SHIFT;
faa95fde
AL
451 ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD1_SR, &srvsel);
452 if (ret < 0)
453 return ret;
518fb721
GG
454 sr = opvsel & VDD1_OP_CMD_MASK;
455 opvsel &= VDD1_OP_SEL_MASK;
456 srvsel &= VDD1_SR_SEL_MASK;
a320e3c3 457 vselmax = 75;
518fb721
GG
458 break;
459 case TPS65910_REG_VDD2:
faa95fde
AL
460 ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD2_OP, &opvsel);
461 if (ret < 0)
462 return ret;
463 ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD2, &mult);
464 if (ret < 0)
465 return ret;
518fb721 466 mult = (mult & VDD2_VGAIN_SEL_MASK) >> VDD2_VGAIN_SEL_SHIFT;
faa95fde
AL
467 ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD2_SR, &srvsel);
468 if (ret < 0)
469 return ret;
518fb721
GG
470 sr = opvsel & VDD2_OP_CMD_MASK;
471 opvsel &= VDD2_OP_SEL_MASK;
472 srvsel &= VDD2_SR_SEL_MASK;
a320e3c3
JEC
473 vselmax = 75;
474 break;
475 case TPS65911_REG_VDDCTRL:
faa95fde
AL
476 ret = tps65910_reg_read(pmic->mfd, TPS65911_VDDCTRL_OP,
477 &opvsel);
478 if (ret < 0)
479 return ret;
480 ret = tps65910_reg_read(pmic->mfd, TPS65911_VDDCTRL_SR,
481 &srvsel);
482 if (ret < 0)
483 return ret;
a320e3c3
JEC
484 sr = opvsel & VDDCTRL_OP_CMD_MASK;
485 opvsel &= VDDCTRL_OP_SEL_MASK;
486 srvsel &= VDDCTRL_SR_SEL_MASK;
487 vselmax = 64;
518fb721
GG
488 break;
489 }
490
491 /* multiplier 0 == 1 but 2,3 normal */
492 if (!mult)
4b579270 493 mult = 1;
518fb721
GG
494
495 if (sr) {
a320e3c3
JEC
496 /* normalise to valid range */
497 if (srvsel < 3)
498 srvsel = 3;
499 if (srvsel > vselmax)
500 srvsel = vselmax;
18039e0f 501 return srvsel - 3;
518fb721
GG
502 } else {
503
a320e3c3
JEC
504 /* normalise to valid range*/
505 if (opvsel < 3)
506 opvsel = 3;
507 if (opvsel > vselmax)
508 opvsel = vselmax;
18039e0f 509 return opvsel - 3;
518fb721 510 }
18039e0f 511 return -EINVAL;
518fb721
GG
512}
513
1f904fd1 514static int tps65910_get_voltage_sel(struct regulator_dev *dev)
518fb721
GG
515{
516 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
faa95fde 517 int ret, reg, value, id = rdev_get_id(dev);
518fb721 518
a320e3c3 519 reg = pmic->get_ctrl_reg(id);
518fb721
GG
520 if (reg < 0)
521 return reg;
522
faa95fde
AL
523 ret = tps65910_reg_read(pmic->mfd, reg, &value);
524 if (ret < 0)
525 return ret;
518fb721
GG
526
527 switch (id) {
528 case TPS65910_REG_VIO:
529 case TPS65910_REG_VDIG1:
530 case TPS65910_REG_VDIG2:
531 case TPS65910_REG_VPLL:
532 case TPS65910_REG_VDAC:
533 case TPS65910_REG_VAUX1:
534 case TPS65910_REG_VAUX2:
535 case TPS65910_REG_VAUX33:
536 case TPS65910_REG_VMMC:
537 value &= LDO_SEL_MASK;
538 value >>= LDO_SEL_SHIFT;
539 break;
03746dcb
MP
540 case TPS65910_REG_VBB:
541 value &= BBCH_BBSEL_MASK;
542 value >>= BBCH_BBSEL_SHIFT;
543 break;
518fb721
GG
544 default:
545 return -EINVAL;
546 }
547
1f904fd1 548 return value;
518fb721
GG
549}
550
551static int tps65910_get_voltage_vdd3(struct regulator_dev *dev)
552{
d9fe28f9 553 return dev->desc->volt_table[0];
518fb721
GG
554}
555
1f904fd1 556static int tps65911_get_voltage_sel(struct regulator_dev *dev)
a320e3c3
JEC
557{
558 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
faa95fde
AL
559 int ret, id = rdev_get_id(dev);
560 unsigned int value, reg;
a320e3c3
JEC
561
562 reg = pmic->get_ctrl_reg(id);
563
faa95fde
AL
564 ret = tps65910_reg_read(pmic->mfd, reg, &value);
565 if (ret < 0)
566 return ret;
a320e3c3
JEC
567
568 switch (id) {
569 case TPS65911_REG_LDO1:
570 case TPS65911_REG_LDO2:
571 case TPS65911_REG_LDO4:
572 value &= LDO1_SEL_MASK;
573 value >>= LDO_SEL_SHIFT;
a320e3c3
JEC
574 break;
575 case TPS65911_REG_LDO3:
576 case TPS65911_REG_LDO5:
577 case TPS65911_REG_LDO6:
578 case TPS65911_REG_LDO7:
579 case TPS65911_REG_LDO8:
580 value &= LDO3_SEL_MASK;
581 value >>= LDO_SEL_SHIFT;
a320e3c3
JEC
582 break;
583 case TPS65910_REG_VIO:
e882eae8
LD
584 value &= LDO_SEL_MASK;
585 value >>= LDO_SEL_SHIFT;
1f904fd1 586 break;
a320e3c3
JEC
587 default:
588 return -EINVAL;
589 }
590
1f904fd1 591 return value;
a320e3c3
JEC
592}
593
94732b97
AL
594static int tps65910_set_voltage_dcdc_sel(struct regulator_dev *dev,
595 unsigned selector)
518fb721
GG
596{
597 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
598 int id = rdev_get_id(dev), vsel;
a320e3c3 599 int dcdc_mult = 0;
518fb721 600
a320e3c3
JEC
601 switch (id) {
602 case TPS65910_REG_VDD1:
780dc9ba 603 dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
a320e3c3
JEC
604 if (dcdc_mult == 1)
605 dcdc_mult--;
780dc9ba 606 vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3;
518fb721 607
faa95fde
AL
608 tps65910_reg_update_bits(pmic->mfd, TPS65910_VDD1,
609 VDD1_VGAIN_SEL_MASK,
610 dcdc_mult << VDD1_VGAIN_SEL_SHIFT);
611 tps65910_reg_write(pmic->mfd, TPS65910_VDD1_OP, vsel);
a320e3c3
JEC
612 break;
613 case TPS65910_REG_VDD2:
780dc9ba 614 dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
a320e3c3
JEC
615 if (dcdc_mult == 1)
616 dcdc_mult--;
780dc9ba 617 vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3;
a320e3c3 618
faa95fde
AL
619 tps65910_reg_update_bits(pmic->mfd, TPS65910_VDD2,
620 VDD1_VGAIN_SEL_MASK,
621 dcdc_mult << VDD2_VGAIN_SEL_SHIFT);
622 tps65910_reg_write(pmic->mfd, TPS65910_VDD2_OP, vsel);
a320e3c3
JEC
623 break;
624 case TPS65911_REG_VDDCTRL:
c4632aed 625 vsel = selector + 3;
faa95fde 626 tps65910_reg_write(pmic->mfd, TPS65911_VDDCTRL_OP, vsel);
518fb721
GG
627 }
628
629 return 0;
630}
631
94732b97
AL
632static int tps65910_set_voltage_sel(struct regulator_dev *dev,
633 unsigned selector)
518fb721
GG
634{
635 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
636 int reg, id = rdev_get_id(dev);
637
a320e3c3 638 reg = pmic->get_ctrl_reg(id);
518fb721
GG
639 if (reg < 0)
640 return reg;
641
642 switch (id) {
643 case TPS65910_REG_VIO:
644 case TPS65910_REG_VDIG1:
645 case TPS65910_REG_VDIG2:
646 case TPS65910_REG_VPLL:
647 case TPS65910_REG_VDAC:
648 case TPS65910_REG_VAUX1:
649 case TPS65910_REG_VAUX2:
650 case TPS65910_REG_VAUX33:
651 case TPS65910_REG_VMMC:
faa95fde
AL
652 return tps65910_reg_update_bits(pmic->mfd, reg, LDO_SEL_MASK,
653 selector << LDO_SEL_SHIFT);
03746dcb
MP
654 case TPS65910_REG_VBB:
655 return tps65910_reg_update_bits(pmic->mfd, reg, BBCH_BBSEL_MASK,
656 selector << BBCH_BBSEL_SHIFT);
518fb721
GG
657 }
658
659 return -EINVAL;
660}
661
94732b97
AL
662static int tps65911_set_voltage_sel(struct regulator_dev *dev,
663 unsigned selector)
a320e3c3
JEC
664{
665 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
666 int reg, id = rdev_get_id(dev);
667
668 reg = pmic->get_ctrl_reg(id);
669 if (reg < 0)
670 return reg;
671
672 switch (id) {
673 case TPS65911_REG_LDO1:
674 case TPS65911_REG_LDO2:
675 case TPS65911_REG_LDO4:
faa95fde
AL
676 return tps65910_reg_update_bits(pmic->mfd, reg, LDO1_SEL_MASK,
677 selector << LDO_SEL_SHIFT);
a320e3c3
JEC
678 case TPS65911_REG_LDO3:
679 case TPS65911_REG_LDO5:
680 case TPS65911_REG_LDO6:
681 case TPS65911_REG_LDO7:
682 case TPS65911_REG_LDO8:
faa95fde
AL
683 return tps65910_reg_update_bits(pmic->mfd, reg, LDO3_SEL_MASK,
684 selector << LDO_SEL_SHIFT);
e882eae8 685 case TPS65910_REG_VIO:
faa95fde
AL
686 return tps65910_reg_update_bits(pmic->mfd, reg, LDO_SEL_MASK,
687 selector << LDO_SEL_SHIFT);
03746dcb
MP
688 case TPS65910_REG_VBB:
689 return tps65910_reg_update_bits(pmic->mfd, reg, BBCH_BBSEL_MASK,
690 selector << BBCH_BBSEL_SHIFT);
a320e3c3
JEC
691 }
692
693 return -EINVAL;
694}
695
696
518fb721
GG
697static int tps65910_list_voltage_dcdc(struct regulator_dev *dev,
698 unsigned selector)
699{
a320e3c3 700 int volt, mult = 1, id = rdev_get_id(dev);
518fb721 701
a320e3c3
JEC
702 switch (id) {
703 case TPS65910_REG_VDD1:
704 case TPS65910_REG_VDD2:
780dc9ba 705 mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
a320e3c3 706 volt = VDD1_2_MIN_VOLT +
4b579270 707 (selector % VDD1_2_NUM_VOLT_FINE) * VDD1_2_OFFSET;
d04156bc 708 break;
a320e3c3
JEC
709 case TPS65911_REG_VDDCTRL:
710 volt = VDDCTRL_MIN_VOLT + (selector * VDDCTRL_OFFSET);
d04156bc
AL
711 break;
712 default:
713 BUG();
714 return -EINVAL;
a320e3c3 715 }
518fb721
GG
716
717 return volt * 100 * mult;
718}
719
a320e3c3
JEC
720static int tps65911_list_voltage(struct regulator_dev *dev, unsigned selector)
721{
722 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
723 int step_mv = 0, id = rdev_get_id(dev);
724
4b579270 725 switch (id) {
a320e3c3
JEC
726 case TPS65911_REG_LDO1:
727 case TPS65911_REG_LDO2:
728 case TPS65911_REG_LDO4:
729 /* The first 5 values of the selector correspond to 1V */
730 if (selector < 5)
731 selector = 0;
732 else
733 selector -= 4;
734
735 step_mv = 50;
736 break;
737 case TPS65911_REG_LDO3:
738 case TPS65911_REG_LDO5:
739 case TPS65911_REG_LDO6:
740 case TPS65911_REG_LDO7:
741 case TPS65911_REG_LDO8:
742 /* The first 3 values of the selector correspond to 1V */
743 if (selector < 3)
744 selector = 0;
745 else
746 selector -= 2;
747
748 step_mv = 100;
749 break;
750 case TPS65910_REG_VIO:
d9fe28f9 751 return pmic->info[id]->voltage_table[selector];
a320e3c3
JEC
752 default:
753 return -EINVAL;
754 }
755
756 return (LDO_MIN_VOLT + selector * step_mv) * 1000;
757}
758
518fb721
GG
759/* Regulator ops (except VRTC) */
760static struct regulator_ops tps65910_ops_dcdc = {
a40a9c43
AL
761 .is_enabled = regulator_is_enabled_regmap,
762 .enable = regulator_enable_regmap,
763 .disable = regulator_disable_regmap,
518fb721
GG
764 .set_mode = tps65910_set_mode,
765 .get_mode = tps65910_get_mode,
18039e0f 766 .get_voltage_sel = tps65910_get_voltage_dcdc_sel,
94732b97 767 .set_voltage_sel = tps65910_set_voltage_dcdc_sel,
01bc3a14 768 .set_voltage_time_sel = regulator_set_voltage_time_sel,
518fb721 769 .list_voltage = tps65910_list_voltage_dcdc,
9fa8175f 770 .map_voltage = regulator_map_voltage_ascend,
518fb721
GG
771};
772
773static struct regulator_ops tps65910_ops_vdd3 = {
a40a9c43
AL
774 .is_enabled = regulator_is_enabled_regmap,
775 .enable = regulator_enable_regmap,
776 .disable = regulator_disable_regmap,
518fb721
GG
777 .set_mode = tps65910_set_mode,
778 .get_mode = tps65910_get_mode,
779 .get_voltage = tps65910_get_voltage_vdd3,
d9fe28f9 780 .list_voltage = regulator_list_voltage_table,
9fa8175f 781 .map_voltage = regulator_map_voltage_ascend,
518fb721
GG
782};
783
03746dcb
MP
784static struct regulator_ops tps65910_ops_vbb = {
785 .is_enabled = regulator_is_enabled_regmap,
786 .enable = regulator_enable_regmap,
787 .disable = regulator_disable_regmap,
788 .set_mode = tps65910_set_mode,
789 .get_mode = tps65910_get_mode,
790 .get_voltage_sel = tps65910_get_voltage_sel,
791 .set_voltage_sel = tps65910_set_voltage_sel,
792 .list_voltage = regulator_list_voltage_table,
793 .map_voltage = regulator_map_voltage_iterate,
794};
795
518fb721 796static struct regulator_ops tps65910_ops = {
a40a9c43
AL
797 .is_enabled = regulator_is_enabled_regmap,
798 .enable = regulator_enable_regmap,
799 .disable = regulator_disable_regmap,
518fb721
GG
800 .set_mode = tps65910_set_mode,
801 .get_mode = tps65910_get_mode,
1f904fd1 802 .get_voltage_sel = tps65910_get_voltage_sel,
94732b97 803 .set_voltage_sel = tps65910_set_voltage_sel,
d9fe28f9 804 .list_voltage = regulator_list_voltage_table,
9fa8175f 805 .map_voltage = regulator_map_voltage_ascend,
518fb721
GG
806};
807
a320e3c3 808static struct regulator_ops tps65911_ops = {
a40a9c43
AL
809 .is_enabled = regulator_is_enabled_regmap,
810 .enable = regulator_enable_regmap,
811 .disable = regulator_disable_regmap,
a320e3c3
JEC
812 .set_mode = tps65910_set_mode,
813 .get_mode = tps65910_get_mode,
1f904fd1 814 .get_voltage_sel = tps65911_get_voltage_sel,
94732b97 815 .set_voltage_sel = tps65911_set_voltage_sel,
a320e3c3 816 .list_voltage = tps65911_list_voltage,
9fa8175f 817 .map_voltage = regulator_map_voltage_ascend,
a320e3c3
JEC
818};
819
1e0c66f4
LD
820static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic,
821 int id, int ext_sleep_config)
822{
823 struct tps65910 *mfd = pmic->mfd;
824 u8 regoffs = (pmic->ext_sleep_control[id] >> 8) & 0xFF;
825 u8 bit_pos = (1 << pmic->ext_sleep_control[id] & 0xFF);
826 int ret;
827
828 /*
829 * Regulator can not be control from multiple external input EN1, EN2
830 * and EN3 together.
831 */
832 if (ext_sleep_config & EXT_SLEEP_CONTROL) {
833 int en_count;
834 en_count = ((ext_sleep_config &
835 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) != 0);
836 en_count += ((ext_sleep_config &
837 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) != 0);
838 en_count += ((ext_sleep_config &
839 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) != 0);
f30b0716
LD
840 en_count += ((ext_sleep_config &
841 TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) != 0);
1e0c66f4
LD
842 if (en_count > 1) {
843 dev_err(mfd->dev,
844 "External sleep control flag is not proper\n");
845 return -EINVAL;
846 }
847 }
848
849 pmic->board_ext_control[id] = ext_sleep_config;
850
851 /* External EN1 control */
852 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1)
3f7e8275 853 ret = tps65910_reg_set_bits(mfd,
1e0c66f4
LD
854 TPS65910_EN1_LDO_ASS + regoffs, bit_pos);
855 else
3f7e8275 856 ret = tps65910_reg_clear_bits(mfd,
1e0c66f4
LD
857 TPS65910_EN1_LDO_ASS + regoffs, bit_pos);
858 if (ret < 0) {
859 dev_err(mfd->dev,
860 "Error in configuring external control EN1\n");
861 return ret;
862 }
863
864 /* External EN2 control */
865 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2)
3f7e8275 866 ret = tps65910_reg_set_bits(mfd,
1e0c66f4
LD
867 TPS65910_EN2_LDO_ASS + regoffs, bit_pos);
868 else
3f7e8275 869 ret = tps65910_reg_clear_bits(mfd,
1e0c66f4
LD
870 TPS65910_EN2_LDO_ASS + regoffs, bit_pos);
871 if (ret < 0) {
872 dev_err(mfd->dev,
873 "Error in configuring external control EN2\n");
874 return ret;
875 }
876
877 /* External EN3 control for TPS65910 LDO only */
878 if ((tps65910_chip_id(mfd) == TPS65910) &&
879 (id >= TPS65910_REG_VDIG1)) {
880 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3)
3f7e8275 881 ret = tps65910_reg_set_bits(mfd,
1e0c66f4
LD
882 TPS65910_EN3_LDO_ASS + regoffs, bit_pos);
883 else
3f7e8275 884 ret = tps65910_reg_clear_bits(mfd,
1e0c66f4
LD
885 TPS65910_EN3_LDO_ASS + regoffs, bit_pos);
886 if (ret < 0) {
887 dev_err(mfd->dev,
888 "Error in configuring external control EN3\n");
889 return ret;
890 }
891 }
892
893 /* Return if no external control is selected */
894 if (!(ext_sleep_config & EXT_SLEEP_CONTROL)) {
895 /* Clear all sleep controls */
3f7e8275 896 ret = tps65910_reg_clear_bits(mfd,
1e0c66f4
LD
897 TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos);
898 if (!ret)
3f7e8275 899 ret = tps65910_reg_clear_bits(mfd,
1e0c66f4
LD
900 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
901 if (ret < 0)
902 dev_err(mfd->dev,
903 "Error in configuring SLEEP register\n");
904 return ret;
905 }
906
907 /*
908 * For regulator that has separate operational and sleep register make
909 * sure that operational is used and clear sleep register to turn
910 * regulator off when external control is inactive
911 */
912 if ((id == TPS65910_REG_VDD1) ||
913 (id == TPS65910_REG_VDD2) ||
914 ((id == TPS65911_REG_VDDCTRL) &&
915 (tps65910_chip_id(mfd) == TPS65911))) {
916 int op_reg_add = pmic->get_ctrl_reg(id) + 1;
917 int sr_reg_add = pmic->get_ctrl_reg(id) + 2;
faa95fde
AL
918 int opvsel, srvsel;
919
920 ret = tps65910_reg_read(pmic->mfd, op_reg_add, &opvsel);
921 if (ret < 0)
922 return ret;
923 ret = tps65910_reg_read(pmic->mfd, sr_reg_add, &srvsel);
924 if (ret < 0)
925 return ret;
926
1e0c66f4
LD
927 if (opvsel & VDD1_OP_CMD_MASK) {
928 u8 reg_val = srvsel & VDD1_OP_SEL_MASK;
faa95fde
AL
929
930 ret = tps65910_reg_write(pmic->mfd, op_reg_add,
931 reg_val);
1e0c66f4
LD
932 if (ret < 0) {
933 dev_err(mfd->dev,
934 "Error in configuring op register\n");
935 return ret;
936 }
937 }
faa95fde 938 ret = tps65910_reg_write(pmic->mfd, sr_reg_add, 0);
1e0c66f4 939 if (ret < 0) {
6d3be300 940 dev_err(mfd->dev, "Error in setting sr register\n");
1e0c66f4
LD
941 return ret;
942 }
943 }
944
3f7e8275 945 ret = tps65910_reg_clear_bits(mfd,
1e0c66f4 946 TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos);
f30b0716
LD
947 if (!ret) {
948 if (ext_sleep_config & TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP)
3f7e8275 949 ret = tps65910_reg_set_bits(mfd,
f30b0716
LD
950 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
951 else
3f7e8275 952 ret = tps65910_reg_clear_bits(mfd,
f30b0716
LD
953 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
954 }
1e0c66f4
LD
955 if (ret < 0)
956 dev_err(mfd->dev,
957 "Error in configuring SLEEP register\n");
f30b0716 958
1e0c66f4
LD
959 return ret;
960}
961
6790178f
RK
962#ifdef CONFIG_OF
963
964static struct of_regulator_match tps65910_matches[] = {
33a6943d
LD
965 { .name = "vrtc", .driver_data = (void *) &tps65910_regs[0] },
966 { .name = "vio", .driver_data = (void *) &tps65910_regs[1] },
967 { .name = "vdd1", .driver_data = (void *) &tps65910_regs[2] },
968 { .name = "vdd2", .driver_data = (void *) &tps65910_regs[3] },
969 { .name = "vdd3", .driver_data = (void *) &tps65910_regs[4] },
970 { .name = "vdig1", .driver_data = (void *) &tps65910_regs[5] },
971 { .name = "vdig2", .driver_data = (void *) &tps65910_regs[6] },
972 { .name = "vpll", .driver_data = (void *) &tps65910_regs[7] },
973 { .name = "vdac", .driver_data = (void *) &tps65910_regs[8] },
974 { .name = "vaux1", .driver_data = (void *) &tps65910_regs[9] },
975 { .name = "vaux2", .driver_data = (void *) &tps65910_regs[10] },
976 { .name = "vaux33", .driver_data = (void *) &tps65910_regs[11] },
977 { .name = "vmmc", .driver_data = (void *) &tps65910_regs[12] },
03746dcb 978 { .name = "vbb", .driver_data = (void *) &tps65910_regs[13] },
6790178f
RK
979};
980
981static struct of_regulator_match tps65911_matches[] = {
33a6943d
LD
982 { .name = "vrtc", .driver_data = (void *) &tps65911_regs[0] },
983 { .name = "vio", .driver_data = (void *) &tps65911_regs[1] },
984 { .name = "vdd1", .driver_data = (void *) &tps65911_regs[2] },
985 { .name = "vdd2", .driver_data = (void *) &tps65911_regs[3] },
986 { .name = "vddctrl", .driver_data = (void *) &tps65911_regs[4] },
987 { .name = "ldo1", .driver_data = (void *) &tps65911_regs[5] },
988 { .name = "ldo2", .driver_data = (void *) &tps65911_regs[6] },
989 { .name = "ldo3", .driver_data = (void *) &tps65911_regs[7] },
990 { .name = "ldo4", .driver_data = (void *) &tps65911_regs[8] },
991 { .name = "ldo5", .driver_data = (void *) &tps65911_regs[9] },
992 { .name = "ldo6", .driver_data = (void *) &tps65911_regs[10] },
993 { .name = "ldo7", .driver_data = (void *) &tps65911_regs[11] },
994 { .name = "ldo8", .driver_data = (void *) &tps65911_regs[12] },
6790178f
RK
995};
996
997static struct tps65910_board *tps65910_parse_dt_reg_data(
84df8c12
LD
998 struct platform_device *pdev,
999 struct of_regulator_match **tps65910_reg_matches)
6790178f
RK
1000{
1001 struct tps65910_board *pmic_plat_data;
1002 struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent);
c92f5dd2 1003 struct device_node *np, *regulators;
6790178f
RK
1004 struct of_regulator_match *matches;
1005 unsigned int prop;
1006 int idx = 0, ret, count;
1007
1008 pmic_plat_data = devm_kzalloc(&pdev->dev, sizeof(*pmic_plat_data),
1009 GFP_KERNEL);
bcb2c0d6 1010 if (!pmic_plat_data)
6790178f 1011 return NULL;
6790178f 1012
b8b27a44 1013 np = pdev->dev.parent->of_node;
4ae1ff7f 1014 regulators = of_get_child_by_name(np, "regulators");
92ab953b
LD
1015 if (!regulators) {
1016 dev_err(&pdev->dev, "regulator node not found\n");
1017 return NULL;
1018 }
6790178f
RK
1019
1020 switch (tps65910_chip_id(tps65910)) {
1021 case TPS65910:
1022 count = ARRAY_SIZE(tps65910_matches);
1023 matches = tps65910_matches;
1024 break;
1025 case TPS65911:
1026 count = ARRAY_SIZE(tps65911_matches);
1027 matches = tps65911_matches;
1028 break;
1029 default:
c92f5dd2 1030 of_node_put(regulators);
7e9a57e6 1031 dev_err(&pdev->dev, "Invalid tps chip version\n");
6790178f
RK
1032 return NULL;
1033 }
1034
08337fda 1035 ret = of_regulator_match(&pdev->dev, regulators, matches, count);
c92f5dd2 1036 of_node_put(regulators);
6790178f
RK
1037 if (ret < 0) {
1038 dev_err(&pdev->dev, "Error parsing regulator init data: %d\n",
1039 ret);
1040 return NULL;
1041 }
1042
84df8c12
LD
1043 *tps65910_reg_matches = matches;
1044
6790178f 1045 for (idx = 0; idx < count; idx++) {
23b11348 1046 if (!matches[idx].of_node)
6790178f
RK
1047 continue;
1048
1049 pmic_plat_data->tps65910_pmic_init_data[idx] =
1050 matches[idx].init_data;
1051
1052 ret = of_property_read_u32(matches[idx].of_node,
1053 "ti,regulator-ext-sleep-control", &prop);
1054 if (!ret)
1055 pmic_plat_data->regulator_ext_sleep_control[idx] = prop;
19228a6a 1056
6790178f
RK
1057 }
1058
1059 return pmic_plat_data;
1060}
1061#else
1062static inline struct tps65910_board *tps65910_parse_dt_reg_data(
84df8c12
LD
1063 struct platform_device *pdev,
1064 struct of_regulator_match **tps65910_reg_matches)
6790178f 1065{
84df8c12 1066 *tps65910_reg_matches = NULL;
74ea0e59 1067 return NULL;
6790178f
RK
1068}
1069#endif
1070
a5023574 1071static int tps65910_probe(struct platform_device *pdev)
518fb721
GG
1072{
1073 struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent);
c172708d 1074 struct regulator_config config = { };
a320e3c3 1075 struct tps_info *info;
518fb721
GG
1076 struct regulator_dev *rdev;
1077 struct tps65910_reg *pmic;
1078 struct tps65910_board *pmic_plat_data;
84df8c12 1079 struct of_regulator_match *tps65910_reg_matches = NULL;
518fb721
GG
1080 int i, err;
1081
1082 pmic_plat_data = dev_get_platdata(tps65910->dev);
6790178f 1083 if (!pmic_plat_data && tps65910->dev->of_node)
84df8c12
LD
1084 pmic_plat_data = tps65910_parse_dt_reg_data(pdev,
1085 &tps65910_reg_matches);
6790178f 1086
7e9a57e6
LD
1087 if (!pmic_plat_data) {
1088 dev_err(&pdev->dev, "Platform data not found\n");
518fb721 1089 return -EINVAL;
7e9a57e6 1090 }
518fb721 1091
9eb0c421 1092 pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
bcb2c0d6 1093 if (!pmic)
518fb721
GG
1094 return -ENOMEM;
1095
518fb721
GG
1096 pmic->mfd = tps65910;
1097 platform_set_drvdata(pdev, pmic);
1098
1099 /* Give control of all register to control port */
cd07e370 1100 err = tps65910_reg_set_bits(pmic->mfd, TPS65910_DEVCTRL,
518fb721 1101 DEVCTRL_SR_CTL_I2C_SEL_MASK);
cd07e370
KL
1102 if (err < 0)
1103 return err;
518fb721 1104
4b579270 1105 switch (tps65910_chip_id(tps65910)) {
a320e3c3 1106 case TPS65910:
fe953904 1107 BUILD_BUG_ON(TPS65910_NUM_REGS < ARRAY_SIZE(tps65910_regs));
a320e3c3 1108 pmic->get_ctrl_reg = &tps65910_get_ctrl_register;
39aa9b6e 1109 pmic->num_regulators = ARRAY_SIZE(tps65910_regs);
1e0c66f4 1110 pmic->ext_sleep_control = tps65910_ext_sleep_control;
a320e3c3 1111 info = tps65910_regs;
8f9165c9
JR
1112 /* Work around silicon erratum SWCZ010: output programmed
1113 * voltage level can go higher than expected or crash
1114 * Workaround: use no synchronization of DCDC clocks
1115 */
1116 tps65910_reg_clear_bits(pmic->mfd, TPS65910_DCDCCTRL,
1117 DCDCCTRL_DCDCCKSYNC_MASK);
d04156bc 1118 break;
a320e3c3 1119 case TPS65911:
fe953904 1120 BUILD_BUG_ON(TPS65910_NUM_REGS < ARRAY_SIZE(tps65911_regs));
a320e3c3 1121 pmic->get_ctrl_reg = &tps65911_get_ctrl_register;
39aa9b6e 1122 pmic->num_regulators = ARRAY_SIZE(tps65911_regs);
1e0c66f4 1123 pmic->ext_sleep_control = tps65911_ext_sleep_control;
a320e3c3 1124 info = tps65911_regs;
d04156bc 1125 break;
a320e3c3 1126 default:
7e9a57e6 1127 dev_err(&pdev->dev, "Invalid tps chip version\n");
a320e3c3
JEC
1128 return -ENODEV;
1129 }
1130
a86854d0
KC
1131 pmic->desc = devm_kcalloc(&pdev->dev,
1132 pmic->num_regulators,
1133 sizeof(struct regulator_desc),
1134 GFP_KERNEL);
bcb2c0d6 1135 if (!pmic->desc)
68d8c1cd 1136 return -ENOMEM;
39aa9b6e 1137
a86854d0
KC
1138 pmic->info = devm_kcalloc(&pdev->dev,
1139 pmic->num_regulators,
1140 sizeof(struct tps_info *),
1141 GFP_KERNEL);
bcb2c0d6 1142 if (!pmic->info)
68d8c1cd 1143 return -ENOMEM;
39aa9b6e 1144
a86854d0
KC
1145 pmic->rdev = devm_kcalloc(&pdev->dev,
1146 pmic->num_regulators,
1147 sizeof(struct regulator_dev *),
1148 GFP_KERNEL);
bcb2c0d6 1149 if (!pmic->rdev)
68d8c1cd 1150 return -ENOMEM;
39aa9b6e 1151
fe953904 1152 for (i = 0; i < pmic->num_regulators; i++, info++) {
518fb721
GG
1153 /* Register the regulators */
1154 pmic->info[i] = info;
1155
1156 pmic->desc[i].name = info->name;
d2cfdb05 1157 pmic->desc[i].supply_name = info->vin_name;
77fa44d0 1158 pmic->desc[i].id = i;
7d38a3cb 1159 pmic->desc[i].n_voltages = info->n_voltages;
94f48ab3 1160 pmic->desc[i].enable_time = info->enable_time_us;
518fb721 1161
a320e3c3 1162 if (i == TPS65910_REG_VDD1 || i == TPS65910_REG_VDD2) {
518fb721 1163 pmic->desc[i].ops = &tps65910_ops_dcdc;
780dc9ba
AM
1164 pmic->desc[i].n_voltages = VDD1_2_NUM_VOLT_FINE *
1165 VDD1_2_NUM_VOLT_COARSE;
01bc3a14 1166 pmic->desc[i].ramp_delay = 12500;
a320e3c3 1167 } else if (i == TPS65910_REG_VDD3) {
01bc3a14 1168 if (tps65910_chip_id(tps65910) == TPS65910) {
a320e3c3 1169 pmic->desc[i].ops = &tps65910_ops_vdd3;
d9fe28f9 1170 pmic->desc[i].volt_table = info->voltage_table;
01bc3a14 1171 } else {
a320e3c3 1172 pmic->desc[i].ops = &tps65910_ops_dcdc;
01bc3a14
AL
1173 pmic->desc[i].ramp_delay = 5000;
1174 }
03746dcb
MP
1175 } else if (i == TPS65910_REG_VBB &&
1176 tps65910_chip_id(tps65910) == TPS65910) {
1177 pmic->desc[i].ops = &tps65910_ops_vbb;
1178 pmic->desc[i].volt_table = info->voltage_table;
a320e3c3 1179 } else {
d9fe28f9 1180 if (tps65910_chip_id(tps65910) == TPS65910) {
a320e3c3 1181 pmic->desc[i].ops = &tps65910_ops;
d9fe28f9
AL
1182 pmic->desc[i].volt_table = info->voltage_table;
1183 } else {
a320e3c3 1184 pmic->desc[i].ops = &tps65911_ops;
d9fe28f9 1185 }
a320e3c3 1186 }
518fb721 1187
1e0c66f4
LD
1188 err = tps65910_set_ext_sleep_config(pmic, i,
1189 pmic_plat_data->regulator_ext_sleep_control[i]);
1190 /*
1191 * Failing on regulator for configuring externally control
1192 * is not a serious issue, just throw warning.
1193 */
1194 if (err < 0)
1195 dev_warn(tps65910->dev,
1196 "Failed to initialise ext control config\n");
1197
518fb721
GG
1198 pmic->desc[i].type = REGULATOR_VOLTAGE;
1199 pmic->desc[i].owner = THIS_MODULE;
a40a9c43 1200 pmic->desc[i].enable_reg = pmic->get_ctrl_reg(i);
b8903eb9 1201 pmic->desc[i].enable_mask = TPS65910_SUPPLY_STATE_ENABLED;
518fb721 1202
c172708d 1203 config.dev = tps65910->dev;
23b11348 1204 config.init_data = pmic_plat_data->tps65910_pmic_init_data[i];
c172708d 1205 config.driver_data = pmic;
a40a9c43 1206 config.regmap = tps65910->regmap;
c172708d 1207
84df8c12
LD
1208 if (tps65910_reg_matches)
1209 config.of_node = tps65910_reg_matches[i].of_node;
6790178f 1210
95095e42
SK
1211 rdev = devm_regulator_register(&pdev->dev, &pmic->desc[i],
1212 &config);
518fb721
GG
1213 if (IS_ERR(rdev)) {
1214 dev_err(tps65910->dev,
1215 "failed to register %s regulator\n",
1216 pdev->name);
95095e42 1217 return PTR_ERR(rdev);
518fb721
GG
1218 }
1219
1220 /* Save regulator for cleanup */
1221 pmic->rdev[i] = rdev;
1222 }
1223 return 0;
518fb721
GG
1224}
1225
1e0c66f4
LD
1226static void tps65910_shutdown(struct platform_device *pdev)
1227{
1228 struct tps65910_reg *pmic = platform_get_drvdata(pdev);
1229 int i;
1230
1231 /*
1232 * Before bootloader jumps to kernel, it makes sure that required
1233 * external control signals are in desired state so that given rails
1234 * can be configure accordingly.
1235 * If rails are configured to be controlled from external control
1236 * then before shutting down/rebooting the system, the external
1237 * control configuration need to be remove from the rails so that
1238 * its output will be available as per register programming even
1239 * if external controls are removed. This is require when the POR
1240 * value of the control signals are not in active state and before
1241 * bootloader initializes it, the system requires the rail output
1242 * to be active for booting.
1243 */
1244 for (i = 0; i < pmic->num_regulators; i++) {
1245 int err;
1246 if (!pmic->rdev[i])
1247 continue;
1248
1249 err = tps65910_set_ext_sleep_config(pmic, i, 0);
1250 if (err < 0)
1251 dev_err(&pdev->dev,
1252 "Error in clearing external control\n");
1253 }
1254}
1255
518fb721
GG
1256static struct platform_driver tps65910_driver = {
1257 .driver = {
1258 .name = "tps65910-pmic",
518fb721
GG
1259 },
1260 .probe = tps65910_probe,
1e0c66f4 1261 .shutdown = tps65910_shutdown,
518fb721
GG
1262};
1263
1264static int __init tps65910_init(void)
1265{
1266 return platform_driver_register(&tps65910_driver);
1267}
1268subsys_initcall(tps65910_init);
1269
1270static void __exit tps65910_cleanup(void)
1271{
1272 platform_driver_unregister(&tps65910_driver);
1273}
1274module_exit(tps65910_cleanup);
1275
1276MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
ae0e6544 1277MODULE_DESCRIPTION("TPS65910/TPS65911 voltage regulator driver");
518fb721
GG
1278MODULE_LICENSE("GPL v2");
1279MODULE_ALIAS("platform:tps65910-pmic");