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regulator: fixed: dt: support for input supply
[mirror_ubuntu-hirsute-kernel.git] / drivers / regulator / tps65910-regulator.c
CommitLineData
518fb721
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1/*
2 * tps65910.c -- TI tps65910
3 *
4 * Copyright 2010 Texas Instruments Inc.
5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/err.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/driver.h>
22#include <linux/regulator/machine.h>
518fb721
GG
23#include <linux/slab.h>
24#include <linux/gpio.h>
25#include <linux/mfd/tps65910.h>
6790178f 26#include <linux/regulator/of_regulator.h>
518fb721 27
518fb721 28#define TPS65910_SUPPLY_STATE_ENABLED 0x1
1e0c66f4
LD
29#define EXT_SLEEP_CONTROL (TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 | \
30 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 | \
f30b0716
LD
31 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 | \
32 TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP)
518fb721 33
d9fe28f9
AL
34/* supported VIO voltages in microvolts */
35static const unsigned int VIO_VSEL_table[] = {
36 1500000, 1800000, 2500000, 3300000,
518fb721
GG
37};
38
a320e3c3
JEC
39/* VSEL tables for TPS65910 specific LDOs and dcdc's */
40
d9fe28f9
AL
41/* supported VDD3 voltages in microvolts */
42static const unsigned int VDD3_VSEL_table[] = {
43 5000000,
518fb721
GG
44};
45
d9fe28f9
AL
46/* supported VDIG1 voltages in microvolts */
47static const unsigned int VDIG1_VSEL_table[] = {
48 1200000, 1500000, 1800000, 2700000,
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GG
49};
50
d9fe28f9
AL
51/* supported VDIG2 voltages in microvolts */
52static const unsigned int VDIG2_VSEL_table[] = {
53 1000000, 1100000, 1200000, 1800000,
518fb721
GG
54};
55
d9fe28f9
AL
56/* supported VPLL voltages in microvolts */
57static const unsigned int VPLL_VSEL_table[] = {
58 1000000, 1100000, 1800000, 2500000,
518fb721
GG
59};
60
d9fe28f9
AL
61/* supported VDAC voltages in microvolts */
62static const unsigned int VDAC_VSEL_table[] = {
63 1800000, 2600000, 2800000, 2850000,
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GG
64};
65
d9fe28f9
AL
66/* supported VAUX1 voltages in microvolts */
67static const unsigned int VAUX1_VSEL_table[] = {
68 1800000, 2500000, 2800000, 2850000,
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GG
69};
70
d9fe28f9
AL
71/* supported VAUX2 voltages in microvolts */
72static const unsigned int VAUX2_VSEL_table[] = {
73 1800000, 2800000, 2900000, 3300000,
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GG
74};
75
d9fe28f9
AL
76/* supported VAUX33 voltages in microvolts */
77static const unsigned int VAUX33_VSEL_table[] = {
78 1800000, 2000000, 2800000, 3300000,
518fb721
GG
79};
80
d9fe28f9
AL
81/* supported VMMC voltages in microvolts */
82static const unsigned int VMMC_VSEL_table[] = {
83 1800000, 2800000, 3000000, 3300000,
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GG
84};
85
86struct tps_info {
87 const char *name;
7d38a3cb 88 u8 n_voltages;
d9fe28f9 89 const unsigned int *voltage_table;
0651eed5 90 int enable_time_us;
518fb721
GG
91};
92
93static struct tps_info tps65910_regs[] = {
94 {
33a6943d 95 .name = "vrtc",
0651eed5 96 .enable_time_us = 2200,
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GG
97 },
98 {
33a6943d 99 .name = "vio",
7d38a3cb
LD
100 .n_voltages = ARRAY_SIZE(VIO_VSEL_table),
101 .voltage_table = VIO_VSEL_table,
0651eed5 102 .enable_time_us = 350,
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103 },
104 {
33a6943d 105 .name = "vdd1",
0651eed5 106 .enable_time_us = 350,
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107 },
108 {
33a6943d 109 .name = "vdd2",
0651eed5 110 .enable_time_us = 350,
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GG
111 },
112 {
33a6943d 113 .name = "vdd3",
7d38a3cb
LD
114 .n_voltages = ARRAY_SIZE(VDD3_VSEL_table),
115 .voltage_table = VDD3_VSEL_table,
0651eed5 116 .enable_time_us = 200,
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GG
117 },
118 {
33a6943d 119 .name = "vdig1",
7d38a3cb
LD
120 .n_voltages = ARRAY_SIZE(VDIG1_VSEL_table),
121 .voltage_table = VDIG1_VSEL_table,
0651eed5 122 .enable_time_us = 100,
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123 },
124 {
33a6943d 125 .name = "vdig2",
7d38a3cb
LD
126 .n_voltages = ARRAY_SIZE(VDIG2_VSEL_table),
127 .voltage_table = VDIG2_VSEL_table,
0651eed5 128 .enable_time_us = 100,
518fb721
GG
129 },
130 {
33a6943d 131 .name = "vpll",
7d38a3cb
LD
132 .n_voltages = ARRAY_SIZE(VPLL_VSEL_table),
133 .voltage_table = VPLL_VSEL_table,
0651eed5 134 .enable_time_us = 100,
518fb721
GG
135 },
136 {
33a6943d 137 .name = "vdac",
7d38a3cb
LD
138 .n_voltages = ARRAY_SIZE(VDAC_VSEL_table),
139 .voltage_table = VDAC_VSEL_table,
0651eed5 140 .enable_time_us = 100,
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GG
141 },
142 {
33a6943d 143 .name = "vaux1",
7d38a3cb
LD
144 .n_voltages = ARRAY_SIZE(VAUX1_VSEL_table),
145 .voltage_table = VAUX1_VSEL_table,
0651eed5 146 .enable_time_us = 100,
518fb721
GG
147 },
148 {
33a6943d 149 .name = "vaux2",
7d38a3cb
LD
150 .n_voltages = ARRAY_SIZE(VAUX2_VSEL_table),
151 .voltage_table = VAUX2_VSEL_table,
0651eed5 152 .enable_time_us = 100,
518fb721
GG
153 },
154 {
33a6943d 155 .name = "vaux33",
7d38a3cb
LD
156 .n_voltages = ARRAY_SIZE(VAUX33_VSEL_table),
157 .voltage_table = VAUX33_VSEL_table,
0651eed5 158 .enable_time_us = 100,
518fb721
GG
159 },
160 {
33a6943d 161 .name = "vmmc",
7d38a3cb
LD
162 .n_voltages = ARRAY_SIZE(VMMC_VSEL_table),
163 .voltage_table = VMMC_VSEL_table,
0651eed5 164 .enable_time_us = 100,
518fb721
GG
165 },
166};
167
a320e3c3 168static struct tps_info tps65911_regs[] = {
c2f8efd7 169 {
33a6943d 170 .name = "vrtc",
0651eed5 171 .enable_time_us = 2200,
c2f8efd7 172 },
a320e3c3 173 {
33a6943d 174 .name = "vio",
7d38a3cb
LD
175 .n_voltages = ARRAY_SIZE(VIO_VSEL_table),
176 .voltage_table = VIO_VSEL_table,
0651eed5 177 .enable_time_us = 350,
a320e3c3
JEC
178 },
179 {
33a6943d 180 .name = "vdd1",
7d38a3cb 181 .n_voltages = 73,
0651eed5 182 .enable_time_us = 350,
a320e3c3
JEC
183 },
184 {
33a6943d 185 .name = "vdd2",
7d38a3cb 186 .n_voltages = 73,
0651eed5 187 .enable_time_us = 350,
a320e3c3
JEC
188 },
189 {
33a6943d 190 .name = "vddctrl",
7d38a3cb 191 .n_voltages = 65,
0651eed5 192 .enable_time_us = 900,
a320e3c3
JEC
193 },
194 {
33a6943d 195 .name = "ldo1",
7d38a3cb 196 .n_voltages = 47,
0651eed5 197 .enable_time_us = 420,
a320e3c3
JEC
198 },
199 {
33a6943d 200 .name = "ldo2",
7d38a3cb 201 .n_voltages = 47,
0651eed5 202 .enable_time_us = 420,
a320e3c3
JEC
203 },
204 {
33a6943d 205 .name = "ldo3",
7d38a3cb 206 .n_voltages = 24,
0651eed5 207 .enable_time_us = 230,
a320e3c3
JEC
208 },
209 {
33a6943d 210 .name = "ldo4",
7d38a3cb 211 .n_voltages = 47,
0651eed5 212 .enable_time_us = 230,
a320e3c3
JEC
213 },
214 {
33a6943d 215 .name = "ldo5",
7d38a3cb 216 .n_voltages = 24,
0651eed5 217 .enable_time_us = 230,
a320e3c3
JEC
218 },
219 {
33a6943d 220 .name = "ldo6",
7d38a3cb 221 .n_voltages = 24,
0651eed5 222 .enable_time_us = 230,
a320e3c3
JEC
223 },
224 {
33a6943d 225 .name = "ldo7",
7d38a3cb 226 .n_voltages = 24,
0651eed5 227 .enable_time_us = 230,
a320e3c3
JEC
228 },
229 {
33a6943d 230 .name = "ldo8",
7d38a3cb 231 .n_voltages = 24,
0651eed5 232 .enable_time_us = 230,
a320e3c3
JEC
233 },
234};
235
1e0c66f4
LD
236#define EXT_CONTROL_REG_BITS(id, regs_offs, bits) (((regs_offs) << 8) | (bits))
237static unsigned int tps65910_ext_sleep_control[] = {
238 0,
239 EXT_CONTROL_REG_BITS(VIO, 1, 0),
240 EXT_CONTROL_REG_BITS(VDD1, 1, 1),
241 EXT_CONTROL_REG_BITS(VDD2, 1, 2),
242 EXT_CONTROL_REG_BITS(VDD3, 1, 3),
243 EXT_CONTROL_REG_BITS(VDIG1, 0, 1),
244 EXT_CONTROL_REG_BITS(VDIG2, 0, 2),
245 EXT_CONTROL_REG_BITS(VPLL, 0, 6),
246 EXT_CONTROL_REG_BITS(VDAC, 0, 7),
247 EXT_CONTROL_REG_BITS(VAUX1, 0, 3),
248 EXT_CONTROL_REG_BITS(VAUX2, 0, 4),
249 EXT_CONTROL_REG_BITS(VAUX33, 0, 5),
250 EXT_CONTROL_REG_BITS(VMMC, 0, 0),
251};
252
253static unsigned int tps65911_ext_sleep_control[] = {
254 0,
255 EXT_CONTROL_REG_BITS(VIO, 1, 0),
256 EXT_CONTROL_REG_BITS(VDD1, 1, 1),
257 EXT_CONTROL_REG_BITS(VDD2, 1, 2),
258 EXT_CONTROL_REG_BITS(VDDCTRL, 1, 3),
259 EXT_CONTROL_REG_BITS(LDO1, 0, 1),
260 EXT_CONTROL_REG_BITS(LDO2, 0, 2),
261 EXT_CONTROL_REG_BITS(LDO3, 0, 7),
262 EXT_CONTROL_REG_BITS(LDO4, 0, 6),
263 EXT_CONTROL_REG_BITS(LDO5, 0, 3),
264 EXT_CONTROL_REG_BITS(LDO6, 0, 0),
265 EXT_CONTROL_REG_BITS(LDO7, 0, 5),
266 EXT_CONTROL_REG_BITS(LDO8, 0, 4),
267};
268
518fb721 269struct tps65910_reg {
39aa9b6e 270 struct regulator_desc *desc;
518fb721 271 struct tps65910 *mfd;
39aa9b6e
AL
272 struct regulator_dev **rdev;
273 struct tps_info **info;
518fb721 274 struct mutex mutex;
39aa9b6e 275 int num_regulators;
518fb721 276 int mode;
a320e3c3 277 int (*get_ctrl_reg)(int);
1e0c66f4
LD
278 unsigned int *ext_sleep_control;
279 unsigned int board_ext_control[TPS65910_NUM_REGS];
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280};
281
282static inline int tps65910_read(struct tps65910_reg *pmic, u8 reg)
283{
3f7e8275 284 unsigned int val;
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GG
285 int err;
286
3f7e8275 287 err = tps65910_reg_read(pmic->mfd, reg, &val);
518fb721
GG
288 if (err)
289 return err;
290
291 return val;
292}
293
518fb721
GG
294static int tps65910_modify_bits(struct tps65910_reg *pmic, u8 reg,
295 u8 set_mask, u8 clear_mask)
296{
297 int err, data;
298
299 mutex_lock(&pmic->mutex);
300
301 data = tps65910_read(pmic, reg);
302 if (data < 0) {
303 dev_err(pmic->mfd->dev, "Read from reg 0x%x failed\n", reg);
304 err = data;
305 goto out;
306 }
307
308 data &= ~clear_mask;
309 data |= set_mask;
3f7e8275 310 err = tps65910_reg_write(pmic->mfd, reg, data);
518fb721
GG
311 if (err)
312 dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg);
313
314out:
315 mutex_unlock(&pmic->mutex);
316 return err;
317}
318
3f7e8275 319static int tps65910_reg_read_locked(struct tps65910_reg *pmic, u8 reg)
518fb721
GG
320{
321 int data;
322
323 mutex_lock(&pmic->mutex);
324
325 data = tps65910_read(pmic, reg);
326 if (data < 0)
327 dev_err(pmic->mfd->dev, "Read from reg 0x%x failed\n", reg);
328
329 mutex_unlock(&pmic->mutex);
330 return data;
331}
332
3f7e8275 333static int tps65910_reg_write_locked(struct tps65910_reg *pmic, u8 reg, u8 val)
518fb721
GG
334{
335 int err;
336
337 mutex_lock(&pmic->mutex);
338
3f7e8275 339 err = tps65910_reg_write(pmic->mfd, reg, val);
518fb721
GG
340 if (err < 0)
341 dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg);
342
343 mutex_unlock(&pmic->mutex);
344 return err;
345}
346
347static int tps65910_get_ctrl_register(int id)
348{
349 switch (id) {
350 case TPS65910_REG_VRTC:
351 return TPS65910_VRTC;
352 case TPS65910_REG_VIO:
353 return TPS65910_VIO;
354 case TPS65910_REG_VDD1:
355 return TPS65910_VDD1;
356 case TPS65910_REG_VDD2:
357 return TPS65910_VDD2;
358 case TPS65910_REG_VDD3:
359 return TPS65910_VDD3;
360 case TPS65910_REG_VDIG1:
361 return TPS65910_VDIG1;
362 case TPS65910_REG_VDIG2:
363 return TPS65910_VDIG2;
364 case TPS65910_REG_VPLL:
365 return TPS65910_VPLL;
366 case TPS65910_REG_VDAC:
367 return TPS65910_VDAC;
368 case TPS65910_REG_VAUX1:
369 return TPS65910_VAUX1;
370 case TPS65910_REG_VAUX2:
371 return TPS65910_VAUX2;
372 case TPS65910_REG_VAUX33:
373 return TPS65910_VAUX33;
374 case TPS65910_REG_VMMC:
375 return TPS65910_VMMC;
376 default:
377 return -EINVAL;
378 }
379}
380
a320e3c3
JEC
381static int tps65911_get_ctrl_register(int id)
382{
383 switch (id) {
384 case TPS65910_REG_VRTC:
385 return TPS65910_VRTC;
386 case TPS65910_REG_VIO:
387 return TPS65910_VIO;
388 case TPS65910_REG_VDD1:
389 return TPS65910_VDD1;
390 case TPS65910_REG_VDD2:
391 return TPS65910_VDD2;
392 case TPS65911_REG_VDDCTRL:
393 return TPS65911_VDDCTRL;
394 case TPS65911_REG_LDO1:
395 return TPS65911_LDO1;
396 case TPS65911_REG_LDO2:
397 return TPS65911_LDO2;
398 case TPS65911_REG_LDO3:
399 return TPS65911_LDO3;
400 case TPS65911_REG_LDO4:
401 return TPS65911_LDO4;
402 case TPS65911_REG_LDO5:
403 return TPS65911_LDO5;
404 case TPS65911_REG_LDO6:
405 return TPS65911_LDO6;
406 case TPS65911_REG_LDO7:
407 return TPS65911_LDO7;
408 case TPS65911_REG_LDO8:
409 return TPS65911_LDO8;
410 default:
411 return -EINVAL;
412 }
413}
414
518fb721
GG
415static int tps65910_set_mode(struct regulator_dev *dev, unsigned int mode)
416{
417 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
418 struct tps65910 *mfd = pmic->mfd;
419 int reg, value, id = rdev_get_id(dev);
a320e3c3
JEC
420
421 reg = pmic->get_ctrl_reg(id);
518fb721
GG
422 if (reg < 0)
423 return reg;
424
425 switch (mode) {
426 case REGULATOR_MODE_NORMAL:
427 return tps65910_modify_bits(pmic, reg, LDO_ST_ON_BIT,
428 LDO_ST_MODE_BIT);
429 case REGULATOR_MODE_IDLE:
430 value = LDO_ST_ON_BIT | LDO_ST_MODE_BIT;
3f7e8275 431 return tps65910_reg_set_bits(mfd, reg, value);
518fb721 432 case REGULATOR_MODE_STANDBY:
3f7e8275 433 return tps65910_reg_clear_bits(mfd, reg, LDO_ST_ON_BIT);
518fb721
GG
434 }
435
436 return -EINVAL;
437}
438
439static unsigned int tps65910_get_mode(struct regulator_dev *dev)
440{
441 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
442 int reg, value, id = rdev_get_id(dev);
443
a320e3c3 444 reg = pmic->get_ctrl_reg(id);
518fb721
GG
445 if (reg < 0)
446 return reg;
447
3f7e8275 448 value = tps65910_reg_read_locked(pmic, reg);
518fb721
GG
449 if (value < 0)
450 return value;
451
58599393 452 if (!(value & LDO_ST_ON_BIT))
518fb721
GG
453 return REGULATOR_MODE_STANDBY;
454 else if (value & LDO_ST_MODE_BIT)
455 return REGULATOR_MODE_IDLE;
456 else
457 return REGULATOR_MODE_NORMAL;
458}
459
18039e0f 460static int tps65910_get_voltage_dcdc_sel(struct regulator_dev *dev)
518fb721
GG
461{
462 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
18039e0f 463 int id = rdev_get_id(dev);
a320e3c3 464 int opvsel = 0, srvsel = 0, vselmax = 0, mult = 0, sr = 0;
518fb721
GG
465
466 switch (id) {
467 case TPS65910_REG_VDD1:
3f7e8275
RK
468 opvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD1_OP);
469 mult = tps65910_reg_read_locked(pmic, TPS65910_VDD1);
518fb721 470 mult = (mult & VDD1_VGAIN_SEL_MASK) >> VDD1_VGAIN_SEL_SHIFT;
3f7e8275 471 srvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD1_SR);
518fb721
GG
472 sr = opvsel & VDD1_OP_CMD_MASK;
473 opvsel &= VDD1_OP_SEL_MASK;
474 srvsel &= VDD1_SR_SEL_MASK;
a320e3c3 475 vselmax = 75;
518fb721
GG
476 break;
477 case TPS65910_REG_VDD2:
3f7e8275
RK
478 opvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD2_OP);
479 mult = tps65910_reg_read_locked(pmic, TPS65910_VDD2);
518fb721 480 mult = (mult & VDD2_VGAIN_SEL_MASK) >> VDD2_VGAIN_SEL_SHIFT;
3f7e8275 481 srvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD2_SR);
518fb721
GG
482 sr = opvsel & VDD2_OP_CMD_MASK;
483 opvsel &= VDD2_OP_SEL_MASK;
484 srvsel &= VDD2_SR_SEL_MASK;
a320e3c3
JEC
485 vselmax = 75;
486 break;
487 case TPS65911_REG_VDDCTRL:
3f7e8275
RK
488 opvsel = tps65910_reg_read_locked(pmic, TPS65911_VDDCTRL_OP);
489 srvsel = tps65910_reg_read_locked(pmic, TPS65911_VDDCTRL_SR);
a320e3c3
JEC
490 sr = opvsel & VDDCTRL_OP_CMD_MASK;
491 opvsel &= VDDCTRL_OP_SEL_MASK;
492 srvsel &= VDDCTRL_SR_SEL_MASK;
493 vselmax = 64;
518fb721
GG
494 break;
495 }
496
497 /* multiplier 0 == 1 but 2,3 normal */
498 if (!mult)
499 mult=1;
500
501 if (sr) {
a320e3c3
JEC
502 /* normalise to valid range */
503 if (srvsel < 3)
504 srvsel = 3;
505 if (srvsel > vselmax)
506 srvsel = vselmax;
18039e0f 507 return srvsel - 3;
518fb721
GG
508 } else {
509
a320e3c3
JEC
510 /* normalise to valid range*/
511 if (opvsel < 3)
512 opvsel = 3;
513 if (opvsel > vselmax)
514 opvsel = vselmax;
18039e0f 515 return opvsel - 3;
518fb721 516 }
18039e0f 517 return -EINVAL;
518fb721
GG
518}
519
1f904fd1 520static int tps65910_get_voltage_sel(struct regulator_dev *dev)
518fb721
GG
521{
522 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
1f904fd1 523 int reg, value, id = rdev_get_id(dev);
518fb721 524
a320e3c3 525 reg = pmic->get_ctrl_reg(id);
518fb721
GG
526 if (reg < 0)
527 return reg;
528
3f7e8275 529 value = tps65910_reg_read_locked(pmic, reg);
518fb721
GG
530 if (value < 0)
531 return value;
532
533 switch (id) {
534 case TPS65910_REG_VIO:
535 case TPS65910_REG_VDIG1:
536 case TPS65910_REG_VDIG2:
537 case TPS65910_REG_VPLL:
538 case TPS65910_REG_VDAC:
539 case TPS65910_REG_VAUX1:
540 case TPS65910_REG_VAUX2:
541 case TPS65910_REG_VAUX33:
542 case TPS65910_REG_VMMC:
543 value &= LDO_SEL_MASK;
544 value >>= LDO_SEL_SHIFT;
545 break;
546 default:
547 return -EINVAL;
548 }
549
1f904fd1 550 return value;
518fb721
GG
551}
552
553static int tps65910_get_voltage_vdd3(struct regulator_dev *dev)
554{
d9fe28f9 555 return dev->desc->volt_table[0];
518fb721
GG
556}
557
1f904fd1 558static int tps65911_get_voltage_sel(struct regulator_dev *dev)
a320e3c3
JEC
559{
560 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
1f904fd1 561 int id = rdev_get_id(dev);
a320e3c3
JEC
562 u8 value, reg;
563
564 reg = pmic->get_ctrl_reg(id);
565
3f7e8275 566 value = tps65910_reg_read_locked(pmic, reg);
a320e3c3
JEC
567
568 switch (id) {
569 case TPS65911_REG_LDO1:
570 case TPS65911_REG_LDO2:
571 case TPS65911_REG_LDO4:
572 value &= LDO1_SEL_MASK;
573 value >>= LDO_SEL_SHIFT;
a320e3c3
JEC
574 break;
575 case TPS65911_REG_LDO3:
576 case TPS65911_REG_LDO5:
577 case TPS65911_REG_LDO6:
578 case TPS65911_REG_LDO7:
579 case TPS65911_REG_LDO8:
580 value &= LDO3_SEL_MASK;
581 value >>= LDO_SEL_SHIFT;
a320e3c3
JEC
582 break;
583 case TPS65910_REG_VIO:
e882eae8
LD
584 value &= LDO_SEL_MASK;
585 value >>= LDO_SEL_SHIFT;
1f904fd1 586 break;
a320e3c3
JEC
587 default:
588 return -EINVAL;
589 }
590
1f904fd1 591 return value;
a320e3c3
JEC
592}
593
94732b97
AL
594static int tps65910_set_voltage_dcdc_sel(struct regulator_dev *dev,
595 unsigned selector)
518fb721
GG
596{
597 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
598 int id = rdev_get_id(dev), vsel;
a320e3c3 599 int dcdc_mult = 0;
518fb721 600
a320e3c3
JEC
601 switch (id) {
602 case TPS65910_REG_VDD1:
780dc9ba 603 dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
a320e3c3
JEC
604 if (dcdc_mult == 1)
605 dcdc_mult--;
780dc9ba 606 vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3;
518fb721 607
518fb721
GG
608 tps65910_modify_bits(pmic, TPS65910_VDD1,
609 (dcdc_mult << VDD1_VGAIN_SEL_SHIFT),
610 VDD1_VGAIN_SEL_MASK);
3f7e8275 611 tps65910_reg_write_locked(pmic, TPS65910_VDD1_OP, vsel);
a320e3c3
JEC
612 break;
613 case TPS65910_REG_VDD2:
780dc9ba 614 dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
a320e3c3
JEC
615 if (dcdc_mult == 1)
616 dcdc_mult--;
780dc9ba 617 vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3;
a320e3c3 618
518fb721
GG
619 tps65910_modify_bits(pmic, TPS65910_VDD2,
620 (dcdc_mult << VDD2_VGAIN_SEL_SHIFT),
621 VDD1_VGAIN_SEL_MASK);
3f7e8275 622 tps65910_reg_write_locked(pmic, TPS65910_VDD2_OP, vsel);
a320e3c3
JEC
623 break;
624 case TPS65911_REG_VDDCTRL:
c4632aed 625 vsel = selector + 3;
3f7e8275 626 tps65910_reg_write_locked(pmic, TPS65911_VDDCTRL_OP, vsel);
518fb721
GG
627 }
628
629 return 0;
630}
631
94732b97
AL
632static int tps65910_set_voltage_sel(struct regulator_dev *dev,
633 unsigned selector)
518fb721
GG
634{
635 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
636 int reg, id = rdev_get_id(dev);
637
a320e3c3 638 reg = pmic->get_ctrl_reg(id);
518fb721
GG
639 if (reg < 0)
640 return reg;
641
642 switch (id) {
643 case TPS65910_REG_VIO:
644 case TPS65910_REG_VDIG1:
645 case TPS65910_REG_VDIG2:
646 case TPS65910_REG_VPLL:
647 case TPS65910_REG_VDAC:
648 case TPS65910_REG_VAUX1:
649 case TPS65910_REG_VAUX2:
650 case TPS65910_REG_VAUX33:
651 case TPS65910_REG_VMMC:
652 return tps65910_modify_bits(pmic, reg,
653 (selector << LDO_SEL_SHIFT), LDO_SEL_MASK);
654 }
655
656 return -EINVAL;
657}
658
94732b97
AL
659static int tps65911_set_voltage_sel(struct regulator_dev *dev,
660 unsigned selector)
a320e3c3
JEC
661{
662 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
663 int reg, id = rdev_get_id(dev);
664
665 reg = pmic->get_ctrl_reg(id);
666 if (reg < 0)
667 return reg;
668
669 switch (id) {
670 case TPS65911_REG_LDO1:
671 case TPS65911_REG_LDO2:
672 case TPS65911_REG_LDO4:
673 return tps65910_modify_bits(pmic, reg,
674 (selector << LDO_SEL_SHIFT), LDO1_SEL_MASK);
675 case TPS65911_REG_LDO3:
676 case TPS65911_REG_LDO5:
677 case TPS65911_REG_LDO6:
678 case TPS65911_REG_LDO7:
679 case TPS65911_REG_LDO8:
a320e3c3
JEC
680 return tps65910_modify_bits(pmic, reg,
681 (selector << LDO_SEL_SHIFT), LDO3_SEL_MASK);
e882eae8
LD
682 case TPS65910_REG_VIO:
683 return tps65910_modify_bits(pmic, reg,
684 (selector << LDO_SEL_SHIFT), LDO_SEL_MASK);
a320e3c3
JEC
685 }
686
687 return -EINVAL;
688}
689
690
518fb721
GG
691static int tps65910_list_voltage_dcdc(struct regulator_dev *dev,
692 unsigned selector)
693{
a320e3c3 694 int volt, mult = 1, id = rdev_get_id(dev);
518fb721 695
a320e3c3
JEC
696 switch (id) {
697 case TPS65910_REG_VDD1:
698 case TPS65910_REG_VDD2:
780dc9ba 699 mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
a320e3c3 700 volt = VDD1_2_MIN_VOLT +
780dc9ba 701 (selector % VDD1_2_NUM_VOLT_FINE) * VDD1_2_OFFSET;
d04156bc 702 break;
a320e3c3
JEC
703 case TPS65911_REG_VDDCTRL:
704 volt = VDDCTRL_MIN_VOLT + (selector * VDDCTRL_OFFSET);
d04156bc
AL
705 break;
706 default:
707 BUG();
708 return -EINVAL;
a320e3c3 709 }
518fb721
GG
710
711 return volt * 100 * mult;
712}
713
a320e3c3
JEC
714static int tps65911_list_voltage(struct regulator_dev *dev, unsigned selector)
715{
716 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
717 int step_mv = 0, id = rdev_get_id(dev);
718
719 switch(id) {
720 case TPS65911_REG_LDO1:
721 case TPS65911_REG_LDO2:
722 case TPS65911_REG_LDO4:
723 /* The first 5 values of the selector correspond to 1V */
724 if (selector < 5)
725 selector = 0;
726 else
727 selector -= 4;
728
729 step_mv = 50;
730 break;
731 case TPS65911_REG_LDO3:
732 case TPS65911_REG_LDO5:
733 case TPS65911_REG_LDO6:
734 case TPS65911_REG_LDO7:
735 case TPS65911_REG_LDO8:
736 /* The first 3 values of the selector correspond to 1V */
737 if (selector < 3)
738 selector = 0;
739 else
740 selector -= 2;
741
742 step_mv = 100;
743 break;
744 case TPS65910_REG_VIO:
d9fe28f9 745 return pmic->info[id]->voltage_table[selector];
a320e3c3
JEC
746 default:
747 return -EINVAL;
748 }
749
750 return (LDO_MIN_VOLT + selector * step_mv) * 1000;
751}
752
518fb721
GG
753/* Regulator ops (except VRTC) */
754static struct regulator_ops tps65910_ops_dcdc = {
a40a9c43
AL
755 .is_enabled = regulator_is_enabled_regmap,
756 .enable = regulator_enable_regmap,
757 .disable = regulator_disable_regmap,
518fb721
GG
758 .set_mode = tps65910_set_mode,
759 .get_mode = tps65910_get_mode,
18039e0f 760 .get_voltage_sel = tps65910_get_voltage_dcdc_sel,
94732b97 761 .set_voltage_sel = tps65910_set_voltage_dcdc_sel,
01bc3a14 762 .set_voltage_time_sel = regulator_set_voltage_time_sel,
518fb721
GG
763 .list_voltage = tps65910_list_voltage_dcdc,
764};
765
766static struct regulator_ops tps65910_ops_vdd3 = {
a40a9c43
AL
767 .is_enabled = regulator_is_enabled_regmap,
768 .enable = regulator_enable_regmap,
769 .disable = regulator_disable_regmap,
518fb721
GG
770 .set_mode = tps65910_set_mode,
771 .get_mode = tps65910_get_mode,
772 .get_voltage = tps65910_get_voltage_vdd3,
d9fe28f9 773 .list_voltage = regulator_list_voltage_table,
518fb721
GG
774};
775
776static struct regulator_ops tps65910_ops = {
a40a9c43
AL
777 .is_enabled = regulator_is_enabled_regmap,
778 .enable = regulator_enable_regmap,
779 .disable = regulator_disable_regmap,
518fb721
GG
780 .set_mode = tps65910_set_mode,
781 .get_mode = tps65910_get_mode,
1f904fd1 782 .get_voltage_sel = tps65910_get_voltage_sel,
94732b97 783 .set_voltage_sel = tps65910_set_voltage_sel,
d9fe28f9 784 .list_voltage = regulator_list_voltage_table,
518fb721
GG
785};
786
a320e3c3 787static struct regulator_ops tps65911_ops = {
a40a9c43
AL
788 .is_enabled = regulator_is_enabled_regmap,
789 .enable = regulator_enable_regmap,
790 .disable = regulator_disable_regmap,
a320e3c3
JEC
791 .set_mode = tps65910_set_mode,
792 .get_mode = tps65910_get_mode,
1f904fd1 793 .get_voltage_sel = tps65911_get_voltage_sel,
94732b97 794 .set_voltage_sel = tps65911_set_voltage_sel,
a320e3c3
JEC
795 .list_voltage = tps65911_list_voltage,
796};
797
1e0c66f4
LD
798static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic,
799 int id, int ext_sleep_config)
800{
801 struct tps65910 *mfd = pmic->mfd;
802 u8 regoffs = (pmic->ext_sleep_control[id] >> 8) & 0xFF;
803 u8 bit_pos = (1 << pmic->ext_sleep_control[id] & 0xFF);
804 int ret;
805
806 /*
807 * Regulator can not be control from multiple external input EN1, EN2
808 * and EN3 together.
809 */
810 if (ext_sleep_config & EXT_SLEEP_CONTROL) {
811 int en_count;
812 en_count = ((ext_sleep_config &
813 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) != 0);
814 en_count += ((ext_sleep_config &
815 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) != 0);
816 en_count += ((ext_sleep_config &
817 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) != 0);
f30b0716
LD
818 en_count += ((ext_sleep_config &
819 TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) != 0);
1e0c66f4
LD
820 if (en_count > 1) {
821 dev_err(mfd->dev,
822 "External sleep control flag is not proper\n");
823 return -EINVAL;
824 }
825 }
826
827 pmic->board_ext_control[id] = ext_sleep_config;
828
829 /* External EN1 control */
830 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1)
3f7e8275 831 ret = tps65910_reg_set_bits(mfd,
1e0c66f4
LD
832 TPS65910_EN1_LDO_ASS + regoffs, bit_pos);
833 else
3f7e8275 834 ret = tps65910_reg_clear_bits(mfd,
1e0c66f4
LD
835 TPS65910_EN1_LDO_ASS + regoffs, bit_pos);
836 if (ret < 0) {
837 dev_err(mfd->dev,
838 "Error in configuring external control EN1\n");
839 return ret;
840 }
841
842 /* External EN2 control */
843 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2)
3f7e8275 844 ret = tps65910_reg_set_bits(mfd,
1e0c66f4
LD
845 TPS65910_EN2_LDO_ASS + regoffs, bit_pos);
846 else
3f7e8275 847 ret = tps65910_reg_clear_bits(mfd,
1e0c66f4
LD
848 TPS65910_EN2_LDO_ASS + regoffs, bit_pos);
849 if (ret < 0) {
850 dev_err(mfd->dev,
851 "Error in configuring external control EN2\n");
852 return ret;
853 }
854
855 /* External EN3 control for TPS65910 LDO only */
856 if ((tps65910_chip_id(mfd) == TPS65910) &&
857 (id >= TPS65910_REG_VDIG1)) {
858 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3)
3f7e8275 859 ret = tps65910_reg_set_bits(mfd,
1e0c66f4
LD
860 TPS65910_EN3_LDO_ASS + regoffs, bit_pos);
861 else
3f7e8275 862 ret = tps65910_reg_clear_bits(mfd,
1e0c66f4
LD
863 TPS65910_EN3_LDO_ASS + regoffs, bit_pos);
864 if (ret < 0) {
865 dev_err(mfd->dev,
866 "Error in configuring external control EN3\n");
867 return ret;
868 }
869 }
870
871 /* Return if no external control is selected */
872 if (!(ext_sleep_config & EXT_SLEEP_CONTROL)) {
873 /* Clear all sleep controls */
3f7e8275 874 ret = tps65910_reg_clear_bits(mfd,
1e0c66f4
LD
875 TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos);
876 if (!ret)
3f7e8275 877 ret = tps65910_reg_clear_bits(mfd,
1e0c66f4
LD
878 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
879 if (ret < 0)
880 dev_err(mfd->dev,
881 "Error in configuring SLEEP register\n");
882 return ret;
883 }
884
885 /*
886 * For regulator that has separate operational and sleep register make
887 * sure that operational is used and clear sleep register to turn
888 * regulator off when external control is inactive
889 */
890 if ((id == TPS65910_REG_VDD1) ||
891 (id == TPS65910_REG_VDD2) ||
892 ((id == TPS65911_REG_VDDCTRL) &&
893 (tps65910_chip_id(mfd) == TPS65911))) {
894 int op_reg_add = pmic->get_ctrl_reg(id) + 1;
895 int sr_reg_add = pmic->get_ctrl_reg(id) + 2;
3f7e8275
RK
896 int opvsel = tps65910_reg_read_locked(pmic, op_reg_add);
897 int srvsel = tps65910_reg_read_locked(pmic, sr_reg_add);
1e0c66f4
LD
898 if (opvsel & VDD1_OP_CMD_MASK) {
899 u8 reg_val = srvsel & VDD1_OP_SEL_MASK;
3f7e8275
RK
900 ret = tps65910_reg_write_locked(pmic, op_reg_add,
901 reg_val);
1e0c66f4
LD
902 if (ret < 0) {
903 dev_err(mfd->dev,
904 "Error in configuring op register\n");
905 return ret;
906 }
907 }
3f7e8275 908 ret = tps65910_reg_write_locked(pmic, sr_reg_add, 0);
1e0c66f4
LD
909 if (ret < 0) {
910 dev_err(mfd->dev, "Error in settting sr register\n");
911 return ret;
912 }
913 }
914
3f7e8275 915 ret = tps65910_reg_clear_bits(mfd,
1e0c66f4 916 TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos);
f30b0716
LD
917 if (!ret) {
918 if (ext_sleep_config & TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP)
3f7e8275 919 ret = tps65910_reg_set_bits(mfd,
f30b0716
LD
920 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
921 else
3f7e8275 922 ret = tps65910_reg_clear_bits(mfd,
f30b0716
LD
923 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
924 }
1e0c66f4
LD
925 if (ret < 0)
926 dev_err(mfd->dev,
927 "Error in configuring SLEEP register\n");
f30b0716 928
1e0c66f4
LD
929 return ret;
930}
931
6790178f
RK
932#ifdef CONFIG_OF
933
934static struct of_regulator_match tps65910_matches[] = {
33a6943d
LD
935 { .name = "vrtc", .driver_data = (void *) &tps65910_regs[0] },
936 { .name = "vio", .driver_data = (void *) &tps65910_regs[1] },
937 { .name = "vdd1", .driver_data = (void *) &tps65910_regs[2] },
938 { .name = "vdd2", .driver_data = (void *) &tps65910_regs[3] },
939 { .name = "vdd3", .driver_data = (void *) &tps65910_regs[4] },
940 { .name = "vdig1", .driver_data = (void *) &tps65910_regs[5] },
941 { .name = "vdig2", .driver_data = (void *) &tps65910_regs[6] },
942 { .name = "vpll", .driver_data = (void *) &tps65910_regs[7] },
943 { .name = "vdac", .driver_data = (void *) &tps65910_regs[8] },
944 { .name = "vaux1", .driver_data = (void *) &tps65910_regs[9] },
945 { .name = "vaux2", .driver_data = (void *) &tps65910_regs[10] },
946 { .name = "vaux33", .driver_data = (void *) &tps65910_regs[11] },
947 { .name = "vmmc", .driver_data = (void *) &tps65910_regs[12] },
6790178f
RK
948};
949
950static struct of_regulator_match tps65911_matches[] = {
33a6943d
LD
951 { .name = "vrtc", .driver_data = (void *) &tps65911_regs[0] },
952 { .name = "vio", .driver_data = (void *) &tps65911_regs[1] },
953 { .name = "vdd1", .driver_data = (void *) &tps65911_regs[2] },
954 { .name = "vdd2", .driver_data = (void *) &tps65911_regs[3] },
955 { .name = "vddctrl", .driver_data = (void *) &tps65911_regs[4] },
956 { .name = "ldo1", .driver_data = (void *) &tps65911_regs[5] },
957 { .name = "ldo2", .driver_data = (void *) &tps65911_regs[6] },
958 { .name = "ldo3", .driver_data = (void *) &tps65911_regs[7] },
959 { .name = "ldo4", .driver_data = (void *) &tps65911_regs[8] },
960 { .name = "ldo5", .driver_data = (void *) &tps65911_regs[9] },
961 { .name = "ldo6", .driver_data = (void *) &tps65911_regs[10] },
962 { .name = "ldo7", .driver_data = (void *) &tps65911_regs[11] },
963 { .name = "ldo8", .driver_data = (void *) &tps65911_regs[12] },
6790178f
RK
964};
965
966static struct tps65910_board *tps65910_parse_dt_reg_data(
84df8c12
LD
967 struct platform_device *pdev,
968 struct of_regulator_match **tps65910_reg_matches)
6790178f
RK
969{
970 struct tps65910_board *pmic_plat_data;
971 struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent);
972 struct device_node *np = pdev->dev.parent->of_node;
973 struct device_node *regulators;
974 struct of_regulator_match *matches;
975 unsigned int prop;
976 int idx = 0, ret, count;
977
978 pmic_plat_data = devm_kzalloc(&pdev->dev, sizeof(*pmic_plat_data),
979 GFP_KERNEL);
980
981 if (!pmic_plat_data) {
982 dev_err(&pdev->dev, "Failure to alloc pdata for regulators.\n");
983 return NULL;
984 }
985
986 regulators = of_find_node_by_name(np, "regulators");
92ab953b
LD
987 if (!regulators) {
988 dev_err(&pdev->dev, "regulator node not found\n");
989 return NULL;
990 }
6790178f
RK
991
992 switch (tps65910_chip_id(tps65910)) {
993 case TPS65910:
994 count = ARRAY_SIZE(tps65910_matches);
995 matches = tps65910_matches;
996 break;
997 case TPS65911:
998 count = ARRAY_SIZE(tps65911_matches);
999 matches = tps65911_matches;
1000 break;
1001 default:
7e9a57e6 1002 dev_err(&pdev->dev, "Invalid tps chip version\n");
6790178f
RK
1003 return NULL;
1004 }
1005
1006 ret = of_regulator_match(pdev->dev.parent, regulators, matches, count);
1007 if (ret < 0) {
1008 dev_err(&pdev->dev, "Error parsing regulator init data: %d\n",
1009 ret);
1010 return NULL;
1011 }
1012
84df8c12
LD
1013 *tps65910_reg_matches = matches;
1014
6790178f
RK
1015 for (idx = 0; idx < count; idx++) {
1016 if (!matches[idx].init_data || !matches[idx].of_node)
1017 continue;
1018
1019 pmic_plat_data->tps65910_pmic_init_data[idx] =
1020 matches[idx].init_data;
1021
1022 ret = of_property_read_u32(matches[idx].of_node,
1023 "ti,regulator-ext-sleep-control", &prop);
1024 if (!ret)
1025 pmic_plat_data->regulator_ext_sleep_control[idx] = prop;
1026 }
1027
1028 return pmic_plat_data;
1029}
1030#else
1031static inline struct tps65910_board *tps65910_parse_dt_reg_data(
84df8c12
LD
1032 struct platform_device *pdev,
1033 struct of_regulator_match **tps65910_reg_matches)
6790178f 1034{
84df8c12 1035 *tps65910_reg_matches = NULL;
74ea0e59 1036 return NULL;
6790178f
RK
1037}
1038#endif
1039
518fb721
GG
1040static __devinit int tps65910_probe(struct platform_device *pdev)
1041{
1042 struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent);
c172708d 1043 struct regulator_config config = { };
a320e3c3 1044 struct tps_info *info;
518fb721
GG
1045 struct regulator_init_data *reg_data;
1046 struct regulator_dev *rdev;
1047 struct tps65910_reg *pmic;
1048 struct tps65910_board *pmic_plat_data;
84df8c12 1049 struct of_regulator_match *tps65910_reg_matches = NULL;
518fb721
GG
1050 int i, err;
1051
1052 pmic_plat_data = dev_get_platdata(tps65910->dev);
6790178f 1053 if (!pmic_plat_data && tps65910->dev->of_node)
84df8c12
LD
1054 pmic_plat_data = tps65910_parse_dt_reg_data(pdev,
1055 &tps65910_reg_matches);
6790178f 1056
7e9a57e6
LD
1057 if (!pmic_plat_data) {
1058 dev_err(&pdev->dev, "Platform data not found\n");
518fb721 1059 return -EINVAL;
7e9a57e6 1060 }
518fb721 1061
9eb0c421 1062 pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
7e9a57e6
LD
1063 if (!pmic) {
1064 dev_err(&pdev->dev, "Memory allocation failed for pmic\n");
518fb721 1065 return -ENOMEM;
7e9a57e6 1066 }
518fb721
GG
1067
1068 mutex_init(&pmic->mutex);
1069 pmic->mfd = tps65910;
1070 platform_set_drvdata(pdev, pmic);
1071
1072 /* Give control of all register to control port */
3f7e8275 1073 tps65910_reg_set_bits(pmic->mfd, TPS65910_DEVCTRL,
518fb721
GG
1074 DEVCTRL_SR_CTL_I2C_SEL_MASK);
1075
a320e3c3
JEC
1076 switch(tps65910_chip_id(tps65910)) {
1077 case TPS65910:
1078 pmic->get_ctrl_reg = &tps65910_get_ctrl_register;
39aa9b6e 1079 pmic->num_regulators = ARRAY_SIZE(tps65910_regs);
1e0c66f4 1080 pmic->ext_sleep_control = tps65910_ext_sleep_control;
a320e3c3 1081 info = tps65910_regs;
d04156bc 1082 break;
a320e3c3
JEC
1083 case TPS65911:
1084 pmic->get_ctrl_reg = &tps65911_get_ctrl_register;
39aa9b6e 1085 pmic->num_regulators = ARRAY_SIZE(tps65911_regs);
1e0c66f4 1086 pmic->ext_sleep_control = tps65911_ext_sleep_control;
a320e3c3 1087 info = tps65911_regs;
d04156bc 1088 break;
a320e3c3 1089 default:
7e9a57e6 1090 dev_err(&pdev->dev, "Invalid tps chip version\n");
a320e3c3
JEC
1091 return -ENODEV;
1092 }
1093
68d8c1cd 1094 pmic->desc = devm_kzalloc(&pdev->dev, pmic->num_regulators *
39aa9b6e
AL
1095 sizeof(struct regulator_desc), GFP_KERNEL);
1096 if (!pmic->desc) {
68d8c1cd
LD
1097 dev_err(&pdev->dev, "Memory alloc fails for desc\n");
1098 return -ENOMEM;
39aa9b6e
AL
1099 }
1100
68d8c1cd 1101 pmic->info = devm_kzalloc(&pdev->dev, pmic->num_regulators *
39aa9b6e
AL
1102 sizeof(struct tps_info *), GFP_KERNEL);
1103 if (!pmic->info) {
68d8c1cd
LD
1104 dev_err(&pdev->dev, "Memory alloc fails for info\n");
1105 return -ENOMEM;
39aa9b6e
AL
1106 }
1107
68d8c1cd 1108 pmic->rdev = devm_kzalloc(&pdev->dev, pmic->num_regulators *
39aa9b6e
AL
1109 sizeof(struct regulator_dev *), GFP_KERNEL);
1110 if (!pmic->rdev) {
68d8c1cd
LD
1111 dev_err(&pdev->dev, "Memory alloc fails for rdev\n");
1112 return -ENOMEM;
39aa9b6e
AL
1113 }
1114
c1fc1480
KM
1115 for (i = 0; i < pmic->num_regulators && i < TPS65910_NUM_REGS;
1116 i++, info++) {
1117
1118 reg_data = pmic_plat_data->tps65910_pmic_init_data[i];
1119
1120 /* Regulator API handles empty constraints but not NULL
1121 * constraints */
1122 if (!reg_data)
1123 continue;
1124
518fb721
GG
1125 /* Register the regulators */
1126 pmic->info[i] = info;
1127
1128 pmic->desc[i].name = info->name;
77fa44d0 1129 pmic->desc[i].id = i;
7d38a3cb 1130 pmic->desc[i].n_voltages = info->n_voltages;
94f48ab3 1131 pmic->desc[i].enable_time = info->enable_time_us;
518fb721 1132
a320e3c3 1133 if (i == TPS65910_REG_VDD1 || i == TPS65910_REG_VDD2) {
518fb721 1134 pmic->desc[i].ops = &tps65910_ops_dcdc;
780dc9ba
AM
1135 pmic->desc[i].n_voltages = VDD1_2_NUM_VOLT_FINE *
1136 VDD1_2_NUM_VOLT_COARSE;
01bc3a14 1137 pmic->desc[i].ramp_delay = 12500;
a320e3c3 1138 } else if (i == TPS65910_REG_VDD3) {
01bc3a14 1139 if (tps65910_chip_id(tps65910) == TPS65910) {
a320e3c3 1140 pmic->desc[i].ops = &tps65910_ops_vdd3;
d9fe28f9 1141 pmic->desc[i].volt_table = info->voltage_table;
01bc3a14 1142 } else {
a320e3c3 1143 pmic->desc[i].ops = &tps65910_ops_dcdc;
01bc3a14
AL
1144 pmic->desc[i].ramp_delay = 5000;
1145 }
a320e3c3 1146 } else {
d9fe28f9 1147 if (tps65910_chip_id(tps65910) == TPS65910) {
a320e3c3 1148 pmic->desc[i].ops = &tps65910_ops;
d9fe28f9
AL
1149 pmic->desc[i].volt_table = info->voltage_table;
1150 } else {
a320e3c3 1151 pmic->desc[i].ops = &tps65911_ops;
d9fe28f9 1152 }
a320e3c3 1153 }
518fb721 1154
1e0c66f4
LD
1155 err = tps65910_set_ext_sleep_config(pmic, i,
1156 pmic_plat_data->regulator_ext_sleep_control[i]);
1157 /*
1158 * Failing on regulator for configuring externally control
1159 * is not a serious issue, just throw warning.
1160 */
1161 if (err < 0)
1162 dev_warn(tps65910->dev,
1163 "Failed to initialise ext control config\n");
1164
518fb721
GG
1165 pmic->desc[i].type = REGULATOR_VOLTAGE;
1166 pmic->desc[i].owner = THIS_MODULE;
a40a9c43
AL
1167 pmic->desc[i].enable_reg = pmic->get_ctrl_reg(i);
1168 pmic->desc[i].enable_mask = TPS65910_SUPPLY_STATE_ENABLED;
518fb721 1169
c172708d
MB
1170 config.dev = tps65910->dev;
1171 config.init_data = reg_data;
1172 config.driver_data = pmic;
a40a9c43 1173 config.regmap = tps65910->regmap;
c172708d 1174
84df8c12
LD
1175 if (tps65910_reg_matches)
1176 config.of_node = tps65910_reg_matches[i].of_node;
6790178f 1177
c172708d 1178 rdev = regulator_register(&pmic->desc[i], &config);
518fb721
GG
1179 if (IS_ERR(rdev)) {
1180 dev_err(tps65910->dev,
1181 "failed to register %s regulator\n",
1182 pdev->name);
1183 err = PTR_ERR(rdev);
39aa9b6e 1184 goto err_unregister_regulator;
518fb721
GG
1185 }
1186
1187 /* Save regulator for cleanup */
1188 pmic->rdev[i] = rdev;
1189 }
1190 return 0;
1191
39aa9b6e 1192err_unregister_regulator:
518fb721
GG
1193 while (--i >= 0)
1194 regulator_unregister(pmic->rdev[i]);
518fb721
GG
1195 return err;
1196}
1197
1198static int __devexit tps65910_remove(struct platform_device *pdev)
1199{
39aa9b6e 1200 struct tps65910_reg *pmic = platform_get_drvdata(pdev);
518fb721
GG
1201 int i;
1202
39aa9b6e
AL
1203 for (i = 0; i < pmic->num_regulators; i++)
1204 regulator_unregister(pmic->rdev[i]);
518fb721 1205
518fb721
GG
1206 return 0;
1207}
1208
1e0c66f4
LD
1209static void tps65910_shutdown(struct platform_device *pdev)
1210{
1211 struct tps65910_reg *pmic = platform_get_drvdata(pdev);
1212 int i;
1213
1214 /*
1215 * Before bootloader jumps to kernel, it makes sure that required
1216 * external control signals are in desired state so that given rails
1217 * can be configure accordingly.
1218 * If rails are configured to be controlled from external control
1219 * then before shutting down/rebooting the system, the external
1220 * control configuration need to be remove from the rails so that
1221 * its output will be available as per register programming even
1222 * if external controls are removed. This is require when the POR
1223 * value of the control signals are not in active state and before
1224 * bootloader initializes it, the system requires the rail output
1225 * to be active for booting.
1226 */
1227 for (i = 0; i < pmic->num_regulators; i++) {
1228 int err;
1229 if (!pmic->rdev[i])
1230 continue;
1231
1232 err = tps65910_set_ext_sleep_config(pmic, i, 0);
1233 if (err < 0)
1234 dev_err(&pdev->dev,
1235 "Error in clearing external control\n");
1236 }
1237}
1238
518fb721
GG
1239static struct platform_driver tps65910_driver = {
1240 .driver = {
1241 .name = "tps65910-pmic",
1242 .owner = THIS_MODULE,
1243 },
1244 .probe = tps65910_probe,
1245 .remove = __devexit_p(tps65910_remove),
1e0c66f4 1246 .shutdown = tps65910_shutdown,
518fb721
GG
1247};
1248
1249static int __init tps65910_init(void)
1250{
1251 return platform_driver_register(&tps65910_driver);
1252}
1253subsys_initcall(tps65910_init);
1254
1255static void __exit tps65910_cleanup(void)
1256{
1257 platform_driver_unregister(&tps65910_driver);
1258}
1259module_exit(tps65910_cleanup);
1260
1261MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
ae0e6544 1262MODULE_DESCRIPTION("TPS65910/TPS65911 voltage regulator driver");
518fb721
GG
1263MODULE_LICENSE("GPL v2");
1264MODULE_ALIAS("platform:tps65910-pmic");