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regulator: da903x: Convert to get_voltage_sel
[mirror_ubuntu-artful-kernel.git] / drivers / regulator / tps65910-regulator.c
CommitLineData
518fb721
GG		 1/*
2 * tps65910.c -- TI tps65910
3 *
4 * Copyright 2010 Texas Instruments Inc.
5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/err.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/driver.h>
22#include <linux/regulator/machine.h>
518fb721
GG		 23#include <linux/slab.h>
24#include <linux/gpio.h>
25#include <linux/mfd/tps65910.h>
26
518fb721 27#define TPS65910_SUPPLY_STATE_ENABLED 0x1
1e0c66f4
LD		 28#define EXT_SLEEP_CONTROL (TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 | \
29 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 | \
f30b0716
LD		 30 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 | \
31 TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP)
518fb721
GG		 32
33/* supported VIO voltages in milivolts */
34static const u16 VIO_VSEL_table[] = {
35 1500, 1800, 2500, 3300,
36};
37
a320e3c3
JEC		 38/* VSEL tables for TPS65910 specific LDOs and dcdc's */
39
40/* supported VDD3 voltages in milivolts */
518fb721
GG		 41static const u16 VDD3_VSEL_table[] = {
42 5000,
43};
44
45/* supported VDIG1 voltages in milivolts */
46static const u16 VDIG1_VSEL_table[] = {
47 1200, 1500, 1800, 2700,
48};
49
50/* supported VDIG2 voltages in milivolts */
51static const u16 VDIG2_VSEL_table[] = {
52 1000, 1100, 1200, 1800,
53};
54
55/* supported VPLL voltages in milivolts */
56static const u16 VPLL_VSEL_table[] = {
57 1000, 1100, 1800, 2500,
58};
59
60/* supported VDAC voltages in milivolts */
61static const u16 VDAC_VSEL_table[] = {
62 1800, 2600, 2800, 2850,
63};
64
65/* supported VAUX1 voltages in milivolts */
66static const u16 VAUX1_VSEL_table[] = {
67 1800, 2500, 2800, 2850,
68};
69
70/* supported VAUX2 voltages in milivolts */
71static const u16 VAUX2_VSEL_table[] = {
72 1800, 2800, 2900, 3300,
73};
74
75/* supported VAUX33 voltages in milivolts */
76static const u16 VAUX33_VSEL_table[] = {
77 1800, 2000, 2800, 3300,
78};
79
80/* supported VMMC voltages in milivolts */
81static const u16 VMMC_VSEL_table[] = {
82 1800, 2800, 3000, 3300,
83};
84
85struct tps_info {
86 const char *name;
87 unsigned min_uV;
88 unsigned max_uV;
7d38a3cb
LD		 89 u8 n_voltages;
90 const u16 *voltage_table;
0651eed5 91 int enable_time_us;
518fb721
GG		 92};
93
94static struct tps_info tps65910_regs[] = {
95 {
96 .name = "VRTC",
0651eed5 97 .enable_time_us = 2200,
518fb721
GG		 98 },
99 {
100 .name = "VIO",
101 .min_uV = 1500000,
102 .max_uV = 3300000,
7d38a3cb
LD		 103 .n_voltages = ARRAY_SIZE(VIO_VSEL_table),
104 .voltage_table = VIO_VSEL_table,
0651eed5 105 .enable_time_us = 350,
518fb721
GG		 106 },
107 {
108 .name = "VDD1",
109 .min_uV = 600000,
110 .max_uV = 4500000,
0651eed5 111 .enable_time_us = 350,
518fb721
GG		 112 },
113 {
114 .name = "VDD2",
115 .min_uV = 600000,
116 .max_uV = 4500000,
0651eed5 117 .enable_time_us = 350,
518fb721
GG		 118 },
119 {
120 .name = "VDD3",
121 .min_uV = 5000000,
122 .max_uV = 5000000,
7d38a3cb
LD		 123 .n_voltages = ARRAY_SIZE(VDD3_VSEL_table),
124 .voltage_table = VDD3_VSEL_table,
0651eed5 125 .enable_time_us = 200,
518fb721
GG		 126 },
127 {
128 .name = "VDIG1",
129 .min_uV = 1200000,
130 .max_uV = 2700000,
7d38a3cb
LD		 131 .n_voltages = ARRAY_SIZE(VDIG1_VSEL_table),
132 .voltage_table = VDIG1_VSEL_table,
0651eed5 133 .enable_time_us = 100,
518fb721
GG		 134 },
135 {
136 .name = "VDIG2",
137 .min_uV = 1000000,
138 .max_uV = 1800000,
7d38a3cb
LD		 139 .n_voltages = ARRAY_SIZE(VDIG2_VSEL_table),
140 .voltage_table = VDIG2_VSEL_table,
0651eed5 141 .enable_time_us = 100,
518fb721
GG		 142 },
143 {
144 .name = "VPLL",
145 .min_uV = 1000000,
146 .max_uV = 2500000,
7d38a3cb
LD		 147 .n_voltages = ARRAY_SIZE(VPLL_VSEL_table),
148 .voltage_table = VPLL_VSEL_table,
0651eed5 149 .enable_time_us = 100,
518fb721
GG		 150 },
151 {
152 .name = "VDAC",
153 .min_uV = 1800000,
154 .max_uV = 2850000,
7d38a3cb
LD		 155 .n_voltages = ARRAY_SIZE(VDAC_VSEL_table),
156 .voltage_table = VDAC_VSEL_table,
0651eed5 157 .enable_time_us = 100,
518fb721
GG		 158 },
159 {
160 .name = "VAUX1",
161 .min_uV = 1800000,
162 .max_uV = 2850000,
7d38a3cb
LD		 163 .n_voltages = ARRAY_SIZE(VAUX1_VSEL_table),
164 .voltage_table = VAUX1_VSEL_table,
0651eed5 165 .enable_time_us = 100,
518fb721
GG		 166 },
167 {
168 .name = "VAUX2",
169 .min_uV = 1800000,
170 .max_uV = 3300000,
7d38a3cb
LD		 171 .n_voltages = ARRAY_SIZE(VAUX2_VSEL_table),
172 .voltage_table = VAUX2_VSEL_table,
0651eed5 173 .enable_time_us = 100,
518fb721
GG		 174 },
175 {
176 .name = "VAUX33",
177 .min_uV = 1800000,
178 .max_uV = 3300000,
7d38a3cb
LD		 179 .n_voltages = ARRAY_SIZE(VAUX33_VSEL_table),
180 .voltage_table = VAUX33_VSEL_table,
0651eed5 181 .enable_time_us = 100,
518fb721
GG		 182 },
183 {
184 .name = "VMMC",
185 .min_uV = 1800000,
186 .max_uV = 3300000,
7d38a3cb
LD		 187 .n_voltages = ARRAY_SIZE(VMMC_VSEL_table),
188 .voltage_table = VMMC_VSEL_table,
0651eed5 189 .enable_time_us = 100,
518fb721
GG		 190 },
191};
192
a320e3c3 193static struct tps_info tps65911_regs[] = {
c2f8efd7
LD		 194 {
195 .name = "VRTC",
0651eed5 196 .enable_time_us = 2200,
c2f8efd7 197 },
a320e3c3
JEC		 198 {
199 .name = "VIO",
200 .min_uV = 1500000,
201 .max_uV = 3300000,
7d38a3cb
LD		 202 .n_voltages = ARRAY_SIZE(VIO_VSEL_table),
203 .voltage_table = VIO_VSEL_table,
0651eed5 204 .enable_time_us = 350,
a320e3c3
JEC		 205 },
206 {
207 .name = "VDD1",
208 .min_uV = 600000,
209 .max_uV = 4500000,
7d38a3cb 210 .n_voltages = 73,
0651eed5 211 .enable_time_us = 350,
a320e3c3
JEC		 212 },
213 {
214 .name = "VDD2",
215 .min_uV = 600000,
216 .max_uV = 4500000,
7d38a3cb 217 .n_voltages = 73,
0651eed5 218 .enable_time_us = 350,
a320e3c3
JEC		 219 },
220 {
221 .name = "VDDCTRL",
222 .min_uV = 600000,
223 .max_uV = 1400000,
7d38a3cb 224 .n_voltages = 65,
0651eed5 225 .enable_time_us = 900,
a320e3c3
JEC		 226 },
227 {
228 .name = "LDO1",
229 .min_uV = 1000000,
230 .max_uV = 3300000,
7d38a3cb 231 .n_voltages = 47,
0651eed5 232 .enable_time_us = 420,
a320e3c3
JEC		 233 },
234 {
235 .name = "LDO2",
236 .min_uV = 1000000,
237 .max_uV = 3300000,
7d38a3cb 238 .n_voltages = 47,
0651eed5 239 .enable_time_us = 420,
a320e3c3
JEC		 240 },
241 {
242 .name = "LDO3",
243 .min_uV = 1000000,
244 .max_uV = 3300000,
7d38a3cb 245 .n_voltages = 24,
0651eed5 246 .enable_time_us = 230,
a320e3c3
JEC		 247 },
248 {
249 .name = "LDO4",
250 .min_uV = 1000000,
251 .max_uV = 3300000,
7d38a3cb 252 .n_voltages = 47,
0651eed5 253 .enable_time_us = 230,
a320e3c3
JEC		 254 },
255 {
256 .name = "LDO5",
257 .min_uV = 1000000,
258 .max_uV = 3300000,
7d38a3cb 259 .n_voltages = 24,
0651eed5 260 .enable_time_us = 230,
a320e3c3
JEC		 261 },
262 {
263 .name = "LDO6",
264 .min_uV = 1000000,
265 .max_uV = 3300000,
7d38a3cb 266 .n_voltages = 24,
0651eed5 267 .enable_time_us = 230,
a320e3c3
JEC		 268 },
269 {
270 .name = "LDO7",
271 .min_uV = 1000000,
272 .max_uV = 3300000,
7d38a3cb 273 .n_voltages = 24,
0651eed5 274 .enable_time_us = 230,
a320e3c3
JEC		 275 },
276 {
277 .name = "LDO8",
278 .min_uV = 1000000,
279 .max_uV = 3300000,
7d38a3cb 280 .n_voltages = 24,
0651eed5 281 .enable_time_us = 230,
a320e3c3
JEC		 282 },
283};
284
1e0c66f4
LD		 285#define EXT_CONTROL_REG_BITS(id, regs_offs, bits) (((regs_offs) << 8) | (bits))
286static unsigned int tps65910_ext_sleep_control[] = {
287 0,
288 EXT_CONTROL_REG_BITS(VIO, 1, 0),
289 EXT_CONTROL_REG_BITS(VDD1, 1, 1),
290 EXT_CONTROL_REG_BITS(VDD2, 1, 2),
291 EXT_CONTROL_REG_BITS(VDD3, 1, 3),
292 EXT_CONTROL_REG_BITS(VDIG1, 0, 1),
293 EXT_CONTROL_REG_BITS(VDIG2, 0, 2),
294 EXT_CONTROL_REG_BITS(VPLL, 0, 6),
295 EXT_CONTROL_REG_BITS(VDAC, 0, 7),
296 EXT_CONTROL_REG_BITS(VAUX1, 0, 3),
297 EXT_CONTROL_REG_BITS(VAUX2, 0, 4),
298 EXT_CONTROL_REG_BITS(VAUX33, 0, 5),
299 EXT_CONTROL_REG_BITS(VMMC, 0, 0),
300};
301
302static unsigned int tps65911_ext_sleep_control[] = {
303 0,
304 EXT_CONTROL_REG_BITS(VIO, 1, 0),
305 EXT_CONTROL_REG_BITS(VDD1, 1, 1),
306 EXT_CONTROL_REG_BITS(VDD2, 1, 2),
307 EXT_CONTROL_REG_BITS(VDDCTRL, 1, 3),
308 EXT_CONTROL_REG_BITS(LDO1, 0, 1),
309 EXT_CONTROL_REG_BITS(LDO2, 0, 2),
310 EXT_CONTROL_REG_BITS(LDO3, 0, 7),
311 EXT_CONTROL_REG_BITS(LDO4, 0, 6),
312 EXT_CONTROL_REG_BITS(LDO5, 0, 3),
313 EXT_CONTROL_REG_BITS(LDO6, 0, 0),
314 EXT_CONTROL_REG_BITS(LDO7, 0, 5),
315 EXT_CONTROL_REG_BITS(LDO8, 0, 4),
316};
317
518fb721 318struct tps65910_reg {
39aa9b6e 319 struct regulator_desc *desc;
518fb721 320 struct tps65910 *mfd;
39aa9b6e
AL		 321 struct regulator_dev **rdev;
322 struct tps_info **info;
518fb721 323 struct mutex mutex;
39aa9b6e 324 int num_regulators;
518fb721 325 int mode;
a320e3c3 326 int (*get_ctrl_reg)(int);
1e0c66f4
LD		 327 unsigned int *ext_sleep_control;
328 unsigned int board_ext_control[TPS65910_NUM_REGS];
518fb721
GG		 329};
330
331static inline int tps65910_read(struct tps65910_reg *pmic, u8 reg)
332{
333 u8 val;
334 int err;
335
336 err = pmic->mfd->read(pmic->mfd, reg, 1, &val);
337 if (err)
338 return err;
339
340 return val;
341}
342
343static inline int tps65910_write(struct tps65910_reg *pmic, u8 reg, u8 val)
344{
345 return pmic->mfd->write(pmic->mfd, reg, 1, &val);
346}
347
348static int tps65910_modify_bits(struct tps65910_reg *pmic, u8 reg,
349 u8 set_mask, u8 clear_mask)
350{
351 int err, data;
352
353 mutex_lock(&pmic->mutex);
354
355 data = tps65910_read(pmic, reg);
356 if (data < 0) {
357 dev_err(pmic->mfd->dev, "Read from reg 0x%x failed\n", reg);
358 err = data;
359 goto out;
360 }
361
362 data &= ~clear_mask;
363 data |= set_mask;
364 err = tps65910_write(pmic, reg, data);
365 if (err)
366 dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg);
367
368out:
369 mutex_unlock(&pmic->mutex);
370 return err;
371}
372
373static int tps65910_reg_read(struct tps65910_reg *pmic, u8 reg)
374{
375 int data;
376
377 mutex_lock(&pmic->mutex);
378
379 data = tps65910_read(pmic, reg);
380 if (data < 0)
381 dev_err(pmic->mfd->dev, "Read from reg 0x%x failed\n", reg);
382
383 mutex_unlock(&pmic->mutex);
384 return data;
385}
386
387static int tps65910_reg_write(struct tps65910_reg *pmic, u8 reg, u8 val)
388{
389 int err;
390
391 mutex_lock(&pmic->mutex);
392
393 err = tps65910_write(pmic, reg, val);
394 if (err < 0)
395 dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg);
396
397 mutex_unlock(&pmic->mutex);
398 return err;
399}
400
401static int tps65910_get_ctrl_register(int id)
402{
403 switch (id) {
404 case TPS65910_REG_VRTC:
405 return TPS65910_VRTC;
406 case TPS65910_REG_VIO:
407 return TPS65910_VIO;
408 case TPS65910_REG_VDD1:
409 return TPS65910_VDD1;
410 case TPS65910_REG_VDD2:
411 return TPS65910_VDD2;
412 case TPS65910_REG_VDD3:
413 return TPS65910_VDD3;
414 case TPS65910_REG_VDIG1:
415 return TPS65910_VDIG1;
416 case TPS65910_REG_VDIG2:
417 return TPS65910_VDIG2;
418 case TPS65910_REG_VPLL:
419 return TPS65910_VPLL;
420 case TPS65910_REG_VDAC:
421 return TPS65910_VDAC;
422 case TPS65910_REG_VAUX1:
423 return TPS65910_VAUX1;
424 case TPS65910_REG_VAUX2:
425 return TPS65910_VAUX2;
426 case TPS65910_REG_VAUX33:
427 return TPS65910_VAUX33;
428 case TPS65910_REG_VMMC:
429 return TPS65910_VMMC;
430 default:
431 return -EINVAL;
432 }
433}
434
a320e3c3
JEC		 435static int tps65911_get_ctrl_register(int id)
436{
437 switch (id) {
438 case TPS65910_REG_VRTC:
439 return TPS65910_VRTC;
440 case TPS65910_REG_VIO:
441 return TPS65910_VIO;
442 case TPS65910_REG_VDD1:
443 return TPS65910_VDD1;
444 case TPS65910_REG_VDD2:
445 return TPS65910_VDD2;
446 case TPS65911_REG_VDDCTRL:
447 return TPS65911_VDDCTRL;
448 case TPS65911_REG_LDO1:
449 return TPS65911_LDO1;
450 case TPS65911_REG_LDO2:
451 return TPS65911_LDO2;
452 case TPS65911_REG_LDO3:
453 return TPS65911_LDO3;
454 case TPS65911_REG_LDO4:
455 return TPS65911_LDO4;
456 case TPS65911_REG_LDO5:
457 return TPS65911_LDO5;
458 case TPS65911_REG_LDO6:
459 return TPS65911_LDO6;
460 case TPS65911_REG_LDO7:
461 return TPS65911_LDO7;
462 case TPS65911_REG_LDO8:
463 return TPS65911_LDO8;
464 default:
465 return -EINVAL;
466 }
467}
468
0651eed5
LD		 469static int tps65910_enable_time(struct regulator_dev *dev)
470{
471 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
472 int id = rdev_get_id(dev);
473 return pmic->info[id]->enable_time_us;
474}
518fb721
GG		 475
476static int tps65910_set_mode(struct regulator_dev *dev, unsigned int mode)
477{
478 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
479 struct tps65910 *mfd = pmic->mfd;
480 int reg, value, id = rdev_get_id(dev);
a320e3c3
JEC		 481
482 reg = pmic->get_ctrl_reg(id);
518fb721
GG		 483 if (reg < 0)
484 return reg;
485
486 switch (mode) {
487 case REGULATOR_MODE_NORMAL:
488 return tps65910_modify_bits(pmic, reg, LDO_ST_ON_BIT,
489 LDO_ST_MODE_BIT);
490 case REGULATOR_MODE_IDLE:
491 value = LDO_ST_ON_BIT | LDO_ST_MODE_BIT;
492 return tps65910_set_bits(mfd, reg, value);
493 case REGULATOR_MODE_STANDBY:
494 return tps65910_clear_bits(mfd, reg, LDO_ST_ON_BIT);
495 }
496
497 return -EINVAL;
498}
499
500static unsigned int tps65910_get_mode(struct regulator_dev *dev)
501{
502 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
503 int reg, value, id = rdev_get_id(dev);
504
a320e3c3 505 reg = pmic->get_ctrl_reg(id);
518fb721
GG		 506 if (reg < 0)
507 return reg;
508
509 value = tps65910_reg_read(pmic, reg);
510 if (value < 0)
511 return value;
512
58599393 513 if (!(value & LDO_ST_ON_BIT))
518fb721
GG		 514 return REGULATOR_MODE_STANDBY;
515 else if (value & LDO_ST_MODE_BIT)
516 return REGULATOR_MODE_IDLE;
517 else
518 return REGULATOR_MODE_NORMAL;
519}
520
18039e0f 521static int tps65910_get_voltage_dcdc_sel(struct regulator_dev *dev)
518fb721
GG		 522{
523 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
18039e0f 524 int id = rdev_get_id(dev);
a320e3c3 525 int opvsel = 0, srvsel = 0, vselmax = 0, mult = 0, sr = 0;
518fb721
GG		 526
527 switch (id) {
528 case TPS65910_REG_VDD1:
529 opvsel = tps65910_reg_read(pmic, TPS65910_VDD1_OP);
530 mult = tps65910_reg_read(pmic, TPS65910_VDD1);
531 mult = (mult & VDD1_VGAIN_SEL_MASK) >> VDD1_VGAIN_SEL_SHIFT;
532 srvsel = tps65910_reg_read(pmic, TPS65910_VDD1_SR);
533 sr = opvsel & VDD1_OP_CMD_MASK;
534 opvsel &= VDD1_OP_SEL_MASK;
535 srvsel &= VDD1_SR_SEL_MASK;
a320e3c3 536 vselmax = 75;
518fb721
GG		 537 break;
538 case TPS65910_REG_VDD2:
539 opvsel = tps65910_reg_read(pmic, TPS65910_VDD2_OP);
540 mult = tps65910_reg_read(pmic, TPS65910_VDD2);
541 mult = (mult & VDD2_VGAIN_SEL_MASK) >> VDD2_VGAIN_SEL_SHIFT;
542 srvsel = tps65910_reg_read(pmic, TPS65910_VDD2_SR);
543 sr = opvsel & VDD2_OP_CMD_MASK;
544 opvsel &= VDD2_OP_SEL_MASK;
545 srvsel &= VDD2_SR_SEL_MASK;
a320e3c3
JEC		 546 vselmax = 75;
547 break;
548 case TPS65911_REG_VDDCTRL:
549 opvsel = tps65910_reg_read(pmic, TPS65911_VDDCTRL_OP);
550 srvsel = tps65910_reg_read(pmic, TPS65911_VDDCTRL_SR);
551 sr = opvsel & VDDCTRL_OP_CMD_MASK;
552 opvsel &= VDDCTRL_OP_SEL_MASK;
553 srvsel &= VDDCTRL_SR_SEL_MASK;
554 vselmax = 64;
518fb721
GG		 555 break;
556 }
557
558 /* multiplier 0 == 1 but 2,3 normal */
559 if (!mult)
560 mult=1;
561
562 if (sr) {
a320e3c3
JEC		 563 /* normalise to valid range */
564 if (srvsel < 3)
565 srvsel = 3;
566 if (srvsel > vselmax)
567 srvsel = vselmax;
18039e0f 568 return srvsel - 3;
518fb721
GG		 569 } else {
570
a320e3c3
JEC		 571 /* normalise to valid range*/
572 if (opvsel < 3)
573 opvsel = 3;
574 if (opvsel > vselmax)
575 opvsel = vselmax;
18039e0f 576 return opvsel - 3;
518fb721 577 }
18039e0f 578 return -EINVAL;
518fb721
GG		 579}
580
1f904fd1 581static int tps65910_get_voltage_sel(struct regulator_dev *dev)
518fb721
GG		 582{
583 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
1f904fd1 584 int reg, value, id = rdev_get_id(dev);
518fb721 585
a320e3c3 586 reg = pmic->get_ctrl_reg(id);
518fb721
GG		 587 if (reg < 0)
588 return reg;
589
590 value = tps65910_reg_read(pmic, reg);
591 if (value < 0)
592 return value;
593
594 switch (id) {
595 case TPS65910_REG_VIO:
596 case TPS65910_REG_VDIG1:
597 case TPS65910_REG_VDIG2:
598 case TPS65910_REG_VPLL:
599 case TPS65910_REG_VDAC:
600 case TPS65910_REG_VAUX1:
601 case TPS65910_REG_VAUX2:
602 case TPS65910_REG_VAUX33:
603 case TPS65910_REG_VMMC:
604 value &= LDO_SEL_MASK;
605 value >>= LDO_SEL_SHIFT;
606 break;
607 default:
608 return -EINVAL;
609 }
610
1f904fd1 611 return value;
518fb721
GG		 612}
613
614static int tps65910_get_voltage_vdd3(struct regulator_dev *dev)
615{
616 return 5 * 1000 * 1000;
617}
618
1f904fd1 619static int tps65911_get_voltage_sel(struct regulator_dev *dev)
a320e3c3
JEC		 620{
621 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
1f904fd1 622 int id = rdev_get_id(dev);
a320e3c3
JEC		 623 u8 value, reg;
624
625 reg = pmic->get_ctrl_reg(id);
626
627 value = tps65910_reg_read(pmic, reg);
628
629 switch (id) {
630 case TPS65911_REG_LDO1:
631 case TPS65911_REG_LDO2:
632 case TPS65911_REG_LDO4:
633 value &= LDO1_SEL_MASK;
634 value >>= LDO_SEL_SHIFT;
a320e3c3
JEC		 635 break;
636 case TPS65911_REG_LDO3:
637 case TPS65911_REG_LDO5:
638 case TPS65911_REG_LDO6:
639 case TPS65911_REG_LDO7:
640 case TPS65911_REG_LDO8:
641 value &= LDO3_SEL_MASK;
642 value >>= LDO_SEL_SHIFT;
a320e3c3
JEC		 643 break;
644 case TPS65910_REG_VIO:
e882eae8
LD		 645 value &= LDO_SEL_MASK;
646 value >>= LDO_SEL_SHIFT;
1f904fd1 647 break;
a320e3c3
JEC		 648 default:
649 return -EINVAL;
650 }
651
1f904fd1 652 return value;
a320e3c3
JEC		 653}
654
94732b97
AL		 655static int tps65910_set_voltage_dcdc_sel(struct regulator_dev *dev,
656 unsigned selector)
518fb721
GG		 657{
658 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
659 int id = rdev_get_id(dev), vsel;
a320e3c3 660 int dcdc_mult = 0;
518fb721 661
a320e3c3
JEC		 662 switch (id) {
663 case TPS65910_REG_VDD1:
780dc9ba 664 dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
a320e3c3
JEC		 665 if (dcdc_mult == 1)
666 dcdc_mult--;
780dc9ba 667 vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3;
518fb721 668
518fb721
GG		 669 tps65910_modify_bits(pmic, TPS65910_VDD1,
670 (dcdc_mult << VDD1_VGAIN_SEL_SHIFT),
671 VDD1_VGAIN_SEL_MASK);
672 tps65910_reg_write(pmic, TPS65910_VDD1_OP, vsel);
a320e3c3
JEC		 673 break;
674 case TPS65910_REG_VDD2:
780dc9ba 675 dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
a320e3c3
JEC		 676 if (dcdc_mult == 1)
677 dcdc_mult--;
780dc9ba 678 vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3;
a320e3c3 679
518fb721
GG		 680 tps65910_modify_bits(pmic, TPS65910_VDD2,
681 (dcdc_mult << VDD2_VGAIN_SEL_SHIFT),
682 VDD1_VGAIN_SEL_MASK);
683 tps65910_reg_write(pmic, TPS65910_VDD2_OP, vsel);
a320e3c3
JEC		 684 break;
685 case TPS65911_REG_VDDCTRL:
c4632aed 686 vsel = selector + 3;
a320e3c3 687 tps65910_reg_write(pmic, TPS65911_VDDCTRL_OP, vsel);
518fb721
GG		 688 }
689
690 return 0;
691}
692
94732b97
AL		 693static int tps65910_set_voltage_sel(struct regulator_dev *dev,
694 unsigned selector)
518fb721
GG		 695{
696 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
697 int reg, id = rdev_get_id(dev);
698
a320e3c3 699 reg = pmic->get_ctrl_reg(id);
518fb721
GG		 700 if (reg < 0)
701 return reg;
702
703 switch (id) {
704 case TPS65910_REG_VIO:
705 case TPS65910_REG_VDIG1:
706 case TPS65910_REG_VDIG2:
707 case TPS65910_REG_VPLL:
708 case TPS65910_REG_VDAC:
709 case TPS65910_REG_VAUX1:
710 case TPS65910_REG_VAUX2:
711 case TPS65910_REG_VAUX33:
712 case TPS65910_REG_VMMC:
713 return tps65910_modify_bits(pmic, reg,
714 (selector << LDO_SEL_SHIFT), LDO_SEL_MASK);
715 }
716
717 return -EINVAL;
718}
719
94732b97
AL		 720static int tps65911_set_voltage_sel(struct regulator_dev *dev,
721 unsigned selector)
a320e3c3
JEC		 722{
723 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
724 int reg, id = rdev_get_id(dev);
725
726 reg = pmic->get_ctrl_reg(id);
727 if (reg < 0)
728 return reg;
729
730 switch (id) {
731 case TPS65911_REG_LDO1:
732 case TPS65911_REG_LDO2:
733 case TPS65911_REG_LDO4:
734 return tps65910_modify_bits(pmic, reg,
735 (selector << LDO_SEL_SHIFT), LDO1_SEL_MASK);
736 case TPS65911_REG_LDO3:
737 case TPS65911_REG_LDO5:
738 case TPS65911_REG_LDO6:
739 case TPS65911_REG_LDO7:
740 case TPS65911_REG_LDO8:
a320e3c3
JEC		 741 return tps65910_modify_bits(pmic, reg,
742 (selector << LDO_SEL_SHIFT), LDO3_SEL_MASK);
e882eae8
LD		 743 case TPS65910_REG_VIO:
744 return tps65910_modify_bits(pmic, reg,
745 (selector << LDO_SEL_SHIFT), LDO_SEL_MASK);
a320e3c3
JEC		 746 }
747
748 return -EINVAL;
749}
750
751
518fb721
GG		 752static int tps65910_list_voltage_dcdc(struct regulator_dev *dev,
753 unsigned selector)
754{
a320e3c3 755 int volt, mult = 1, id = rdev_get_id(dev);
518fb721 756
a320e3c3
JEC		 757 switch (id) {
758 case TPS65910_REG_VDD1:
759 case TPS65910_REG_VDD2:
780dc9ba 760 mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
a320e3c3 761 volt = VDD1_2_MIN_VOLT +
780dc9ba 762 (selector % VDD1_2_NUM_VOLT_FINE) * VDD1_2_OFFSET;
d04156bc 763 break;
a320e3c3
JEC		 764 case TPS65911_REG_VDDCTRL:
765 volt = VDDCTRL_MIN_VOLT + (selector * VDDCTRL_OFFSET);
d04156bc
AL		 766 break;
767 default:
768 BUG();
769 return -EINVAL;
a320e3c3 770 }
518fb721
GG		 771
772 return volt * 100 * mult;
773}
774
775static int tps65910_list_voltage(struct regulator_dev *dev,
776 unsigned selector)
777{
778 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
779 int id = rdev_get_id(dev), voltage;
780
781 if (id < TPS65910_REG_VIO || id > TPS65910_REG_VMMC)
782 return -EINVAL;
783
7d38a3cb 784 if (selector >= pmic->info[id]->n_voltages)
518fb721
GG		 785 return -EINVAL;
786 else
7d38a3cb 787 voltage = pmic->info[id]->voltage_table[selector] * 1000;
518fb721
GG		 788
789 return voltage;
790}
791
a320e3c3
JEC		 792static int tps65911_list_voltage(struct regulator_dev *dev, unsigned selector)
793{
794 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
795 int step_mv = 0, id = rdev_get_id(dev);
796
797 switch(id) {
798 case TPS65911_REG_LDO1:
799 case TPS65911_REG_LDO2:
800 case TPS65911_REG_LDO4:
801 /* The first 5 values of the selector correspond to 1V */
802 if (selector < 5)
803 selector = 0;
804 else
805 selector -= 4;
806
807 step_mv = 50;
808 break;
809 case TPS65911_REG_LDO3:
810 case TPS65911_REG_LDO5:
811 case TPS65911_REG_LDO6:
812 case TPS65911_REG_LDO7:
813 case TPS65911_REG_LDO8:
814 /* The first 3 values of the selector correspond to 1V */
815 if (selector < 3)
816 selector = 0;
817 else
818 selector -= 2;
819
820 step_mv = 100;
821 break;
822 case TPS65910_REG_VIO:
7d38a3cb 823 return pmic->info[id]->voltage_table[selector] * 1000;
a320e3c3
JEC		 824 default:
825 return -EINVAL;
826 }
827
828 return (LDO_MIN_VOLT + selector * step_mv) * 1000;
829}
830
18039e0f
LD		 831static int tps65910_set_voltage_dcdc_time_sel(struct regulator_dev *dev,
832 unsigned int old_selector, unsigned int new_selector)
833{
834 int id = rdev_get_id(dev);
835 int old_volt, new_volt;
836
837 old_volt = tps65910_list_voltage_dcdc(dev, old_selector);
838 if (old_volt < 0)
839 return old_volt;
840
841 new_volt = tps65910_list_voltage_dcdc(dev, new_selector);
842 if (new_volt < 0)
843 return new_volt;
844
845 /* VDD1 and VDD2 are 12.5mV/us, VDDCTRL is 100mV/20us */
846 switch (id) {
847 case TPS65910_REG_VDD1:
848 case TPS65910_REG_VDD2:
849 return DIV_ROUND_UP(abs(old_volt - new_volt), 12500);
850 case TPS65911_REG_VDDCTRL:
851 return DIV_ROUND_UP(abs(old_volt - new_volt), 5000);
852 }
853 return -EINVAL;
854}
855
518fb721
GG		 856/* Regulator ops (except VRTC) */
857static struct regulator_ops tps65910_ops_dcdc = {
a40a9c43
AL		 858 .is_enabled = regulator_is_enabled_regmap,
859 .enable = regulator_enable_regmap,
860 .disable = regulator_disable_regmap,
0651eed5 861 .enable_time = tps65910_enable_time,
518fb721
GG		 862 .set_mode = tps65910_set_mode,
863 .get_mode = tps65910_get_mode,
18039e0f 864 .get_voltage_sel = tps65910_get_voltage_dcdc_sel,
94732b97 865 .set_voltage_sel = tps65910_set_voltage_dcdc_sel,
18039e0f 866 .set_voltage_time_sel = tps65910_set_voltage_dcdc_time_sel,
518fb721
GG		 867 .list_voltage = tps65910_list_voltage_dcdc,
868};
869
870static struct regulator_ops tps65910_ops_vdd3 = {
a40a9c43
AL		 871 .is_enabled = regulator_is_enabled_regmap,
872 .enable = regulator_enable_regmap,
873 .disable = regulator_disable_regmap,
0651eed5 874 .enable_time = tps65910_enable_time,
518fb721
GG		 875 .set_mode = tps65910_set_mode,
876 .get_mode = tps65910_get_mode,
877 .get_voltage = tps65910_get_voltage_vdd3,
878 .list_voltage = tps65910_list_voltage,
879};
880
881static struct regulator_ops tps65910_ops = {
a40a9c43
AL		 882 .is_enabled = regulator_is_enabled_regmap,
883 .enable = regulator_enable_regmap,
884 .disable = regulator_disable_regmap,
0651eed5 885 .enable_time = tps65910_enable_time,
518fb721
GG		 886 .set_mode = tps65910_set_mode,
887 .get_mode = tps65910_get_mode,
1f904fd1 888 .get_voltage_sel = tps65910_get_voltage_sel,
94732b97 889 .set_voltage_sel = tps65910_set_voltage_sel,
518fb721
GG		 890 .list_voltage = tps65910_list_voltage,
891};
892
a320e3c3 893static struct regulator_ops tps65911_ops = {
a40a9c43
AL		 894 .is_enabled = regulator_is_enabled_regmap,
895 .enable = regulator_enable_regmap,
896 .disable = regulator_disable_regmap,
0651eed5 897 .enable_time = tps65910_enable_time,
a320e3c3
JEC		 898 .set_mode = tps65910_set_mode,
899 .get_mode = tps65910_get_mode,
1f904fd1 900 .get_voltage_sel = tps65911_get_voltage_sel,
94732b97 901 .set_voltage_sel = tps65911_set_voltage_sel,
a320e3c3
JEC		 902 .list_voltage = tps65911_list_voltage,
903};
904
1e0c66f4
LD		 905static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic,
906 int id, int ext_sleep_config)
907{
908 struct tps65910 *mfd = pmic->mfd;
909 u8 regoffs = (pmic->ext_sleep_control[id] >> 8) & 0xFF;
910 u8 bit_pos = (1 << pmic->ext_sleep_control[id] & 0xFF);
911 int ret;
912
913 /*
914 * Regulator can not be control from multiple external input EN1, EN2
915 * and EN3 together.
916 */
917 if (ext_sleep_config & EXT_SLEEP_CONTROL) {
918 int en_count;
919 en_count = ((ext_sleep_config &
920 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) != 0);
921 en_count += ((ext_sleep_config &
922 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) != 0);
923 en_count += ((ext_sleep_config &
924 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) != 0);
f30b0716
LD		 925 en_count += ((ext_sleep_config &
926 TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) != 0);
1e0c66f4
LD		 927 if (en_count > 1) {
928 dev_err(mfd->dev,
929 "External sleep control flag is not proper\n");
930 return -EINVAL;
931 }
932 }
933
934 pmic->board_ext_control[id] = ext_sleep_config;
935
936 /* External EN1 control */
937 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1)
938 ret = tps65910_set_bits(mfd,
939 TPS65910_EN1_LDO_ASS + regoffs, bit_pos);
940 else
941 ret = tps65910_clear_bits(mfd,
942 TPS65910_EN1_LDO_ASS + regoffs, bit_pos);
943 if (ret < 0) {
944 dev_err(mfd->dev,
945 "Error in configuring external control EN1\n");
946 return ret;
947 }
948
949 /* External EN2 control */
950 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2)
951 ret = tps65910_set_bits(mfd,
952 TPS65910_EN2_LDO_ASS + regoffs, bit_pos);
953 else
954 ret = tps65910_clear_bits(mfd,
955 TPS65910_EN2_LDO_ASS + regoffs, bit_pos);
956 if (ret < 0) {
957 dev_err(mfd->dev,
958 "Error in configuring external control EN2\n");
959 return ret;
960 }
961
962 /* External EN3 control for TPS65910 LDO only */
963 if ((tps65910_chip_id(mfd) == TPS65910) &&
964 (id >= TPS65910_REG_VDIG1)) {
965 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3)
966 ret = tps65910_set_bits(mfd,
967 TPS65910_EN3_LDO_ASS + regoffs, bit_pos);
968 else
969 ret = tps65910_clear_bits(mfd,
970 TPS65910_EN3_LDO_ASS + regoffs, bit_pos);
971 if (ret < 0) {
972 dev_err(mfd->dev,
973 "Error in configuring external control EN3\n");
974 return ret;
975 }
976 }
977
978 /* Return if no external control is selected */
979 if (!(ext_sleep_config & EXT_SLEEP_CONTROL)) {
980 /* Clear all sleep controls */
981 ret = tps65910_clear_bits(mfd,
982 TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos);
983 if (!ret)
984 ret = tps65910_clear_bits(mfd,
985 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
986 if (ret < 0)
987 dev_err(mfd->dev,
988 "Error in configuring SLEEP register\n");
989 return ret;
990 }
991
992 /*
993 * For regulator that has separate operational and sleep register make
994 * sure that operational is used and clear sleep register to turn
995 * regulator off when external control is inactive
996 */
997 if ((id == TPS65910_REG_VDD1) ||
998 (id == TPS65910_REG_VDD2) ||
999 ((id == TPS65911_REG_VDDCTRL) &&
1000 (tps65910_chip_id(mfd) == TPS65911))) {
1001 int op_reg_add = pmic->get_ctrl_reg(id) + 1;
1002 int sr_reg_add = pmic->get_ctrl_reg(id) + 2;
1003 int opvsel = tps65910_reg_read(pmic, op_reg_add);
1004 int srvsel = tps65910_reg_read(pmic, sr_reg_add);
1005 if (opvsel & VDD1_OP_CMD_MASK) {
1006 u8 reg_val = srvsel & VDD1_OP_SEL_MASK;
1007 ret = tps65910_reg_write(pmic, op_reg_add, reg_val);
1008 if (ret < 0) {
1009 dev_err(mfd->dev,
1010 "Error in configuring op register\n");
1011 return ret;
1012 }
1013 }
1014 ret = tps65910_reg_write(pmic, sr_reg_add, 0);
1015 if (ret < 0) {
1016 dev_err(mfd->dev, "Error in settting sr register\n");
1017 return ret;
1018 }
1019 }
1020
1021 ret = tps65910_clear_bits(mfd,
1022 TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos);
f30b0716
LD		 1023 if (!ret) {
1024 if (ext_sleep_config & TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP)
1025 ret = tps65910_set_bits(mfd,
1026 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
1027 else
1028 ret = tps65910_clear_bits(mfd,
1029 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
1030 }
1e0c66f4
LD		 1031 if (ret < 0)
1032 dev_err(mfd->dev,
1033 "Error in configuring SLEEP register\n");
f30b0716 1034
1e0c66f4
LD		 1035 return ret;
1036}
1037
518fb721
GG		 1038static __devinit int tps65910_probe(struct platform_device *pdev)
1039{
1040 struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent);
c172708d 1041 struct regulator_config config = { };
a320e3c3 1042 struct tps_info *info;
518fb721
GG		 1043 struct regulator_init_data *reg_data;
1044 struct regulator_dev *rdev;
1045 struct tps65910_reg *pmic;
1046 struct tps65910_board *pmic_plat_data;
518fb721
GG		 1047 int i, err;
1048
1049 pmic_plat_data = dev_get_platdata(tps65910->dev);
1050 if (!pmic_plat_data)
1051 return -EINVAL;
1052
9eb0c421 1053 pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
518fb721
GG		 1054 if (!pmic)
1055 return -ENOMEM;
1056
1057 mutex_init(&pmic->mutex);
1058 pmic->mfd = tps65910;
1059 platform_set_drvdata(pdev, pmic);
1060
1061 /* Give control of all register to control port */
1062 tps65910_set_bits(pmic->mfd, TPS65910_DEVCTRL,
1063 DEVCTRL_SR_CTL_I2C_SEL_MASK);
1064
a320e3c3
JEC		 1065 switch(tps65910_chip_id(tps65910)) {
1066 case TPS65910:
1067 pmic->get_ctrl_reg = &tps65910_get_ctrl_register;
39aa9b6e 1068 pmic->num_regulators = ARRAY_SIZE(tps65910_regs);
1e0c66f4 1069 pmic->ext_sleep_control = tps65910_ext_sleep_control;
a320e3c3 1070 info = tps65910_regs;
d04156bc 1071 break;
a320e3c3
JEC		 1072 case TPS65911:
1073 pmic->get_ctrl_reg = &tps65911_get_ctrl_register;
39aa9b6e 1074 pmic->num_regulators = ARRAY_SIZE(tps65911_regs);
1e0c66f4 1075 pmic->ext_sleep_control = tps65911_ext_sleep_control;
a320e3c3 1076 info = tps65911_regs;
d04156bc 1077 break;
a320e3c3
JEC		 1078 default:
1079 pr_err("Invalid tps chip version\n");
1080 return -ENODEV;
1081 }
1082
39aa9b6e
AL		 1083 pmic->desc = kcalloc(pmic->num_regulators,
1084 sizeof(struct regulator_desc), GFP_KERNEL);
1085 if (!pmic->desc) {
1086 err = -ENOMEM;
9eb0c421 1087 goto err_out;
39aa9b6e
AL		 1088 }
1089
1090 pmic->info = kcalloc(pmic->num_regulators,
1091 sizeof(struct tps_info *), GFP_KERNEL);
1092 if (!pmic->info) {
1093 err = -ENOMEM;
1094 goto err_free_desc;
1095 }
1096
1097 pmic->rdev = kcalloc(pmic->num_regulators,
1098 sizeof(struct regulator_dev *), GFP_KERNEL);
1099 if (!pmic->rdev) {
1100 err = -ENOMEM;
1101 goto err_free_info;
1102 }
1103
c1fc1480
KM		 1104 for (i = 0; i < pmic->num_regulators && i < TPS65910_NUM_REGS;
1105 i++, info++) {
1106
1107 reg_data = pmic_plat_data->tps65910_pmic_init_data[i];
1108
1109 /* Regulator API handles empty constraints but not NULL
1110 * constraints */
1111 if (!reg_data)
1112 continue;
1113
518fb721
GG		 1114 /* Register the regulators */
1115 pmic->info[i] = info;
1116
1117 pmic->desc[i].name = info->name;
77fa44d0 1118 pmic->desc[i].id = i;
7d38a3cb 1119 pmic->desc[i].n_voltages = info->n_voltages;
518fb721 1120
a320e3c3 1121 if (i == TPS65910_REG_VDD1 || i == TPS65910_REG_VDD2) {
518fb721 1122 pmic->desc[i].ops = &tps65910_ops_dcdc;
780dc9ba
AM		 1123 pmic->desc[i].n_voltages = VDD1_2_NUM_VOLT_FINE *
1124 VDD1_2_NUM_VOLT_COARSE;
a320e3c3
JEC		 1125 } else if (i == TPS65910_REG_VDD3) {
1126 if (tps65910_chip_id(tps65910) == TPS65910)
1127 pmic->desc[i].ops = &tps65910_ops_vdd3;
1128 else
1129 pmic->desc[i].ops = &tps65910_ops_dcdc;
1130 } else {
1131 if (tps65910_chip_id(tps65910) == TPS65910)
1132 pmic->desc[i].ops = &tps65910_ops;
1133 else
1134 pmic->desc[i].ops = &tps65911_ops;
1135 }
518fb721 1136
1e0c66f4
LD		 1137 err = tps65910_set_ext_sleep_config(pmic, i,
1138 pmic_plat_data->regulator_ext_sleep_control[i]);
1139 /*
1140 * Failing on regulator for configuring externally control
1141 * is not a serious issue, just throw warning.
1142 */
1143 if (err < 0)
1144 dev_warn(tps65910->dev,
1145 "Failed to initialise ext control config\n");
1146
518fb721
GG		 1147 pmic->desc[i].type = REGULATOR_VOLTAGE;
1148 pmic->desc[i].owner = THIS_MODULE;
a40a9c43
AL		 1149 pmic->desc[i].enable_reg = pmic->get_ctrl_reg(i);
1150 pmic->desc[i].enable_mask = TPS65910_SUPPLY_STATE_ENABLED;
518fb721 1151
c172708d
MB		 1152 config.dev = tps65910->dev;
1153 config.init_data = reg_data;
1154 config.driver_data = pmic;
a40a9c43 1155 config.regmap = tps65910->regmap;
c172708d
MB		 1156
1157 rdev = regulator_register(&pmic->desc[i], &config);
518fb721
GG		 1158 if (IS_ERR(rdev)) {
1159 dev_err(tps65910->dev,
1160 "failed to register %s regulator\n",
1161 pdev->name);
1162 err = PTR_ERR(rdev);
39aa9b6e 1163 goto err_unregister_regulator;
518fb721
GG		 1164 }
1165
1166 /* Save regulator for cleanup */
1167 pmic->rdev[i] = rdev;
1168 }
1169 return 0;
1170
39aa9b6e 1171err_unregister_regulator:
518fb721
GG		 1172 while (--i >= 0)
1173 regulator_unregister(pmic->rdev[i]);
39aa9b6e
AL		 1174 kfree(pmic->rdev);
1175err_free_info:
1176 kfree(pmic->info);
1177err_free_desc:
1178 kfree(pmic->desc);
9eb0c421 1179err_out:
518fb721
GG		 1180 return err;
1181}
1182
1183static int __devexit tps65910_remove(struct platform_device *pdev)
1184{
39aa9b6e 1185 struct tps65910_reg *pmic = platform_get_drvdata(pdev);
518fb721
GG		 1186 int i;
1187
39aa9b6e
AL		 1188 for (i = 0; i < pmic->num_regulators; i++)
1189 regulator_unregister(pmic->rdev[i]);
518fb721 1190
39aa9b6e
AL		 1191 kfree(pmic->rdev);
1192 kfree(pmic->info);
1193 kfree(pmic->desc);
518fb721
GG		 1194 return 0;
1195}
1196
1e0c66f4
LD		 1197static void tps65910_shutdown(struct platform_device *pdev)
1198{
1199 struct tps65910_reg *pmic = platform_get_drvdata(pdev);
1200 int i;
1201
1202 /*
1203 * Before bootloader jumps to kernel, it makes sure that required
1204 * external control signals are in desired state so that given rails
1205 * can be configure accordingly.
1206 * If rails are configured to be controlled from external control
1207 * then before shutting down/rebooting the system, the external
1208 * control configuration need to be remove from the rails so that
1209 * its output will be available as per register programming even
1210 * if external controls are removed. This is require when the POR
1211 * value of the control signals are not in active state and before
1212 * bootloader initializes it, the system requires the rail output
1213 * to be active for booting.
1214 */
1215 for (i = 0; i < pmic->num_regulators; i++) {
1216 int err;
1217 if (!pmic->rdev[i])
1218 continue;
1219
1220 err = tps65910_set_ext_sleep_config(pmic, i, 0);
1221 if (err < 0)
1222 dev_err(&pdev->dev,
1223 "Error in clearing external control\n");
1224 }
1225}
1226
518fb721
GG		 1227static struct platform_driver tps65910_driver = {
1228 .driver = {
1229 .name = "tps65910-pmic",
1230 .owner = THIS_MODULE,
1231 },
1232 .probe = tps65910_probe,
1233 .remove = __devexit_p(tps65910_remove),
1e0c66f4 1234 .shutdown = tps65910_shutdown,
518fb721
GG		 1235};
1236
1237static int __init tps65910_init(void)
1238{
1239 return platform_driver_register(&tps65910_driver);
1240}
1241subsys_initcall(tps65910_init);
1242
1243static void __exit tps65910_cleanup(void)
1244{
1245 platform_driver_unregister(&tps65910_driver);
1246}
1247module_exit(tps65910_cleanup);
1248
1249MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
ae0e6544 1250MODULE_DESCRIPTION("TPS65910/TPS65911 voltage regulator driver");
518fb721
GG		 1251MODULE_LICENSE("GPL v2");
1252MODULE_ALIAS("platform:tps65910-pmic");
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