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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
a0ff4aa6 OR |
2 | /* |
3 | * Copyright (c) 2017 Pengutronix, Oleksij Rempel <kernel@pengutronix.de> | |
a0ff4aa6 OR |
4 | */ |
5 | ||
79806d32 | 6 | #include <linux/arm-smccc.h> |
a0ff4aa6 OR |
7 | #include <linux/clk.h> |
8 | #include <linux/err.h> | |
9 | #include <linux/interrupt.h> | |
10 | #include <linux/kernel.h> | |
2df70620 | 11 | #include <linux/mailbox_client.h> |
a0ff4aa6 OR |
12 | #include <linux/mfd/syscon.h> |
13 | #include <linux/module.h> | |
14 | #include <linux/of_address.h> | |
b29b4249 | 15 | #include <linux/of_reserved_mem.h> |
a0ff4aa6 OR |
16 | #include <linux/of_device.h> |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/regmap.h> | |
19 | #include <linux/remoteproc.h> | |
2df70620 PF |
20 | #include <linux/workqueue.h> |
21 | ||
22 | #include "remoteproc_internal.h" | |
a0ff4aa6 OR |
23 | |
24 | #define IMX7D_SRC_SCR 0x0C | |
25 | #define IMX7D_ENABLE_M4 BIT(3) | |
26 | #define IMX7D_SW_M4P_RST BIT(2) | |
27 | #define IMX7D_SW_M4C_RST BIT(1) | |
28 | #define IMX7D_SW_M4C_NON_SCLR_RST BIT(0) | |
29 | ||
30 | #define IMX7D_M4_RST_MASK (IMX7D_ENABLE_M4 | IMX7D_SW_M4P_RST \ | |
31 | | IMX7D_SW_M4C_RST \ | |
32 | | IMX7D_SW_M4C_NON_SCLR_RST) | |
33 | ||
34 | #define IMX7D_M4_START (IMX7D_ENABLE_M4 | IMX7D_SW_M4P_RST \ | |
35 | | IMX7D_SW_M4C_RST) | |
36 | #define IMX7D_M4_STOP IMX7D_SW_M4C_NON_SCLR_RST | |
37 | ||
38 | /* Address: 0x020D8000 */ | |
39 | #define IMX6SX_SRC_SCR 0x00 | |
40 | #define IMX6SX_ENABLE_M4 BIT(22) | |
41 | #define IMX6SX_SW_M4P_RST BIT(12) | |
42 | #define IMX6SX_SW_M4C_NON_SCLR_RST BIT(4) | |
43 | #define IMX6SX_SW_M4C_RST BIT(3) | |
44 | ||
45 | #define IMX6SX_M4_START (IMX6SX_ENABLE_M4 | IMX6SX_SW_M4P_RST \ | |
46 | | IMX6SX_SW_M4C_RST) | |
47 | #define IMX6SX_M4_STOP IMX6SX_SW_M4C_NON_SCLR_RST | |
48 | #define IMX6SX_M4_RST_MASK (IMX6SX_ENABLE_M4 | IMX6SX_SW_M4P_RST \ | |
49 | | IMX6SX_SW_M4C_NON_SCLR_RST \ | |
50 | | IMX6SX_SW_M4C_RST) | |
51 | ||
f638a197 | 52 | #define IMX_RPROC_MEM_MAX 32 |
a0ff4aa6 | 53 | |
79806d32 PF |
54 | #define IMX_SIP_RPROC 0xC2000005 |
55 | #define IMX_SIP_RPROC_START 0x00 | |
56 | #define IMX_SIP_RPROC_STARTED 0x01 | |
57 | #define IMX_SIP_RPROC_STOP 0x02 | |
58 | ||
a0ff4aa6 OR |
59 | /** |
60 | * struct imx_rproc_mem - slim internal memory structure | |
61 | * @cpu_addr: MPU virtual address of the memory region | |
62 | * @sys_addr: Bus address used to access the memory region | |
63 | * @size: Size of the memory region | |
64 | */ | |
65 | struct imx_rproc_mem { | |
66 | void __iomem *cpu_addr; | |
67 | phys_addr_t sys_addr; | |
68 | size_t size; | |
69 | }; | |
70 | ||
71 | /* att flags */ | |
72 | /* M4 own area. Can be mapped at probe */ | |
73 | #define ATT_OWN BIT(1) | |
1024db50 | 74 | #define ATT_IOMEM BIT(2) |
a0ff4aa6 OR |
75 | |
76 | /* address translation table */ | |
77 | struct imx_rproc_att { | |
78 | u32 da; /* device address (From Cortex M4 view)*/ | |
79 | u32 sa; /* system bus address */ | |
80 | u32 size; /* size of reg range */ | |
81 | int flags; | |
82 | }; | |
83 | ||
52bda8d3 PF |
84 | /* Remote core start/stop method */ |
85 | enum imx_rproc_method { | |
86 | IMX_RPROC_NONE, | |
87 | /* Through syscon regmap */ | |
88 | IMX_RPROC_MMIO, | |
89 | /* Through ARM SMCCC */ | |
90 | IMX_RPROC_SMC, | |
91 | }; | |
92 | ||
a0ff4aa6 OR |
93 | struct imx_rproc_dcfg { |
94 | u32 src_reg; | |
95 | u32 src_mask; | |
96 | u32 src_start; | |
97 | u32 src_stop; | |
98 | const struct imx_rproc_att *att; | |
99 | size_t att_size; | |
52bda8d3 | 100 | enum imx_rproc_method method; |
a0ff4aa6 OR |
101 | }; |
102 | ||
103 | struct imx_rproc { | |
104 | struct device *dev; | |
105 | struct regmap *regmap; | |
106 | struct rproc *rproc; | |
107 | const struct imx_rproc_dcfg *dcfg; | |
f638a197 | 108 | struct imx_rproc_mem mem[IMX_RPROC_MEM_MAX]; |
a0ff4aa6 | 109 | struct clk *clk; |
2df70620 PF |
110 | struct mbox_client cl; |
111 | struct mbox_chan *tx_ch; | |
112 | struct mbox_chan *rx_ch; | |
113 | struct work_struct rproc_work; | |
114 | struct workqueue_struct *workqueue; | |
5e4c1243 | 115 | void __iomem *rsc_table; |
a0ff4aa6 OR |
116 | }; |
117 | ||
79806d32 PF |
118 | static const struct imx_rproc_att imx_rproc_att_imx8mn[] = { |
119 | /* dev addr , sys addr , size , flags */ | |
120 | /* ITCM */ | |
1024db50 | 121 | { 0x00000000, 0x007E0000, 0x00020000, ATT_OWN | ATT_IOMEM }, |
79806d32 PF |
122 | /* OCRAM_S */ |
123 | { 0x00180000, 0x00180000, 0x00009000, 0 }, | |
124 | /* OCRAM */ | |
125 | { 0x00900000, 0x00900000, 0x00020000, 0 }, | |
126 | /* OCRAM */ | |
127 | { 0x00920000, 0x00920000, 0x00020000, 0 }, | |
128 | /* OCRAM */ | |
129 | { 0x00940000, 0x00940000, 0x00050000, 0 }, | |
130 | /* QSPI Code - alias */ | |
131 | { 0x08000000, 0x08000000, 0x08000000, 0 }, | |
132 | /* DDR (Code) - alias */ | |
133 | { 0x10000000, 0x40000000, 0x0FFE0000, 0 }, | |
134 | /* DTCM */ | |
1024db50 | 135 | { 0x20000000, 0x00800000, 0x00020000, ATT_OWN | ATT_IOMEM }, |
79806d32 PF |
136 | /* OCRAM_S - alias */ |
137 | { 0x20180000, 0x00180000, 0x00008000, ATT_OWN }, | |
138 | /* OCRAM */ | |
139 | { 0x20200000, 0x00900000, 0x00020000, ATT_OWN }, | |
140 | /* OCRAM */ | |
141 | { 0x20220000, 0x00920000, 0x00020000, ATT_OWN }, | |
142 | /* OCRAM */ | |
143 | { 0x20240000, 0x00940000, 0x00040000, ATT_OWN }, | |
144 | /* DDR (Data) */ | |
145 | { 0x40000000, 0x40000000, 0x80000000, 0 }, | |
146 | }; | |
147 | ||
4ab8f960 PF |
148 | static const struct imx_rproc_att imx_rproc_att_imx8mq[] = { |
149 | /* dev addr , sys addr , size , flags */ | |
150 | /* TCML - alias */ | |
1024db50 | 151 | { 0x00000000, 0x007e0000, 0x00020000, ATT_IOMEM}, |
4ab8f960 PF |
152 | /* OCRAM_S */ |
153 | { 0x00180000, 0x00180000, 0x00008000, 0 }, | |
154 | /* OCRAM */ | |
155 | { 0x00900000, 0x00900000, 0x00020000, 0 }, | |
156 | /* OCRAM */ | |
157 | { 0x00920000, 0x00920000, 0x00020000, 0 }, | |
158 | /* QSPI Code - alias */ | |
159 | { 0x08000000, 0x08000000, 0x08000000, 0 }, | |
160 | /* DDR (Code) - alias */ | |
161 | { 0x10000000, 0x80000000, 0x0FFE0000, 0 }, | |
162 | /* TCML */ | |
1024db50 | 163 | { 0x1FFE0000, 0x007E0000, 0x00020000, ATT_OWN | ATT_IOMEM}, |
4ab8f960 | 164 | /* TCMU */ |
1024db50 | 165 | { 0x20000000, 0x00800000, 0x00020000, ATT_OWN | ATT_IOMEM}, |
4ab8f960 PF |
166 | /* OCRAM_S */ |
167 | { 0x20180000, 0x00180000, 0x00008000, ATT_OWN }, | |
168 | /* OCRAM */ | |
169 | { 0x20200000, 0x00900000, 0x00020000, ATT_OWN }, | |
170 | /* OCRAM */ | |
171 | { 0x20220000, 0x00920000, 0x00020000, ATT_OWN }, | |
172 | /* DDR (Data) */ | |
173 | { 0x40000000, 0x40000000, 0x80000000, 0 }, | |
174 | }; | |
175 | ||
d59eedc0 PF |
176 | static const struct imx_rproc_att imx_rproc_att_imx8ulp[] = { |
177 | {0x1FFC0000, 0x1FFC0000, 0xC0000, ATT_OWN}, | |
178 | {0x21000000, 0x21000000, 0x10000, ATT_OWN}, | |
179 | {0x80000000, 0x80000000, 0x60000000, 0} | |
180 | }; | |
181 | ||
c8a1a56d PF |
182 | static const struct imx_rproc_att imx_rproc_att_imx7ulp[] = { |
183 | {0x1FFD0000, 0x1FFD0000, 0x30000, ATT_OWN}, | |
184 | {0x20000000, 0x20000000, 0x10000, ATT_OWN}, | |
185 | {0x2F000000, 0x2F000000, 0x20000, ATT_OWN}, | |
186 | {0x2F020000, 0x2F020000, 0x20000, ATT_OWN}, | |
187 | {0x60000000, 0x60000000, 0x40000000, 0} | |
188 | }; | |
189 | ||
a0ff4aa6 OR |
190 | static const struct imx_rproc_att imx_rproc_att_imx7d[] = { |
191 | /* dev addr , sys addr , size , flags */ | |
192 | /* OCRAM_S (M4 Boot code) - alias */ | |
193 | { 0x00000000, 0x00180000, 0x00008000, 0 }, | |
194 | /* OCRAM_S (Code) */ | |
195 | { 0x00180000, 0x00180000, 0x00008000, ATT_OWN }, | |
196 | /* OCRAM (Code) - alias */ | |
197 | { 0x00900000, 0x00900000, 0x00020000, 0 }, | |
198 | /* OCRAM_EPDC (Code) - alias */ | |
199 | { 0x00920000, 0x00920000, 0x00020000, 0 }, | |
200 | /* OCRAM_PXP (Code) - alias */ | |
201 | { 0x00940000, 0x00940000, 0x00008000, 0 }, | |
202 | /* TCML (Code) */ | |
1024db50 | 203 | { 0x1FFF8000, 0x007F8000, 0x00008000, ATT_OWN | ATT_IOMEM }, |
a0ff4aa6 OR |
204 | /* DDR (Code) - alias, first part of DDR (Data) */ |
205 | { 0x10000000, 0x80000000, 0x0FFF0000, 0 }, | |
206 | ||
207 | /* TCMU (Data) */ | |
1024db50 | 208 | { 0x20000000, 0x00800000, 0x00008000, ATT_OWN | ATT_IOMEM }, |
a0ff4aa6 OR |
209 | /* OCRAM (Data) */ |
210 | { 0x20200000, 0x00900000, 0x00020000, 0 }, | |
211 | /* OCRAM_EPDC (Data) */ | |
212 | { 0x20220000, 0x00920000, 0x00020000, 0 }, | |
213 | /* OCRAM_PXP (Data) */ | |
214 | { 0x20240000, 0x00940000, 0x00008000, 0 }, | |
215 | /* DDR (Data) */ | |
216 | { 0x80000000, 0x80000000, 0x60000000, 0 }, | |
217 | }; | |
218 | ||
219 | static const struct imx_rproc_att imx_rproc_att_imx6sx[] = { | |
220 | /* dev addr , sys addr , size , flags */ | |
221 | /* TCML (M4 Boot Code) - alias */ | |
1024db50 | 222 | { 0x00000000, 0x007F8000, 0x00008000, ATT_IOMEM }, |
a0ff4aa6 OR |
223 | /* OCRAM_S (Code) */ |
224 | { 0x00180000, 0x008F8000, 0x00004000, 0 }, | |
225 | /* OCRAM_S (Code) - alias */ | |
226 | { 0x00180000, 0x008FC000, 0x00004000, 0 }, | |
227 | /* TCML (Code) */ | |
1024db50 | 228 | { 0x1FFF8000, 0x007F8000, 0x00008000, ATT_OWN | ATT_IOMEM }, |
a0ff4aa6 OR |
229 | /* DDR (Code) - alias, first part of DDR (Data) */ |
230 | { 0x10000000, 0x80000000, 0x0FFF8000, 0 }, | |
231 | ||
232 | /* TCMU (Data) */ | |
1024db50 | 233 | { 0x20000000, 0x00800000, 0x00008000, ATT_OWN | ATT_IOMEM }, |
a0ff4aa6 OR |
234 | /* OCRAM_S (Data) - alias? */ |
235 | { 0x208F8000, 0x008F8000, 0x00004000, 0 }, | |
236 | /* DDR (Data) */ | |
237 | { 0x80000000, 0x80000000, 0x60000000, 0 }, | |
238 | }; | |
239 | ||
79806d32 PF |
240 | static const struct imx_rproc_dcfg imx_rproc_cfg_imx8mn = { |
241 | .att = imx_rproc_att_imx8mn, | |
242 | .att_size = ARRAY_SIZE(imx_rproc_att_imx8mn), | |
243 | .method = IMX_RPROC_SMC, | |
244 | }; | |
245 | ||
4ab8f960 PF |
246 | static const struct imx_rproc_dcfg imx_rproc_cfg_imx8mq = { |
247 | .src_reg = IMX7D_SRC_SCR, | |
248 | .src_mask = IMX7D_M4_RST_MASK, | |
249 | .src_start = IMX7D_M4_START, | |
250 | .src_stop = IMX7D_M4_STOP, | |
251 | .att = imx_rproc_att_imx8mq, | |
252 | .att_size = ARRAY_SIZE(imx_rproc_att_imx8mq), | |
52bda8d3 | 253 | .method = IMX_RPROC_MMIO, |
4ab8f960 PF |
254 | }; |
255 | ||
d59eedc0 PF |
256 | static const struct imx_rproc_dcfg imx_rproc_cfg_imx8ulp = { |
257 | .att = imx_rproc_att_imx8ulp, | |
258 | .att_size = ARRAY_SIZE(imx_rproc_att_imx8ulp), | |
259 | .method = IMX_RPROC_NONE, | |
260 | }; | |
261 | ||
c8a1a56d PF |
262 | static const struct imx_rproc_dcfg imx_rproc_cfg_imx7ulp = { |
263 | .att = imx_rproc_att_imx7ulp, | |
264 | .att_size = ARRAY_SIZE(imx_rproc_att_imx7ulp), | |
265 | .method = IMX_RPROC_NONE, | |
266 | }; | |
267 | ||
a0ff4aa6 OR |
268 | static const struct imx_rproc_dcfg imx_rproc_cfg_imx7d = { |
269 | .src_reg = IMX7D_SRC_SCR, | |
270 | .src_mask = IMX7D_M4_RST_MASK, | |
271 | .src_start = IMX7D_M4_START, | |
272 | .src_stop = IMX7D_M4_STOP, | |
273 | .att = imx_rproc_att_imx7d, | |
274 | .att_size = ARRAY_SIZE(imx_rproc_att_imx7d), | |
52bda8d3 | 275 | .method = IMX_RPROC_MMIO, |
a0ff4aa6 OR |
276 | }; |
277 | ||
278 | static const struct imx_rproc_dcfg imx_rproc_cfg_imx6sx = { | |
279 | .src_reg = IMX6SX_SRC_SCR, | |
280 | .src_mask = IMX6SX_M4_RST_MASK, | |
281 | .src_start = IMX6SX_M4_START, | |
282 | .src_stop = IMX6SX_M4_STOP, | |
283 | .att = imx_rproc_att_imx6sx, | |
284 | .att_size = ARRAY_SIZE(imx_rproc_att_imx6sx), | |
52bda8d3 | 285 | .method = IMX_RPROC_MMIO, |
a0ff4aa6 OR |
286 | }; |
287 | ||
288 | static int imx_rproc_start(struct rproc *rproc) | |
289 | { | |
290 | struct imx_rproc *priv = rproc->priv; | |
291 | const struct imx_rproc_dcfg *dcfg = priv->dcfg; | |
292 | struct device *dev = priv->dev; | |
79806d32 | 293 | struct arm_smccc_res res; |
a0ff4aa6 OR |
294 | int ret; |
295 | ||
79806d32 PF |
296 | switch (dcfg->method) { |
297 | case IMX_RPROC_MMIO: | |
298 | ret = regmap_update_bits(priv->regmap, dcfg->src_reg, dcfg->src_mask, | |
299 | dcfg->src_start); | |
300 | break; | |
301 | case IMX_RPROC_SMC: | |
302 | arm_smccc_smc(IMX_SIP_RPROC, IMX_SIP_RPROC_START, 0, 0, 0, 0, 0, 0, &res); | |
303 | ret = res.a0; | |
304 | break; | |
305 | default: | |
306 | return -EOPNOTSUPP; | |
307 | } | |
308 | ||
a0ff4aa6 | 309 | if (ret) |
79806d32 | 310 | dev_err(dev, "Failed to enable remote core!\n"); |
a0ff4aa6 OR |
311 | |
312 | return ret; | |
313 | } | |
314 | ||
315 | static int imx_rproc_stop(struct rproc *rproc) | |
316 | { | |
317 | struct imx_rproc *priv = rproc->priv; | |
318 | const struct imx_rproc_dcfg *dcfg = priv->dcfg; | |
319 | struct device *dev = priv->dev; | |
79806d32 | 320 | struct arm_smccc_res res; |
a0ff4aa6 OR |
321 | int ret; |
322 | ||
79806d32 PF |
323 | switch (dcfg->method) { |
324 | case IMX_RPROC_MMIO: | |
325 | ret = regmap_update_bits(priv->regmap, dcfg->src_reg, dcfg->src_mask, | |
326 | dcfg->src_stop); | |
327 | break; | |
328 | case IMX_RPROC_SMC: | |
329 | arm_smccc_smc(IMX_SIP_RPROC, IMX_SIP_RPROC_STOP, 0, 0, 0, 0, 0, 0, &res); | |
330 | ret = res.a0; | |
331 | if (res.a1) | |
332 | dev_info(dev, "Not in wfi, force stopped\n"); | |
333 | break; | |
334 | default: | |
c8a1a56d | 335 | return -EOPNOTSUPP; |
79806d32 | 336 | } |
c8a1a56d | 337 | |
a0ff4aa6 | 338 | if (ret) |
79806d32 | 339 | dev_err(dev, "Failed to stop remote core\n"); |
a0ff4aa6 OR |
340 | |
341 | return ret; | |
342 | } | |
343 | ||
344 | static int imx_rproc_da_to_sys(struct imx_rproc *priv, u64 da, | |
1024db50 | 345 | size_t len, u64 *sys, bool *is_iomem) |
a0ff4aa6 OR |
346 | { |
347 | const struct imx_rproc_dcfg *dcfg = priv->dcfg; | |
348 | int i; | |
349 | ||
350 | /* parse address translation table */ | |
351 | for (i = 0; i < dcfg->att_size; i++) { | |
352 | const struct imx_rproc_att *att = &dcfg->att[i]; | |
353 | ||
354 | if (da >= att->da && da + len < att->da + att->size) { | |
355 | unsigned int offset = da - att->da; | |
356 | ||
357 | *sys = att->sa + offset; | |
1024db50 DA |
358 | if (is_iomem) |
359 | *is_iomem = att->flags & ATT_IOMEM; | |
a0ff4aa6 OR |
360 | return 0; |
361 | } | |
362 | } | |
363 | ||
9ce3bf22 | 364 | dev_warn(priv->dev, "Translation failed: da = 0x%llx len = 0x%zx\n", |
a0ff4aa6 OR |
365 | da, len); |
366 | return -ENOENT; | |
367 | } | |
368 | ||
40df0a91 | 369 | static void *imx_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem) |
a0ff4aa6 OR |
370 | { |
371 | struct imx_rproc *priv = rproc->priv; | |
372 | void *va = NULL; | |
373 | u64 sys; | |
374 | int i; | |
375 | ||
9ce3bf22 | 376 | if (len == 0) |
a0ff4aa6 OR |
377 | return NULL; |
378 | ||
379 | /* | |
380 | * On device side we have many aliases, so we need to convert device | |
381 | * address (M4) to system bus address first. | |
382 | */ | |
1024db50 | 383 | if (imx_rproc_da_to_sys(priv, da, len, &sys, is_iomem)) |
a0ff4aa6 OR |
384 | return NULL; |
385 | ||
f638a197 | 386 | for (i = 0; i < IMX_RPROC_MEM_MAX; i++) { |
a0ff4aa6 OR |
387 | if (sys >= priv->mem[i].sys_addr && sys + len < |
388 | priv->mem[i].sys_addr + priv->mem[i].size) { | |
389 | unsigned int offset = sys - priv->mem[i].sys_addr; | |
390 | /* __force to make sparse happy with type conversion */ | |
391 | va = (__force void *)(priv->mem[i].cpu_addr + offset); | |
392 | break; | |
393 | } | |
394 | } | |
395 | ||
9ce3bf22 CL |
396 | dev_dbg(&rproc->dev, "da = 0x%llx len = 0x%zx va = 0x%p\n", |
397 | da, len, va); | |
a0ff4aa6 OR |
398 | |
399 | return va; | |
400 | } | |
401 | ||
b29b4249 PF |
402 | static int imx_rproc_mem_alloc(struct rproc *rproc, |
403 | struct rproc_mem_entry *mem) | |
404 | { | |
405 | struct device *dev = rproc->dev.parent; | |
406 | void *va; | |
407 | ||
408 | dev_dbg(dev, "map memory: %p+%zx\n", &mem->dma, mem->len); | |
409 | va = ioremap_wc(mem->dma, mem->len); | |
410 | if (IS_ERR_OR_NULL(va)) { | |
411 | dev_err(dev, "Unable to map memory region: %p+%zx\n", | |
412 | &mem->dma, mem->len); | |
413 | return -ENOMEM; | |
414 | } | |
415 | ||
416 | /* Update memory entry va */ | |
417 | mem->va = va; | |
418 | ||
419 | return 0; | |
420 | } | |
421 | ||
422 | static int imx_rproc_mem_release(struct rproc *rproc, | |
423 | struct rproc_mem_entry *mem) | |
424 | { | |
425 | dev_dbg(rproc->dev.parent, "unmap memory: %pa\n", &mem->dma); | |
426 | iounmap(mem->va); | |
427 | ||
428 | return 0; | |
429 | } | |
430 | ||
10a3d407 | 431 | static int imx_rproc_prepare(struct rproc *rproc) |
b29b4249 PF |
432 | { |
433 | struct imx_rproc *priv = rproc->priv; | |
434 | struct device_node *np = priv->dev->of_node; | |
435 | struct of_phandle_iterator it; | |
436 | struct rproc_mem_entry *mem; | |
437 | struct reserved_mem *rmem; | |
438 | u32 da; | |
439 | ||
440 | /* Register associated reserved memory regions */ | |
441 | of_phandle_iterator_init(&it, np, "memory-region", NULL, 0); | |
442 | while (of_phandle_iterator_next(&it) == 0) { | |
443 | /* | |
444 | * Ignore the first memory region which will be used vdev buffer. | |
445 | * No need to do extra handlings, rproc_add_virtio_dev will handle it. | |
446 | */ | |
447 | if (!strcmp(it.node->name, "vdev0buffer")) | |
448 | continue; | |
449 | ||
450 | rmem = of_reserved_mem_lookup(it.node); | |
451 | if (!rmem) { | |
452 | dev_err(priv->dev, "unable to acquire memory-region\n"); | |
453 | return -EINVAL; | |
454 | } | |
455 | ||
456 | /* No need to translate pa to da, i.MX use same map */ | |
457 | da = rmem->base; | |
458 | ||
459 | /* Register memory region */ | |
460 | mem = rproc_mem_entry_init(priv->dev, NULL, (dma_addr_t)rmem->base, rmem->size, da, | |
461 | imx_rproc_mem_alloc, imx_rproc_mem_release, | |
462 | it.node->name); | |
463 | ||
464 | if (mem) | |
465 | rproc_coredump_add_segment(rproc, da, rmem->size); | |
466 | else | |
467 | return -ENOMEM; | |
468 | ||
469 | rproc_add_carveout(rproc, mem); | |
470 | } | |
471 | ||
472 | return 0; | |
473 | } | |
474 | ||
475 | static int imx_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw) | |
476 | { | |
10a3d407 | 477 | int ret; |
b29b4249 PF |
478 | |
479 | ret = rproc_elf_load_rsc_table(rproc, fw); | |
480 | if (ret) | |
481 | dev_info(&rproc->dev, "No resource table in elf\n"); | |
482 | ||
483 | return 0; | |
484 | } | |
485 | ||
2df70620 PF |
486 | static void imx_rproc_kick(struct rproc *rproc, int vqid) |
487 | { | |
488 | struct imx_rproc *priv = rproc->priv; | |
489 | int err; | |
490 | __u32 mmsg; | |
491 | ||
492 | if (!priv->tx_ch) { | |
493 | dev_err(priv->dev, "No initialized mbox tx channel\n"); | |
494 | return; | |
495 | } | |
496 | ||
497 | /* | |
498 | * Send the index of the triggered virtqueue as the mu payload. | |
499 | * Let remote processor know which virtqueue is used. | |
500 | */ | |
501 | mmsg = vqid << 16; | |
502 | ||
503 | err = mbox_send_message(priv->tx_ch, (void *)&mmsg); | |
504 | if (err < 0) | |
505 | dev_err(priv->dev, "%s: failed (%d, err:%d)\n", | |
506 | __func__, vqid, err); | |
507 | } | |
508 | ||
5e4c1243 PF |
509 | static int imx_rproc_attach(struct rproc *rproc) |
510 | { | |
511 | return 0; | |
512 | } | |
513 | ||
514 | static struct resource_table *imx_rproc_get_loaded_rsc_table(struct rproc *rproc, size_t *table_sz) | |
515 | { | |
516 | struct imx_rproc *priv = rproc->priv; | |
517 | ||
518 | /* The resource table has already been mapped in imx_rproc_addr_init */ | |
519 | if (!priv->rsc_table) | |
520 | return NULL; | |
521 | ||
522 | *table_sz = SZ_1K; | |
523 | return (struct resource_table *)priv->rsc_table; | |
524 | } | |
525 | ||
a0ff4aa6 | 526 | static const struct rproc_ops imx_rproc_ops = { |
10a3d407 | 527 | .prepare = imx_rproc_prepare, |
5e4c1243 | 528 | .attach = imx_rproc_attach, |
a0ff4aa6 OR |
529 | .start = imx_rproc_start, |
530 | .stop = imx_rproc_stop, | |
2df70620 | 531 | .kick = imx_rproc_kick, |
a0ff4aa6 | 532 | .da_to_va = imx_rproc_da_to_va, |
b29b4249 PF |
533 | .load = rproc_elf_load_segments, |
534 | .parse_fw = imx_rproc_parse_fw, | |
535 | .find_loaded_rsc_table = rproc_elf_find_loaded_rsc_table, | |
5e4c1243 | 536 | .get_loaded_rsc_table = imx_rproc_get_loaded_rsc_table, |
b29b4249 PF |
537 | .sanity_check = rproc_elf_sanity_check, |
538 | .get_boot_addr = rproc_elf_get_boot_addr, | |
a0ff4aa6 OR |
539 | }; |
540 | ||
541 | static int imx_rproc_addr_init(struct imx_rproc *priv, | |
542 | struct platform_device *pdev) | |
543 | { | |
544 | const struct imx_rproc_dcfg *dcfg = priv->dcfg; | |
545 | struct device *dev = &pdev->dev; | |
546 | struct device_node *np = dev->of_node; | |
547 | int a, b = 0, err, nph; | |
548 | ||
549 | /* remap required addresses */ | |
550 | for (a = 0; a < dcfg->att_size; a++) { | |
551 | const struct imx_rproc_att *att = &dcfg->att[a]; | |
552 | ||
553 | if (!(att->flags & ATT_OWN)) | |
554 | continue; | |
555 | ||
f638a197 | 556 | if (b >= IMX_RPROC_MEM_MAX) |
a0ff4aa6 OR |
557 | break; |
558 | ||
1024db50 DA |
559 | if (att->flags & ATT_IOMEM) |
560 | priv->mem[b].cpu_addr = devm_ioremap(&pdev->dev, | |
561 | att->sa, att->size); | |
562 | else | |
563 | priv->mem[b].cpu_addr = devm_ioremap_wc(&pdev->dev, | |
564 | att->sa, att->size); | |
68a39a3e | 565 | if (!priv->mem[b].cpu_addr) { |
1896b3d8 | 566 | dev_err(dev, "failed to remap %#x bytes from %#x\n", att->size, att->sa); |
68a39a3e | 567 | return -ENOMEM; |
a0ff4aa6 OR |
568 | } |
569 | priv->mem[b].sys_addr = att->sa; | |
570 | priv->mem[b].size = att->size; | |
571 | b++; | |
572 | } | |
573 | ||
574 | /* memory-region is optional property */ | |
575 | nph = of_count_phandle_with_args(np, "memory-region", NULL); | |
576 | if (nph <= 0) | |
577 | return 0; | |
578 | ||
579 | /* remap optional addresses */ | |
580 | for (a = 0; a < nph; a++) { | |
581 | struct device_node *node; | |
582 | struct resource res; | |
583 | ||
584 | node = of_parse_phandle(np, "memory-region", a); | |
7fe45e34 DA |
585 | /* Not map vdevbuffer, vdevring region */ |
586 | if (!strncmp(node->name, "vdev", strlen("vdev"))) | |
8f2d8961 | 587 | continue; |
a0ff4aa6 OR |
588 | err = of_address_to_resource(node, 0, &res); |
589 | if (err) { | |
590 | dev_err(dev, "unable to resolve memory region\n"); | |
591 | return err; | |
592 | } | |
593 | ||
6e962bfe PF |
594 | of_node_put(node); |
595 | ||
f638a197 | 596 | if (b >= IMX_RPROC_MEM_MAX) |
a0ff4aa6 OR |
597 | break; |
598 | ||
ecadcc47 PF |
599 | /* Not use resource version, because we might share region */ |
600 | priv->mem[b].cpu_addr = devm_ioremap(&pdev->dev, res.start, resource_size(&res)); | |
18cda801 | 601 | if (!priv->mem[b].cpu_addr) { |
1896b3d8 | 602 | dev_err(dev, "failed to remap %pr\n", &res); |
18cda801 | 603 | return -ENOMEM; |
a0ff4aa6 OR |
604 | } |
605 | priv->mem[b].sys_addr = res.start; | |
606 | priv->mem[b].size = resource_size(&res); | |
c1a4ab83 | 607 | if (!strcmp(node->name, "rsc-table")) |
5e4c1243 | 608 | priv->rsc_table = priv->mem[b].cpu_addr; |
a0ff4aa6 OR |
609 | b++; |
610 | } | |
611 | ||
612 | return 0; | |
613 | } | |
614 | ||
2df70620 PF |
615 | static void imx_rproc_vq_work(struct work_struct *work) |
616 | { | |
617 | struct imx_rproc *priv = container_of(work, struct imx_rproc, | |
618 | rproc_work); | |
619 | ||
620 | rproc_vq_interrupt(priv->rproc, 0); | |
621 | rproc_vq_interrupt(priv->rproc, 1); | |
622 | } | |
623 | ||
624 | static void imx_rproc_rx_callback(struct mbox_client *cl, void *msg) | |
625 | { | |
626 | struct rproc *rproc = dev_get_drvdata(cl->dev); | |
627 | struct imx_rproc *priv = rproc->priv; | |
628 | ||
629 | queue_work(priv->workqueue, &priv->rproc_work); | |
630 | } | |
631 | ||
632 | static int imx_rproc_xtr_mbox_init(struct rproc *rproc) | |
633 | { | |
634 | struct imx_rproc *priv = rproc->priv; | |
635 | struct device *dev = priv->dev; | |
636 | struct mbox_client *cl; | |
637 | int ret; | |
638 | ||
639 | if (!of_get_property(dev->of_node, "mbox-names", NULL)) | |
640 | return 0; | |
641 | ||
642 | cl = &priv->cl; | |
643 | cl->dev = dev; | |
644 | cl->tx_block = true; | |
645 | cl->tx_tout = 100; | |
646 | cl->knows_txdone = false; | |
647 | cl->rx_callback = imx_rproc_rx_callback; | |
648 | ||
649 | priv->tx_ch = mbox_request_channel_byname(cl, "tx"); | |
650 | if (IS_ERR(priv->tx_ch)) { | |
651 | ret = PTR_ERR(priv->tx_ch); | |
652 | return dev_err_probe(cl->dev, ret, | |
653 | "failed to request tx mailbox channel: %d\n", ret); | |
654 | } | |
655 | ||
656 | priv->rx_ch = mbox_request_channel_byname(cl, "rx"); | |
657 | if (IS_ERR(priv->rx_ch)) { | |
658 | mbox_free_channel(priv->tx_ch); | |
659 | ret = PTR_ERR(priv->rx_ch); | |
660 | return dev_err_probe(cl->dev, ret, | |
661 | "failed to request rx mailbox channel: %d\n", ret); | |
662 | } | |
663 | ||
664 | return 0; | |
665 | } | |
666 | ||
667 | static void imx_rproc_free_mbox(struct rproc *rproc) | |
668 | { | |
669 | struct imx_rproc *priv = rproc->priv; | |
670 | ||
671 | mbox_free_channel(priv->tx_ch); | |
672 | mbox_free_channel(priv->rx_ch); | |
673 | } | |
674 | ||
5e4c1243 PF |
675 | static int imx_rproc_detect_mode(struct imx_rproc *priv) |
676 | { | |
c8a1a56d | 677 | struct regmap_config config = { .name = "imx-rproc" }; |
5e4c1243 PF |
678 | const struct imx_rproc_dcfg *dcfg = priv->dcfg; |
679 | struct device *dev = priv->dev; | |
c8a1a56d | 680 | struct regmap *regmap; |
79806d32 | 681 | struct arm_smccc_res res; |
5e4c1243 PF |
682 | int ret; |
683 | u32 val; | |
684 | ||
c8a1a56d PF |
685 | switch (dcfg->method) { |
686 | case IMX_RPROC_NONE: | |
687 | priv->rproc->state = RPROC_DETACHED; | |
688 | return 0; | |
79806d32 PF |
689 | case IMX_RPROC_SMC: |
690 | arm_smccc_smc(IMX_SIP_RPROC, IMX_SIP_RPROC_STARTED, 0, 0, 0, 0, 0, 0, &res); | |
691 | if (res.a0) | |
692 | priv->rproc->state = RPROC_DETACHED; | |
693 | return 0; | |
c8a1a56d PF |
694 | default: |
695 | break; | |
696 | } | |
697 | ||
698 | regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon"); | |
699 | if (IS_ERR(regmap)) { | |
700 | dev_err(dev, "failed to find syscon\n"); | |
701 | return PTR_ERR(regmap); | |
702 | } | |
703 | ||
704 | priv->regmap = regmap; | |
705 | regmap_attach_dev(dev, regmap, &config); | |
706 | ||
707 | ret = regmap_read(regmap, dcfg->src_reg, &val); | |
5e4c1243 PF |
708 | if (ret) { |
709 | dev_err(dev, "Failed to read src\n"); | |
710 | return ret; | |
711 | } | |
712 | ||
713 | if (!(val & dcfg->src_stop)) | |
714 | priv->rproc->state = RPROC_DETACHED; | |
715 | ||
716 | return 0; | |
717 | } | |
718 | ||
cc0316c1 PF |
719 | static int imx_rproc_clk_enable(struct imx_rproc *priv) |
720 | { | |
721 | const struct imx_rproc_dcfg *dcfg = priv->dcfg; | |
722 | struct device *dev = priv->dev; | |
723 | int ret; | |
724 | ||
725 | /* Remote core is not under control of Linux */ | |
726 | if (dcfg->method == IMX_RPROC_NONE) | |
727 | return 0; | |
728 | ||
729 | priv->clk = devm_clk_get(dev, NULL); | |
730 | if (IS_ERR(priv->clk)) { | |
731 | dev_err(dev, "Failed to get clock\n"); | |
732 | return PTR_ERR(priv->clk); | |
733 | } | |
734 | ||
735 | /* | |
736 | * clk for M4 block including memory. Should be | |
737 | * enabled before .start for FW transfer. | |
738 | */ | |
739 | ret = clk_prepare_enable(priv->clk); | |
740 | if (ret) { | |
741 | dev_err(dev, "Failed to enable clock\n"); | |
742 | return ret; | |
743 | } | |
744 | ||
745 | return 0; | |
746 | } | |
747 | ||
a0ff4aa6 OR |
748 | static int imx_rproc_probe(struct platform_device *pdev) |
749 | { | |
750 | struct device *dev = &pdev->dev; | |
751 | struct device_node *np = dev->of_node; | |
752 | struct imx_rproc *priv; | |
753 | struct rproc *rproc; | |
a0ff4aa6 | 754 | const struct imx_rproc_dcfg *dcfg; |
a0ff4aa6 OR |
755 | int ret; |
756 | ||
a0ff4aa6 OR |
757 | /* set some other name then imx */ |
758 | rproc = rproc_alloc(dev, "imx-rproc", &imx_rproc_ops, | |
759 | NULL, sizeof(*priv)); | |
99a31adf CJ |
760 | if (!rproc) |
761 | return -ENOMEM; | |
a0ff4aa6 OR |
762 | |
763 | dcfg = of_device_get_match_data(dev); | |
de6f83f8 CJ |
764 | if (!dcfg) { |
765 | ret = -EINVAL; | |
766 | goto err_put_rproc; | |
767 | } | |
a0ff4aa6 OR |
768 | |
769 | priv = rproc->priv; | |
770 | priv->rproc = rproc; | |
a0ff4aa6 OR |
771 | priv->dcfg = dcfg; |
772 | priv->dev = dev; | |
773 | ||
774 | dev_set_drvdata(dev, rproc); | |
2df70620 PF |
775 | priv->workqueue = create_workqueue(dev_name(dev)); |
776 | if (!priv->workqueue) { | |
777 | dev_err(dev, "cannot create workqueue\n"); | |
778 | ret = -ENOMEM; | |
779 | goto err_put_rproc; | |
780 | } | |
781 | ||
782 | ret = imx_rproc_xtr_mbox_init(rproc); | |
783 | if (ret) | |
784 | goto err_put_wkq; | |
a0ff4aa6 OR |
785 | |
786 | ret = imx_rproc_addr_init(priv, pdev); | |
787 | if (ret) { | |
16a3c637 | 788 | dev_err(dev, "failed on imx_rproc_addr_init\n"); |
2df70620 | 789 | goto err_put_mbox; |
a0ff4aa6 OR |
790 | } |
791 | ||
5e4c1243 PF |
792 | ret = imx_rproc_detect_mode(priv); |
793 | if (ret) | |
794 | goto err_put_mbox; | |
795 | ||
cc0316c1 PF |
796 | ret = imx_rproc_clk_enable(priv); |
797 | if (ret) | |
2df70620 | 798 | goto err_put_mbox; |
a0ff4aa6 | 799 | |
2df70620 PF |
800 | INIT_WORK(&priv->rproc_work, imx_rproc_vq_work); |
801 | ||
e13d1a43 PF |
802 | if (rproc->state != RPROC_DETACHED) |
803 | rproc->auto_boot = of_property_read_bool(np, "fsl,auto-boot"); | |
804 | ||
a0ff4aa6 OR |
805 | ret = rproc_add(rproc); |
806 | if (ret) { | |
807 | dev_err(dev, "rproc_add failed\n"); | |
808 | goto err_put_clk; | |
809 | } | |
810 | ||
99a31adf | 811 | return 0; |
a0ff4aa6 OR |
812 | |
813 | err_put_clk: | |
814 | clk_disable_unprepare(priv->clk); | |
2df70620 PF |
815 | err_put_mbox: |
816 | imx_rproc_free_mbox(rproc); | |
817 | err_put_wkq: | |
818 | destroy_workqueue(priv->workqueue); | |
a0ff4aa6 OR |
819 | err_put_rproc: |
820 | rproc_free(rproc); | |
99a31adf | 821 | |
a0ff4aa6 OR |
822 | return ret; |
823 | } | |
824 | ||
825 | static int imx_rproc_remove(struct platform_device *pdev) | |
826 | { | |
827 | struct rproc *rproc = platform_get_drvdata(pdev); | |
828 | struct imx_rproc *priv = rproc->priv; | |
829 | ||
830 | clk_disable_unprepare(priv->clk); | |
831 | rproc_del(rproc); | |
2df70620 | 832 | imx_rproc_free_mbox(rproc); |
eed411fc | 833 | destroy_workqueue(priv->workqueue); |
a0ff4aa6 OR |
834 | rproc_free(rproc); |
835 | ||
836 | return 0; | |
837 | } | |
838 | ||
839 | static const struct of_device_id imx_rproc_of_match[] = { | |
c8a1a56d | 840 | { .compatible = "fsl,imx7ulp-cm4", .data = &imx_rproc_cfg_imx7ulp }, |
a0ff4aa6 OR |
841 | { .compatible = "fsl,imx7d-cm4", .data = &imx_rproc_cfg_imx7d }, |
842 | { .compatible = "fsl,imx6sx-cm4", .data = &imx_rproc_cfg_imx6sx }, | |
4ab8f960 PF |
843 | { .compatible = "fsl,imx8mq-cm4", .data = &imx_rproc_cfg_imx8mq }, |
844 | { .compatible = "fsl,imx8mm-cm4", .data = &imx_rproc_cfg_imx8mq }, | |
79806d32 PF |
845 | { .compatible = "fsl,imx8mn-cm7", .data = &imx_rproc_cfg_imx8mn }, |
846 | { .compatible = "fsl,imx8mp-cm7", .data = &imx_rproc_cfg_imx8mn }, | |
d59eedc0 | 847 | { .compatible = "fsl,imx8ulp-cm33", .data = &imx_rproc_cfg_imx8ulp }, |
a0ff4aa6 OR |
848 | {}, |
849 | }; | |
850 | MODULE_DEVICE_TABLE(of, imx_rproc_of_match); | |
851 | ||
852 | static struct platform_driver imx_rproc_driver = { | |
853 | .probe = imx_rproc_probe, | |
854 | .remove = imx_rproc_remove, | |
855 | .driver = { | |
856 | .name = "imx-rproc", | |
857 | .of_match_table = imx_rproc_of_match, | |
858 | }, | |
859 | }; | |
860 | ||
861 | module_platform_driver(imx_rproc_driver); | |
862 | ||
863 | MODULE_LICENSE("GPL v2"); | |
4ab8f960 | 864 | MODULE_DESCRIPTION("i.MX remote processor control driver"); |
a0ff4aa6 | 865 | MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>"); |